JP2001308258A - Semiconductor package and method of manufacturing it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor package wherein, even though a plurality of semiconductor chips are mounted, a package size can be made small and thin and the number of wiring on a substrate can be reduced, and to provide the method of manufacturing it. SOLUTION: The semiconductor package has the substrate 1 comprising an opening part la and a surface provided with the wiring 4, a large diameter chip (a semiconductor chip of large diameter) 2 that faces the opening part 1a and is electrically connected to the wiring 4 in the periphery of the opening part 1a via a bump 7, and a small diameter chip (a semiconductor chip of small diameter) 3 that is fitted in the opening part 1a in a state of facing the large diameter chip 2 and is electrically connected to the large diameter chip 2 via a bump 7'.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor package and a method of manufacturing the same, and more particularly, to a semiconductor package having a plurality of semiconductor chips mounted on a same substrate and a method of manufacturing the same.

[0002]

2. Description of the Related Art In general, many semiconductor packages include one semiconductor package.
One semiconductor element (semiconductor chip) in one package
However, in recent years, due to the limitations of high functionality and high integration of a single semiconductor chip, by incorporating two or more semiconductor chips in one package,
There have been known ones that have realized substantial multifunctionality. As shown in FIG. 18, two or more semiconductor chips 10 are mounted on the same substrate 101 as shown in FIG.
2 and 103 are also disclosed in JP-A-9-51015.

[0003] In addition, there is another type in which the functions of two semiconductor chips are built in one semiconductor chip, thereby realizing a high-performance semiconductor package.

[0004]

However, when two or more semiconductor chips are incorporated in one package,
Since routing of wiring in a substrate on which a semiconductor chip is mounted becomes complicated, problems such as an increase in package size and an increase in cost arise.

On the other hand, when the functions of two semiconductor chips (for example, memory and logic) are built in one semiconductor chip, the wafer process becomes longer, causing problems such as a decrease in yield and an increase in cost. further,
Since the design man-hours increase, it is necessary to design each time, even if the problem that timely design is not possible or the memory size is changed according to the user's request, the design man-hours increase In addition, problems such as the production of masks and the management of inventory due to the increase in the number of types occur.

Accordingly, the present invention provides a semiconductor package and a method of manufacturing the same, which can reduce the package size and the number of wirings on a substrate while mounting a plurality of semiconductor chips. The purpose is to:

[0007]

According to the present invention, there is provided a semiconductor package having an opening and having a wiring provided on a surface thereof. The large-diameter semiconductor chip is provided to face the opening and is electrically connected to wiring around the opening via a bump. A small-diameter semiconductor chip is fitted in the opening so as to face the large-diameter semiconductor chip, and the small-diameter semiconductor chip and the large-diameter semiconductor chip are electrically connected via bumps.

In the semiconductor package having such a configuration,
Since the connection between the small-diameter semiconductor chip and the large-diameter semiconductor chip is performed without through the wiring on the substrate, the number of wirings on the substrate is reduced. Further, since the small-diameter semiconductor chip can be accommodated in the large-diameter semiconductor chip, the package size can be reduced. In addition, since the small-diameter semiconductor chip is accommodated in the opening of the substrate, the package thickness does not increase.

In a first method of manufacturing a semiconductor package according to the present invention, a step of electrically connecting a large-diameter semiconductor chip and a small-diameter semiconductor chip which are arranged to face each other via a bump; Fitting a small-diameter semiconductor chip into the formed opening, and electrically connecting the large-diameter semiconductor chip to the wiring provided on the substrate around the opening via a bump.

Further, according to a second method of manufacturing a semiconductor package of the present invention, a large-diameter semiconductor chip is disposed so as to face an opening formed in a substrate, and the semiconductor chip is provided on the substrate around the opening. Electrically connecting a large-diameter semiconductor chip to the wiring via a bump, and fitting a small-diameter semiconductor chip into the opening in a state facing the large-diameter semiconductor chip, and connecting the large-diameter semiconductor via the bump. Electrically connecting the chip and the small-diameter semiconductor chip.

According to such a manufacturing method, the large-diameter semiconductor chip and the small-diameter semiconductor chip are connected without passing through the wiring on the substrate, and the large-diameter semiconductor chip is connected to the wiring on the substrate. In addition, a semiconductor package in which a small-diameter semiconductor chip is accommodated in an opening formed in the substrate is obtained.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor package according to the present invention and a method for manufacturing the same will be described below in detail with reference to the drawings.

FIG. 1 is a sectional view showing an example of a semiconductor package according to the present invention. The semiconductor package shown in FIG. 1 includes a substrate 1, a large-diameter semiconductor chip (hereinafter, referred to as a large-diameter chip) 2, and a small-diameter semiconductor chip (hereinafter, referred to as a small-diameter chip) 3.

The substrate 1 is an ordinary printed substrate, a ceramic substrate, a film-like substrate made of a polyimide resin or the like, and has an opening 1a at the center. The opening 1a is smaller than the large diameter chip 2 and the small diameter chip 3
It has a larger diameter than that. Also, substrate 1
Has a plurality of connection holes 1b in addition to the opening 1a. Further, wirings 4 are provided on the surface of the substrate 1.

The wiring 4 extends to the vicinity of the periphery of the opening 1a, and is provided with a certain area as an electrode pad around the opening 1a. The wiring 4 is exposed on the back surface side of the substrate 1 through a connection hole 1b provided in the substrate 1 and, for example, through a conductive material 5 provided in a state of being embedded in the connection hole 1b. Substrate 1
Is connected to a solder ball 6 provided on the back surface side.
The conductive material 5 is made of, for example, the same material as the wiring 4.

The connection holes 1b formed in the substrate 1 are usually arranged outside the large-diameter chip 2 and the small-diameter chip 3 for stress relaxation.

The large-diameter chip 2 is made of, for example, a logic semiconductor element, and is arranged on the front side of the substrate 1 (ie, the side on which the wiring 4 is provided) so as to face the opening 1a. The surface of this large diameter chip 2 (opening 1a
The surface facing the opening 1a of the substrate 1 is located at a position corresponding to the electrode pad portion of the wiring 4 provided around the opening 1a, and at a position slightly inside the electrode pad portion. Are formed. The external electrodes of the large-diameter chip 2 and the wirings 4 (electrode pad portions) of the substrate 1 are electrically connected via bumps 7.

Here, for example, when the substrate 1 is in the form of a film, a support (so-called stiffener) 8 for securing the strength of the substrate 1 as necessary surrounds the large-diameter chip 2. It is assumed that the substrate 1 is fixed to the front surface side with an adhesive 9. The support 8 is, for example, a ring material made of a metal material such as Cu or stainless steel, a printed circuit board material, an epoxy resin or a thermoplastic resin formed by molding. When the substrate 1 is a printed circuit board, it is not necessary to provide the support 8.

On the other hand, the small-diameter chip 3 is made of, for example, a semiconductor element of a memory system, and is fitted into the opening 1a in a state of facing the surface of the large-diameter chip 2. On the surface of the small-diameter chip 3 (the surface facing the large-diameter chip 2), external electrodes (not shown) are formed at positions corresponding to the external electrodes provided on the large-diameter chip 2. And
The external electrodes of the large-diameter chip 2 and the external electrodes of the small-diameter chip 3 are electrically connected via bumps 7 '.

Further, between the large diameter chip 2 and the small diameter chip 3, between the substrate 1 and the large diameter chip 2 and the small diameter chip 3, the surface of the large diameter chip 2 and the surface of the small diameter chip 3, and furthermore, the large diameter chip The space between 2 and support 8 is sealed by filling with resin 10.

According to the semiconductor package having such a configuration, the small-diameter chip 3 and the large-diameter chip 2 are connected without the interposition of the wiring 4 on the substrate 1, so that the number of wirings 4 on the substrate 1 is reduced. be able to. As a result, the wiring design can be simplified, and the size of the package can be reduced and the cost can be reduced.

Further, according to the semiconductor package having such a configuration, the small-diameter chip 3 can be accommodated within the range of the large-diameter chip 2, so that the package size can be reduced. Moreover, the small-diameter chip 3 is placed in the opening 1a of the substrate 1.
Is stored, so that the package thickness does not increase. Further, in general, the semiconductor chip may be thinned in order to reduce the package thickness. However, when the thinned semiconductor chip is bonded to the substrate 1, the warpage of the semiconductor package increases, so that It becomes difficult to mount a semiconductor chip on a semiconductor device. However, in the present embodiment, since the small-diameter chip 3 and the large-diameter chip 2 are overlapped facing each other, the chip thickness is ensured, and the warpage of the semiconductor package is suppressed to be small. For this reason, mounting on a mounting substrate is also facilitated.

The case where one small-diameter chip 3 is connected to one large-diameter chip 2 has been described in the semiconductor package described with reference to FIG. However, the semiconductor package of the present invention is not limited to this. As shown in FIG. 2, a plurality of (two in the drawing) small-diameter chips 3 and 3 ′ are connected to one large-diameter chip 2. You may let it. In this case, the small-diameter chips 3 and 3 ′ are arranged in such a manner that the front surfaces of the small-diameter chips 3 and 3 ′ face the large-diameter chips 2. And
The opening 1a formed in the substrate 1 is formed to have an inner diameter enough to accommodate the small-diameter chips 3 and 3 'connected to the large-diameter chip 2, and each of the small-diameter chips 3 and 3' is formed in the opening 1a.
3 'shall be inserted.

Further, in such a case, although not shown here, a configuration may be adopted in which a plurality of openings are formed in the substrate 1 and the small-diameter chips 3 and 3 'are fitted into the respective openings. In this case, the wiring 4 on the substrate 1 can be connected to the large-diameter chip 2 in the portion of the substrate 1 between the openings, and the degree of freedom of the wiring 4 on the substrate 1 can be increased. improves.

In the semiconductor package shown in FIG. 1, the case where the resin 10 is filled between the large-diameter chip 2 and the small-diameter chip 3 has been described. However, as shown in FIG. 3, by providing a conductive layer 21 on the surface of the small-diameter chip 3 via an insulating film (not shown), the large-diameter chip 2 and the small-diameter chip 3 are cut off by the conductive layer 21. You may do it. This conductive layer 2
1 is provided so as to be insulated from the large-diameter chip 2 and the small-diameter chip 3 and may be connected to, for example, a ground or a power supply line. In this case, the resin 10 is filled between the conductive layer 21 and the large-diameter chip 2.

In the semiconductor chip having such a configuration, the conductive layer 21 serves as a shield for noise generated from the memory (small-diameter chip 3) or a shield for externally affecting the memory. Therefore, the memory (small diameter chip 3)
And the logic (large-diameter chip 2) can be prevented from malfunctioning, and the reliability of the semiconductor package can be improved.

Further, in the semiconductor package of FIG. 1, between the large diameter chip 2 and the small diameter chip 3, between the substrate 1 and the large diameter chip 2 and the small diameter chip 3, the surface of the large diameter chip 2 and the small diameter chip 3 The case where the surface, and furthermore, the space between the large-diameter chip 2 and the support 8 is sealed with the resin 10 is shown. However, the filling state of the resin 10 is not limited to this.

For example, as shown in FIGS. 2 and 3 and FIG. 4, the substrate 1 is located between the large-diameter chip 2 and the small-diameter chip 3.
Between the large-diameter chip 2 and the large-diameter chip 2, the surface of the large-diameter chip 2 and the surface of the small-diameter chip 3 are sealed with the resin 10, and the space between the large-diameter chip 2 and the support 8 is not filled with the resin 10. good.

Here, as shown in FIG. 5, the resin 10
At least between the large-diameter chip 2 and the small-diameter chip 3, the substrate 1
And the large-diameter tip 2.

FIG. 6 shows a semiconductor package according to the present invention.
To the configuration shown in FIG.

For example, in the semiconductor package, as shown in FIG. 6, the inside of the connection hole 1b provided in the substrate 1 is filled with a conductive material 5 'different from the wiring 4 (for example, the same solder as the solder ball 6). May be adopted.

As shown in FIG. 7, the semiconductor package is soldered to the front side of the substrate 1 (that is, the side on which the wiring 4 is provided, here, the side on which the large-diameter chip 2 is mounted). A configuration in which the ball 6 is provided may be used. In this case, it is assumed that the periphery of the large-diameter chip 2 on the front surface side of the substrate 1 is covered with the solder resist layer 22 so as to bury the wiring 4. This solder resist layer 22
Is formed with a connection hole 22b reaching the wiring 4, and the wiring 4 and the solder ball 6 are connected via the connection hole 22b. In this case, it is assumed that the support 8 is adhered to the back side of the substrate 1 (that is, the side on which the wiring 4 is not provided).

In each of the above drawings, the BGA
(Ball Grid Array) semiconductor package is shown. However, the semiconductor package of the present invention is, for example, shown in FIG.
Also, as shown in FIG. 9, the present invention can be similarly applied to an LGA (Land Grid Array) configuration having no solder ball (6). In this case, as shown in FIG. 8, the inside of the connection hole 1b of the substrate 1 may not be buried with a conductive material, and as shown in FIG. The structure may be embedded with the conductive material 5.

Further, as shown in FIG. 10, the semiconductor package may have a configuration in which a support (8) having a shape surrounding the large-diameter chip 2 or the small-diameter chip 3 is not provided on the substrate 1.

In addition, a semiconductor package is shown in FIG.
As shown in (1), the substrate 1 and the large-diameter chip 2 may have substantially the same size. In this case, the connection holes 1b and the solder balls 6 provided in the substrate 1 are provided within the size range of the large-diameter chip 2 and below the large-diameter chip 2 in the drawing.

FIGS. 12 and 13 show the mounting state of the semiconductor package described above. However, here, as a representative of the semiconductor package described with reference to FIGS. 1 to 11, the mounting state of the semiconductor package having the configuration described with reference to FIG. 1 is shown in FIG. FIG. 13 shows a mounting state of the semiconductor package.

As shown in these figures, the semiconductor package P is arranged with the surface on which the solder balls 6 are provided facing the surface on which the wiring patterns 32 are formed on the mounting substrate 31. Then, the wiring 4 of the semiconductor package P and the wiring pattern 32 on the mounting board 31 are connected via the solder balls 6 provided on the semiconductor package P.

The mounting substrate 31 and the semiconductor package P
(That is, the small-diameter chip 3 in FIG. 12 and the large-diameter chip 2 in FIG. 13) may be provided with a heat radiating plate 33. By using a material having the same coefficient of thermal expansion as that of the semiconductor chip, it is possible to prevent the semiconductor chips 2 and 3 from warping. For example, when the semiconductor chip is made of silicon, silicon (Si), Inconel, or the like can be preferably used as the heat sink 33. Here, a resin mixed with silver (Ag) or Cu can be suitably used for bonding between the semiconductor chips 2 and 3 and the heat sink 33 and between the heat sink 33 and the mounting substrate 31.

By adopting such a mounting mode, the heat of the semiconductor package is transferred from the heat sink 33 to the mounting board 3.
It is possible to release to one side.

In FIGS. 12 and 13, the case where the heat of the semiconductor package is released to the mounting substrate 31 via the heat sink 33 has been described. However, by adopting a mounting mode in which the semiconductor chip (that is, the small-diameter chip 3 in FIG. 12 and the large-diameter chip 2 in FIG. 13) is in direct contact with the mounting substrate 31, the heat of the semiconductor package is reduced. Can be directly discharged to the mounting substrate 31 from the substrate. However, when such a mounting mode is adopted, the thickness of the semiconductor chips 2 and 3 provided on the mounting substrate 31 is adjusted so that the semiconductor chips 2 and 3 and the mounting substrate 31 are in contact with each other in the mounted state. I decided to.

Although the case where the solder balls 6 are provided on the semiconductor package P side has been described here, when the semiconductor package has an LGA configuration, the solder balls 6 are provided on the mounting substrate 31 side. It shall be.

FIG. 14 is a sectional process view showing an example of a method for manufacturing a semiconductor package according to the present invention. Here, as an example, a method of manufacturing a semiconductor package having the configuration described with reference to FIG. 1 will be described. Note that the same components as those described with reference to FIG.

First, as shown in FIG. 14A, bumps 7 'are formed on a small-diameter chip (that is, a memory chip) 3.

At this time, first, in a wafer state before each small-diameter chip 3 is cut out, a titanium (Ti) layer and a nickel (Ni) layer (not shown) are sequentially formed on the entire surface of the wafer by sputtering. Form. After that, a resist pattern having an opening in the portion where the bump 7 'is formed is formed, and gold (A) is formed in the opening by performing electrolytic plating.
u) or a bump 7 'made of solder is formed. next,
The resist pattern is removed, and the Ti / Ni layer is patterned by etching using the new resist pattern as a mask. As a result, an external electrode formed by patterning the Ti / Ni layer serving as the base of the bump 7 'is formed below the bump 7', and a conductive layer made of the Ti / Ni layer is formed. This conductive layer can be connected to a ground or a power supply line, so that noise generated by the memory or noise externally affecting the memory can be shielded by such a conductive layer. Thereafter, the back surface of the wafer is polished (back-grinding) to a predetermined thickness, and further diced to obtain small-diameter chips 3 for memory. This small-diameter chip 3 has a bump 7 '.

The bumps 7 'are not limited to those formed by electrolytic plating, but may be stacked bumps (so-called ball bumps) formed on external electrodes by applying a wire bonding technique. Is also good. Further, as the external electrode, a conductive film having an adhesive layer formed on both sides may be bonded to the upper surface of the wafer. In this case, as the adhesive, a thermoplastic polyimide resin, a thermosetting epoxy resin, or the like can be used.
Further, the conductive film used at this time may be made of a resin-based conductive polymer other than a metal foil such as copper (Cu).

Next, the small-diameter chip 3 having such bumps 7 'is aligned with the large-diameter chip 2 for logic. Here, the small-diameter chips 3 are aligned with the wafer 2a before the large-diameter chips 2 are cut out. At this time, the surface of the small-diameter chip 3 (the surface on which the bumps 7 'are formed) is arranged to face the surface of the wafer 2a on which the large-diameter chip 2 is formed.

Next, as shown in FIG. 14 (2), a bump 7 'is bonded to an external electrode (not shown) of each large-diameter chip 2 formed in the wafer 2a. ', The small-diameter chip 3 and the large-diameter chip 2 are electrically connected. Then, large diameter tip 2 and small diameter tip 3
A resin (underfill) 10 is poured into the gap between the large-diameter chip 2 and the small-diameter chip 3 with the resin 10.

Here, when bonding the external electrodes (not shown) of the large-diameter chip 2 to the bumps 7 ′, for example, the small-diameter chip 3 is heated from 150 ° C. to 350 ° C. In the state heated to the range of room temperature to 250 ° C,
The bonding is performed by applying a pressure of 10 g to 200 g per bump 7 '. In particular, when the external electrode of the large-diameter chip 2 is aluminum (Al), the temperature of the small-diameter chip 3 is set to 250 ° C. and the temperature of the large-diameter chip 2 is set to 150 ° C. In such a heat and pressure bonding, the bump 7 'and the external electrode are bonded together while forming an alloy while melting. Here, ultrasonic waves may be applied simultaneously. In this case, the small-diameter tip 3 can be joined at room temperature.

In addition to the above joining method, a resin which is cured by heating or a resin containing conductive particles (an adhesive containing a conductive filler) is placed on the large-diameter chip 2, and the small-diameter chip 3 is placed thereon. , The resin sealing between the chips may be performed simultaneously with the bonding of the bumps 7 ′ and the external electrodes of the large-diameter chip 2. According to such a method, the large-diameter chip 2 and the small-diameter chip 3 are pressure-bonded by the shrinkage when the resin is cured, whereby the bump 7 ′ and the external electrode of the large-diameter chip 2 are joined. At this time, a liquid resin may be placed on the large-diameter chips 2 and the chips may be partially sealed with resin.

Next, as shown in FIG. 14C, the wafer on which the large-diameter chips 2 are formed is divided into each large-diameter chip 2 by dicing. A bonding chip including the chip 3 is formed.

Thereafter, as shown in FIG. 14 (4), a substrate 1 having an opening 1a which is slightly larger than the small-diameter chip 3 and slightly smaller than the large-diameter chip 2 is prepared. As the substrate 1, a normal printed substrate, a ceramic substrate, a polyimide tape or the like is used, and wirings 4 are provided on the surface. The wiring 4 extends to the vicinity of the periphery of the opening 1a, and is provided with a certain area as an electrode pad around the opening 1a. A conductive material 5 is buried in the connection hole 1b formed in the substrate 1 in a state of being connected to the wiring 4. On the surfaces of the wiring 4 and the conductive material 5, a plating layer 5a is provided.

Then, on the electrode pad portion of the wiring 4,
The bump 7 is formed via the plating layer 5a. The bump 7 may be a stud bump or may be formed by electrolytic plating, and is made of Au or an Au alloy.

Here, the large-diameter chip 2 and the wiring 4 on the substrate 1 are electrically connected via the bumps 7 on the substrate 1. At this time, the front side of the large-diameter chip 2 (the surface on which the external electrodes are formed) is opposed to the opening 1a on the front side of the substrate 1 (the side on which the wiring 4 is formed). Insert the small diameter tip 3. Next, for example, the external electrodes of the large-diameter chip 2 are bonded to the bumps 7 formed on the wiring 4 of the substrate 1, thereby electrically connecting the wiring 4 on the substrate 1 and the large-diameter chip 2. Let it.

Here, the bonding between the bump 7 and the external electrode of the large-diameter chip 2 is performed by, for example, heat and pressure bonding. The large-diameter chip 2 is heated from 200 ° C. to 350 ° C. In a state of being heated to a temperature of about ℃, bonding is performed by applying a pressure of 10 g to 200 g per bump 7.
Also, here, ultrasonic waves may be applied simultaneously, and in such a case, the large-diameter tip 2 can be joined at room temperature.

In addition to the above, as described with reference to FIG. 14B, the substrate 1 is formed by using an adhesive containing a conductive filler.
The upper bump 7 and the external electrode of the large-diameter chip 2 may be electrically connected, and the space between the large-diameter chip 2 and the substrate 1 may be sealed with a resin (adhesive).

Next, as shown in FIG. 14 (5), the support 8 is bonded and fixed to the wiring 4 forming surface side of the substrate 1 using an adhesive 9 in a state surrounding the large-diameter chip 2. A resin 10 is poured between the substrate 1 and the large-diameter chips 2 and the small-diameter chips 3 and further between the support 8 and the large-diameter chips 2 and cured.
The space between the substrate 1 and the large-diameter chip 2 and the small-diameter chip 3 is sealed.
It should be noted that, in the process described with reference to FIG.
-When the resin is not filled between the small-diameter chips 3, the distance between the substrate 1 and the small-diameter chips 3 is reduced to several mm or less so that the large-diameter chips 2 and the small-diameter chips 3 are formed in this process. The resin 10 can also be poured.

Thereafter, as shown in FIG. 14 (6), solder balls 6 are formed in a state of being connected to the conductive material 5 in the connection holes 1b of the substrate 1 to complete a semiconductor package.

In the above manufacturing method, the small-diameter tip 3
The bump 7 ′ connecting the large diameter chip 2 to the large diameter chip 2 has been described as being formed on the small diameter chip 3, but may be formed on the large diameter chip 2. Similarly, the large-diameter chip 2 and the substrate 1
Has been described as being formed on the substrate 1, but may be formed on the large-diameter chip 2.
When these bumps 7 and bumps 7 'are formed on the large-diameter chip 2, these bumps 7 and bumps 7' may be formed simultaneously.

When the bumps 7 connecting the substrate 1 and the large-diameter chip 2 are provided as stud bumps on the substrate 1, the surface of the plating layer 5a on the wiring 4 of the substrate 1 is Au. It is a plating layer or a palladium (Pd) plating layer. When the surface is an Au plating layer, a nickel (Ni) plating layer or a Pd plating layer is provided as a base.

Next, FIGS. 15 to 17 show examples of the method of forming the wiring 4 and the bumps 7 on the substrate 1. Hereinafter, taking the case where the film-shaped substrate 1 is used as an example, the forming method will be described in order from the example shown in FIG.

First, as shown in FIG. 15A, a substrate 1 made of an insulating film such as polyimide is prepared, and a punched hole serving as an opening 1a and a connection hole 1b is formed in the substrate 1 by using a die. Form. Next, as shown in FIG. 15B, a copper foil 4a is attached to the substrate 1 using an adhesive (not shown).
Then, the adhesive in the opening 1a and the connection hole 1b is removed. As the adhesive, a thermosetting resin such as an epoxy resin or a thermoplastic resin such as a polyimide resin is used. Thereafter, as shown in FIG. 15C, a resist pattern 4 having a shape exposing only the bottom of the connection hole 1b is formed.
1 is formed on the front surface and the back surface of the substrate 1, and the resist pattern 41 is removed after the conductive material 5 by Cu plating is buried in the connection hole 1 b using the mask as a mask.

Next, as shown in FIG. 15D, after a new resist pattern 42 is formed on both surfaces of the substrate 1,
As shown in FIG. 15 (5), the copper foil 4a is etched using the resist pattern 42 as a mask, and the wiring 4 formed by patterning the copper foil 4a on the front surface of the substrate 1 is formed. Next, as shown in FIG. 15 (6), after removing the resist pattern (42), the surface of the wiring 4 and the connection hole 1b are removed.
Ni plating and Au plating are sequentially performed on the surface of the inner conductive material 5 to form a plating layer 5a, and then, if necessary, as shown in FIG. The bump 7 is formed through.

The method shown in FIG. 16 is performed as follows. First, as shown in FIG. 16A, a substrate 1 made of an insulating film such as polyimide is prepared, and a copper thin film layer (not shown) is formed on the surface side of the substrate 1 by flash plating or sputtering. A resist pattern 43 is formed on the substrate 1. Next, as shown in FIG. 16 (2), the wiring 4 made of a copper plating layer is formed on the copper thin film layer on the surface of the substrate 1 by electrolytic plating from the resist pattern 43.

Next, as shown in FIG. 16 (3), the resist pattern (43) is removed, and further, the copper thin film layer on the surface of the substrate 1 is removed. Then, as shown in FIG.
A new resist pattern 44 is formed on the front surface and the back surface of the substrate 1, and the substrate 1 is etched from the back surface side (that is, the surface side on which the wiring 4 is not provided) using this as a mask. Thus, a connection hole 1b reaching the wiring 4 is formed in the substrate 1 together with the opening 1a.

Thereafter, as shown in FIG. 16 (5), the conductive material 5 is buried in the connection hole 1b by plating the wiring 4 exposed at the bottom of the connection hole 1b. Next, as shown in FIG. 16 (6), after removing the resist pattern (44), Ni plating and Au plating are sequentially performed on the surface of the wiring 4 and the surface of the conductive material 5 inside the connection hole 1b to perform plating. The layer 5a is formed, and thereafter, if necessary, as shown in FIG. 16 (7), the bump 7 is formed on the wiring 4 via the plating layer 5a.

The method shown in FIG. 17 is performed as follows. First, as shown in FIG.
A resin material (for example, liquid polyimide) is applied to one surface of the substrate 1 to form a semi-cured substrate 1. Next, as shown in FIG. 17 (2), a resist pattern 45 is formed on the back side of the substrate 1 (the side opposite to the Cu tape 4b), and the substrate 1 is etched by using the resist pattern 45 as a mask. The opening 1a and the connection hole 1b are formed, and then the resist pattern 45 is removed.

After the above, the steps shown in FIGS. 17 (3) to 17 (7) are performed in the same manner as described with reference to FIGS. 15 (3) to 15 (7). That is, as shown in FIG. 17 (3), the conductive material 5 is buried in the connection hole 1b, and then a new resist pattern 46 is formed as shown in FIG. 17 (4). As shown, the Cu tape 4b is etched using the resist pattern 46 as a mask to pattern the wiring 4. Next, as shown in FIG. 17 (6), after a plating layer 5a is formed on the surface of the wiring 4 and the surface of the conductive material 5, bumps 7 are formed as necessary as shown in FIG. 17 (7). .

The method for forming the substrate 1, the wiring 4, the opening 1a, and the connection hole 1b is not limited to the method described above with reference to FIGS.

[0069]

As described above, according to the semiconductor package and the method of manufacturing the same of the present invention, the large-diameter semiconductor chip and the small-diameter semiconductor chip are connected without interposing the wiring on the substrate, so that the , The number of wirings can be reduced. In addition, by stacking the large-diameter semiconductor chip and the small-diameter semiconductor chip, the package size can be reduced. In addition, since a small-diameter semiconductor chip is accommodated in the opening of the substrate, it is possible to prevent the package thickness from increasing. As a result, it is possible to obtain a low-cost semiconductor package which is thin, small, and has a small number of wirings on a substrate, while mounting a plurality of semiconductor chips.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a first example of a semiconductor package of the present invention.

FIG. 2 is a sectional view showing a second example of the semiconductor package of the present invention.

FIG. 3 is a sectional view showing a third example of the semiconductor package of the present invention.

FIG. 4 is a sectional view showing a fourth example of the semiconductor package of the present invention.

FIG. 5 is a sectional view showing a fifth example of the semiconductor package of the present invention.

FIG. 6 is a sectional view showing a sixth example of the semiconductor package of the present invention.

FIG. 7 is a sectional view showing a seventh example of the semiconductor package of the present invention.

FIG. 8 is a sectional view showing an eighth example of the semiconductor package of the present invention.

FIG. 9 is a sectional view showing a ninth example of the semiconductor package of the present invention.

FIG. 10 is a sectional view showing a tenth example of the semiconductor package of the present invention.

FIG. 11 is a sectional view showing an eleventh example of the semiconductor package of the present invention.

FIG. 12 is a cross-sectional view illustrating a first example of a mounting mode of a semiconductor package.

FIG. 13 is a cross-sectional view illustrating a second example of a mounting mode of the semiconductor package.

FIG. 14 is a sectional process view illustrating the method for manufacturing a semiconductor package of the present invention.

FIG. 15 is a sectional process view illustrating a first example of a method of manufacturing a substrate used for a semiconductor package.

FIG. 16 is a sectional process view illustrating a second example of a method for manufacturing a substrate used for a semiconductor package.

FIG. 17 is a sectional process view illustrating a third example of a method for manufacturing a substrate used for a semiconductor package.

FIG. 18 is a cross-sectional view illustrating a configuration of a conventional semiconductor package.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... board | substrate, 1a ... opening part, 2 ... large diameter chip (large diameter semiconductor chip), 3 ... small diameter chip (small diameter semiconductor chip),
4 wiring, 7, 7 'bump, 10 resin, 21 conductive layer, P semiconductor package

Claims (5)

[Claims] A substrate having an opening and a wiring provided on a surface thereof, provided opposite to the opening, and electrically connected to the wiring around the opening via a bump. A large-diameter semiconductor chip, and a small-diameter semiconductor chip fitted into the opening facing the large-diameter semiconductor chip and electrically connected to the large-diameter semiconductor chip via a bump. A semiconductor package characterized by the above-mentioned. 2. The semiconductor package according to claim 1, wherein a conductive layer is provided between the large-diameter semiconductor chip and the small-diameter semiconductor chip. 3. The semiconductor package according to claim 1, wherein a resin is filled between at least the large-diameter semiconductor chip and the substrate and between the large-diameter semiconductor chip and the small-diameter semiconductor chip. A semiconductor package characterized by the above-mentioned. 4. A step of electrically connecting a large-diameter semiconductor chip and a small-diameter semiconductor chip, which are arranged to face each other, via bumps, and fitting the small-diameter semiconductor chip into an opening formed in a substrate. Electrically connecting the large-diameter semiconductor chip via bumps to wiring provided on the substrate around the opening. 5. A semiconductor chip having a large diameter is disposed so as to face an opening formed in a substrate, and a wiring provided on the substrate around the opening is provided via a bump on a wiring provided on the substrate. Electrically connecting the chip; fitting a small-diameter semiconductor chip into the opening while facing the large-diameter semiconductor chip; and electrically connecting the large-diameter semiconductor chip and the small-diameter semiconductor chip via bumps. A method of manufacturing a semiconductor package.