JP2001306547A - Device and method for computation - Google Patents

Abstract

PROBLEM TO BE SOLVED: To highly accurately perform FFT computation which demodulates an OFDM signal. SOLUTION: An FFT computation circuit 1 is provided with a bit quantity control circuit 8 for controlling the bit quantity of arithmetic data, while referring to the butterfly computation result stored in a work memory 7. When data, having the bit quantity with the possibility of overflow in the butterfly computation, are contained by more than a fixed number, the bit quantity control circuit 8 shifts the bits of all data in the worm memory 7 to the LSB side. When data, having the bit quantity with the possibility of overflow in the butterfly computation are less than the fixed number, the bit quantity control circuit 8 chips the MSB bits of the relevant data having the bit quantity with the possibility of an overflow.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to orthogonal frequency division multiplexing transmission (OFDM).
The present invention relates to an arithmetic device and an arithmetic method for performing an FFT (Fast Fourier Transform) operation used at the time of receiving a digital broadcast or the like by a multiplexing method.

[0002]

2. Description of the Related Art In recent years, as a system for transmitting digital signals, an orthogonal frequency division multiplexing system (OFDM) has been proposed.
A modulation method called "requency division multiplexing" has been proposed. In this OFDM system, a number of orthogonal subcarriers (subcarriers) are provided in a transmission band, data is allocated to the amplitude and phase of each subcarrier, and PSK (Phase Shift Keying) and QAM (Quadraturtu
This is a method of performing digital modulation by re-amplitude modulation.

In this OFDM system, since the transmission band is divided by a large number of subcarriers, the band per subcarrier wave becomes narrow and the modulation speed becomes slow, but the total transmission speed is different from that of the conventional modulation system. There is no feature. Further, the OFDM scheme has a feature that the symbol rate is reduced because a large number of subcarriers are transmitted in parallel. Therefore, in the OFDM system, the time length of the multipath relative to the time length of the symbol can be shortened, and multipath interference is reduced. Further, in the OFDM system, data is allocated to a plurality of subcarriers, so that an inverse Fourier transform is performed during modulation (Inverse Fast Fourier Transform).
orm) arithmetic circuit, FFT that performs Fourier transform during demodulation
By using a (Fast Fourier Transform) arithmetic circuit, a transmission / reception circuit can be configured.

[0004] From the above characteristics, the OFDM system is widely studied for application to terrestrial digital broadcasting which is strongly affected by multipath interference. Such OF
As terrestrial digital broadcasting to which the DM system is applied, for example, DVB-T (Digital Video Broadcasting-Terres
trial) and ISDB-T (Integrated Services Digital)
Broadcasting-Terrestrial) has been proposed.

[0005] A digital television broadcast receiving apparatus (OFDM receiving apparatus) based on the OFDM system will be described. FIG. 2 is a block diagram of the OFDM receiver.

In FIG. 2, when a signal transmitted between blocks is a complex signal, a signal component is represented by a thick line, and when a signal transmitted between blocks is a real number signal, a signal component is represented by a thin line. Is expressed.

As shown in FIG. 2, an OFDM receiver 100 includes an antenna 101, a tuner 102, a band-pass filter (BPF) 103, and an A / D conversion circuit 104.
, Digital quadrature demodulation circuit 105, and fc correction circuit 10
6, the FFT operation circuit 107, and the narrow-band fc error calculation /
Window synchronization circuit 108, wideband fc error calculation circuit 109, and numerical control oscillation circuit (NCO) 110
, CPE cancel circuit 112, and CPE calculation circuit 1
13, an equalizer 114, and a detection / error correction circuit 1
15 and a transmission control information demodulation circuit 116.

[0008] A broadcast wave of a digital television broadcast broadcast from a broadcasting station is received by an antenna 101 of an OFDM receiving apparatus 100 and is transmitted as a RF signal to a tuner 102.
Supplied to

[0009] The RF signal received by the antenna 101 is frequency-converted into an IF signal by a tuner 102 comprising a local oscillator 102a and a multiplier 102b.
103. The IF signal is filtered by the BPF 103, digitized by the A / D conversion circuit 104, and supplied to the digital quadrature demodulation circuit 105.

The digital quadrature demodulation circuit 105 quadrature demodulates the digitized IF signal using a carrier signal of a predetermined frequency (fc: carrier frequency) and outputs a baseband OFDM signal. The baseband OFDM signal output from the digital quadrature demodulation circuit 105 is a so-called time domain signal before the FFT operation. For this reason, the baseband signal after the digital quadrature demodulation and before the FFT operation is hereinafter referred to as an OFDM time domain signal. This OFDM time domain signal is subjected to quadrature demodulation, and as a result, a real axis component (I channel signal) and an imaginary axis component (Q
Channel signal). The OFDM time domain signal output from the digital quadrature demodulation circuit 105 is supplied to the fc correction circuit 106.

The fc correction circuit 106 performs complex multiplication of the carrier frequency error correction signal output from the NCO 110 and the OFDM time domain signal to correct the carrier frequency error of the OFDM time domain signal. The carrier frequency error is an error in the center frequency position of the OFDM time-domain signal caused by, for example, a shift in the reference frequency output from the local oscillator 102a. As the error increases, the error rate of the output data increases. The OFDM time domain signal whose carrier frequency error has been corrected by the fc correction circuit 106 is
It is supplied to the FFT operation circuit 107 and the narrow-band fc error calculation / window synchronization circuit 108.

The FFT operation circuit 107 performs an FFT operation on the OFDM time domain signal, and extracts and outputs data orthogonally modulated on each subcarrier. This FF
The signal output from the T operation circuit 107 is a so-called frequency domain signal after the FFT. From this,
The signal after the FFT operation is called an OFDM frequency domain signal.

Here, the OFDM time domain signal is transmitted in a symbol unit called an OFDM symbol, as shown in FIG. This OFDM symbol is transmitted at the IF
It is composed of an effective symbol which is a signal period in which FT is performed, and a guard interval in which a waveform of a part of the latter half of the effective symbol is copied as it is. This guard interval is provided in the first half of the OFDM symbol. In the OFDM system, multipath resistance is improved by providing such guard intervals. For example, DVB-T standard (2K mode)
In the above, 2048 subcarriers are included in the effective symbol, and the subcarrier interval is 4.14.
Hz. Also, data is modulated on 1705 subcarriers out of the 2048 subcarriers in the effective symbol. The guard interval is a signal having a time length of 1/4 of the effective symbol. Note that O
In the DVB-T standard (2K mode), the FDM receiving apparatus 100 sets the effective symbol of this OFDM time domain signal to 2048 samples and sets the guard interval to 512.
A / D with clock as sampled by sample
The quantization is performed by the conversion circuit 104.

The FFT operation circuit 107 has one OFDM
A signal in the effective symbol length range (for example, 2048 samples) is extracted from a symbol, that is, one OFDM
The FFT operation is performed on the extracted OFDM time domain signal of 2048 samples excluding the guard interval range from the symbol. Specifically, as shown in FIG. 3, the calculation start position is from the boundary of the OFDM symbol (the position A in FIG. 3) to the end position of the guard interval (B in FIG. 3).
Position). This calculation range is called an FFT window.

As described above, the OFDM frequency domain signal output from the FFT operation circuit 107 is a complex composed of a real axis component (I channel signal) and an imaginary axis component (Q channel signal), like the OFDM time domain signal. Signal.
The OFDM frequency domain signal is converted to a wideband fc error calculation circuit 1
09, CPE cancel circuit 112, CPE calculation circuit 1
13 is supplied.

The narrow-band fc error calculating / window synchronizing circuit 108 and the wide-band fc error calculating circuit 109 generate O
A carrier frequency error included in the FDM time domain signal is calculated. Specifically, the narrowband fc error calculation / window synchronization circuit 108 calculates a narrowband carrier frequency error with an accuracy of ± 1/2 or less of the subcarrier frequency interval (for example, 4.14 Hz). Broadband fc error calculation circuit 109
Calculates a wideband carrier frequency error with subcarrier frequency (eg, 4.14 Hz) spacing accuracy. Narrow band f
c error calculation / window synchronization circuit 108 and wideband fc
The carrier frequency errors obtained by the error calculation circuit 109 are supplied to the NCO 110, respectively. The narrowband fc error calculation / window synchronization circuit 108 calculates the narrowband carrier frequency error with an accuracy of ± 1/2 or less of the subcarrier frequency interval, calculates the boundary position of the OFDM symbol, and FFT by
The start timing of the calculation is obtained, and the calculation range of the FFT (FF
T window).

The NCO 110 calculates a narrow-band carrier frequency error of ± 1/2 accuracy of the sub-carrier frequency interval calculated by the narrow-band fc error calculation / window synchronization circuit 108 and a sub-carrier calculated by the wide band fc error calculation circuit 109. A carrier frequency error correction signal whose frequency increases or decreases according to the carrier frequency error obtained by adding the wideband carrier frequency error with the frequency interval accuracy is output. The carrier frequency error correction signal is a complex signal and is supplied to the fc correction circuit 106. This carrier frequency error correction signal is output by the fc correction circuit 106 to O
The FDM time domain signal is subjected to complex multiplication, and the carrier frequency error component of the OFDM time domain signal is removed.

The CPE cancel circuit 112 is an OFDM
By complex multiplying the frequency domain signal by the CPE correction signal calculated by the CPE calculation circuit 113,
CPE (Common) included in the OFDM frequency domain signal
Phase Error) is removed. This CPE is noise due to the phase fluctuation of the subcarrier caused by the low frequency component of the phase noise, and is the noise riding on all the subcarriers at the same phase. CPE is the CPE calculation circuit 1
13 and supplied to the CPE cancel circuit 112. The OFDM frequency domain signal from which the CPE has been removed by the CPE cancel circuit 112 is output to the equalizer 11.
4 is supplied.

The equalizer 114 uses the scattered pilot signal (SP signal) to perform phase equalization and amplitude equalization of the OFDM frequency domain signal. The OFDM frequency domain signal that has undergone phase equalization and amplitude equalization is supplied to a detection / error correction circuit 115.

The detection / error correction circuit 115 detects information modulated on each subcarrier according to the modulation method, and performs data mapping and decodes the data. Thereafter, the detection / error correction circuit 115 performs an error correction process on the decoded data, for example, MPEG-2.
Output the transport stream.

The transmission control information demodulation circuit 116 transmits a TMCC (Transmission) modulated to a predetermined subcarrier position.
and Multiplexing Configuration Control) and TPS
(Transmission Parameter Signaling). The demodulated transmission control information is supplied to, for example, a system controller (not shown) and used for demodulation and reproduction control.

Next, regarding the FFT operation circuit 107,
This will be described in more detail.

The FFT operation circuit 107 performs, for example, an 11-stage radix-2 loop-type butterfly operation on an OFDM time-domain signal of data for one effective symbol (for example, 2048 samples), thereby converting the data from the time domain to the frequency domain. To generate an OFDM frequency domain signal.

The FFT operation circuit 107 includes an input buffer memory 121 and an input selector 122 as shown in FIG.
, Butterfly operation circuit 123, output selector 124
, A work memory 125, a block floating circuit 126, and an output buffer memory 127.

The input buffer memory 121 stores the OFDM time domain signal supplied from the fc correction circuit 106. The data stored in the input buffer memory 121 is based on the FFT window control signal supplied from the narrow-band fc error calculation and window
The DM time domain signal is cut out and supplied for each effective symbol length (2048 samples). Data is sequentially updated in the input buffer memory 121 for each OFDM symbol unit. That is, the input buffer memory 121
In, the OFDM time domain signal in a state in which guard interval data is removed from the OFDM symbol is sequentially stored for each OFDM symbol in FFT window units. Since the OFDM time domain signal stored in the input buffer memory 121 is a complex signal, the storage capacity of the input buffer memory 121 is at least twice as large as the number of valid symbol samples (2048 samples) (4096 bytes). Is required.

The input selector 122 stores the data stored in the input buffer memory 121 or the work memory 125.
The 48-sample complex signal data (input signal sequence)
The data is sequentially read out two points at a time in accordance with a predetermined calculation order, and supplied to the butterfly calculation circuit 123. When performing the first-stage butterfly operation, the input selector 122 reads data from the input buffer memory 121,
When performing the butterfly operation of the second and subsequent stages, data is read from the work memory 125.

The butterfly operation circuit 123 has a built-in R
Rotation operator data W ^K _N stored in the OM (W ^K _N = e
xp (-j2πk / N), where N is an integer) as appropriate,
Using this rotation operator data W ^K _N , the input selector 1
Two of the data supplied from the 22 (A, B) butterfly operation with respect to perform ^{_{(R 1 = A + W K}} B, R 2 = W K A + B), outputting two operation result data (R _1, R ₂₎ I do. The butterfly operation circuit 123 performs such a butterfly operation on all data (data of 2048 samples) for one effective symbol, and outputs operation result data of 2048 samples. The operation result data obtained by the butterfly operation is also a complex signal.
Since the FFT operation circuit 107 performs an eleven-stage loop-type butterfly operation, the butterfly operation circuit 123
Means that the butterfly operation is performed 11 times on an input signal system of the number of samples (2048 samples) for one effective symbol.

When the butterfly operation circuit 123 performs the final (11th) stage butterfly operation, the output selector 124 supplies the operation result data of the final stage to the output buffer memory 127. Also, the output selector 124
When the butterfly operation circuit 123 performs the butterfly operation before the last stage, the operation result data is stored in the work memory 125.

The work memory 125 stores operation result data output from the butterfly operation circuit 123. The operation result data stored in the work memory 125 is read by the input selector 122 and supplied to the butterfly operation circuit 123 via the block floating circuit 126 again.

The block floating circuit 126 monitors the bit amount of the operation result data stored in the work memory 125, and performs the next-stage butterfly operation using the operation result data stored in the work memory 125. In this case, it is determined whether the operation result output does not overflow (data of a certain bit or more). If there is a possibility of overflow, the operation result data of all 2048 samples stored in the work memory 125 is replaced with LSB (Least Significant Bi
Bit shift to the t) side to reduce the total bit amount and avoid overflow of the operation result output.

The output buffer memory 127 stores final operation result data (ie, data for one effective symbol of an OFDM frequency domain signal) obtained by performing an 11-stage loop-type butterfly operation. The OFDM frequency domain signal for one symbol stored in the output buffer memory 127 is supplied to the CPE cancel circuit 112 and the CPE calculation circuit 113.

In the above-described FFT operation circuit 107,
The operation result data of the butterfly operation by the butterfly operation circuit 123 is stored in the work memory 125, and the operation result data is fed back as an input signal sequence of the butterfly operation circuit 123 to perform an 11-stage loop-type butterfly operation. In the FFT operation circuit 107, the butterfly operation circuit 123 multiplies the data of the number of samples (2048 samples) for one effective symbol by the rotation operator data W in each stage.
By performing the calculation while appropriately replacing ^K _N , the butterfly calculation is performed on all the data for one effective symbol (data of 2048 samples). This allows 20
A 48-domain time-domain signal can be converted into a frequency-domain signal frequency-decomposed into 2048 subcarriers.

In the butterfly operation, as described above, in the case of a radix-2 operation, a predetermined complex number (rotation operator) is applied to one data B (complex number) of two data A and B. ) W ^K _N (= (exp (−j2π
k / N)), N is after it has been multiplied by an integer), and to calculate the result of the operation, the sum (operation result of the butterfly operation R = A + W ^K B) with the other data A (complex).

At this time, the bit amount (dynamic range) that can be taken by the real part and the imaginary part of the operation result R of the one-stage butterfly operation is (1 + 2 ¹ ) of the dynamic range of the data A and B before the operation. ^{/ 2} ) times.

The reason will be described with reference to FIG.

It is assumed that a butterfly operation is performed on two data A and B in which the dynamic range of the real part and the dynamic range of the imaginary part are within the range of the section [-a, a]. In other words, the dynamic range of the data A and B (complex numbers) to be calculated is calculated with respect to the origin of the complex plane.
It is assumed that one side is within the square area 2a. The rotation operator W ^K is an operator that rotates the position by a predetermined angle around the origin. Therefore, W ^K B is the result of the multiplication of the rotation operators W ^K and the data B, the dynamic range of the real and imaginary part, the interval [-2 ^1/2 a, 2
^{1 /} 2a]. Furthermore, the sum of W ^KB and A, that is, the calculation result R of the butterfly operation, has a dynamic range of the real part and the imaginary part thereof in the section [-(1 + 2 ^1/2 ) a,
(1 + 2 ^1/2 ) a].

Therefore, when a radix-2 butterfly operation is performed, the bit amount of output data may increase to (1 + 2 ^1/2 ) times the bit rate of the original data. Even in the case of a butterfly operation such as a radix 4 or a radix 8, the bit amount may similarly increase (although the multiples that increase in the radix 2, radix 4, and radix 8 are different).

However, for example, the work memory 12
5 and 1 assigned to the output buffer memory 127
The bit amount for one data is set to a predetermined value in advance, and even if an operation result that exceeds the bit amount is output, it cannot be stored in these memories and overflows.

Therefore, in general, in the FFT operation circuit, for example, the above-mentioned block floating circuit 126 is provided at the subsequent stage of the butterfly operation circuit 123 or the subsequent stage of the work memory 125 to prevent overflow of the operation result after the butterfly operation. ing.

As a result, in a general FFT operation circuit,
For example, even for an input signal having a large power variation at each frequency as shown in FIG. 6, all frequency components are represented within a defined bit range without overflowing a specific frequency component having a large power. be able to.

[0041]

By the way, an OFDM signal broadcast from a broadcasting station or the like is a signal having a characteristic that power is uniformly distributed within a set frequency band as shown in FIG. is there. That is, in the OFDM signal broadcast from a broadcasting station or the like, the power of each subcarrier is almost the same.

However, at the time of transmission, for example,
When a signal of a specific frequency such as a video carrier and an audio carrier of an analog television broadcast is superimposed on the OFDM signal as noise, as shown in FIG.
This results in a signal that includes power that protrudes by the frequency component of the specific frequency. The received signal on which the noise component of relatively large power of a specific frequency is superimposed is subjected to FFT.
In the case of conversion, due to the influence of the block floating circuit as described above, in order to secure the dynamic range of this noise component, the entire operation result is bit-shifted during butterfly operation. For this reason, bits are allocated to noise components having a large power that are irrelevant to the original, so that the amount of bits allocated to the original signal components other than the noise components decreases.

As described above, in the FFT operation circuit used in the conventional OFDM receiver, for example, when a signal of a specific frequency having relatively large power is superimposed on the received signal as noise, the FFT operation circuit performs Not only does it contain noise, it also reduces the amount of bits to represent the original signal component relative to the magnitude of the noise power,
There is a problem that bit precision is deteriorated. In addition, there is a problem that the use efficiency of the work memory and the output buffer memory is reduced due to the influence of the noise component.

The present invention has been made in view of the above situation, and is directed to an orthogonal frequency division multiplexing (OFDM) signal including subcarriers whose power has been greatly increased due to the influence of noise or the like. However, it is an object of the present invention to provide an arithmetic device and an arithmetic method capable of reducing the influence of noise and the like, performing fast Fourier transform with improved arithmetic accuracy, and improving the efficiency of memory use. .

[0045]

An arithmetic unit according to the present invention converts an orthogonal frequency division multiplexing (OFDM) signal consisting of a time signal sequence in which the number of samples of the effective symbol length is set to m into a fast Fourier transform in units of the effective symbol length. An arithmetic unit that converts the signal into a frequency signal sequence by performing conversion.
A butterfly operation circuit that performs a butterfly operation on the supplied input signal sequence, and a bit amount control circuit that controls a bit amount of the input signal sequence supplied to the butterfly operation circuit, wherein the bit amount control circuit includes: When the input signal sequence contains more than n (n <m) signal points having a bit amount that may overflow when the butterfly operation is performed, all signal points of the input signal sequence When data points are shifted to the LSB (Least Significant Bit) side and a signal point having a bit amount that may overflow when a butterfly operation is performed is included in the input signal sequence in the number of n or less, Clipping MSB (Most Significant Bit) side bits of data at a signal point having a bit amount that may overflow. That.

In this arithmetic unit, when the number of signal points having a bit amount that may overflow when the butterfly operation is performed is included in the input signal sequence more than n (n <m), the input signal sequence The data of all signal points of the signal sequence are bit-shifted to the LSB (Least Significant Bit) side, and a signal point having a bit amount that may overflow when the butterfly operation is performed is included in the input signal sequence in n or less. In this case, the MSB (Most Significant Bit) side bit of the data of the signal point having the bit amount that may overflow is clipped.

According to the operation method of the present invention, a frequency signal is obtained by performing a fast Fourier transform on an orthogonal frequency division multiplexing (OFDM) signal composed of a time signal sequence in which the number of samples of the effective symbol length is set to m in units of the effective symbol length. An arithmetic method for converting into a sequence, wherein when performing the fast Fourier transform by performing a butterfly operation on a supplied input signal sequence, a signal having a bit amount that may overflow when the butterfly operation is performed. If the number of points is larger than n (n <m) in the input signal sequence, the data of all signal points of the input signal sequence is bit-shifted to the LSB (Least Significant Bit) side, and the butterfly operation is performed. , Signal points having a bit amount that may overflow may be included in the input signal sequence in the number of n or less. If it is is characterized by clipping the bit of the MSB (Most Significant Bit) side of the data signal points having a bit amount that may be the overflow.

According to this operation method, when the input signal sequence contains more than n (n <m) signal points having a bit amount that may overflow when the butterfly operation is performed, The data of all signal points of the signal sequence are bit-shifted to the LSB (Least Significant Bit) side, and a signal point having a bit amount that may overflow when the butterfly operation is performed is included in the input signal sequence in n or less. In this case, the MSB (Most Significant Bit) side bit of the data of the signal point having the bit amount that may overflow is clipped.

[0049]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, as an embodiment of the present invention, an FFT operation circuit applied to a digital broadcast receiving apparatus (OFDM receiving apparatus) based on the OFDM system (DVB-T standard (2K mode)) will be described. .

FIG. 1 shows a block diagram of an FFT operation circuit to which the present invention is applied. The FFT operation circuit 1 shown in FIG. 1 is used in place of the FFT operation circuit 107 provided in the OFDM receiver 100 shown in FIG.

The FFT operation circuit 1 performs, for example, an eleven-stage radix-2 loop-type butterfly operation on an OFDM time-domain signal of data (2048 samples) for one effective symbol, thereby shifting the data from the time domain to the frequency domain. OF
This is for orthogonally transforming a DM signal to generate an OFDM frequency domain signal.

As shown in FIG. 1, the FFT operation circuit 1
It has an input buffer memory 2, an input selector 3, a butterfly operation circuit 4, an output selector 5, an output buffer memory 6, a work memory 7, and a bit amount control circuit 8.

The input buffer memory 2 stores the OFDM time domain signal supplied from the fc correction circuit 106 shown in FIG. The data stored in the input buffer memory 2 is obtained by cutting out the OFDM time domain signal by one effective symbol length (2048 samples) based on the FFT window control signal supplied from the narrow band fc error calculation / window synchronization circuit 108 described above. It is. Data is sequentially updated in the input buffer memory 121 for each OFDM symbol unit. That is, the input buffer memory 121 sequentially stores the OFDM time domain signals in a state where data for the guard interval has been removed from the OFDM symbols for each OFDM symbol. The OF stored in the input buffer memory 121
Since the DM time domain signal is a complex signal, the storage capacity of the input buffer memory 121 is at least twice as large as the number of effective symbol samples (2048 samples) (4
096 bytes).

The input selector 3 has an input buffer memory 3
Alternatively, the complex signal data (input signal sequence) of 2048 samples stored in the work memory 13 is sequentially read out two points at a time in accordance with a predetermined calculation order, and supplied to the butterfly calculation circuit 123. The input selector 3
When performing the first-stage butterfly operation, data is read from the input buffer memory 2, and when performing the second-stage or later butterfly operation, data is read from the work memory 7.

The butterfly operation circuit 4 has a built-in ROM
Rotation operator data W ^K _N (W ^K _N = exp
(−j2πk / N), where N is an integer), and the two data A and B are read using the rotation operator data W ^K.
Computation (R ₁ = A + W ^KB ) and (R ₂
= W ^K A + B) and outputs _two calculation results (R ₁ , R ₂ ). The butterfly operation circuit 4 performs such a butterfly operation on all data (20
This is performed for 48 samples of data), and the generated operation result (2048 samples of data) is output. The operation result obtained by the butterfly operation is also a complex signal.

The output selector 5 supplies the result of the last butterfly operation (11th stage) to the output buffer memory 6 and the previous (10th to 10th) butterfly operation result to the work memory 7. Store.

The butterfly operation circuit 4 has a built-in ROM
Rotation operator data W ^K _N (W ^K _N = exp
(-J2πk / N), N reads an integer) as appropriate, by utilizing the rotary operator data W ^K _N, input selector 122
Performs butterfly operation on the two data supplied _{(A, B) (R 1} = A + W K B, R 2 = W K A + B) from
Two operation result data (R ₁ , R ₂ ) are output. The butterfly operation circuit 4 performs such a butterfly operation on all data (data of 2048 samples) for one effective symbol, and outputs operation result data of 2048 samples. The operation result data obtained by the butterfly operation is also a complex signal. Since the FFT operation circuit 1 performs an eleven-stage loop-type butterfly operation, the butterfly operation circuit 4 performs eleven butterfly operations on an input signal system having the number of samples (2048 samples) for one effective symbol. Will do.

The output selector 5 includes a butterfly operation circuit 4
When the butterfly operation of the final stage (the eleventh stage) is performed, the operation result data of the final stage is stored in the buffer memory 12.
7 Further, when the butterfly operation circuit 4 performs the butterfly operation before the last stage, the output selector 124 stores the operation result data in the work memory 7.

The work memory 7 stores butterfly operation result data output from the butterfly operation circuit 4. The operation result data stored in the work memory 7 is read by the input selector 3 and supplied to the butterfly operation circuit 4 again via the bit amount control circuit 8.

The output buffer memory 6 stores final operation result data (ie, data for one effective symbol of an OFDM frequency domain signal) obtained by performing an eleven-stage loop-type butterfly operation. The OFDM frequency domain signal for one symbol stored in the output buffer memory 6 is supplied to the CPE cancel circuit 112 and the CPE calculation circuit 113 described above.

The bit amount control circuit 8 monitors the bit amounts of all the butterfly operation results of the 2048 samples stored in the work memory 7 and, based on the monitoring result, the butterfly operation stored in the work memory 7. Controls the amount of bits in the result.

The bit amount control circuit 8 is, specifically,
The following processing is performed.

First, the bit amount control circuit 8 determines the order of the next butterfly operation to be performed on the data stored in the work memory 7.

The case where the butterfly operation to be performed next is not the last stage, that is, the case where the butterfly operation performed in the butterfly operation circuit 4 is not the eleventh stage (the butterfly operation from the second stage to the tenth stage) Performs the same processing as the conventional bit floating circuit. That is, the bit amount control circuit 8
When the butterfly operation of the next stage is performed with reference to the operation result data stored in the data storage device, it is determined whether or not data having a bit amount that may overflow when the butterfly operation is performed is included. As a result of that judgment,
When data having a bit amount that may overflow is included, the bit amount control circuit 8 converts the value of all the data of 2048 samples stored in the work memory 7 into the LSB side. Is supplied to the butterfly operation circuit 4, and if data having a bit amount that may cause an overflow is not included, no data is stored in the work memory 7. The signal is supplied to the butterfly operation circuit 4 without performing the processing.

The bit amount control circuit 8 performs the butterfly operation in the final stage (in the FFT operation device 1, 11
If it is (stage), the following processing is performed.

First, the bit amount control circuit 8 refers to the operation result data stored in the work memory 7 and stores data having a bit amount that may overflow when the next-stage butterfly operation is performed. Determine if it is included.

As a result of the determination, if data having a bit amount that may cause an overflow is included in the work memory 7, the number of data that may overflow is counted. As a result of the counting, it is determined whether or not the number is equal to or less than an arbitrary number n (n <2048, for example, n = 4). If the number of data that may overflow is less than or equal to an arbitrary number n, the MSB side bit of the data that may overflow is clipped, and data other than the data that may overflow may be clipped. The processing is not performed at all, and is supplied to the butterfly operation circuit 4. If the number of samples that may overflow is larger than the arbitrary number n, the value of all the data of 2048 samples stored in the work memory 7 is bit-shifted to the LSB side. , And to the butterfly operation circuit 4.

As a result of the determination, if data having a bit amount that may cause overflow is not included in the work memory 7, no processing is performed on the data stored in the work memory 7. , And to the butterfly operation circuit 4.

By performing such processing, the bit amount control circuit 8 avoids the overflow of the result of the FFT operation. A high-precision FFT operation is performed without reducing the bit amount allocated to the component.

That is, even if the bit amount control circuit 8 includes data having a bit amount which may overflow, if the number is small, the bit amount control circuit 8
Rather than sacrifice bit precision for all eight sample data, instead of securing a dynamic range to avoid overflow, the MSB side of the data that may overflow is clipped and other data is With a large number of bits. That is, since the power difference between the subcarriers is small in the OFDM signal, a subcarrier having a significantly large power should not be transmitted. Therefore, even if data having a bit amount that may cause an overflow is included, if the number is extremely small, it is possible to determine that the data is data reflecting noise. Therefore, even if such data is clipped, the overall calculation accuracy does not deteriorate, and conversely, the bit accuracy of other data is improved, so that the overall calculation accuracy is improved.

In the present embodiment, the clipping process is performed by the bit amount control circuit 8 on only the last stage of the 11-stage butterfly operation. This is because the number of subcarriers affected by clipping is smaller when data is processed. However, for example, if clip processing is applied in consideration of the number of subcarriers that finally affect the value, clip processing may be performed not only at the final stage but also at other stages of butterfly computation. For example, when performing the ninth-stage butterfly operation,
, And when performing the butterfly operation of the tenth stage, the above-mentioned n is set to 2, and when performing the butterfly operation of the eleventh stage, the above-mentioned n is set to 4, and so on. Is also good.

In this embodiment, an example has been described in which the present invention is applied to an FFT operation device that performs a loop-type butterfly operation. However, the present invention is not limited to a loop-type butterfly operation, but may be a pipeline-type butterfly operation. It can also be applied to calculations.

Further, in the present embodiment, an example has been described in which the present invention is applied to an FFT operation device that performs a radix-2 butterfly operation. However, the present invention is not limited to a radix-2 butterfly operation, and may be, for example, a radix-4 or a radix-2. The present invention may be applied to an FFT operation device that performs a butterfly operation such as radix-8. However, in that case, the dynamic range in which the overflow occurs is different from the case of the radix-2.

Further, in the present embodiment, the bit amount control circuit 8 performs clip processing on data that may overflow, before performing butterfly computation. However, the present invention is not limited to this. For example, the data may be directly processed without clipping before the calculation, and data overflowed after the calculation may be clipped to the maximum value.

[0075]

In the arithmetic device and the arithmetic method according to the present invention, the input signal sequence contains more than n (n <m) signal points having a bit amount that may overflow when the butterfly operation is performed. In this case, the data of all the signal points of the input signal series is LSB (Least Signif
icant Bit) side, and if the signal point having a bit amount that may overflow when the butterfly operation is performed is included in the input signal sequence below n, the overflow possibility may occur. MSB (Most Signifi) of data of a signal point having a certain bit amount
Clip the bit on the cant Bit) side. As a result, in the present invention, even if an orthogonal frequency division multiplexing (OFDM) signal includes a subcarrier whose power has been significantly increased due to the influence of noise or the like, the influence of the noise or the like is reduced. Fast Fourier transform with improved calculation accuracy can be performed, and the memory use efficiency can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of an FFT operation circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram of an OFDM receiver.

FIG. 3 is a diagram for explaining a guard interval of an OFDM signal.

FIG. 4 is a block diagram of a conventional FFT operation circuit.

FIG. 5 is a diagram for comparing a dynamic range before calculation and a dynamic range after calculation when FFT calculation is performed.

FIG. 6 is a frequency characteristic diagram of an input signal having a large power variation for each frequency.

FIG. 7 is a frequency characteristic diagram of an OFDM signal.

FIG. 8 is a frequency characteristic diagram of an OFDM signal in which a frequency component having significantly large power is superimposed as noise on the OFDM signal.

[Explanation of symbols]

0 FFT operation circuit, 2 input buffer memory, 3 input selector, 4 butterfly operation circuit, 5 output selector, 6 output buffer memory, 7 work memory, 8
Bit amount control circuit

Continuation of the front page (72) Inventor Yasunari Ozaki 6-73 Kita Shinagawa, Shinagawa-ku, Tokyo F-term in Sony Corporation (reference) 5B056 BB13 CC03 FF01 FF02 FF04 FF05 FF07 FF16 5K022 DD01 DD13 DD19 DD33

Claims (10)

[Claims] 1. An orthogonal frequency division multiplexing (OF) comprising a time signal sequence in which the number of samples of an effective symbol length is m.
DM) A signal processing device for converting a signal into a frequency signal sequence by performing a fast Fourier transform in units of the effective symbol length, wherein the butterfly operation circuit performs a butterfly operation on the supplied input signal sequence, and is supplied to the butterfly operation circuit. A bit amount control circuit for controlling the bit amount of the input signal sequence to be performed, wherein the bit amount control circuit includes a signal point having a bit amount that may overflow when performing a butterfly operation in the input signal sequence. , The data of all the signal points of the input signal sequence is bit-shifted to the LSB (Least Significant Bit) side, and a bit that may overflow when the butterfly operation is performed is performed. If a signal point having an amount is included in the input signal sequence below n, the overflow Arithmetic apparatus characterized by clipping the bit of the MSB (Most Significant Bit) side of the data signal points having a bit amount that may be over. 2. An input buffer memory for taking in the OFDM signal consisting of a time signal sequence, a working memory for holding a butterfly operation result by the butterfly operation circuit, and outputs of the input buffer memory and the working memory. A selector that selectively extracts and supplies the input signal series to the butterfly operation circuit and an output buffer memory that holds a final operation result by the butterfly operation circuit, wherein the butterfly operation circuit outputs the butterfly operation result to the A plurality of butterfly operations are performed on the OFDM signal by storing the OFDM signal in a working memory, and the bit amount control circuit controls a bit amount of a signal sequence stored in the working memory. The arithmetic device according to claim 1, wherein 3. The bit amount control circuit according to claim 1, wherein, when performing a butterfly operation in a final stage, a signal point having a bit amount that may overflow when the butterfly operation is performed is included in the input signal sequence by n (n <n m)
If more signal points are included, data points of all signal points of the input signal sequence are bit-shifted to the LSB side, and a signal point having a bit amount that may overflow when a butterfly operation is performed is included in the input signal sequence. If n is less than or equal to n, the bit at the MSB side of the data of the signal point having a bit amount that may overflow may be clipped, and the butterfly operation other than the last stage may be performed. In the case where signal points having a bit amount that may cause an overflow are included in the input signal sequence, data of all signal points of the input signal sequence is bit-shifted to the LSB side. The arithmetic unit according to claim 2, wherein 4. The butterfly operation circuit includes a plurality of butterfly operation units having a pipeline configuration, and the bit amount control circuit controls a bit amount of a signal sequence supplied to the butterfly operation unit. The arithmetic device according to claim 1, wherein 5. The butterfly operation circuit according to claim 1, wherein, when performing a butterfly operation at a final stage, a signal point having a bit amount that may overflow when the butterfly operation is performed is included in the input signal sequence by n (n <m )
If more signal points are included, data points of all signal points of the input signal sequence are bit-shifted to the LSB side, and a signal point having a bit amount that may overflow when a butterfly operation is performed is included in the input signal sequence. If n is less than or equal to n, the bit at the MSB side of the data of the signal point having a bit amount that may overflow may be clipped, and the butterfly operation other than the last stage may be performed. In the case where signal points having a bit amount that may cause an overflow are included in the input signal sequence, data of all signal points of the input signal sequence is bit-shifted to the LSB side. The arithmetic unit according to claim 4, wherein 6. An orthogonal frequency division multiplexing (OF) comprising a time signal sequence in which the sampling number of the effective symbol length is m.
DM) a method for converting a signal into a frequency signal sequence by performing a fast Fourier transform on the effective symbol length unit, wherein the butterfly operation is performed on the supplied input signal sequence to perform the fast Fourier transform. If the input signal sequence contains more than n (n <m) signal points having a bit amount that may overflow when the butterfly operation is performed, all signal points of the input signal sequence LSB (Least Signif)
icant Bit) side, and when the signal point having a bit amount that may overflow when the butterfly operation is performed is included in the input signal sequence below n, the possibility of the overflow may occur. MSB (Most Signifi) of data of a signal point having a certain bit amount
An arithmetic method characterized by clipping the bit on the cant Bit) side. 7. The operation method according to claim 6, wherein a loop-type butterfly operation is performed. 8. When performing a butterfly operation at the final stage, a signal point having a bit amount that may overflow when the butterfly operation is performed includes n signal points in the input signal sequence.
If more than (n <m) are included, the signal points of all the signal points of the input signal sequence are bit-shifted to the LSB side, and a signal point having a bit amount that may overflow when a butterfly operation is performed. If the input signal sequence includes n or less, the MSB side bit of the data of the signal point having a bit amount that may overflow is clipped, and butterfly operations other than the final stage are performed. At this time, when a signal point having a bit amount that may overflow when a butterfly operation is performed is included in the input signal sequence, the data of all signal points of the input signal sequence is LSB
8. The method according to claim 7, wherein a bit is shifted to the side. 9. The method according to claim 6, wherein a pipeline type butterfly operation is performed. 10. When performing the last-stage butterfly operation,
A signal point having a bit amount that may overflow when performing a butterfly operation has n in the input signal sequence.
If more than (n <m) are included, the signal points of all the signal points of the input signal sequence are bit-shifted to the LSB side, and a signal point having a bit amount that may overflow when a butterfly operation is performed. If the input signal sequence includes n or less, the MSB side bit of the data of the signal point having a bit amount that may overflow is clipped, and butterfly operations other than the final stage are performed. At this time, when a signal point having a bit amount that may overflow when a butterfly operation is performed is included in the input signal sequence, the data of all signal points of the input signal sequence is LSB
10. The calculation method according to claim 9, wherein the bit is shifted to the side.