JP2001298739A - Coder and its method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a coder and its method that realize a system to apply variable length coding to a multi-value image with a simple processing and a configuration for a processing unit to execute the variable length coding system at a high-speed, which has not conventionally been established yet. SOLUTION: In the case of applying variable length coding to multi-value image data on the basis of individual parameters by each sub block of the data, controlling count of an up-down counter 713 on the basis of the result of comparison between difference values DS and DS+1 of a variable length code quantity in existence between adjacent parameters with a prescribed value N so as to converge the count to optimum values of the parameters.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an encoding apparatus and method for encoding image data.

[0002]

2. Description of the Related Art Generally, an image, particularly a multi-valued image, contains a very large amount of information, and there is a problem that the amount of data handled when storing and transmitting the image becomes enormous.
For this reason, when storing and transmitting images, it is necessary to remove the redundancy of the images and tolerate some deterioration in image quality.
High-efficiency coding for reducing the amount of data is used.

As one of these high-efficiency codings, JPE
G-system compression encoding is known. In this method, a multi-valued image is converted into frequency components by performing DCT conversion for each block, and the obtained conversion coefficients are quantized and subjected to variable-length coding.

[0004] The encoding using the DCT transform has a problem that if a high compression ratio is set, block distortion occurs in a decoded image. In recent years, in order to eliminate such distortion, a new encoding method using a wavelet transform has been proposed.

[0005] Also, variable length coding is often applied as a part of these various high-efficiency codings.

[0006]

However, a system for performing variable-length coding on multi-valued images by simple processing, and a configuration of a processing device for executing this variable-length coding system at high speed, are described below. At present, it has not been established yet.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an encoding device and a method for performing variable-length encoding of a multivalued image easily and at high speed.

[0008]

As one means for achieving the above object, the coding apparatus of the present invention has the following arrangement.

More specifically, the present invention provides an encoding apparatus having encoding means for encoding a symbol group into a variable-length code portion and a fixed-length code portion based on parameters, wherein the variable-length code portion between adjacent parameters is encoded. A difference means for calculating a difference value of the code amount, a comparison means for comparing the difference value with a predetermined value, and a count applied based on the comparison result to generate a parameter to be applied to the encoding in the encoding means. And generating means for performing the processing.

For example, the parameter indicates a code length of the fixed-length code portion.

For example, the encoding means performs Golomb-Rice encoding.

For example, the symbol group corresponds to a sub-block obtained by performing a wavelet transform on multi-valued image data.

For example, the predetermined value in the comparing means is
This is the number of symbols to be encoded in the symbol group.

For example, the generation means is an up / down counter which counts up or down based on the result of comparison by the comparison means.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described below in detail with reference to the drawings.

<First Embodiment> In the present embodiment,
An example of encoding 8-bit monochrome image data will be described. However, the present invention is not limited to this. For example, a monochrome image in which each pixel is represented by 4 bits, or a color component (RGB / Lab / YCrCb)
The present invention is also applicable to encoding of a color multi-valued image expressed by bits. When the present invention is applied to a color multivalued image, each color component may be encoded as a monochrome image.

FIG. 1 is a block diagram showing a configuration of an encoding apparatus to which the present embodiment is applied. In FIG.
Is an image input unit, 102 is a data storage unit, 103 is a discrete wavelet transform unit, 104 is a coefficient quantization unit, 105 is a coding parameter selection unit, 106 is a variable length coding unit,
07 is a bit plane scanning unit, 108 is a buffer, 10
9 is a code output unit.

First, the image input unit 101 inputs pixel data to be encoded in raster scan order. The image input unit 101 includes, for example, an imaging device such as a scanner or a digital camera, an imaging device such as a CCD, or an image data input process from a network line interface or the like.

The image data storage unit 102 is constituted by, for example, a RAM and stores image data inputted by the image input unit 101, but may be constituted by a recording medium such as an MO, a hard disk, a magnetic tape, or the like.

The discrete wavelet transform unit 103 performs a well-known discrete wavelet transform on the image data for one screen stored in the image data storage unit 102 to decompose the image data into a plurality of frequency bands. In the present embodiment, it is assumed that the discrete wavelet transform for the image data sequence represented by x (n) is performed based on the following equation.

R (n) = floor {(x (2n) + x (2n + 1)) / 2} d (n) = x (2n + 2) -x (2n + 3) + floor {(-r ( n) + r (n + 2) +2) / 4} where r (n) and d (n) are conversion coefficients, and r
(n) is a low frequency component and d (n) is a high frequency component.

In the above equation, floor {X} represents the maximum integer value not exceeding X. Although this conversion formula is for one-dimensional data, it is possible to perform two-dimensional conversion by applying this conversion in the horizontal and vertical directions in this order. By performing this two-dimensional conversion on the input image data sequence, LL, HL, and LL as shown in FIG.
It can be divided into four frequency bands (sub blocks) of LH and HH. These transform data are stored in the data storage unit 102 in order to smoothly output the data to the next-stage coefficient quantization unit 104 or to perform further wavelet transform.

The generated LL component is further subjected to a discrete wavelet transform in the same procedure as shown in FIG.
It is decomposed into seven frequency bands (sub-blocks) as shown in FIG. Then, another discrete wavelet transform is performed again to convert the image data sequence into LL, HL3, LH3, HH3, HL2, LH as shown in FIG.
2, HH2, HL1, LH1, and HH1 can be divided into ten frequency bands (sub-blocks), and the transform coefficients are stored in the data storage unit 102.

The conversion coefficients are LL, HL3, LH3, HH
3, HL2, LH2, HH2, HL1, LH1, HH1
Are output from the data storage unit 102 to the coefficient quantization unit 104 in the order of the sub-blocks and in the order of raster scan for each sub-block.

The coefficient quantization unit 104 quantizes each of the wavelet transform coefficients by a quantization step determined for each frequency component, and outputs the quantized value to the coding parameter selection unit 105 and the buffer 108.

Here, assuming that the coefficient value is X and the value of the quantization step for the frequency component to which the coefficient belongs is q, the quantized value Q (X) after quantization is obtained by the following equation.

Q (X) = floor {(X / q) +0.5} FIG. 3 shows the relationship between each frequency component and the quantization step in the present embodiment. As shown in FIG.
L, etc.) (HL1, LH1, HH1, etc.)
Has a larger quantization step. This allows
The compression ratio is improved by reducing the information of high frequency components that are hardly noticeable in deterioration.

The above-mentioned quantization value is evaluated by the encoding parameter selection unit 105, and the buffer is used until the variable parameter encoding unit 106 at the subsequent stage determines the k parameter necessary for encoding this quantization value. 108.

The coding parameter selection unit 105 selects a k parameter to be used in the subsequent variable length coding unit 106 based on the quantization value.

The k parameter refers to Goromice (Go
lomb Rice) is a value indicating the code length of the fixed-length part when performing variable-length encoding called encoding. For the sake of explanation, before describing the encoding parameter selection unit 105, the Golomb-Rice encoding process in the variable length encoding unit 106 will be described.

Although the basic method of the Golomb-Rice encoding process performed by the variable length encoding unit 106 is well known, the basic operation of the encoding and the characteristic parts of the present invention will be described below.

First, the buffer 108 storing the quantized value
, One sub-block of data is sequentially read. next,
The variable-length coding unit 106 performs the following preprocessing and Golomb-Rice coding based on the k parameter corresponding to the sub-block.

The variable length coding unit 106 checks the positive / negative of each input quantized value and outputs a negative sign bit. Specifically, when the quantization value is 0 or positive, “0” is output, and when the quantization value is negative, “1” is output, and then the quantization value is converted into an absolute value. Note that, although this processing is not strictly included in the Golomb-Rice encoding processing, in the present embodiment, this processing is performed as
Within

Next, the absolute value is subjected to Golomb-Rice encoding. The Golomb-Rice encoding process when the absolute value of the quantization value to be encoded is V and the value of the k parameter applied to the sub-block to be processed is k is performed in the following procedure.

First, after binary-shifted V is shifted to the right by k bits, “0” s are successively arranged by the number of obtained values, and then “1” is arranged as a delimiter bit. Next, by arranging the lower k bits of the original V, a variable length code (Golomb-Rice code) is generated.

FIG. 4 shows an example of a Golomb-Rice code for V = 0 to 7, k = 0, 1, 2. As can be seen from the figure, the code length of each variable-length code obtained from the absolute value V and the parameter k is V >> k (value obtained by shifting V right by k bits) +1 (delimiter bit) + k (parameter value) It can be easily guessed that it is a bit. Further, if a negative sign bit indicating positive / negative is added, the bit is further increased by one bit.

As can be seen from the figure, the Golomb-Rice code length with respect to V = 0 when k = 0 is k = 1, 2
It is especially shorter than at the time. This indicates that since the group of quantized values to be coded is biased toward 0, it is more suitable to perform coding with a small k parameter.

The Golomb-Rice coding used here has the effect that the coding and decoding can be executed by simple calculations without actually holding the code table as shown in FIG. In a variable length coding such as a normal Huffman coding, a table indicating a variable length code for a value to be coded must be held. In particular, when a plurality of variable length codes are appropriately switched for a value to be encoded in accordance with a related state, it is necessary to have a plurality of the above tables.

As described above, encoded data composed of a negative sign bit (representing +/-) and a variable length code (Golomb-Rice code) for the input quantized value is generated, and the bit plane scanning unit 107 at the subsequent stage is generated. Output to

Next, the processing in the coding parameter selection unit 105 for generating the k parameter required in the above-described variable length coding unit 106 will be described.

The total code amount T of the sub-block to be coded is
Assuming that the value of the k parameter is p, T _p = Σ (Vi >> p (value of Vi shifted right by p bits) +2 (negative bit and delimiter bit) + p) (1)

Assuming that the number of quantization values in the sub-block to be encoded is N, the above equation (1) becomes as follows.

T _p = (p + 2) × N + ΣVi >> p (2) The first term of the above equation (2): (p + 2) × N indicates the code amount by the fixed-length code part, and the second term: ΣVi >> p indicates the code amount of the variable length code portion. Here only the second term, and expressed as S _p in other words the following variable length code amount (3) as equation.

S _p = ΣVi >> p (3) This S _p increases as the value of p decreases. On the other hand, the code amount of the fixed-length code portion increases in proportion to the value of p, and p
Is increased by one, the code amount increases by N bits.

Next, consider the number of "1" in each bit plane when Vi is represented in binary. Vi>
The number of “1” existing in the plane of the least significant bit of> p is B _{p +1} and is represented by the following equation (4).

B _{p + 1} = Σ (Vi >> p) & 1 (4) That is, B ₁ represents the number of “1” in the least significant bit plane of Vi, and B ₂ represents the least significant bit of Vi. Represents the number of "1" in the second plane from the bit. From the above, from the relationship ΣVi >> p = (2 × ΣVi >> (p + 1)) + (Σ (Vi >> p) & 1) (5) and from the expressions (3) and (4) , S _p = 2 × S _{p + 1} + B _{p + 1} (6)

Here, assuming that the difference between S _p-1 and S _{p in which} the value of the k parameter differs by one is D _p , D _p = S _p-1 −S _p = (2 × S _p + B _p ) −S _p = S _p + B _p (p ≧ 1) (7) This D _p indicates how much the variable-length code amount increases as the value of the k parameter changes from p to p−1. Things. If this value is smaller than N, the total code amount is
Since reduced by N-D _p, the value of k parameters than p p
It is more efficient to set it to -1. Conversely, if D _p ≧ N, k
It is better to set the value of the parameter to p.

When the above equation (7) is further modified, D _p-1 = S _p-1 + B _p-1 = (2 × S _p + B _p ) + B _p-1 = (S _p + B _p ) + _{S p + B p-1 =} D p + S p + B p-1 , where, S _p, B because it is _{p-1 ≧ 0 D p-} 1 ≧ D p ··· (8) (8) The following can be said from the relationship between the expressions and the above description.

"Numerical sequence: D ₁ , D ₂ , D ₃ ,..., D _p-1 ,
_{D p, D p + 1,} ..., the _{D m, D 1 ≧ D 2} ≧ D 3 ≧ ... ≧ D p-1
≧ D _p ≧ D _{p + 1} ≧... ≧ D _m , and D _q ≧ N ≧
When there is q that _satisfies D _{q + 1} , q is _one of the optimal values of the k parameter (N is the number of quantized values in the sub-block). Here, the optimal value means a value that minimizes the entire code amount when Golomb-Rice encoding is performed. In addition, m is the largest value of p in B _p that is not zero, and S _m corresponding to this _m is zero. This is because when the largest quantized absolute value is shifted right by m bits, it becomes zero. Therefore, D _m = B _m ≦ N.

That is, when the k parameter changes from q to q + 1, the code amount increases by _{ND q + 1,} and when the k parameter changes from q to q-1, the code amount increases by D _q -N. However, when D _{q + 1} = N or D _q = N, the code amount does not increase and remains at the minimum. When D _{q + 1} = N, q +
1 is also an optimal value, and when _Dq = N, q-1 is also an optimal value.

There can be up to three optimum values of the k parameter. The condition is when D _q = N = D _{q + 1} holds,
In other words, this is the time when Sq _-1 = 0, _Sq = N, _{Sq + 1} = 2N. That is, q-1, q, and q + 1 are optimal values of the k parameter, and the total code amount T takes an extreme value (minimum value).
Therefore, as the k parameter moves away from the optimum value, the total code amount increases.

On the other hand, when q does not exist, N> D
It is the time when it becomes ₁ , and in this case, the value of the k parameter is 0 and the total code amount becomes the minimum. Then, the total code amount monotonically increases with a change (increase) in the value of k.

Here, in order to generalize the relationship between the sequence and the optimum value, it is defined as D ₀ = D ₁ + 2N. Then, the following can be said.

"Numerical sequence: D ₀ , D ₁ , D ₂ , D ₃ ,...
_{D p-1, D p,} D p + 1, ..., the _{D m, D 0 ≧ D 1} ≧ D 2 ≧ D
₃ ≧... ≧ D _p−1 ≧ D _p ≧ D _{p + 1} ≧... ≧ D _m , and when there exists _q satisfying D _q ≧ N ≧ D _{q + 1} , this q
Is one of the optimal values of the k parameter. As a result, the existence of the optimum value q becomes clear.

Here, if the comparison result C _p between D _p and N is defined as follows: C _p = 1: when D _p > N C _p = 0: when D _p ≦ N 9) in the above _{D 0 ≧ D 1 ≧ D 2} ≧ D 3 ≧ ... ≧ D p-1 ≧ D p ≧ D p + 1 ≧
.. ≧ D _m , C ₀ ≧ C ₁ ≧ C ₂ ≧ C ₃ ≧.
relationship of _{p-1 ≧ C p ≧ C} p + 1 ≧ ... ≧ C m is obtained. This means that C ₀ , C ₁ , C ₂ , C ₃ ,..., C _p−1 , C _p , C _{p + 1} ,
.., C _m indicate that the sequence starts from C ₀ = 1 and ends at C _m = 0, and there is one transition point from 1 to 0 on the way, but there is no transition point from 0 to 1. .

In the above sequence (C ₀ , C ₁ , C ₂ ,...), The point where the value changes from 1 to 0 is where the magnitude relationship between D _p and N is reversed.

[0057] except for the top C ₀ = 1, and 1 starting from C ₁
When q is q, that is, when C _q = 1 and C _{q + 1} = 0, D _q ≧ N> D _{q + 1} holds, so q is the optimal value of the k parameter.

In the present embodiment, the encoding parameter selection unit 105 is configured using the above principle. 7A and 7B show a block configuration of the encoding parameter selection unit 105.

In FIG. 7A, reference numeral 701 denotes a coefficient quantization unit 1
This terminal is a terminal for inputting the quantized value sent from the terminal 04. Here, it is assumed that the maximum number of effective bits of data input from the terminal 701 is 11 bits.

702a, 702b, 702c,... 7
02j is a bit shifter for sequentially shifting the input quantized value data to the right by one bit, 703a, 703b,
, 703k are accumulators for accumulating N data input to each of them, 704a, 704b, 70
Reference numerals 4c,..., 704j denote subtracters for calculating the difference between the outputs of two adjacent accumulators.

In FIG. 7B, 705 and 706 are
Output D of subtracters 704a to 704j ₁~ D_TenAny of
Are first and second selectors for selecting.

707 is a first comparator for comparing the output value of the first selector 705 with a predetermined value N, and 708 is a second comparator
Comparing the output value of the selector 706 with the predetermined value N
Is a terminal for inputting a predetermined value N.

As described above, the predetermined value N corresponds to the number of quantization values in the sub-block. Therefore, the value of N may be counted in advance at the time of quantization in coefficient quantization section 104.

711 is an inverter for inverting the output signal of the first comparator 707, 713 is an up / down counter for counting up or down based on the comparison result of the first and second comparators 707 and 708, 7
Reference numeral 17 denotes a detector that detects that the processing of the encoding parameter selection unit 105 has been completed, 719 denotes a terminal that outputs a signal of the detector 717, and 721 denotes a terminal that outputs the obtained optimal value of the k parameter. is there.

The accumulated values S _{0 to} S ₁₀ obtained by the accumulators 703a to 703k respectively have k parameters of 0, 1, 2,.
Indicates the code amount of the variable-length code portion when. That is, after all the quantized values in the sub-block have been input, S _{0 to} S ₁₀ are output from the accumulators 703a to 703k, respectively.

By passing the output values S _{0 to} S ₁₀ of these accumulators through subtractors 704a to 704j, (7)
The difference value D _p of the variable length code amount defined by the equation is obtained (p
= 1,2, ..., 9,10), these are the first and second
Are input to the selectors 705 and 706 of FIG.

On the other hand, the predetermined value N input from the terminal 709
Is input to the first selector 705 as D ₀ .
Note that D ₀ is different from the definition described above, but D ₀ ≧
If the value satisfies N, the encoding parameter selection unit 105 of the present embodiment can function normally.

First, the up / down counter 713
The operation when the initial value of is "0" will be described.

The counter 713 has an initial value “0” until all the quantized values are input by a control signal (not shown).
And when all the quantized values have been input, the holding is released and the operation is performed as follows.

[0070] The value of the counter 713 is sent to the first and second selectors 705 and 706, when the count value is S, a first selector 705 D _s, the second selector 7
06 selects and outputs Ds _{+ 1} . Therefore, when the counter 713 is an initial value, the count value S is “0”.
Therefore, the first selector 705 selects D ₀ and the second selector 706 selects D ₁ .

D₀, D₁Are the first and second comparisons, respectively.
Are sent to the devices 707 and 708 and compared with a predetermined value N. Up
As described above, the predetermined value N is D₀Satisfies ≧ N. Further here
Then D₀≧ D₁≧ D_Two≧ D_Three≧ N> D_Four≧ D_Five≧ ・ ・ ・ and provisional
Set. So in this case D ₀, D₁Both are more than N
From the first and second comparators 707 and 708,
“1” is output.

The output of the first comparator 707 is inverted to “0” by the inverter 711 and
13 is input to the countdown control terminal. On the other hand, the output “1” of the second comparator 708 is directly input to the count-up control terminal of the up-down counter 713. Therefore, the up / down counter 713 enters the count-up mode, and the count value increases from “0” to “1” based on a clock input (not shown).

When the count value is 1, D ₁ is output from the first selector 705 and D ₂ is output from the second selector 706. Since D ₁ and D ₂ ≧ N, the count value of the up / down counter 713 is increased from 1 to 2 as in the case of the above-described count value = 0. Similarly, when the count value is 2, the count value is increased from "2" to "3".

However, when the count value becomes 3, the operation of the up / down counter 713 differs because the comparison results in the first and second comparators 707 and 708 are different from those before. In this case, D ₃ is output from the first selector 705, D ₄ from the second selector 706 are output, each output of the corresponding comparator 707, 708 "1", it becomes "0". That is, the output of the second comparator 708 changes, and “0” is input to the count-up terminal of the up / down counter 713, which has been input “1”. Thus, the up / down counter 713 does not perform any of the count-up / count-down operations, and the count value “3”
Is held.

The count value of the up / down counter 713 is output from a terminal 721. At this time, the detector 717 detects that the outputs of the first and second comparators 707 and 708 have become “1” and “0”, respectively,
19 is output as "1". That is, the completion of the selection process of the optimum value of the k parameter is notified to the outside.

The case where the initial value of the up / down counter 713 is "0" has been described above. next,
The case where the initial value is "10" will be described.

When the count value of the up / down counter 713 is “10”, the first selector 705
_10, the second selector 706 selects "0" as the D _11. Here, D ₁₀ and "0" is smaller than N, the first and second comparators 707 and 708 together to output a "0". The output of the first comparator 707 is inverted to “1” by the inverter 711 and supplied to the countdown control terminal of the up / down counter 713. Thus, the counter value is reduced from “10” to “9” by inputting one clock (not shown).

When the count value of the up / down counter 713 is 9, the first selector
₉ is outputted, D ₁₀ is outputted from the second selector 706. Then, since D9 and D10 <N, the count value of the up / down counter 713 is reduced from "9" to "8" as in the case where the count value = "10" described above. Similarly, when the count value is 8, 7, 6, 5, 4, the count value is counted down from "8" to "3".

When the count value becomes "3", the first
Since the comparison results in the second and third comparators 707 and 708 are different from those before, the operation of the up / down counter 713 differs. In this case, the first selector 705
From D ₃ is output, D ₄ from the second selector 706 are output, each output of the corresponding comparator 707, 708 "1", it becomes "0". That is, the output of the first comparator 707 changes, and “0” is input to the count-down terminal of the up / down counter 713, which has been input “1”. Thus, the up / down counter 713 does not perform any of the count-up / count-down operations, and holds the count value “3”.

The count value of the up / down counter 713 is output from a terminal 721. At this time, the detector 717 detects that the outputs of the first and second comparators 707 and 708 have become “1” and “0”, respectively,
19 is output as "1". That is, the completion of the selection process of the optimum value of the k parameter is notified to the outside.

As described above, in the up / down counter 713, "0", "10"
In any case, it is understood that the same result is obtained as the optimum k parameter because the count value finally converges to the same count value. Of course, the same result is obtained even when an initial value other than “0” and “10” is set.

If the initial value is limited to "0", the up / down counter 713 does not require a countdown operation, and can be replaced with a simple up counter. Similarly, if the initial value is limited to "10", the count-up operation is not required, and can be replaced with a down-counter.

The encoding parameter selection unit 105 derives an optimal k parameter by performing the above-described processing, and the variable-length encoding unit 106, which has already been described, performs an encoding process based on the k parameter. Execute.
The encoded data is transmitted to the next bit plane scanning unit 1
07.

In the bit plane scanning unit 107,
It receives coded data that has been coded and output for each quantization value, rearranges the coded data on a bit-plane basis, and outputs it. This is performed for each frequency component (sub-block) described above.

First, the coded data generated by the variable length coding section 106 is separated into a fixed length code portion and a variable length code portion determined by the value of the k parameter. In addition, the sign includes a negative sign bit fixed at 1 bit.

Then, scanning is started from important information.
First, the negative bit is scanned for all the quantized values in the sub-block. Next, a variable length code portion having information on upper bits of the quantized value is sequentially scanned from the upper bit plane. Finally, the fixed length code portion is scanned in order from the upper bit plane.

FIG. 5 shows a Golomb-Rice code (in which the variable-length code portion and the fixed-length code portion are separated) for each quantized value generated when the k parameter is 2 in this embodiment, and its 4 shows an example of a scanning order. Hereinafter, the scanning of the variable-length code portion will be described in more detail with reference to FIG. Since the code length of the variable length code is not constant, it is not uniquely determined how the short code and the long code are aligned. Therefore, in the present embodiment, it is assumed that the first bits of the variable length codes are arranged in the same plane. That is, the variable length codes are arranged so as to be filled in order from the top of the variable length code area shown in FIG. When the bit plane information is scanned in order from the upper bits, information (code bits) is lost from an intermediate plane in a short code, so that a scan with a code without information is skipped. Therefore, the information (code bits) to be scanned decreases as going to lower bit planes.

FIG. 6 shows an arrangement of bit information obtained by scanning the code shown in FIG. 5 in the above order (negative bit, variable length code, fixed length code).

In the bit plane scanning unit 107,
Such a bit plane scan is performed in L
L, HL3, LH3, HH3, HL2, LH2, HH
2, HL1, LH1, and HH1.

The bit string output from the bit plane scanning unit 107 is sequentially transferred to the code output unit 109 at the next stage. The transfer destination may be a recording medium such as a hard disk or a DVD, or may be an interface such as the Internet, a general public line, or a wireless line.

The coded data generated in this embodiment includes various information required at the time of decoding, that is,
The image size, the number of bits per pixel, the quantization step for each frequency component, the value of the k parameter, and the like are appropriately added as additional information.

As described above, according to the present embodiment,
When the image data sequence is subjected to Golomb-Rice encoding based on the parameter k, the optimal value of k can be increased at a high speed by sequentially comparing the difference value of the variable length code amount for each k with a predetermined value with a simple configuration. Can be determined.

[Modification of First Embodiment] As a configuration of the encoding parameter selection unit 105 shown in the first embodiment, a configuration shown in FIG. 8 can be considered. This configuration corresponds to the subtractor group (704a) shown in FIGS. 7A and 7B in the first embodiment.
704 j) and the arrangement of the selector groups (705, 706) are interchanged, so that ten subtractors 704
a to 704j are reduced to two (804, 805).

That is, the selectors 801 to 803 shown in FIG.
, The output S ₀ to S ₁₀ of accumulator 703a~703k directly inputted. Then, from each selector, the count value P of the up / down counter 713 is given by S
_p-1 , _Sp , and _{Sp + 1} are output. These are subtractors 80
By being input to 4,805, from the subtractor 804 D _p is obtained as _{S p-1 -S p, D} p + 1 is obtained as S _p -S _{p + 1} from the subtractor 805.

Thereafter, by operating in the same manner as in the first embodiment, the optimum value of the k parameter can be obtained.

<Second Embodiment> Hereinafter, a second embodiment according to the present invention will be described.
An embodiment will be described. The configuration of the encoding device according to the second embodiment is the same as that of FIG. 1 described above.

FIG. 9 shows a detailed configuration of the coding parameter selection unit 105 in the second embodiment. In the figure,
Components performing the same operations as those in the first embodiment described above with reference to FIGS. 7A and 7B are denoted by the same reference numerals, and description thereof will be omitted.

[0098] In the first embodiment described above, to determine the D _p and D _{p + 1,} which is a difference value of the variable-length code amount, although the configuration using a subtractor (704a~704j),
The second embodiment is characterized in that an adder is used. The method of obtaining D _p and D _{p + 1} by the addition operation is shown in the above-mentioned equation (7).

D _p = S _p−1 −S _p = (2 × S _p + B _p ) −S _p = S _p + B _p (p ≧ 1) (7) In order to apply this equation (7) Is the number of “1” s in each bit plane of the input quantization value (B ₁ , B ₂ , B ₃ ,.
·· B _10, B ₁₁₎ is a counter for counting the need.

In FIG. 9, 901a, 901b, 90
, 901j are a group of counters for counting the number of "1" in each bit plane of the input quantization value. Reference numerals 902 and 903 denote the up-down counter 7
13 is a selector for selecting and outputting S _p and S _{p + 1 in accordance} with the count value P of the counter 13, and 904 and 905 are B _p and B _{p + 1} corresponding to the count value P of the up / down counter 713.
This is a selector for selecting and outputting. 906,907
It is an adder which adds S _p and B _p, and S _{p + 1} and B _{p + 1,} respectively.

After D _p and D _{p + 1} are obtained by the configuration shown in FIG. 9, the processing is performed by the same configuration as the selectors 705 and 706 shown in FIG. 7B in the first embodiment.

When all the quantized values in the sub-block have been input, the accumulators 703a to 703k, the counter 901
is _{S 0 ~S 10, B 1 ~B} 10 respectively output from A～901j, is input to the selector 902 to 905. Note that “0” is input to the selector 904 instead of the value of B ₀ corresponding to P = 0.

Count value of up / down counter 713
In response to P, selector 902 _pTo the selector 90
3 is S_{p + 1}And the selector 904 sets B_pTo the selector 905
Is B_{p +1}Select and output.

These are added by adders 906 and 907, and S _p + B _p (= D _p ) from adder 906 and S _{p + 1} + B _{p + 1} (= D _{p +} ) from adder 907. ₁ ) is output. When P = 0, D _{0 is set} as S ₀ + 0 = S ₀ (≧
N) is output.

As described above, since the difference values D _p and D _{p + 1 of the} variable length code amounts input to the comparators 707 and 708 are completely the same as the configuration shown in FIG. 7B of the first embodiment, By the same operation as in the first embodiment, the optimum value of the k parameter can be finally output.

In the configuration shown in FIG. 9, accumulator 703a for obtaining S ₀ may be omitted, and predetermined value N may be input to selector 902 instead of S ₀ .

As described above, according to the second embodiment, the optimum value of the parameter k can be determined at high speed even with a simple configuration as shown in FIG.

<Third Embodiment> Hereinafter, a third embodiment according to the present invention will be described.
An embodiment will be described. The configuration of the encoding device according to the third embodiment is the same as that of FIG. 1 described above.

In the above-described first and second embodiments, the description has been given of the configuration in which the processing for obtaining the optimum value of the k parameter is started after all the quantization values in the sub-block have been input. Therefore, it takes several clocks to obtain the optimal value of the k parameter, and the processing of the next sub-block cannot be started immediately.

Therefore, the third embodiment is characterized in that a process for obtaining the optimum value of the k parameter is started before all the quantization values in the sub-block have been input.

In the third embodiment, the following property regarding the k parameter is used.

"The optimal k parameter is greatly affected by the next input quantization value while the number of input quantization values is small, but when the number of input quantization values increases,
For example, assuming that the number of all quantized values in a sub-block is 50, the value of the k parameter is originally obtained after all 50 quantized values are input. Should be done. In the third embodiment, for example, when 40 quantized values are input, it is interpreted that all the quantized values have been input, and k
The processing for obtaining the optimum value of the parameter is started. Therefore,
During this process, the quantization values are input one after another. However, since the process of obtaining the optimum value of the k parameter is always performed based on the updated latest information, the value of the k parameter converges toward the latest information.

For example, k for 49 quantized value inputs
Even if there is one difference between the optimal value of the parameter and the optimal value for the input of 50 quantized values, it can be followed in one clock, so that virtually all the quantized values have been input at the same time. The optimal value of the k parameter is obtained.

FIGS. 7A and 7C show a detailed configuration of the coding parameter selection unit 105 in the third embodiment. In FIG. 7C, components that perform the same operations as those in the configuration in FIG. 7B described in the first embodiment described above are given the same reference numerals, and descriptions thereof will be omitted.

Coding Parameter Selection Unit 1 of Third Embodiment
In FIG. 05, in order to realize the processing described above, FIG.
In addition to the configurations shown in A and B, a second counter 750 for counting the number of input quantization values is provided. Then, the value of the second counter 750 is input to the terminal 709 instead of “N”, and the value of the
Each time a quantization value is input, the count value of the up / down counter 713 is controlled so as to approach the optimum value of the k parameter at that time.

There are various possible timings for releasing the holding of the initial value of the up / down counter 713 and proceeding to the above processing. In the example described above, the holding of the initial value is released when there are 40 inputs for all 50 quantized values. For example, if the holding of the initial value is released when there are 32 inputs, the added second
The holding of the initial value may be released at the timing when the signal of the 6th bit of the counter becomes "1", and simpler control becomes possible.

More simply, the initial value is not held at all, and at the timing when the first quantized value is input, k
The processing for obtaining the optimum value of the parameter may be started. It is also possible to omit the setting of the initial value.

As described above, according to the third embodiment, since the transition to the processing of the next sub-block is performed promptly, the optimum value of the parameter k can be determined more quickly.

The control described in the third embodiment is similar to the control shown in FIG.
Not only the configuration shown in FIG. 1 but also each embodiment described later can be applied as long as the configuration uses an up-down counter.

<Fourth Embodiment> Hereinafter, a fourth embodiment according to the present invention will be described.
An embodiment will be described. The configuration of the encoding device according to the fourth embodiment is the same as that of FIG. 1 described above.

FIGS. 7A and 10 show the detailed configuration of the coding parameter selection unit 105 in the fourth embodiment. In FIG. 10, the same operations as those in the configuration in FIG. 7B described in the first embodiment described above are denoted by the same reference numerals, and description thereof will be omitted.

In the first to third embodiments described above, the configuration in which two comparators (707, 708) are used in the encoding parameter selection unit 105 has been described.
The embodiment is characterized in that only the comparator 707 is provided. Accordingly, only one selector 705 is provided.

In the configuration having two comparators, the first
As described in detail in the embodiment, the two comparators output the same value until the k parameter converges to the optimum value. When the two parameters converge, one output of the comparator is “1” and the other output is “1”. Becomes “0”. Therefore, it can be seen that just before the convergence, only one comparator sufficiently functions.

However, when one comparator is used, a convergence state cannot be maintained by the same method as in the first to third embodiments. Therefore, a method for determining the optimum value in the fourth embodiment will be described below.

In FIG. 10, reference numeral 1001 denotes an up / down counter having the same count-up control terminal and down-count control terminal; 1003, a 1-bit D-type flip-flop (hereinafter, referred to as D-FF);
5 is an exclusive OR element (hereinafter, referred to as EXOR), 1
007 is a register.

In the fourth embodiment, the number N of quantized values in the sub-block is input to the terminal 709, and the initial value of the up / down counter 1001 is set to 0. And N
After inputting all the quantized values, the process of obtaining the optimum value of the k parameter is started. Also, as in the description of the first embodiment, it is assumed that D ₁ ≧ D ₂ ≧ D ₃ ≧ N> D ₄ ≧ D ₅ ≧.

The value of the up / down counter 1001 is
705. In the selector 705, the count
In response to the value “0”, N
To D ₀Output as

The output value D ₀ from the selector 705 is compared with a predetermined value N in a comparator 707, where D ₀ = N
Therefore, the comparator 707 outputs “1”.

The output of the comparator 707 is a 1-bit DF
F1003 and up-down counter 1
001 is input to the count control terminal. The up / down counter 1001 enters a count-up mode by a control signal “1”, and the count value S increases from “0” to “1” based on a clock input (not shown).

[0130] In the count value = 1, D ₁ is output from the selector 705. Here, since D ₁ ≧ N, the count value is “1” as in the case of D ₀ described above.
To "2". Also, the count value = 2,3
Similarly, the count value further increases from "2" to "3" and from "3" to "4".

On the other hand, the count value S is also stored in the register 1007.
Is input, and the count value is captured and output in synchronization with the clock input. For example, when the count value is “4”
At this point, the register 1007 outputs “3” to the terminal 721 and “4” has been input.

At this time (count value S = 4), the selector 7
Since D ₄ output from 05 satisfies D ₄ <N, the output of the comparator 707 which has been “1” is changed to “0”. Then, the EXOR 1005 detects this change and sends a control signal “1” to the register 1007 to keep the output data.

When the output of the comparator 707 changes to "0", the up / down counter 1001 changes to a countdown mode, and counts down from "4" to "3" based on a clock input (not shown). . Further, the output of the D-FF 1003 becomes “0”.

When the count value of the up / down counter 1001 returns to “3”, the output of the comparator 707 also returns to “1”. However, the output of EXOR 1005 remains unchanged at "1".
Remains. As a result, the output of the register 1007 is also kept at “3”.

Then, the up / down counter 1001
The mode changes to the count-up mode again, and counts up from "3" to "4" by the clock input. In the subsequent count values, “3” and “4” alternately change.

FIG. 11 is a timing chart for the configuration shown in FIG. 10 described above. In FIG.
Indicates the count value S, (b) indicates the output of the comparator 707, (c) indicates the output of the EXOR 1005, and (d) indicates the output of the register 1007.

According to FIG. 11, after the cycle in which the output of the comparator 707 first becomes "0", the output of the EXOR 1005 becomes "1" and the output value of the register 1007 is held at "3". I understand.

As described above, according to the configuration shown in FIG. 10, when the terminal 719, which is the output of the EXOR 1005, becomes "1", the optimum value of the k parameter is determined. Output terminal 721
Is obtained.

As described above, according to the fourth embodiment, the optimum value of the parameter k is determined at high speed by a simpler configuration having only one selector and comparator as shown in FIG. be able to.

<Fifth Embodiment> Hereinafter, a fifth embodiment according to the present invention will be described.
An embodiment will be described. The configuration of the encoding device according to the fifth embodiment is the same as that of FIG. 1 described above.

In the above-described fourth embodiment, an example in which the initial value of the up / down counter 1001 is set to “0” has been described. However, in the fifth embodiment, the initial value of the up / down counter is set to the maximum candidate of the k parameter. It is characterized in that the value is set to "10".

FIGS. 7A and 12 show a detailed configuration of the coding parameter selection unit 105 in the fifth embodiment. 12, the same operations as those in the configuration of FIG. 10 shown in the above-described fourth embodiment are denoted by the same reference numerals, and description thereof will be omitted.

In FIG. 12, reference numeral 1201 denotes a 1-bit D-type flip-flop having a reset function (hereinafter referred to as DF).
F) 1203 is a two-input logical sum element (hereinafter, referred to as F).
A register 1205 receives input data when the control signal is "1" and holds data being output when the control signal is "0".

Also in the fifth embodiment, the number N of the quantized values in the sub-block is input to the terminal 709, and after all the N quantized values are input, the processing for obtaining the optimum value of the k parameter is started. I do. Further, as in the fourth embodiment, D ₁ ≧
It is assumed that D ₂ ≧ D ₃ ≧ N> D ₄ ≧ D ₅ ≧.

In the configuration shown in FIG. 12, the up / down counter 1001 is initialized to "10" as described above, and in response to the initialization, the D-FF 1201 is reset to "0" by a control signal (not shown). Is done.

[0146] The initial value of the up-down counter 1001 "10" is sent to the selector 705, D ₁₀ is outputted corresponding to the initial value from the selector 705.

The output value D ₁₀ of the selector 705 is
At 07, the value is compared with a predetermined value N. Since D ₁₀ <N, the comparator 707 outputs “0”.

The output of the comparator 707 is input to the OR 1203 and the up / down counter 1001 and is also supplied to the register 1205 as a control signal. When the control signal is “0”, the register 1205 does not take in the count value S (input data) sent from the up / down counter 1001 and keeps holding the value held before that. The output of the OR 1203 remains "0", and the same "0" as its own output is input to the D-FF 1201, and the D-FF 1201 keeps outputting "0" even in the next cycle.

On the other hand, the up / down counter 1001
By the control signal “0” input from the comparator 707,
In the countdown mode, the countdown is performed from “10” to “9” by a clock input (not shown).

When the count value = 9, the selector 70
5 outputs D ₉ . Here, since D ₉ <N,
As with the D ₁₀ as described above, the count value is down to "8" to "9". Count value = 8, 7, 6, 5,
Similarly, in the case of No. 4, the countdown is continued until the count value becomes "3". Meanwhile, register 1205, D
-The output of the FF 1201 does not change.

When the count value of the up / down counter 1001 becomes "3", the output of the comparator 707 becomes "1" for the first time. The comparison result is input to the OR 1203 and the up / down counter 1001 and the register 1
205 is provided as a control signal. As a result, OR1
The output of 203 becomes “1” and the up / down counter 1
001 is a count-up mode. The output of the D-FF 1201 changes from “0” to “1” by a clock input (not shown), and the counter counts up to “4”. On the other hand, the register 1205 stores the value of the comparator 7
The count value “3” is fetched and output using the comparison result “1” from 07 as a control signal.

When the count value of the up / down counter 1001 returns to "4", the output of the comparator 707 also returns to "0". As a result, the up / down counter 1001 returns to the countdown mode, and “4” is input by the clock input.
Counts down to "3". On the other hand, register 1
Since 205 is in the holding state, “3” is continuously output. The output of the OR 1203 remains “1” as before, and the output of the D-FF 1201 is also maintained at “1”.

When the count value of the up / down counter 1001 becomes "3" again, the output of the comparator 707 also changes to "1" again. As a result, the up / down counter 1001 enters the count-up mode again, and counts up from “3” to “4” by the clock input. At this time, since the register 1205 takes in the same value as the value already held, there is no change in its output. Thereafter, the count value of the up / down counter 1001 alternates between “3” and “4”.

FIG. 13 is a timing chart for the configuration shown in FIG. In the figure, (a) is the count value, (b) is the output of the comparator 707, and (c) is the D-FF1.
201 shows the output of the register 1205.

According to FIG. 13, from the next cycle after the cycle in which the output of the comparator 707 first becomes "1", D-
The output of the FF 1201 becomes “1” and the register 1205
It can be seen that the output value of is maintained at "3".

As described above, according to the configuration shown in FIG. 12, when the terminal 719, which is the output of the D-FF 1201, becomes "1", the optimum value of the k parameter is determined, and the value is stored in the register. Terminal 721 which is the output of 1205
Is obtained.

As described above, according to the fifth embodiment, the optimal value of the parameter k can be determined at high speed while limiting the maximum candidate value of the k parameter by the initial value of the up / down counter.

<Sixth Embodiment> Hereinafter, a sixth embodiment according to the present invention will be described.
An embodiment will be described. The configuration of the encoding device according to the sixth embodiment is the same as that of FIG. 1 described above.

In the first to fifth embodiments described above, the configuration using the up / down counter is shown. The sixth embodiment is characterized in that a down counter having no count-up mode is used.
That is, the initial value of the down counter is set to the maximum candidate value “10” of the k parameter, and while counting down to “0”, the optimum value of the k parameter is detected.

FIGS. 7A and 14 show the detailed configuration of the coding parameter selection unit 105 in the sixth embodiment. 14, the same operations as those in the configuration in FIG. 12 described in the fifth embodiment described above are denoted by the same reference numerals, and description thereof will be omitted.

In FIG. 14, reference numeral 1401 denotes a down counter for performing only countdown, and 1403 denotes a register 1
This is a detector that generates a control signal for causing the count value of the down counter 1401 to be taken into the 205.

Also in the sixth embodiment, the number N of the quantized values in the sub-block is input to the terminal 709, and after all the N quantized values are input, the processing for obtaining the optimum value of the k parameter is started. I do. Further, as in the fifth embodiment, D ₁ ≧
It is assumed that D ₂ ≧ D ₃ ≧ N> D ₄ ≧ D ₅ ≧.

As in the fifth embodiment, the down counter 1401 is first initialized to "10" and continues to count down until the count value becomes "3".

When the count value of down counter 1401 becomes "3", the output of comparator 707 becomes "1" for the first time. Then, the comparison result “1” and the output “0” of the D-FF 1201 are detected by the detector 1403, and the detection result “1” is provided to the register 1205 as a control signal.

The register 1205 receives the control signal “1” as a load (register fetch) signal, fetches the count value “3”, and outputs it.

The down counter 1401 includes a comparator 707
While the control signal is "0", the countdown operation is performed, but when the count value becomes "3", the comparator 70
The output of 7 changes to "1" and the counting operation is stopped.
Therefore, the count value is fixed at “3”.

In the first cycle in which the count value becomes "3", the output of the detector 1403 becomes "1", but from the next cycle, the input / output signal of the D-FF 1201 (2 to the detector 1403). Since both input signals are “1”, the output of the detector 1403 thereafter becomes “0”.

Therefore, the output of the register 1205 is also "3".
And output to the terminal 721 as the optimum value of the k parameter.

FIG. 15 is a timing chart for the configuration shown in FIG. In the figure, (a) is the count value, (b) is the output of the comparator 707, and (c) is the D-FF1.
201 output, (d) is a control signal to the register 1205,
(E) shows the output of the register 1205.

According to FIG. 15, when the output of the D-FF 1201 changes from “0” to “1”, the register 1
It is clear that the output of 205 is determined.

In the fifth embodiment described above, FIG.
As shown in FIG. 12, when the output of the comparator 707 becomes "1" even once, the D-FF 1201 holds the output, that is, a two-input OR element (see FIG. By providing the EXOR 1203), it is not necessary to keep the count value of the down counter 1401 at “3”, and the countdown may be continued. In this case, a control signal from the comparator 707 to the down counter 1401 becomes unnecessary.

As described above, according to the sixth embodiment, the optimum value of the parameter k can be determined at high speed even with the configuration using the down counter.

<Seventh Embodiment> Hereinafter, a seventh embodiment according to the present invention will be described.
An embodiment will be described. The configuration of the encoding device according to the seventh embodiment is the same as that of FIG. 1 described above.

In the first to sixth embodiments described above, one or two sets of selectors and comparators for comparing the selector output with a predetermined value are used. The seventh embodiment is characterized in that three sets of the selector and the comparator are provided. In the seventh embodiment, the search for the optimum value of the k parameter can be performed at higher speed by increasing the number of pairs of selectors and comparators.

FIGS. 7A and 16 show a detailed configuration of the coding parameter selection unit 105 in the seventh embodiment. In FIG. 16, the same operations as those in the configuration in FIG. 7B described in the first embodiment described above are denoted by the same reference numerals, and description thereof will be omitted.

In FIG. 16, reference numeral 1603 denotes a third selector, 1605 denotes a third comparator for comparing the output value of the third selector 1603 with a predetermined value N, and 1607 denotes a signal from the up / down counter 713 shown in FIG. This is an up / down counter from which the lower one bit has been deleted.

In the seventh embodiment, as the count values of the up / down counter 1607, it is necessary to recognize two logical values L and physical values P in a relationship of L = P × 2. . That is, the logical value L is limited to an even number. In the count-up or count-down operation of the up / down counter 1607, physically, +1, -1
Is logically interpreted as being +2, -2. Other basic operations are the same as those of the first embodiment.

First to third selectors 705, 706,
1603 selects and outputs D _L , D _{L + 1} , and D _{L + 2} for the logical value L of the up / down counter 1607.

In the seventh embodiment, when the output of the first comparator 707 becomes "1" and the output of the third comparator 1605 becomes "0", the operation of the up / down counter 1607 stops, and k The optimal value of the parameter is determined. If the logical value of the up / down counter 1607 at this time is T, k
The optimum value of the parameter is T or T + 1.

In the seventh embodiment, when the optimum value of the k parameter is determined, two states are considered: the case where the output of the second comparator 708 is “0” and the case where the output is “1”. .

The former is the same state as in the first embodiment described above, and the logical value T of the up / down counter 1607 is the optimum value of the k parameter. In this former state, only an even number can be taken as the k parameter. However, in the other case, the latter, it takes an odd number as the k parameter.

In the latter case, that is, when the output of the second comparator 708 is “1”, control is performed so that the up / down counter 713 counts up in the first embodiment. This means that the optimum value of the k parameter is larger than the logical value of the up / down counter 713. Therefore, in the seventh embodiment, if the logical value of the up / down counter 1607 is T,
It is determined that the optimal value of the k parameter is T + 1.

In the seventh embodiment, by adding the output of the second comparator 706 to the least significant bit of the physical count value P output from the up / down counter 1607, the optimum value of the k parameter can be obtained. Generate a T + 1 value. The method of generating the optimum value is similarly applied to the former case, that is, the case where the output of the second comparator 708 is “0”.

As described above, in the configuration shown in FIG. 16, although the number of sets of selectors and comparators is increased as compared with the configuration of FIG. 7B shown in the first embodiment, the output value of the selector is Since the types are halved, the circuit scale of each selector can be reduced to nearly half.
Further, the number of bits of the up / down counter 1607 is also reduced by one bit. Therefore, although the circuit scale seems to increase due to the increase in the number of components, the size of each component is actually reduced, and the search time (number of cycles) for the optimum value of the k parameter is reduced to almost half. can do.

As described above, according to the seventh embodiment, it is possible to determine the optimum value of the parameter k more quickly while reducing the circuit scale comprehensively.

<Eighth Embodiment> Hereinafter, an eighth embodiment according to the present invention will be described.
An embodiment will be described. The configuration of the encoding device according to the eighth embodiment is the same as that of FIG. 1 described above.

In the above-described seventh embodiment, a configuration in which three sets of selectors and comparators are provided has been described. In the eighth embodiment, the number of sets is increased to five to search for the optimum value of the k parameter. Is performed at a higher speed.

FIGS. 7A and 17 show a detailed configuration of the coding parameter selection unit 105 in the eighth embodiment. In FIG. 17, the same operations as those in the configuration of FIG. 16 described in the seventh embodiment described above are denoted by the same reference numerals, and description thereof will be omitted.

In FIG. 17, reference numeral 1704 denotes a fourth selector, 1705 denotes a fifth selector, 1707 denotes a fourth comparator for comparing the output value of the fourth selector 1704 with a predetermined value N, and 1708 denotes a fifth selector. A fifth comparator for comparing the output value of 1705 with a predetermined value N. FIG.
This is an up / down counter obtained by further removing the least significant bit from the up / down counter 1607 shown in FIG. 6, that is, two bits less than the up / down counter 713 shown in FIG. 7B in the first embodiment. Reference numeral 1713 denotes an encoder that encodes the outputs of the second, third, and fourth comparators 708, 1605, and 1707 into 2-bit signals.

Also in the eighth embodiment, as the count values of the up / down counter 1711, it is necessary to recognize two logical values L and physical values P in a relationship of L = P × 4. . That is, the logical value L is limited to a multiple of four. In the count-up or count-down operation of the up / down counter 1711, physically +1,
Although -1 is performed, this is logically interpreted as being +4, -4. Other basic operations are the same as in the above-described seventh embodiment.

The first to fifth selectors 705, 706,
Reference numerals 1603, 1704, and 1705 denote D _L and D with respect to the logical value L of the up / down counter 1711, respectively.
_{L + 1} , _{DL + 2} , _{DL + 3} and _{DL + 4} are selected and output.

In the eighth embodiment, when the output of the first comparator 707 becomes "1" and the output of the fifth comparator 1708 becomes "0", the operation of the up / down counter 1711 stops, and k The optimal value of the parameter is determined. If the logical value of the up / down counter 1711 at this time is T, k
The optimal value of the parameter is T, T + 1, T + 2 or T
+3.

In the eighth embodiment, when the optimum value of the k parameter is determined, the second to fourth comparators 708, 1
As a combination of the outputs of 605 and 1707, "00"
There are four possible states of “0”, “100”, “110”, and “111”, where “ABC” indicates that the outputs of the second to fourth comparators 708, 1605, and 1707 are “A”, respectively. , “B”, and “C”.

The above four states correspond to the four k parameter values (T, T + 1, T + 2, T + 3) described above. Therefore, in the encoder 1713, the above four states are respectively set to “00”, “01”, “10”, “11”.
An optimal value of the k parameter can be generated by encoding into a 2-bit code and adding the lower 2 bits to the physical count value P output from the up / down counter 1711.

As described above, according to the eighth embodiment, the optimum value of the parameter k is searched for twice as fast as in the seventh embodiment and about four times as fast as in the first embodiment. can do. If the number of selectors and comparators is further increased, a higher-speed search can be performed.

<Ninth Embodiment> Hereinafter, a ninth embodiment according to the present invention will be described.
An embodiment will be described. The configuration of the encoding device according to the ninth embodiment is the same as that of FIG. 1 described above.

FIGS. 7A and 18 show the detailed configuration of the coding parameter selection unit 105 in the ninth embodiment. In FIG. 18, the same operations as those in the configuration in FIG. 7B described in the first embodiment described above are denoted by the same reference numerals, and description thereof will be omitted.

In the seventh and eighth embodiments described above, the configuration in which the suffix of the D parameter (the difference value of the variable length code amount) output from the selector is continuous has been described. In the ninth embodiment, a configuration in which the subscripts of the D parameter are not continuous will be described. In the ninth embodiment, four sets of selectors and comparators are used.
Are characteristic.

In FIG. 18, reference numeral 1803 denotes a third selector, 1804 denotes a fourth selector, 1805 denotes a third comparator for comparing the output value of the third selector 1803 with a predetermined value N, and 1806 denotes a fourth selector. Is a fourth comparator for comparing the output value of the second comparator with a predetermined value N. 1807 is the third comparator 1
An inverter 805 inverts the output signal, and 1809 is a multi-mode up / down counter having a plurality of count modes.

Third and fourth selectors 1803, 180
4 selects and outputs D _T−2 and D _{T + 3} with respect to the count value T of the up / down counter 1809. The first and second selectors 705 and 706 correspond to the first selector 705 described above.
As in the embodiment, _DT and _{DT + 1} are selected and output. The control of the up / down counter 1809 based on the outputs of the first and second comparators 707 and 708 is also performed by the first control described above.
This is the same as the embodiment.

In the ninth embodiment, the count value of the up / down counter 1809 at the time when the output of the first comparator 707 becomes “1” and the output of the second comparator 708 becomes “0” is the k parameter Is determined as the optimal value of.

Here, when the output of the third comparator 1805 is “0”, since D _T−2 <N, the optimal value of the k parameter is 3 times larger than the current count value T of the up / down counter 1809. It turns out that it is smaller than one.

On the other hand, when the output of the fourth comparator 1806 is “1”, since D _{T + 3} ≧ N, the optimal value of the k parameter is three more than the current count value T of the up / down counter 1809. It turns out that it is large above.

Therefore, in the ninth embodiment, when the output of the third comparator 1805 is “0”, the count value of the up / down counter 1809 is set to −4, and the output of the fourth comparator 1806 is set to “1”. "", The count value of the up / down counter 1809 is controlled to be +4. As described above, when the count value is controlled to be ± 4, it is conceivable that the count value may be increased or decreased by one extra. In such a case, the first and second comparators 707 and 70 may be used.
The count value of the up-down counter 1809 is controlled to be returned by one based on the output of No. 8 to determine the count value.

In the ninth embodiment, first, the up / down counter 1809 is controlled by ± 4, and the finer parts are further controlled by ± 1, so that the count value converges to the optimum value of the k parameter at high speed. Let it.

FIG. 19 shows four comparators 18 shown in FIG.
05, 707, 708, 1806 output signals (a) to
The count amount (e) of the up / down counter 1809 with respect to (d) is shown. As shown in the figure, the count amount of the up / down counter 1809 is controlled according to the output of each comparator. FIG. 19 shows only an example of the counter control. For example, it is also effective to set the count amount to +3, -3 or +5, -5 instead of +4, -4.

The configuration shown in FIG. 18 in the ninth embodiment is not limited to the four pairs of selectors and comparators, but is applicable to the case where three or five or more pairs of selectors and comparators are used. Easy to apply.

As described above, according to the ninth embodiment, the optimum value of the parameter k can be determined more quickly by controlling the count amount of the up / down counter.

[0209]

[Other Embodiments] Even if the present invention is applied to a system including a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), an apparatus (for example, a copying machine) Machine, facsimile machine, etc.).

Further, an object of the present invention is to supply a storage medium (or a recording medium) on which a program code of software for realizing the functions of the above-described embodiments is recorded to a system or an apparatus, and to provide a computer (a computer) of the system or the apparatus. It is needless to say that the present invention can also be achieved by a CPU or an MPU) reading and executing the program code stored in the storage medium. In this case, the program code itself read from the storage medium implements the functions of the above-described embodiment, and the storage medium storing the program code constitutes the present invention. Also,
When the computer executes the readout program code, not only the functions of the above-described embodiments are realized, but also the operating system (OS) running on the computer based on the instructions of the program code.
It goes without saying that a case where the functions of the above-described embodiments are implemented by performing some or all of the actual processing, and the processing performs the functions of the above-described embodiments.

Further, after the program code read from the storage medium is written in the memory provided in the function expansion card inserted into the computer or the function expansion unit connected to the computer, the program code is read based on the instruction of the program code. Needless to say, the CPU included in the function expansion card or the function expansion unit performs part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

[0212]

As described above, according to the present invention, a multi-valued image can be subjected to simple and high-speed variable-length coding.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an encoding device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a state of a discrete wavelet transform.

FIG. 3 is a diagram illustrating an example of a quantization step used for a frequency component (sub-block).

FIG. 4 is a diagram illustrating an example of a code obtained by Golomb-Rice encoding.

FIG. 5 is a diagram illustrating an example of a Golomb-Rice code for each bit plane in the embodiment.

FIG. 6 is a diagram illustrating an example of a bit stream that is finally output in the present embodiment.

FIG. 7A is a block diagram illustrating a detailed configuration of an encoding parameter selection unit according to the present embodiment.

FIG. 7B is a block diagram illustrating a detailed configuration of an encoding parameter selection unit according to the present embodiment.

FIG. 7C is a block diagram illustrating a detailed configuration of an encoding parameter selection unit according to the third embodiment.

FIG. 8 is a block diagram illustrating a detailed configuration of an encoding parameter selection unit according to a modification of the present embodiment.

FIG. 9 is a block diagram illustrating a detailed configuration of an encoding parameter selection unit according to the second embodiment.

FIG. 10 is a block diagram illustrating a detailed configuration of an encoding parameter selection unit according to a fourth embodiment.

FIG. 11 is a timing chart in the configuration shown in FIG. 10;

FIG. 12 is a block diagram illustrating a detailed configuration of an encoding parameter selection unit according to a fifth embodiment.

13 is a timing chart in the configuration shown in FIG.

FIG. 14 is a block diagram illustrating a detailed configuration of an encoding parameter selection unit according to a sixth embodiment.

FIG. 15 is a timing chart in the configuration shown in FIG. 14;

FIG. 16 is a block diagram illustrating a detailed configuration of an encoding parameter selection unit according to a seventh embodiment.

FIG. 17 is a block diagram illustrating a detailed configuration of a coding parameter selection unit according to an eighth embodiment.

FIG. 18 is a block diagram illustrating a detailed configuration of an encoding parameter selection unit according to a ninth embodiment.

FIG. 19 is a diagram illustrating a control example of an up-down counter according to the ninth embodiment.

[Explanation of symbols]

Reference Signs List 101 Image input unit 102 Data storage unit 103 Discrete wavelet transform unit 104 Coefficient quantization unit 105 Coding parameter selection unit 106 Variable length coding unit 107 Bit plane scanning unit 108 Buffer 109 Code output unit 702 Bit shifter group 703 Accumulator group 704 Subtractor group 705, 706, 902, 903, 904, 905, 1
603, 1704, 1705, 1803, 1804 Selectors 707, 708, 1605, 1707, 1708, 18
05, 1806 Comparators 713, 1001, 1607, 1711 Up / down counter 901 Counter group 906, 907 Adder 1205 Register 1401 Down counter 1809 Multi mode up / down counter

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5C059 KK03 KK11 MA24 ME01 ME13 PP01 UA02 UA39 5C078 AA04 BA21 CA31 DA01 DA02 DA06 DB00 5J064 AA03 BA09 BA16 BC01 BC03 BC05 BC08 BC14 BD02 9A001 EE04 GG17 HH27

Claims (18)

[Claims] 1. An encoding apparatus comprising encoding means for encoding a symbol group into a variable-length code portion and a fixed-length code portion based on parameters, wherein the variable-length code portion between adjacent parameters is encoded. A difference means for calculating a difference value of the code amount, a comparing means for comparing the difference value with a predetermined value, and generating a parameter to be applied to the encoding in the encoding means by performing a count based on the comparison result. An encoding device, comprising: 2. The encoding apparatus according to claim 1, wherein the parameter indicates a code length of the fixed-length code portion. 3. The encoding apparatus according to claim 2, wherein said encoding means performs Golomb-Rice encoding. 4. The encoding apparatus according to claim 1, wherein the symbol group corresponds to a sub-block obtained by performing a wavelet transform on multi-valued image data. 5. The encoding apparatus according to claim 1, wherein the predetermined value in the comparing means is the number of encoding target symbols in the symbol group. 6. The encoding apparatus according to claim 1, wherein the generation unit is a counter that counts up or down based on a comparison result of the comparison unit. 7. An accumulator for accumulating symbol groups in parallel for each bit plane to obtain a plurality of accumulated values, and performing subtraction in parallel between the plurality of accumulated values to obtain a plurality of the difference values. 2. The encoding device according to claim 1, further comprising: a subtraction unit that outputs. 8. The image processing apparatus according to claim 1, further comprising a selection unit that selects a specific difference value from the plurality of difference values based on the count value in the generation unit, wherein the comparison unit determines the difference value selected by the selection unit. 8. The method according to claim 7, wherein the predetermined value is compared with the predetermined value.
An encoding device according to claim 1. 9. The accumulating means for accumulating a plurality of symbol values in parallel for each bit plane to obtain a plurality of accumulated values, and a predetermined number of accumulative values from the plurality of accumulated values based on the count value in the generating means. 2. The encoding apparatus according to claim 1, further comprising: selecting means for selecting a specific accumulated value; and subtracting means for performing subtraction between the selected specific accumulated values and outputting the difference value. 10. The accumulation means for accumulating a symbol group for each bit plane, a counting means for counting the number of 1s for each bit plane of the symbol group, an accumulation value in the accumulation means and the counting means. 2. The encoding apparatus according to claim 1, further comprising: an adding unit that outputs the difference value by adding the count value of the encoding unit. 11. The apparatus according to claim 1, further comprising counting means for counting the number of symbols input to said difference means, wherein said comparison means sets the count value of said counting means to said predetermined value. Encoding device. 12. The apparatus according to claim 11, further comprising a storage unit configured to store the parameter generated by the generation unit based on a comparison result of the comparison unit, wherein the comparison unit includes a single comparator. 2. The encoding device according to 1. 13. The encoding apparatus according to claim 12, wherein the generation unit sets an initial value of a count based on the comparison result to a maximum candidate value of the parameter. 14. The encoding apparatus according to claim 13, wherein said generating means is a down counter that counts down based on a comparison result of said comparing means. 15. At least three sets of said selecting means and said comparing means are provided, wherein said generating means generates by deleting lower bits of said parameter, and compares said lower bits of said generated parameter with said comparing means. 9. The encoding apparatus according to claim 8, wherein a result is added and output. 16. The encoding apparatus according to claim 1, wherein said generation means is an up / down counter for controlling a count up or count down based on a comparison result of said comparison means. 17. An encoding method for encoding a symbol group into a variable length code portion and a fixed length code portion based on parameters, wherein a difference in code amount of the variable length code portion between adjacent parameters is provided. A difference step of calculating a value, a comparison step of comparing the difference value with a predetermined value, and a generation step of generating a parameter applied to the encoding by performing a count based on the comparison result. Characteristic encoding method. 18. A recording medium recording an encoding method program for encoding a symbol group into a variable-length code portion and a fixed-length code portion based on parameters, the program comprising at least an adjacent parameter A code of a difference step for calculating a difference value of the code amount of the variable-length code portion between the codes; a code of a comparison step of comparing the difference value with a predetermined value; and And a code for a generation step of generating a parameter to be applied to the conversion.