JP2001292064A - Analog/digital conversion circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an analog/digital conversion circuit of a successive approximation type that attains high-speed conversion while suppressing deterioration in the analog/digital conversion accuracy due to the effect of a decreased speed of a comparator. SOLUTION: The comparator compares an analog input voltage with an analog output voltage outputted from the digital/analog conversion circuit from the most significant bit toward the least significant bit and sets the comparison result to a corresponding bit of a successive approximation register in the analog/digital conversion circuit, which is provided with a control circuit that controls an analog/digital conversion period for at least the least significant bit to be longer than the conversion period of the other bits so as to increase the speed of the clock used for the conversion for the other bits.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an analog-to-digital converter, and more particularly to a successive approximation type analog-to-digital converter.

[0002]

2. Description of the Related Art An example of a conventional successive approximation type analog-to-digital (AD) conversion circuit will be described with reference to FIG.
The outline will be described. The input analog voltage Vi
n is supplied via an analog switch 1 to a comparator including a capacitor 2, an inverter 3 and an analog switch 4. Here, the analog switches 1 and 4 are turned on during a period when the conversion start signal CONV is at the Low level (that is, when the conversion operation is not being performed). The output voltage Vr of the DAC 5 that divides the reference voltage Vref and outputs the divided signal by the control signal from the control circuit 7 in the digital / analog conversion circuit 5 (DAC) via the analog switch 6 is input to this comparator. . Here, the analog switch 6 outputs the conversion start signal CONV
It turns on only during the High period (during the conversion operation).

The comparator compares the analog input voltage Vin with the output voltage Vr from the DAC 5, and sets the comparison result in the successive approximation register 8 from the most significant bit to the least significant bit. Note that the capacitor 2
The inverter 3 functions as a sample-and-hold capacitor, and compares the analog input voltage Vin with the output voltage Vr from the DAC 5 (whether or not the difference between Vin and Vr is greater than 0) by the inverter 3 and determines a comparison result signal. (Logic signal) is set. The analog switch 4 is turned off when the conversion start signal CONV is High (at the time of conversion operation),
Turns on when the conversion start signal CONV is Low, and resets the comparator (inverter 3). Inverter 3
May be configured as a comparator in which the non-inverting input terminal is grounded and the terminal of the capacitor 2 is connected to the inverting input terminal.

[0006] The timing of these comparison operations and the timing of storage in the successive approximation register 8 are controlled by a control circuit 7.

The operation of the AD conversion circuit shown in FIG. 1 will be described. FIG. 4 is a timing chart of the AD conversion operation in the AD conversion circuit. Here, before the start of the A / D conversion, that is, during a period in which the conversion start signal CONV is Low, the analog switches 1 and 4 are both in the off state, and the input voltage Vin is input to the comparator and held in the capacitor 2.

When the conversion start signal CONV becomes High, the output signal Vr from the DAC 5 is input to the comparator, and is compared with the input voltage Vin. At this time, D
The output voltage Vr of AC5 is Vr = (１ ／) Vref
(The voltage corresponding to the most significant bit “1” and all other bits “0”).

In the comparator, the input voltage Vin and the output voltage Vr of the DAC 5 are compared, and Vin> Vr
In this case, "1" is set to the most significant bit of the successive approximation register 8.

Thereafter, the output voltage Vr of the DAC 5 changes to Vr = (1/2) Vref + (1/4) Vref = (3/4) Vref according to a control signal (digital code) from the control circuit 7.

On the other hand, if the input voltage Vin <the output voltage Vr of the DAC, "0" is set to the most significant bit of the successive approximation register 8, and Vr = (1/2) Vref- (1/4) Vref = (1/4) Vref, and shifts to the AD conversion operation of the next bit.

Also in the AD conversion operation for the next bit, the magnitude of the input voltage Vin and the DAC output voltage Vr are compared, and the value of the successive approximation register 8 is determined.

As a result, the DAC output voltage Vr becomes
The voltage corresponding to (１ ／) Vref is increased or decreased with respect to the previous value.

By repeating such an operation up to the least significant bit, digital values corresponding to the input analog voltage Vin are sequentially determined.

[0013]

However, in a conventional successive approximation type A / D conversion circuit, in order to realize high-speed A / D conversion, a reference clock φ for defining a conversion operation is used.
When the frequency is increased, the conversion period of each bit is the same, and as the conversion proceeds to the lower bits, the difference between the input voltage Vin and the output voltage Vr of the DAC becomes smaller. The influence cannot be ignored and the AD conversion accuracy is reduced.

That is, in the conventional AD conversion circuit,
When the speed of the reference clock φ is increased, the difference between the input voltage Vin and the output voltage Vr of the DAC 5 becomes smaller as the conversion of the lower bit becomes smaller. Let me do it.

A due to a decrease in the comparison speed of the comparator
In order to avoid the influence on the D conversion accuracy, it is conceivable to increase the gain of the comparator. However, the A / D conversion accuracy deteriorates due to noise from outside the A / D conversion circuit and switching noise inside the A / D conversion circuit. Therefore, the gain of the comparator cannot be increased more than necessary.

For example, Japanese Utility Model Laid-Open Publication No. 56-56243 discloses a successive approximation type AD converter that successively compares each bit of a successive approximation register in synchronization with a clock pulse to obtain a digital signal corresponding to an analog input voltage. A counter for counting clock pulses, a frequency dividing circuit for dividing the clock to generate a plurality of clock pulse trains having different frequencies, and selectively selecting a plurality of clock pulse trains in relation to the count value of the counter. The successive approximation type AD converter is provided with a data selector for selecting and transmitting the data to the successive approximation register. The lower bit side of the successive approximation register performs successive approximation with a short-period clock pulse train. It has been disclosed. Japanese Patent Application Laid-Open No. 6-318870
Japanese Patent Application Laid-Open Publication No. H11-163873 discloses that in a successive approximation register, at least one bit operation is performed at least twice during a successive approximation processing period to be sequentially executed, or a generation interval of a timing control signal for controlling the successive approximation processing is set to a predetermined bit. After the successive approximation processing, an AD conversion circuit has been proposed in which the timing control means generates the signals at different occurrence intervals.

Accordingly, the present invention has been made in view of the above problems, and has as its object to provide a successive approximation type AD.
It is an object of the present invention to provide an AD conversion circuit capable of suppressing a decrease in AD conversion accuracy due to a decrease in the speed of a comparator and capable of high-speed conversion.

[0018]

According to the present invention, which achieves the above object, the present invention realizes high-speed AD conversion by extending the conversion period of the least significant bit to increase the speed of a reference clock for providing a conversion clock. Things. The present invention sequentially compares an analog input voltage from the most significant bit side to the least significant bit side with an analog output voltage output from a digital-to-analog conversion circuit using a comparator.
In the AD conversion circuit set to the corresponding bit of the successive approximation register, at least the least significant bit
A control circuit is provided to control the conversion period to be set longer than the conversion period of the other bits, so that the clock for controlling the AD conversion operation can be speeded up.

[0019]

Embodiments of the present invention will be described below. The present invention compares the input analog signal with a reference voltage to determine the most significant bit (MSB).
In the successive approximation type AD conversion circuit for sequentially determining the digital value from the least significant bit (LSB) to the least significant bit (LSB), by setting the conversion period of the least significant bit longer than the conversion period of the other bits, the input voltage and the This prevents a decrease in the AD conversion accuracy due to a decrease in the speed of the comparator caused by a decrease in the difference from the reference voltage, and realizes a high-accuracy and high-speed AD conversion circuit by increasing the speed of the reference clock.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. The basic configuration of the AD converter according to the embodiment of the present invention is the same as that of the successive approximation AD converter described with reference to FIG. That is, referring to FIG. 1, the input analog voltage Vin is supplied via an analog switch 1 to a comparator including a capacitor 2, an inverter 3 and an analog switch 4. here,
The analog switches 1 and 4 are turned on only while the conversion start signal CONV is Low.

On the other hand, a digital / analog conversion circuit 5 is connected to this comparator via an analog switch 6.
(DAC), the output voltage Vr of the DAC 5 that divides and outputs the reference voltage Vref according to the control signal from the control circuit 7 is input. Here, the analog switch 6 is turned on only during a period when the conversion start signal CONV is High.

The input voltage Vin and the output voltage Vr from the DAC 5 are compared by a comparator, and the result is set in the successive approximation register 8 from the most significant bit to the least significant bit.

The control circuit 7 controls these comparison operations and the timing of storing them in the successive approximation register.

Here, before the start of the AD conversion, that is, during the period when the conversion start signal CONV is Low, the analog switches 1 and 4 are both in the OFF state, the input voltage Vin is input to the comparator, and is held in the capacitor 2. Is done.

When the conversion start signal CONV becomes High, the output signal Vr from the DAC 5 is input to the comparator, and is compared with the input voltage Vin. At this time, D
The output voltage Vr of AC5 is Vr = (1/2) Vref.

In the comparator, the input voltage Vin is compared with the output voltage Vr of the DAC 5, and Vin> Vr
In this case, "1" is set to the most significant bit of the successive approximation register 8.

After that, the output voltage Vr of the DAC 5 is changed by the control circuit 7 to Vr = (）) Vref + (１ ／) Vref = (／) Vref.

On the other hand, if the input voltage Vin <the output voltage Vr of the DAC, "0" is set to the most significant bit of the successive approximation register 8, and Vr = (1/2) Vref- (1/4) Vref = (1/4) Vref, and shifts to the AD conversion operation of the next bit.

Also in the AD conversion operation for the next bit, the magnitude of the input voltage Vin and the output voltage Vr of the DAC 5 are compared, and the value of the successive approximation register 8 is determined.

According to the result, the output voltage Vr of the DAC 5 is obtained.
Is increased or decreased by (１ ／) Vref from the previous value.

By repeating such an operation from the most significant bit to the least significant bit (conversion periods T0 to T
n), digital values corresponding to the input analog voltage Vin are sequentially determined.

In one embodiment of the present invention, as shown in the timing chart of FIG. 3, the conversion period (Tn) of the least significant bit, in which the effect of the reduction in the speed of the comparator is remarkable, is shown. Period (T0 to Tn
By setting the value to twice the value of -1), a decrease in AD conversion accuracy is avoided. The voltage output of the corresponding bit from the DAC 5 and the comparison operation in the comparator and the setting of the comparison result in the successive approximation register 8 are performed in one cycle of the clock supplied from the control circuit 7.

FIG. 2 is a diagram showing a configuration of the control circuit 7 according to one embodiment of the present invention. In one embodiment of the present invention, as shown in FIG. 2, the control circuit 7 compares only the conversion period Tn between the input voltage Vin and the output voltage Vr of the least significant bit with that of the other bits by two bits. By using a control circuit that can be set to double, it is possible to realize an AD conversion circuit that can suppress a decrease in AD conversion accuracy due to a decrease in the speed of the comparator and minimize the decrease in the speed. That is, the control circuit 7 includes a frequency dividing circuit 72 for dividing the input reference clock.
The input of the output clock and the reference clock, the frequency-divided clock output from the frequency divider 72 is selected for the conversion of the least significant bit, and the DAC5 is selected based on the frequency-divided clock.
Control (output of digital code to DAC5, etc.)
And a control circuit 71 having a function of performing switching so as to control the successive approximation register 8.

In the above-described embodiment, the conversion period of the least significant bit is set to be twice to suppress the decrease in AD conversion accuracy. However, in order to further increase the speed of AD conversion, the frequency of the reference clock is changed. It is also effective to further extend the conversion period of the least significant bit in consideration of the effect of the decrease in the speed of the comparator in the case of raising, or to set the conversion period longer for the higher-order bits of the least significant bit. . It should be noted that the configuration of the successive approximation type AD conversion circuit shown in FIG. 1 is an example for explaining the present invention in an easy-to-understand manner, and the present invention is not limited to the configuration of FIG. Of course, the present invention can be applied to the configuration of any successive approximation type AD conversion circuit.

[0035]

As described above, according to the present invention, the following effects can be obtained.

The first effect of the present invention occurs because the difference between the input voltage Vin and the output voltage Vr of the DAC is reduced by setting the AD conversion period of the least significant bit longer than that of the other bits. That is, it is possible to suppress a decrease in AD conversion accuracy due to the influence of a decrease in the speed of the comparator.

A second effect of the present invention is that the first effect enables the conversion period other than the least significant bit to be shortened while maintaining the AD conversion accuracy. Therefore, the speed of the reference clock φ is increased. That is, a high-precision and high-speed AD conversion circuit can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a control circuit according to one embodiment of the present invention.

FIG. 3 is a timing chart for explaining the operation of one embodiment of the present invention.

FIG. 4 is a timing chart for explaining the operation of a conventional AD conversion circuit.

[Explanation of symbols]

 1, 4, 6 Analog switch 2 Capacitor 3 Inverter 5 DA converter 7 Control circuit 8 Successive comparison register

Claims (5)

[Claims] A comparator sequentially compares an analog input voltage with an analog output voltage output from a digital-to-analog conversion circuit from a most significant bit to a least significant bit by a comparator. An analog-to-digital conversion circuit that is set to a corresponding bit, comprising: a control circuit that controls at least the conversion period of the least significant bit to be longer than the conversion period of the other bits; An analog-to-digital conversion circuit, which is capable of responding to a high-speed clock for controlling a conversion operation. A control circuit for inputting a reference clock for controlling an A / D conversion operation, and performing the A / D conversion of the least significant bit, using a clock obtained by dividing the reference clock by a frequency dividing circuit; 2. The analog-digital conversion according to claim 1, wherein by controlling a register and the digital-analog conversion circuit, the conversion period of the least significant bit is set to be at least twice the clock cycle of the reference clock. circuit. 3. The conversion period of each bit from the least significant bit to a predetermined number of upper bits in addition to the least significant bit is longer than the conversion period of the remaining bits including the most significant bit. 3. The analog-to-digital conversion circuit according to claim 1, wherein the setting is performed. 4. A digital-to-analog conversion circuit that divides a reference voltage based on a digital code and outputs the divided voltage, a first switch that is turned on when a conversion start signal is inactive, and is turned on when the conversion start signal is active. And a second switch that switches the input analog signal voltage through the first switch.
An analog output voltage of the digital-to-analog conversion circuit is supplied to a comparator via the second switch, and a comparison result output from the comparator is stored in a corresponding bit of a successive approximation register. And a control circuit for controlling the digital-to-analog conversion circuit and controlling the timing of storing the data in the successive approximation register includes a frequency dividing circuit for dividing the reference clock, the least significant bit, or the least significant bit. At the time of conversion of each bit of a predetermined number of higher bits from the bit, the digital / analog conversion circuit and the successive approximation register use a clock obtained by dividing the reference clock by the frequency divider circuit as a clock for controlling a conversion period. During conversion of other bits, the reference clock is controlled during the conversion period. Used as a clock for the controls the successive approximation register and the digital-analog converter circuit is configured, the analog-digital converter, characterized in that. 5. An output of a voltage corresponding to a corresponding bit from the digital / analog conversion circuit, and a comparison operation in the comparator and a setting of a comparison result in the successive approximation register are performed by a clock for controlling the conversion period. 5. The analog-to-digital conversion circuit according to claim 1, wherein the conversion is performed in one cycle.