JP2001290608A - Disk controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a disk controller, which improves I/O performance, is immune to a power source fault and can be run easily. SOLUTION: Concerning a multiprocessor control disk array controller 10 having plural processors 19 and 21, a shared memory for storing the control information of the respective processors 19 and 20 is composed of a nonvolatile shared memory 15 and a volatile shared memory 16. Thus, high I/O performance can be provided by making the shared memory versatile. By providing a nonvolatile shared memory plane, the power source fault can be coped with as well. By making only a part of the shared memory into nonvolatile shared memory plane, difficulties in circuit configuration or cost are reduced and running is facilitated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk controller, and more particularly, to a disk controller which has high I / O performance, is resistant to power failure, and can be easily implemented.

[0002]

2. Description of the Related Art FIG. 8 is a block diagram showing an example of a conventional disk controller. The disk controller 1 includes a plurality of host interface units 2 each having a processor MP and interfacing with a host computer H, and a plurality of disk interfaces each including a processor MP and interfacing with a plurality of disk drives 3. A cache memory for temporarily storing data to be written to the disk drive;
(B), shared memories 6 (A) and 6 (B) for storing control information of each processor MP, a data common bus 7 and a control information common bus 8. The shared memory 6 (A)
Corresponds to the cache memory 5 (A) and stores information indicating which data is stored at which position on the cache memory 5 (A). The shared memory 6
(B) corresponds to the cache memory 5 (B) and stores information indicating which data is stored at which position on the cache memory 5 (B). Information such as the hardware configuration of the disk drive 3 is double-written in the shared memories 6 (A) and 6 (B). Further, these shared memories A side 6 (A), 6 (B) are backed up by a battery in case of power failure.

On the other hand, in the disk controller disclosed in Japanese Patent Application Laid-Open No. 10-333836, the shared memory is multi-layered (that is, the memory is divided into two or more and distributed over a plurality of independent paths) to achieve I / O. Performance has been improved.

[0004]

In the disk control device 1 shown in FIG. 8, since it is backed up by a battery,
Even when a power failure occurs, the information stored in the shared memory 6 is protected. However, when the number of I / O processing requests increases, communication becomes congested on the control information common bus 8, and this causes a bottleneck in system performance.

On the other hand, the disk controller disclosed in Japanese Patent Application Laid-Open No. 10-333836 has high I / O performance because the shared memory is multifaceted. However, since the shared memory is not backed up by a battery, there is a problem that information stored in the shared memory is lost when a power failure occurs.

[0006] By combining the above prior arts,
It is considered that if the multifaceted shared memory disclosed in Japanese Patent Application Laid-Open No. 0-333836 is backed up by a battery, I / O performance can be improved and power failure can be improved. However, backing up all of the multifaceted shared memories with a battery is difficult and impractical in view of the complexity of the circuit configuration and cost. SUMMARY OF THE INVENTION An object of the present invention is to provide a disk control device that has high I / O performance, is robust against power supply failure, and can be easily implemented.

[0007]

According to a first aspect, the present invention is a multiprocessor control disk controller having a plurality of processors, comprising a shared memory for storing control information of each processor. The disk control device is characterized in that the memory comprises a nonvolatile shared memory surface and a volatile shared memory surface. The disk control device according to the first aspect has a configuration in which the shared memory is divided into a nonvolatile shared memory surface and a volatile shared memory surface. In addition, the I / O performance can be improved by increasing the number of volatile shared memories, and the provision of a nonvolatile shared memory makes it more resistant to power failure. Further, since the volatile shared memory surface is not backed up by a battery, difficulties in circuit configuration and cost are reduced, and the implementation is facilitated.

According to a second aspect of the present invention, in the disk control device having the above configuration, each of the processors classifies information to be written into the shared memory into double-write information and single-write information, and The write information is written twice in the nonvolatile shared memory surface and the volatile shared memory surface.
A disk control device is provided, wherein the overwriting information is written only on the volatile shared memory surface. In the disk control device according to the second aspect, for example, important information that would cause the destruction of customer data when lost is double-written on both the nonvolatile shared memory surface and the volatile shared memory surface,
The control information that can be reconstructed even if it disappears and does not affect the customer data can be operated in such a manner that the control information is overwritten only on the volatile shared memory surface. In general, information to be double-written is smaller than information to be single-written, so that the capacity of the nonvolatile shared memory surface can be made smaller than the total capacity of the volatile shared memory surface. Therefore, it is possible to employ a nonvolatile semiconductor memory and eliminate the battery backup itself.

According to a third aspect of the present invention, in the disk control device having the above configuration, the nonvolatile shared memory surface is arranged so as to be able to supply power from any of two or more independent power supply systems, and the volatile shared memory surface is A disk control device is provided which is separately arranged in each of the power supply systems. In the disk control device according to the third aspect, even if one of the power supply systems goes down, the share of the volatile shared memory surface of the power supply system is allocated to the other volatile shared memory surface of the power supply system that is not down. , Operation can be continued.

According to a fourth aspect of the present invention, in the disk control device having the above configuration, the nonvolatile shared memory surface includes:
A disk control device including a disk drive is provided. In the disk control device according to the fourth aspect, if there is enough battery capacity for writing the double-write information to the disk drive, any long-term power failure can be handled.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. Note that the present invention is not limited by this. FIG. 1 is a configuration diagram of a disk array control device according to an embodiment of the present invention. The disk array controller 10 includes a host adapter 12, a disk adapter 13, a cache memory 14, a nonvolatile shared memory 15, a shared memory path switch 17, and a number of disk drives 18.

The disk array controller 10 is divided into two independent power supply systems, cluster A and cluster B. Each of the clusters A and B has one or more host adapters 12 and one or more disk adapters 1
3, one or more of the cache memories 14 and one or more of the shared memory path switches 17. Also,
The nonvolatile shared memory 15 belongs to both the clusters A and B. That is, the nonvolatile shared memory 15 is supplied with power from any of the clusters A and B. The cache memory 14 and the non-volatile shared memory 15 are backed up by a battery (not shown).

The host adapter 12 has a channel processor 19 for controlling the host adapter 12 and a host computer H in accordance with an instruction from the channel processor 19.
A channel interface circuit 20 for transferring data between the disk array controller 10 and the volatile shared memory 16 for storing control information of the disk array controller 10.

The disk adapter 13 includes a disk processor 21 for controlling the disk adapter 13, a disk interface circuit 22 for transferring data between the disk drive 18 and the cache memory 14 according to an instruction from the disk processor 21, and a disk array controller 10 Is provided with a volatile shared memory 16 for storing the control information.

The channel processor 19 and the disk processor 21 are connected by a shared memory path 23
It is connected to the shared memory path switch 17. The shared memory path switch 17 performs a path connection with the nonvolatile shared memory 15 or the volatile shared memory 16 in response to an access request from the channel processor 19 or the disk processor 21. Thereby, the channel processor 19 and the disk processor 21 can access any of the nonvolatile shared memory 15 or the volatile shared memory 16.

The channel interface circuit 20 of the host adapter 12 and the disk interface circuit 22 of the disk adapter 13 are connected to the cache memory 14 by a data bus (not shown). Thereby, the channel interface circuit 20
The disk interface circuit 22 can access any of the cache memories 14.

FIG. 2 shows how the nonvolatile shared memory 15 and volatile shared memory 16 are divided into areas and how information is written. The nonvolatile shared memory 15 has only a double writing area. The double writing area includes a configuration information area 30, a light pending information area 31,
A write command communication area 32 is provided. The volatile shared memory 16 has a double writing area and a single writing area. The double writing area includes a configuration information area 30, a light pending information area 31, and a write command communication area 32. The single writing area includes a read command communication area 33 and a cache directory area 34.

The configuration information area 30 is a double write area, and the same contents are written to both the nonvolatile shared memory 15 and the volatile shared memory 16. The content to be written is information such as the hardware configuration of the disk array control device 10 and, for example, information as to which physical drive the data is stored in. The write pending information area 31 is a double writing area, and the same contents are written to both the nonvolatile shared memory 15 and the volatile shared memory 16. The content to be written is data written from the host computer H to the cache memory 14 and information on where and how much data is not reflected on the disk drive 18 on the cache memory 14. The write command communication area 32 is a double write area, and the same contents are written to both the nonvolatile shared memory 15 and the volatile shared memory 16. The content to be written is information on communication performed by the channel processor 19 and the disk processor 21 in the process when a data write request is issued from the host computer H.

The read command communication area 33 has 1
This is a double writing area, and the contents are written only in the volatile shared memory 16. The content to be written is information on communication performed by the channel processor 19 and the disk processor 21 in a process when a data read request is issued from the host computer H. The cache directory area 34 is a single write area, and the volatile shared memory 16
Is written only to The content to be written is information indicating which data is stored in which position on the cache memory 14. This information is used to determine hit / miss of read data.

FIG. 3 shows a disk array controller 1 when a data read request is issued from the host computer H.
It is a flowchart which shows operation | movement of 0. In step 40, the channel processor 19 of the host adapter 12 receives the read request from the host computer H, and checks whether or not the requested data exists in the cache memory 14 via the shared memory path switch 17, Cache directory area 34 of volatile shared memory 16
See In step 40a, if the requested data is not on the cache memory 14, the process proceeds to step 41, and if the requested data is on the cache memory 14, the process proceeds to step 46.

In step 41, the channel processor 1
Reference numeral 9 refers to the configuration information area 30 of the volatile shared memory 16 and determines the disk processor 21 that reads the requested data from the disk drive 18 and writes the read data to the cache memory 14. In step 42, the channel processor 19 reads the read command communication area 33 of the volatile shared memory 16 corresponding to the determined disk processor 21.
Then, a data read command specifying a data write address to the cache memory 14 is written. In step 43, the disk processor 21, which is polling the read command communication area 33 of the volatile shared memory 16 corresponding to itself, reads the written data read command, reads the requested data from the disk drive 18, and reads the requested data from the cache memory. Write to the designated 14 data write addresses. In step 44, the disk processor 21 updates the cache directory information in the cache directory area 34 of the volatile shared memory 16. In step 45, the disk processor 21 writes an execution completion flag in the read command communication area 33 of the volatile shared memory 16 corresponding to the channel processor 19 that has issued the data read command. When the channel processor 19 polling the read command communication area 33 of the volatile shared memory 16 corresponding to itself reads the written execution completion flag, the process proceeds to step 46.

In step 46, the channel processor 1
9 reads the requested data from the cache memory 14 and transfers it to the host computer H. If a data read command has been written to the read command communication area 33 of the volatile shared memory 16, the data read command is deleted. Then, the read operation ends.

As described above, when there is a data read request from the host computer H, the channel processor 19 and the disk processor 21
The read operation is controlled by using only For this reason, the read I / O performance is governed by the access performance of the multi-faced volatile shared memory 16, and a sufficient read I / O performance can be obtained regardless of the access performance of the nonvolatile shared memory 15.

FIG. 4 shows the disk array controller 1 when a data write request is issued from the host computer H.
It is a flowchart which shows operation | movement of 0. In step 50, the channel processor 1 of the channel interface circuit 12
9 receives the write request from the host computer H, refers to the configuration information area 30 of the volatile shared memory 16 via the shared memory path switch 17, and determines the disk processor 21 that writes the write data to the disk drive 18. . In step 51, the channel processor 19 writes the write data on the cache memory 14. In step 52, the channel processor 1
9 is a light pending information area 31 of the volatile shared memory 16 corresponding to the determined disk processor 21.
Then, at which address in the cache memory 14 the write data not reflected in the disk drive is written. Subsequently, the same contents are written in the write pending information area 31 of the nonvolatile shared memory 15. In step 53, the channel processor 19 reports the completion of the data write to the host computer H.

In step 54, the channel processor 1
9 writes a data write command specifying the address of the write data in the cache memory 14 to the write command communication area 32 of the volatile shared memory 16 corresponding to the determined disk processor 21. Subsequently, the same contents are written in the write command communication area 32 of the nonvolatile shared memory 15. In step 55, the disk processor 21 polling the write command communication area 32 of the volatile shared memory 16 corresponding to itself,
When the written data write command is read, the write data at the address of the cache memory 14 written in the write pending information area 31 is written to the disk drive 18. In step 56, the disk processor 21 updates the cache directory information in the cache directory area 34 of the volatile shared memory 16. In step 57, the disk processor 21 writes an execution completion flag in the write command communication area 32 of the volatile shared memory 16 corresponding to the channel processor 19 that has issued the data write command. In step 58, the channel processor 19 polling the write command communication area 32 of the volatile shared memory 16 corresponding to itself reads the written execution completion flag, and stores it in the write pending information area 31 of the volatile shared memory 16. The written address and the data write command written to the write command communication area 32 are erased. Subsequently, the address written in the write pending information area 31 of the nonvolatile shared memory 15 and the data write command written in the write command communication area 32 are also erased. Then, the write operation ends.

As described above, when there is a data write request from the host computer H, access to the non-volatile shared memory 15 occurs only for address writing to the write pending information area 31 and command writing to the write command communication area 32. , And all other shared memory accesses are made to the volatile shared memory 16. For this reason, the write I / O performance is also governed by the access performance of the volatile shared memory 16 that is multifaceted, and a sufficient write I / O performance can be obtained regardless of the access performance of the nonvolatile shared memory 15.

As is apparent from the above description, in both data read / write operations, the access to the shared memory is
Access to the volatile shared memory 16 is dominant. Therefore, the I / O performance depends on the volatile shared memory 1
6 becomes dominant and the volatile shared memory 16
The disk array controller 10
I / O performance can be improved.

FIG. 5 is an explanatory diagram showing the operation of the disk array controller 10 when a power failure occurs. The power failure includes a single cluster power failure 70 in which a failure occurs in only one cluster and a power failure (both cluster power failure) 71 in which a failure occurs in both clusters.

In the case of a single-cluster power failure 70, if the channel processor 19 of the non-failed cluster 72 itself issues a command to the disk processor 21 of the failed cluster 73, the channel processor 19
By reissuing the command to the second disk processor 21, the operation is continued using only the non-failed cluster 72.

A failure cluster 73 in the case of a single cluster power failure 70 or a failure cluster 73 in the case of a power failure 71
(All clusters) stop operating while a failure occurs. If the failure occurs during the read operation (75), the data on the disk drive 18 will not be destroyed, so the disk array controller 10 does not perform any special processing. It is determined whether the host computer H has received the read data. If the read data has not been received, the host computer H may reissue the data read request after the failure recovery. If the failure occurs during the write operation (76), the write completion may be reported to the host computer H in a state where the write data is not reflected on the disk drive 18. For this reason, after recovery from the failure, the channel processor 19 and the disk processor 21 refer to the write pending information area 31 and the write command communication area 32 of the nonvolatile Write to. As a result, the recognition on the host computer H side and the data state of the disk drive 18 can be matched, and data loss due to a power failure can be prevented.

FIG. 6 shows a first example of the nonvolatile shared memory 15.
It is a block diagram of an example. The nonvolatile shared memory 15 of the first example
Includes a plurality of memory control circuits 81 corresponding to each cluster, a volatile memory 82 for storing shared memory information, a voltage drop detection circuit 83 for monitoring a drop in the supply voltage from the normal power supply system 84, and a normal power supply system 84 and a battery power supply. System 8
5 to the nonvolatile shared memory system 86 (including the memory control circuit 81 and the volatile memory 82)
And a power supply switching circuit 87 for selectively switching power supply to the power supply.

The memory control circuit 81 is connected to the channel processor 19 arriving via the shared memory path 23.
Alternatively, data is read / written from / to the volatile memory 82 in accordance with an instruction from the disk processor 21. The plurality of memory control circuits 81 are connected to each other via a communication line 88, and arbitrate for access to the same address on the volatile memory 82 so as to avoid collision.

The voltage drop detection circuit 83 constantly monitors the voltage of the normal power supply system 84. When the voltage drop of the normal power supply system 84 is detected, the voltage drop detection circuit 83 controls the power supply switching circuit 87 via a control line 89. Then, the power supply to the non-volatile shared memory system 86 is switched to the battery power supply system 85, and the data in the volatile memory 82 is protected from loss due to power interruption. As a result, while the battery backup to the nonvolatile shared memory system 86 can be continued, the data in the shared memory 82 can be protected from power interruption. Therefore, the capacity of the backup battery needs to be determined from the capacity of the volatile memory 82 and the required backup time.

The normal power supply system 84 includes a cluster A
And the power supply system of the cluster B.

FIG. 7 shows a second example of the nonvolatile shared memory 15.
It is a block diagram of an example. The nonvolatile shared memory 15 of the second example
Are a plurality of memory control circuits 91 corresponding to each cluster, a volatile memory 92 for storing shared memory information, a disk controller 93, a destage controller 9
4. a disk drive 95, a voltage drop detection circuit 96 for monitoring a drop in the supply voltage of the normal power supply system 97, and a non-volatile shared memory system 99 (the memory control circuit 91, the volatile The power supply switching circuit 100 selectively switches power supply to the memory 92, the disk controller 93, the destage controller 94, and the disk drive 95.

The memory control circuit 91 is connected to the channel processor 19 arriving via the shared memory path 23.
Alternatively, data is read / written from / to the volatile memory 92 in accordance with an instruction from the disk processor 21. The plurality of memory control circuits 91 are connected to each other via a communication line 101, and arbitrate for access to the same address on the volatile memory 92 so as to avoid collision.

The voltage drop detection circuit 96 constantly monitors the voltage of the normal power supply system 97, and when detecting the voltage drop of the normal power supply system 97, controls the power supply switching circuit 100 via the control line 102. And a non-volatile shared memory system 9
The power supply to the power supply 9 is switched to the battery power supply system 98 to protect data on the volatile memory 92 from loss due to power interruption. At the same time, the voltage drop detection circuit 96 notifies the destage controller 94 of the occurrence of power interruption via the notification line 104. The destage controller 94 that has received the notification controls the disk controller 93 and copies all data in the volatile memory 92 to the disk drive 95. Thus, data can be protected from a long-term power interruption regardless of the battery capacity. For this reason, the capacity of the backup battery may be determined so that power can be supplied only for the time required to write the data in the volatile shared memory 92 to the disk drive 95. For example, if the capacity of the volatile memory 92 is 2 GB and the data transfer speed to the disk drive 95 is 10 MB / s, it is sufficient that power can be supplied for at least 200 seconds.

When detecting that the normal power supply system 97 has recovered from the fault, the voltage drop detection circuit 96 switches the power supply to the non-volatile shared memory system 99 to the normal power supply system 97. Further, the failure recovery is notified to the destage controller 94 via the notification line 104. The destage controller 94 that has received this notification controls the disk controller 93 to return the data copied on the disk drive 95 to the volatile memory 92, so that the channel processor 19 or the disk processor 21 can access the shared memory information. To do.

The normal power supply system 97 is connected to the cluster A
And the power supply system of the cluster B. Further, instead of the disk drive 95, another nonvolatile storage device (such as an optical disk) or a nonvolatile memory (flash memory or Magnetic RAM) may be used.

Although the above description has been made on the assumption that a power failure occurs, even if a failure occurs in any of the volatile shared memories 16, the sharing of the failed volatile shared memory 16 is performed without any other failure. By allocating to the shared memory 16, the operation can be continued.

[0041]

According to the disk control apparatus of the present invention, high I / O performance can be obtained by increasing the number of planes of the shared memory, and a power supply failure can be coped with by providing a nonvolatile shared memory surface. Further, by using only a part of the shared memory as the non-volatile shared memory surface, difficulties in circuit configuration and cost are reduced, and the implementation is facilitated.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a disk array control device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing area division of a shared memory and classification of information written in each area.

FIG. 3 is a flowchart showing an operation of the disk array control device during a data read operation.

FIG. 4 is a flowchart showing an operation of the disk array control device during a data write operation.

FIG. 5 is an explanatory diagram showing a recovery method of the disk array control device after a power failure occurs.

FIG. 6 is a configuration diagram illustrating a first embodiment of a nonvolatile shared memory.

FIG. 7 is a configuration diagram showing a second embodiment of the nonvolatile shared memory.

FIG. 8 is a configuration diagram illustrating an example of a conventional disk array control device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Disk controller 2 Host interface unit 3 Disk drive 4 Disk interface unit 5 Cache memory 6 Shared memory 7 Data common bus 8 Control information common bus 10 Disk array controller 12 Host adapter 13 Disk adapter 14 Cache memory 15 Nonvolatile shared memory Reference Signs List 16 volatile shared memory 17 shared memory path switch 18 disk drive 19 channel processor 20 channel interface circuit 21 disk processor 22 disk interface circuit 23 shared memory path 30 configuration information area 31 write pending information area 32 write command communication area 33 read command communication area 34 Cache directory area 81 Memory control circuit 82 Volatile memory 82 Existence memory 83, 96 Voltage drop detection circuit 84, 97 Normal power supply system 85, 98 Battery power supply system 86 Non-volatile shared memory system 87, 100 Power supply switching circuit 88, 101 Communication line 89, 102 Control line 91 Memory control circuit 92 Volatile memory 92 volatile shared memory 93 disk controller 94 destage controller 95 disk drive 99 non-volatile shared memory system 104 message line H host computer MP processor

Claims (4)

[Claims] 1. A multiprocessor control disk controller having a plurality of processors, comprising a shared memory for storing control information of each processor, wherein the shared memory comprises a nonvolatile shared memory surface and a volatile shared memory surface. A disk control device characterized by the above-mentioned. 2. The disk control device according to claim 1, wherein each of the processors classifies information to be written to the shared memory into double-write information and single-write information, and
A disk control device, wherein overwriting information is written to both the nonvolatile shared memory surface and the volatile shared memory surface, and the single writing information is written only to the volatile shared memory surface. 3. The disk control device according to claim 1, wherein the non-volatile shared memory surface is arranged so as to be able to supply power from any of two or more independent power supply systems, and the volatile shared memory surface is connected to the non-volatile shared memory surface. A disk control device, which is arranged separately for each of a power supply system. 4. The disk control device according to claim 1, wherein the non-volatile shared memory surface includes a disk drive.