JP2001285802A - Device/method for reproduction and device/method for processing signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize constitution which copes with the video signal of a different format and outputs the video output of plural systems and which is inexpensive and can be miniaturized. SOLUTION: Format information embedded to a reproducing video signal is taken out by a detection circuit 11 and supplied to an output control circuit 18. An output format instruction is supplied to the circuit 18 and output circuits 16 and 17. The operation of vertical filter blocks 14 and 15 is controlled based on format information and an output format instruction. The outputs of system conversion circuits 20, 23, vertical filter circuits 21, 24 and delay adjusting circuits 22 and 25 are outputted by matching respective phases and selected by input switching circuits 30, 31, 34 and 35 based on the output format instruction. The circuits 16 and 17 output video signals with synchronization in accordance with each output format instruction. The blocks 14 and 15 are controlled independently by each luminance component Y and color component C and the circuits 16 and 17 are controlled independently. Input and output can independently cope with the video signals of plural formats and also cope with the change of chroma-format.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reproducing apparatus and method capable of processing digital video signals of a plurality of types of formats and performing digital video signal format conversion, and a signal processing apparatus and method.

[0002]

2. Description of the Related Art In the prior art, a VTR (Video Tape Recorder) capable of reproducing a video signal of two or more signal formats and converting the format of the video signal has already been proposed. ing. Such a VTR is disclosed in Japanese Patent Application Laid-Open No. Hei 2-171090.
There is a VTR described in the issue.

[0003] Japanese Patent Application Laid-Open No. Hei 2-171090 discloses a VTR in which the operation state of a format converter and the like is automatically changed according to the format of a reproduced video signal and a set video signal format. Has been described. Further, Japanese Patent Application Laid-Open No. 2-171090 describes that the discrimination of the recorded television standard system is performed by measuring a field frequency or the like.

On the other hand, in recent years, practical use of digital television broadcasting has been promoted, and the broadcasting system has been diversified. For this reason, a multi-format compatible VTR for a broadcasting station has been developed which can support a plurality of formats with one unit. In addition to support for NTSC and PAL such as the VTR described in JP-A-2-171090 described above, one frame corresponds to one frame.
VTRs have been developed that are compatible with progressive scanning composed of fields and HD (High Definition) systems with higher resolution.

[0005]

In such a format, for example, 480I (480 lines, interlaced scanning) and 480P (480 lines, progressive scanning)
Consider a VTR that can be recorded and reproduced together.
In the case of 480I and 480P, the field frequency is both 60 Hz.
As in the case of the example, the format cannot be determined by measuring the field frequency of the video signal.

[0006] The format of video signals used in digital television broadcasting in recent years has become very complicated. For example, even if the signal is 480P, the chroma format is not only the 4: 2: 2 standard but also a standard called SMPTE 294M, which is defined to transmit the signal in the 4: 2: 0 band. Also exists. In order to output a 4: 2: 2 video signal having a chroma format according to this standard, it is necessary to perform band limitation in the vertical direction only for the chroma signal. That is, in this case,
In addition to performing system conversion, it becomes necessary to select whether or not to perform filter processing on the chroma signal. Conventionally, there was a problem that a VTR having such an option did not exist.

Further, in a VTR for a broadcasting station, it is necessary to output a video signal in synchronization with an external reference. Even when the above-mentioned 480I and 480P signals are output simultaneously, it is desirable that the 480P signal be synchronized with the frame period (30 Hz) of the 480I signal. This is due to reasons such as editing corresponding to the conventional time code and compatibility with the dual link system defined in SMPTE 294M. In the dual link method, a progressive scan video signal is
This is a system in which transmission is alternately performed for each line to link A and link B. Odd lines and even lines are switched for each field. Normally, a 480I signal is
I / P conversion for converting to 80P and 480P for 48
The time required for the processing is different from that of the P / I conversion for converting to 0I.

Even in such a situation, when there is only one output, the reproduction start phase of the output video signal of the VTR is adjusted (preceded) to the external reference, so that the phase of the output signal is adjusted to the external reference. Can be matched. However, if the output has two systems, a system that performs system conversion and a system that does not perform system conversion, in order to match the two systems to the correct phase, some phase adjustment must be performed between the system that performs system conversion and the system that does not perform system conversion. Required. Conventionally, there has been a problem that a VTR that takes this point into consideration has not existed.

Further, the output of a VTR for a broadcasting station may be used as a reference for synchronization of another device. For this reason, for example, even when a tape is switched and the reproduction of a video signal in a format different from the previous one is started, it is necessary that the output signal be correctly output without disturbing the synchronization. Also, when the format of the reproduction signal changes with the replacement of the tape, the operation mode of the reproduction circuit system such as an error correction circuit, a video decoding circuit, and a system conversion circuit is changed inside the VTR. It takes several seconds to several tens of seconds for the operation to stabilize after the operation mode is changed, during which time a malfunctioning signal is output.

In the above description, for example, 480I and 4
Video signals of different formats such as 80P
Although the description has been made on the premise that the VTR performs system output, there may be a case where it is desired to output only one format of a signal in two systems depending on a user's request or a product form.

Further, in the 480I format, when performing variable speed reproduction such as 1/2 speed reproduction in which the tape speed at the time of reproduction is の of that at the time of recording, the interlace structure of the reproduced video signal is changed. Crumble. That is, the first field is continuously output for two fields, and then the second field is continuously output for two fields, thereby performing 1/2 speed reproduction. In this case, the signal of the first first field is displayed at the original line position of the first field, but the signal of the next first field which is continuously reproduced is displayed.
The signal of the field is displayed at the line position of the second field. The same applies to the signal in the second field. As a result, the vertical pitch (vertical movement) of 1/2 line width is displayed on the display screen.
There is a problem that a problem occurs.

Further, in order to incorporate a configuration for solving the above-listed problems into a VTR, conventionally,
There is a problem that the circuit becomes large-scale and the cost increases.

Accordingly, an object of the present invention is to provide a reproducing apparatus and method, and a signal processing apparatus and method, which are compatible with different format video signals, have a plurality of video outputs, can be reduced in size and are inexpensive. To provide.

[0014]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention can reproduce video signals of a plurality of signal formats, and can convert the format of the reproduced video signals and output them. A reproducing device for reproducing a video signal recorded with embedded format information from a recording medium; a format detecting device for detecting format information from the video signal reproduced by the reproducing device; Output format instructing means for instructing the format, and format converting means for converting the format of the video signal reproduced by the reproducing means, wherein the format information detected by the format detecting means and the output format Automatically converts format based on instructions A reproducing apparatus being characterized in that to switch the operation.

According to the present invention, in a reproducing method capable of reproducing video signals of a plurality of signal formats and converting and outputting the format of the reproduced video signal, format information is embedded and recorded. A reproducing step of reproducing the reproduced video signal from the recording medium; a format detecting step of detecting format information from the video signal reproduced in the reproducing step;
An output format instructing step instructing a format of an output video signal, and a format converting step of converting a format of the video signal reproduced in the reproducing step, and format information detected in the format detecting step A reproduction method characterized in that the operation in the format conversion step is automatically switched based on the output format instruction in the output format instruction step.

Further, the present invention provides a reproducing apparatus capable of reproducing video signals of a plurality of signal formats and simultaneously outputting the reproduced video signals in a plurality of formats. A reproducing means for reproducing, a format converting means for converting a format of a video signal reproduced by the reproducing means, and a phase of the video signal reproduced by the reproducing means, A plurality of output means for selecting and outputting a video signal output from the format conversion means and a video signal output from the bypass means; A playback device that outputs a signal.

Further, according to the present invention, in a reproducing method capable of reproducing video signals of a plurality of signal formats and simultaneously outputting the reproduced video signals in a plurality of formats, a video signal recorded on a recording medium is recorded. A reproduction step of reproducing the video signal, a format conversion step of converting the format of the video signal reproduced in the reproduction step, and a video signal reproduced in the reproduction step, wherein the format conversion is performed in the format conversion step. A plurality of output steps for selecting and outputting a video signal output from the format conversion step and a video signal output from the bypass step, and a bypass step of outputting the video signal in phase with the output video signal. Video signal output from multiple output steps simultaneously. A reproducing method and performing.

According to the present invention, in a signal processing apparatus capable of inputting video signals of a plurality of signal formats and converting the format of the input video signal and outputting the converted signal, the signal processing apparatus is embedded in the input video signal. Format detecting means for detecting the format information output, output format instructing means for instructing the format of the output video signal, and format converting means for converting the format of the input video signal. The signal processing device is characterized in that the operation of the format conversion means is automatically switched based on the format information thus given and the output format instruction by the output format instruction means.

According to the present invention, in a signal processing method capable of reproducing video signals of a plurality of signal formats and converting the format of the reproduced video signal and outputting the converted video signal, Having a format detection step of detecting embedded format information, an output format instruction step of instructing a format of an output video signal, and a format conversion step of converting a format of an input video signal, A signal processing method characterized in that an operation of a format conversion step is automatically switched based on format information detected in a format detection step and an output format instruction in an output format instruction step. .

Further, the present invention provides a signal processing apparatus capable of inputting video signals of a plurality of signal formats and simultaneously outputting the input video signals in a plurality of formats. A format conversion unit for converting, a video signal output from the format conversion unit, a bypass unit for outputting the input video signal in phase with the video signal output by format conversion by the format conversion unit, And a plurality of output means for selecting and outputting the video signal output from the means, and outputting the video signal from the plurality of output means simultaneously.

According to the present invention, there is provided a signal processing method capable of inputting video signals of a plurality of signal formats and simultaneously outputting the input video signals in a plurality of formats. A format conversion step of converting the format of the input video signal, a bypass step of outputting the input video signal in phase with the video signal converted and output in the format conversion step, and an output by the format conversion step And a plurality of output steps for selecting and outputting the output video signal and the video signal output by the bypass step, and outputting the video signal simultaneously from the plurality of output steps. This is a signal processing method.

As described above, according to the first and ninth aspects of the present invention, the format is automatically converted based on the format information embedded at the time of recording detected from the reproduced video signal and the output format instruction. Is switched, it is possible to cope with reproduction and output of video signals of a plurality of formats.

According to the tenth and sixteenth aspects of the present invention, a video signal which is detected from a reproduced video signal and which is format-converted based on format information embedded at the time of recording, and a reproduction which is bypassed from the format conversion The video signal and the video signal can be output simultaneously at the same phase.

According to the seventeenth and twenty-fifth aspects of the present invention, the format conversion operation is automatically switched based on the format information embedded in advance and the output format information detected from the input video signal. Therefore, it is possible to cope with input and output of video signals of a plurality of formats.

The invention according to claims 26 and 32 provides a video signal which has been detected from an input video signal and which has been format-converted based on format information embedded in advance, and a reproduced video which has been bypassed in format conversion. And the signals can be output simultaneously at the same phase.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. First, a recording format applicable to the present invention will be described for easy understanding.
The digital video signal is compression-coded by a predetermined method. In this embodiment, DCT (Discrete Cosine T
MPEG2 (Moving Pictures E), which is a compression encoding method using motion compensation based on
The compression encoding of the digital video signal is performed using xperts Group 2). The compression-encoded digital video signal is added with inner code parity and outer code parity,
Error correction coding is performed using a product code. Then, an SYNC pattern for detecting synchronization, an ID for identifying a sync block, and a DID indicating information on the content of data to be recorded are added to the error-correction-coded data in units of inner code parity. Thus, a sync block is configured. Data is handled as packets in sync block units.

The data to which the SYNC pattern, ID and DID have been added are recorded on a magnetic tape by a helical scan method by a magnetic head provided on a rotating drum. A plurality of magnetic heads are provided at positions facing each other on the rotating drum. That is,
When the magnetic tape is wound around the rotary head at a winding angle of about 180 °, a plurality of tracks can be simultaneously formed by rotating the rotary head by 180 °. The magnetic heads are formed as a set of two magnetic heads having different azimuths. The plurality of magnetic heads are arranged such that azimuths of adjacent tracks are different from each other.

FIG. 1 shows an example of a track format formed on a magnetic tape by the rotary head described above. This is an example in which video and audio data per frame are recorded on eight tracks. For example, the frame frequency is 29.97 Hz, and the rate is 50 Mbp
s, the number of effective lines is 480, and the number of effective horizontal pixels is 720
A pixel interlace signal (480I signal) and an audio signal are recorded. When the frame frequency is 25H
z, the rate is 50 Mbps, the number of effective lines is 576, and the number of effective horizontal pixels is 720.
6I signal) and audio signal can also be recorded in the same tape format as in FIG.

One segment is composed of two tracks having different azimuths. That is, eight tracks are composed of four segments. Track number corresponding to azimuth for a set of tracks constituting a segment

[0] and a track number [1] are assigned. In the example shown in FIG. 1, the track numbers are exchanged between the first eight tracks and the second eight tracks, and different track sequences are assigned to each frame. Thus, even if one of the set of magnetic heads having different azimuths becomes unreadable due to clogging or the like, the effect of the error can be removed by using the data of the previous frame, and the data can be modified. Can be performed well.

In each of the tracks, a video sector in which video data is recorded is arranged on both ends, and an audio sector in which audio data is recorded is interposed between the video sectors. FIG. 1 and FIG. 2, which will be described later, show the arrangement of sectors on the tape.

In this example, 8-channel audio data can be handled. A1 to A8
Indicates audio data channels 1 to 8 respectively. The audio data is recorded with its arrangement changed in segment units. In this example, in this example, data of four error correction blocks is interleaved for one track, and Upper Side and Low
It is divided into sectors of r Side and recorded. Lowe
In the video sector of r Side, a system area is provided at a predetermined position.

In FIG. 1, SAT1 (Tr) and SAT2 (Tm) are areas where servo lock signals are recorded. In addition, a gap of a predetermined size (Vg1, Sg1, Ag, Sg) is provided between the recording areas.
2, Sg3 and Vg2).

FIG. 1 shows an example in which data per frame is recorded on eight tracks. However, depending on the format of data to be recorded / reproduced, data per frame is recorded in four tracks.
Recording can be performed on tracks, six tracks, and the like.
FIG. 2A shows a format in which one frame has six tracks. In this example, the track sequence is

Only [0] is set.

As shown in FIG. 2B, the data recorded on the tape is composed of a plurality of equally-spaced blocks called sync blocks. FIG. 2C schematically shows the configuration of a sync block. From the top of the sync block, a SYNC pattern, ID, DID, and inner code parity are arranged in this order. The smallest data unit to be recorded or reproduced is one sync block. A number of sync blocks are arranged (FIG. 2B) to form, for example, a video sector (FIG. 2A).

The ID consists of two parts, ID0 and ID1, and stores information for identifying each sync block. FIG. 3A shows an example of the bit assignment of ID0 and ID1. ID0 is identification information (SY) for identifying each of the sync blocks in one track.
NC ID) is stored. The SYNC ID is, for example, a serial number. The SYNC ID is represented by 8 bits.

The ID 1 stores information about the track of the sync block. When the MSB side is bit 7 and the LSB side is bit 0, with respect to this sync block,
Bit 7 indicates whether the track is above (upper) or below (Lo)
wer), and bits 5 to 2 indicate the segment of the track. Bit 1 indicates the track number corresponding to the azimuth of the track.
Indicates which of the video data and the audio data the sync block is.

The DID stores information on the payload. The content of DID differs between video and audio based on the value of bit 0 of ID1 described above. FIG. 3B
Shows an example of bit assignment of DID in the case of video. Bits 7 to 4 are undefined (Reserve
d). Bits 3 and 2 are the mode of the payload, for example, indicating the type of the payload.
Bits 3 and 2 are auxiliary. Bit 1 indicates that one or two macroblocks are stored in the payload. Bit 0 indicates whether the video data stored in the payload is an outer code parity.

FIG. 3C shows an example of bit assignment of DID in the case of audio. Bits 7-4 are R
Eserved. Bit 3 indicates whether the data stored in the payload is audio data or general data. If compression-encoded audio data is stored in the payload, bit 3 is a value indicating the data.

[Amode2] of bit 2 to bit 0,
[Amode1] and [Amode0] are NTSC
In the method, information of a five-field sequence is stored. That is, in the NTSC system, an audio signal for one field of a video signal has 800 samples and 8 samples when the sampling frequency is 48 kHz.
01 sequence, and this sequence is prepared every five fields. Bit 2 to bit 0 indicate where in the sequence it is located.

As will be described later, these bits 2 to 0 are bits when [7] is represented by the three bits.
The subsequent data is AUX2, which is information for identifying a video recording format.

In the present invention, one video tape recorder (hereinafter, referred to as VTR) handles video signals of a plurality of formats. FIG. 4 illustrates a plurality of formats of the video signal. For example, corresponding to 14 different format modes, the image frame size is 720 pixels × 480 lines, 72
It corresponds to two types of 0 pixels × 576 lines. In each of the format modes, for example, the rate at the time of compression encoding of video data is set so that the shortest recording wavelengths at the time of recording on the magnetic tape are substantially equal to each other.

This format supports two types of screen scanning methods, interlaced scanning and progressive (non-interlaced) scanning. In interlaced scanning, one frame is composed of two fields. on the other hand,
In progressive scanning, a screen is completed in one frame. In the progressive scan, one frame period corresponds to two field periods. In each of the format modes shown in FIG. 4, "p" is appended to the number of lines in progressive scan and "i" in interlaced scan to represent these.

FIG. 4 shows that the frames are classified in the column direction by the frame frequency, and each is identified by Edit Freq. For example, if the frame frequency is 23.976 Hz, 25
Hz, 29.97 Hz, 50 Hz and 59.97 Hz
For EditFreq

[0],
Each value of [2], [3], [5] and [6] is assigned.

When the frame frequency is 23.976 Hz, 50
The columns of Hz and 59.94 Hz are groups in which progressive scanning is performed, and each group defines two modes having different video rates. The mode in which the frame frequency is 23.976 Hz is a mode corresponding to cinema, and one frame is composed of, for example, two fields of the same image. Also, the group with the frame frequency of 25 Hz and 29.97 Hz,
Each has two modes with different video rates for interlaced scanning and two modes with different video rates for progressive scanning. In the progressive scanning mode of this group, one frame is composed of, for example, two fields of the same image as in the above-described cinema mode. [1] or [1] for scanning method and video rate respectively

A flag having any value of [0] is assigned. In this example, the flags of the values [1] are all assigned to the number of lines.

That is, each video format mode shown in FIG. 4 has a value of [EditFreq],
It can be identified by the flags of [line], [scan] and [rate].

On the other hand, with respect to audio data, the sampling frequency and the number of quantization bits are common, for example, 48 KHz, and 16 bits per sample. The number of channels corresponds to eight channels and four channels. In this embodiment, audio data is treated uncompressed, and the length of a sync block for storing audio data is constant depending on the number of bits per sample and the frame frequency. That is, as long as the number of bits per sample and the frame frequency are the same, the length of the sync block that stores the audio data is a constant value regardless of the video image frame and the compression rate.

FIGS. 5 to 7 show examples of the arrangement of audio data in one error correction block for each frame frequency. 5 to 7 show the arrangement after the outer code parity is added. As shown in FIG. 5A, FIG. 6A and FIG. 7A, in one field period or 1P frame period, 10
Two error correction blocks with outer code parity for the sync block are formed.

The audio data of each channel constitutes one error correction block with even-numbered samples and odd-numbered samples in one field period. That is, two error correction blocks are formed in one field period. 5B, 6B and 7B, each frame in one error correction block represents one sample of data.
The number is a sample number given in sample order. The outer code parity is indicated by PV0 to PV9. In this example, since one sample is 16 bits (2 bytes),
Each frame is 16-bit data.

FIG. 5 shows that the frame frequency is 59.94 Hz.
This is an example of (progressive scanning) or 29.97 Hz (interless scanning), and audio data in one field period is 800 or 801 samples. FIG.
Indicates that the frame frequency is 50 Hz (progressive scanning)
Alternatively, it is an example of 25 Hz (interlace scanning),
The audio data in the field period consists of 960 samples. FIG. 7 shows that the frame frequency is 23.976.
Hz, and the audio data for one field period is composed of 1001 samples. Common to FIGS. 5 to 7,
Each row is a packet constituting one sync block, and one error correction block includes data for eight sync blocks and outer code parity for ten sync blocks.

In each of the first three sync blocks of each error correction block, AU is added to the first sample.
X data is stored. FIG. 8 shows an example of the content of each AUX data. FIG. 8A shows an example of bit assignment of AUX data, and FIG. 8B shows the meaning of each data.

AUX0 is 2 representing an audio editing point.
Bit data EF, 1-bit bit length data B indicating whether the quantization bit number is 16 bits or 24 bits, 1 indicating whether the data is uncompressed audio data
Bit data D, 2-bit data Amd for identifying an audio mode, a sampling frequency of 48 KHz,
It consists of 2-bit data FS indicating which of 44.1 KHz, 32 KHz and 96 Hz. If the subsequent 8 bits and one sample are 24 bits, another 8 bits are reserved.

AUX1 is entirely reserved.
(Reserved).

The data AUX2 has a format mode in the first 8 bits. If the subsequent 8 bits and one sample are 24 bits, another 8 bits are reserved. The format mode includes 2-bit [Line mode], 2-bit [Rate], 1-bit [Scan], and 3-bit [Freq]. These [Line mod
e], [Rate], [Scan] and [Freq]
Are shown in the above-mentioned FIG.
q], [line], [scan] and [rate]
Corresponding to That is, the video format can be known by looking at the data AUX2.

FIG. 9 shows an example of a track format for recording video data and audio data. FIG. 9 shows the same track format as in FIG. 2 described above, and six tracks correspond to a 1P frame. As shown in FIG. 9A, in this example, eight audio sectors are arranged for each track, and each audio sector includes six sync blocks. One frame of data is recorded on 6 tracks, and audio data is 6 sync blocks × 6 tracks, for a total of 36 sync blocks, and corresponds to FIGS. 5 to 7 described above.

As shown in FIG. 9B, each audio sector is assigned a continuous block ID (FF, FE, FD, FC, FB, FA: all in hexadecimal) from the head trace direction. As shown in FIG. 9C, each sync block is provided with a 2-byte SYNC pattern, a 2-byte block ID, and a 1-byte DID in the head trace direction, and is a data packet in which audio data is subsequently stored. Is arranged. Following the audio data packet, a 12-byte inner code parity is arranged. The data packet is D
Data is packed in byte units in the order of 0, D1, D2,.... That is, AUX0, A
The first 8 bits of UX1 and data AUX2 will be stored in D0 at the beginning of the data packet.

In this example, predetermined information is stored for the above-described DID, and when the predetermined information is obtained from the DID, the first 8 bytes of data AUX2 are stored in D0 of the subsequent data packet. Is shown. More specifically, in the DID bit assignment described above,
Lower 3 bits (Amode) of DID of audio data
0, Amode1 and Amode2) to [7]
Is represented, D0 of the subsequent data packet is determined to be the data AUX2.

Next, an embodiment of the present invention will be described.
This will be described with reference to the drawings. FIG. 10 shows a configuration of an example of a reproduction system of a digital VTR according to an embodiment of the present invention. A digital video signal recorded on a magnetic tape in the format described above can be reproduced by this configuration. In the following description, the digital VTR is 480 lines / interlace scan (4
80I) and 480 lines / progressive scan (480P).

In a digital VTR, a reproduction signal reproduced from a magnetic tape is supplied to a reproduction circuit 10 by a magnetic head provided on a rotating drum (not shown). The reproduction circuit 10 includes a reproduction amplifier, a reproduction equalizer, P
It includes an LL (Phase Locked Loop), a demodulation circuit, and the like, and converts the supplied reproduction signal into digital data.

The digital data output from the reproducing circuit 10 is supplied to a SYNC / ID detecting circuit 11,
The NC pattern, ID and DID are extracted. If it is determined based on the extracted DID that the sync block is a block including AUX of audio data,
AUX2 is read, and the recording format of the video signal is determined. In this example, the recording format is 480
It is determined whether it is I or 480P. Based on the result of this determination, a reproduction format instruction signal for instructing a reproduction format is output. The reproduction format instruction signal is supplied to the output control circuit 18 and also to the error correction circuit 12 and the video decoding circuit 13.

The data output from the SYNC / ID detection circuit is supplied to the error correction circuit 12. The error correction circuit 12 performs an error correction code decoding process on the reproduction data supplied from the SYNC / ID detection circuit 11 according to the instruction of the reproduction format instruction signal, and corrects the error. At this time, if an error exists beyond the error correction capability of the error correction code, error correction is not performed and an error flag indicating that an error exists is output. The error flag is used, for example, in an error correction circuit (not shown).

The data corrected by the error correction circuit 12 is supplied to a video decoding circuit 13. The video decoding circuit 13 performs MPEG2 decoding on the supplied reproduction data according to the instruction of the reproduction format instruction signal, expands the compression-encoded signal, and outputs a baseband digital video signal. The luminance component Y of the digital video signal output from the video decoding circuit 13
Is supplied to the vertical filter block 14, and the color component C is supplied to the vertical filter block 15.

The vertical filter block 14 includes a system conversion circuit 20, a vertical filter circuit 21, and a delay adjustment circuit 22.
Consists of The system conversion circuit 20 performs a conversion from progressive scanning to interlaced scanning (P / I conversion) and a conversion from interlaced scanning to progressive scanning (I / P conversion) on the supplied video signal.

The vertical filter circuit 21 is generated, for example, when the field polarity of the reference signal supplied from the outside and the video signal output from the video decoding circuit 13, that is, the correspondence between the ODD field and the EVEN field is different. Eliminate the vertical swing of the display screen.

On the other hand, the delay adjusting circuit 22 is a circuit for obtaining a non-converted output, and is supplied with a digital video signal supplied in order to match the phase of the digital video signal output from the system conversion circuit 20 and the vertical filter circuit 21. Is given a predetermined amount of delay. The signals output from the system conversion circuit 20, the vertical filter circuit 21, and the delay adjustment circuit 22 are input to the input switching circuit 30 of the output circuits 16 and 17.
And 34 respectively.

The vertical filter block 15 comprises a system conversion circuit 23, a vertical filter circuit 24, and a delay adjustment circuit 25, like the above-described vertical filter block 14, and can be controlled independently of the vertical filter block 14. It is. The color signal component C of the digital video signal supplied to the vertical filter block 15 is subjected to predetermined processing by these circuits in the same manner as described above, and is supplied to the input switching circuits 31 and 35 of the output circuits 16 and 17, respectively. .

Input switching circuits 30 and 34 selectively select digital video signals output from delay adjustment circuit 22, system conversion circuit 20 and vertical filter circuit 21 based on a selection instruction signal output from output control circuit 18. Switch and output. Similarly, the input switching circuits 31 and 35 switch the digital video signals output from the delay adjustment circuit 25, the format conversion circuit 23, and the vertical filter circuit 24 based on the selection instruction signal output from the output control circuit 18, and output the signals. I do.

For example, when the reproduction of the 480P format signal is instructed by the reproduction format instruction signal and the output of the 480I format signal is instructed by the output format instruction signal, the signal reproduced in the 480P format is converted to the 480I format. It indicates that the format needs to be converted and output. Therefore, the output of the system conversion circuit 20 is selected by the input switching circuit 30, and the output of the system conversion circuit 23 is selected by the input switching circuit 31.

In the output circuit 16, the input switching circuit 30
The luminance signal Y and the chrominance signal C output from the circuits 31 and 31, respectively, are supplied to the mute circuit 32. Mute circuit 3
2 displays the supplied luminance signal Y and color signal C in a predetermined signal, for example, gray, for a predetermined period after the format of the reproduced video signal is changed based on an instruction from a control circuit (not shown). The output is replaced with such a signal. Replacement of the signal by the mute circuit 32
The operation is continued for several seconds until the operation of a reproduction system circuit, for example, the video decoding circuit 13 is stabilized.

The digital video signal output from the mute circuit 32 is supplied to a synchronization signal generation / addition circuit 33. The synchronization signal generation / addition circuit 33 has, for example, a counter and generates a sync pattern based on a synchronization signal (reference signal) supplied from the outside. The digital video signal supplied to the synchronizing signal generation / addition circuit 33 is output with the generated sync pattern added thereto in a predetermined manner.

The synchronizing signal generation / addition circuit 33 is adapted to continue operating in accordance with a certain format, for example, in accordance with an output format instruction set by a switch provided on the panel surface of the VTR.

In the output circuit 17, the input switching circuit 3
4 and 35, a mute circuit 36 and a synchronizing signal generation / addition circuit 37 perform the same processing as the above-described output circuit 16, and a digital video signal is output. The input of the external synchronization signal to the output circuits 16 and 17 and the instruction of the output format can be performed independently. Therefore, output circuits 16 and 17
Can output digital video signals of different formats independently of each other.

The output control circuit 18 outputs a reproduction format instruction signal supplied from the SYNC / ID detection circuit 11,
For example, a selection instruction signal for the input switching circuits 30 and 31 and the input switching signals 34 and 35 is output based on an output format instruction signal based on an operation from the panel surface of the VTR. For example, when the reproduction format instruction signal indicates 480P reproduction and the output format instruction signal indicates 480I output,
In the input switching circuit 30 and the input switching circuit 31, the output of the system conversion circuit 20 and the output of the system conversion circuit 23 are selected, respectively. The output format instruction signal can be input to two independent systems corresponding to the output circuits 16 and 17.

As described above, in the present invention, the system conversion circuit, the vertical filter circuit, and the delay adjustment circuit are provided independently for the luminance signal Y and the chrominance signal C, and their output phases are matched. The luminance signal Y and the chrominance signal C are independently switched by an input switching circuit arranged at the head of the output circuit. Then, the reproduced digital video signal of the signal format of 480I and 480P reproduced from the magnetic tape is freely converted in format between 480I and 480P with respect to the output of two systems, and can be output respectively. .

Here, the digital video signal input to the vertical filter block 14 will be schematically described. FIG. 11 shows that the signal formats are 480I and 48
The positional relationship between the lines of the digital video signal of 0P will be described. The field frequencies are 480P and 4
Both are set to 60 Hz in the 80I format. Note that the vertical filter block 15 is
Therefore, detailed description is omitted.

When the signal format is 480P, as shown in FIG. 11A, one field is composed of 525 lines. Of the total 525 lines, the number of valid lines displayed on the screen is 480. On the other hand, when the signal format is 480I, as shown in an example in FIG. 11B, all 525 lines are in the first field and the second field.
The first and second fields make up one frame. The first field is the first
The second field from the 264th line starts with a delay of １ ／ line from the start line (the first line) of the first field.
That is, in the 480I format, the second field is displayed at a position 1/2 line lower than the first field on the screen.

Here, a case will be considered in which a magnetic tape on which such a video signal is recorded is reproduced at a speed different from that at the time of recording, and variable-speed reproduction is performed. Here, it is assumed that the variable speed reproduction is 1/2 speed reproduction in which reproduction is performed at a speed lower than 1x speed, for example, half the speed at the time of recording. In the following, the first field in the case of interlaced scanning is “ODD field”, and the second field is “EVE field”.
N field ".

FIG. 12 schematically shows the output order of the ODD and EVEN fields in interlaced scanning during 1/2 × speed reproduction. At the time of 1/2 speed reproduction, one frame is output during the period of the original two frames during normal reproduction, and as shown in an example in FIG. 12B, the ODD and EVEN fields are output during the original one frame period. Are continuously output twice each. This is different from the output order of the original ODD and EVEN fields as shown in FIG.
There are fields that are reversed with respect to the order of the N fields.

On the other hand, when the video signal output from the VTR is synchronized with an externally supplied synchronization signal and displayed on a monitor, for example, the ODD and the EV are used.
In the field where EN is reversed, the signal of the EVEN field is displayed at the line position of the original ODD field, and conversely, the signal of the ODD field is displayed at the line position of the original EVEN field.
Inconvenience occurs.

In order to avoid this, the output video signal is normally subjected to a vertical filtering process to shift the center of gravity of the screen. In this embodiment, this processing is performed in the vertical filter blocks 14 and 15.

Next, the vertical filter blocks 14 and 1
5 will be described in more detail. Since the vertical filter blocks 14 and 15 can be realized with substantially the same configuration, the vertical filter block 14 will be described below. FIG. 13 shows an example of the configuration of the vertical filter block 14 in more detail. The reproduced video signal output from the video decoding circuit 13 is divided into four delay circuits 50A to 50D.
And supplied to the coefficient multiplier 51A.
Outputs of the delay circuits 50A to 50D are supplied to coefficient multipliers 51B to 51E, respectively.

The quadruple delay circuits 50A to 50D, coefficient multipliers 51A to 51D and adder 52 constitute a vertical filter. Each of the four delay circuits 50A to 50D is formed of, for example, a line memory, and delays an input signal by one line. The delay of one line is equivalent to 64 μs when the signal format is 480I, and is equivalent to 48 μs.
At 0P, it corresponds to 32 μs.

FIG. 14 shows the coefficient multipliers 51A to 51E in more detail. Each of the coefficient multipliers 51A to 51E selects a coefficient set in the two coefficient registers by a coefficient selection circuit, and multiplies the selected coefficient and an input video signal by a multiplication circuit. These coefficient multipliers 51
Since A to 51E have the same configuration, only the coefficient multiplier 51A will be described. Coefficients a1 and b1 are set in the two coefficient registers. One of the coefficients a1 and b1 is selected by the coefficient selection circuit 53A based on the reproduction format instruction signal and the output format instruction signal described above. The digital video signal input to the multiplying circuit 54A is output after being multiplied by the coefficient selected by the coefficient selecting circuit 53A.

In the coefficient multiplication circuits 51B to 51E,
Similarly, coefficients a2 to a5 and b2 to b5 are selected, and the input digital video signal is multiplied by a coefficient. The signals output from each of the coefficient multiplying circuits 51A to 51E are added by an adder 52, synthesized into a signal for one line, and output.

FIG. 15 shows examples of coefficients a1 to a5 and b1 to b5. Each coefficient shown in FIG. 15 is a well-known value used at the time of format conversion of a video signal. In FIG. 15, the coefficients a1 to a5, b1 of the column (a)
B5 are coefficients generally used at the time of I / P conversion. When coefficients a1 to a5 are used, the center of gravity is.
When the shift is 5H and the coefficients b1 to b5 are used, the center of gravity does not shift. When the coefficients in column (a) are used, the frequency characteristics of the signal are reduced by half.

The coefficients a1 to a5 in the column (b) are coefficients generally used in 1/2 speed reproduction, and the coefficients a1 to a5 are used.
The center of gravity is shifted by ／ H when using 〜a5, and the center of gravity is shifted by ８H when using coefficients b1 to b5. As will be described later, in this embodiment, the coefficients a1 to a5 and b1 to b5 of this column (b) are used to determine the center of gravity shift at the time of inversion of the ODD / EVEN field in 1/2 speed reproduction in the conventional usage. Used to correct,
Also used for I / P conversion.

Also, the coefficients a1 to a5, b1 to
b5 is a coefficient used when performing P / I conversion.
Since the same value is used for each of the coefficients a1 to a5 and the coefficients b1 to b5, a change in the center of gravity does not occur in the conversion using the column (c). In the conversion by the column (c), the frequency characteristic of the signal is reduced to half as in the conversion by the column (a).

As can be seen from FIG. 15, in the coefficient of column (b), the deviation of the center of gravity due to the vertical filter is 5 / 8H. In addition, even in the case of processing that does not shift the center of gravity, the center of gravity is actually shifted by 1 / 8H. Further, in columns (a) and (c), coefficients are used so that the frequency characteristics are lowered. This makes it possible to keep the quality of the output video signal constant between when the video signal is interpolated by the vertical filter and when it is not. For this purpose, vertical filter processing is performed using such a set of coefficients having similar frequency characteristics. Thus, flicker of the output video signal can be prevented.

Coefficients a1 to a5 and coefficient b1 shown in FIG.
To b5 are switched at predetermined timing by coefficient selection circuits 53A to 53E, and selectively multiplied by
A to 54E. FIG. 16 is a time chart showing an example of the operation of the coefficient selection circuits 53A to 53E. The coefficient selecting circuits 53A to 53E all perform the same operation, and therefore, here, the coefficient multiplier 51A and the coefficient selecting circuit 53A will be described as an example.

FIG. 16A shows a video signal input to the coefficient multiplier 51A, and D0, D1, D2,... Each represent pixel data. The pixel data is 1 / 13.5M based on the field frequency of the 480I format.
It is input at a cycle of Hz. As shown in FIG. 16B,
The coefficient switching instruction signal COESEL instructs the selection of the coefficient selection circuit 53A to be switched at a cycle of 入 力 of the input cycle of the pixel data. The coefficients a1 and b1 are switched in the order of the coefficient a1 and the coefficient b1 by the coefficient switching instruction signal COESEL in a half cycle of the input cycle of the pixel data and supplied to the multiplying circuit 54A. Therefore, as shown in FIG. 16C, a signal whose center of gravity is raised by 0.5H and a signal whose center of gravity is not changed are combined and output from coefficient multiplier 51A during the period of one pixel data, as shown in FIG. 16C. . That is, the output of the multiplication circuit 54A has a data rate twice that of the input signal.

As described above, by switching the coefficients a1 and b1 at a cycle of 1/2 of the input cycle of the pixel data, a signal for two lines is generated. In FIG. 16C, F0 ′, F1 ′, F2 ′,...
., F0, F1, F2,...
Indicates the pixel data on the line at the original line position where the coefficient b1 is multiplied and the center of gravity is not raised.

The output of the coefficient multiplier 51A is similarly added to the outputs of the other coefficient multipliers 51B to 51E multiplied by the coefficients a2 to a5 and b2 to b5, respectively, and added to the output of the vertical filter by the adder 52. Is done. The output of the vertical filter is supplied to a delay circuit 56 for giving a delay of 32 μs.
A to 56D. The delay circuits 56A to 56D
This is for adjusting the amount of delay, and for example, each comprises a FIFO (First In-First Out) memory.

The structure after the delay circuits 56A to 56D is the same as the structure as the vertical filter circuit 21 and the method conversion circuit 20.
Configuration. The video output as the vertical filter circuit 21 is taken out from the selector 63, and the video output as the output from the format conversion circuit 20 is supplied to the selector 60.
Taken out of First, the configuration and processing of the vertical filter circuit 21 will be described.

The output of the delay circuit 56A is taken out and supplied to the selector 63, and the outputs of the delay circuit 56B and the delay circuit 56D are supplied to the selector 63 via the center-of-gravity selection circuits 61A and 61B, respectively.

The center-of-gravity selection circuits 61A and 61B will be described. FIG. 17 shows the center-of-gravity selection circuits 61A and 61B.
5 is a time chart showing an example of the operation of the embodiment. FIG. 17A
FIG. 17C is a diagram showing the output of the vertical filter and corresponding to FIG. 16C described above. As described above, the output of the vertical filter, that is, the signal output from the adder 52 has a center of gravity of .0.
The data raised by 5H and the data whose center of gravity is not changed are signals that are combined during the period of the original data of one pixel. This signal is selected and output by the center-of-gravity selecting circuits 61A and 61B as a signal whose center of gravity is changed and a signal whose center of gravity is not changed.

More specifically, when the field polarity is inverted between the reproduced video signal output from the video decoding circuit 13 and the reference at the final output, for example, an external synchronization signal, the coefficients a1 to a5 (FIG. 17)
C) is selected, and if not inverted, the coefficients b1 to b
5 (FIG. 17B) is selected and supplied to the selector 63 at the same timing.

For example, the center-of-gravity selection circuit 61A is composed of two latch circuits that operate at a half cycle of the input cycle of the pixel data. In a field where the field polarity is not inverted between the reproduced video signal and the reference, Data F0, F1, F2,... Of the vertical filter output of FIG.
Is selectively latched once and output in synchronization with the data timing for one pixel (FIG. 17B). On the other hand, in the field where the field polarity is inverted between the reproduced video signal and the reference, the data F out of the vertical filter output is output.
0 ', F1', F2 ',... Are selectively latched twice and output in synchronization with the data timing of one pixel (FIG. 17C). The operation and configuration of the center of gravity selection circuit 61B are the same as those of the center of gravity selection circuit 61A.

At the time of variable-speed reproduction of a 480I format video signal, the selector 63 controls the video decoding circuit 13
Circuit 5 based on the relationship between the field polarity of the reproduced video signal output from the controller and the field polarity of a reference signal such as an external synchronization signal supplied from the outside.
The signals supplied from 6B and 56D are selectively output. In this embodiment, if the field polarity of the reproduced video signal is ODD and the field polarity of the reference signal is EVEN, the output of the delay circuit 56B is selected; otherwise, the output of the delay circuit 56D is selected. Select

When outputting a 480P format video signal, the selector 63 selects the output of the delay circuit 56A.

FIGS. 18 and 19 show the relationship between the center of gravity of the reproduced video signal output from the video decoding circuit 13 and the output video signal output from the selector 63 during 1/2 × speed reproduction. The processing by the above configuration will be described.

FIG. 18 shows an example in which the ODD and EVEN fields of the reference are not inverted with respect to the input reproduced video signal. FIG. 18C shows a video signal reproduced by interlaced scanning, that is, a 480I format video signal, and FIGS. 18A and 18B show FIG.
18D and 18E show the EVEN field output based on the signal of FIG. 18C. When the signal in FIG. 18C is output in the 480I format, as shown in FIGS. 18A and 18E, the signal can be output without any processing in any of the ODD and EVEN fields.

That is, the video signal output from the video decoding circuit 13 and input to the vertical filter block 14 is supplied to the four delay circuits 50A to 50D, taken out from the third-stage delay circuit 50C, and Output as converted output. This output is supplied to input switching circuits 30 and 34 at the subsequent stage.

On the other hand, when the signal shown in FIG. 18C is output in progressive scanning, that is, in the 480P format, a 480P line is generated and output by interpolation as shown in FIGS. 18B and 18D, respectively.
The line interpolation is performed by the above-described vertical filter including the delay circuits 50A to 50D, the coefficient multipliers 51A to 51E, and the adder 52. Coefficient multipliers 51A to 51E
The coefficients a1 to a5 and b1 to b5 shown in the column (a) of FIG. 15 described above are stored in the coefficient register described above, and interpolation is performed by switching the coefficient selection circuits 53A to 53E to predetermined values. The interpolated signal is supplied to the delay circuit 56A, adjusted in phase, and output via the selector 63.

FIG. 19 shows a field in which the ODD and EVEN fields are inverted, and an interlaced scan.
That is, this is an example of outputting in the 480I format. FIG. 19D shows a video signal reproduced at 480I, and this signal is output in the ODD field as shown in FIG. 19A through the processing of FIGS. 19C and 19B. Similarly, FIG.
The signal D is output in the EVEN field as shown in FIG. 19F through the processing of FIG. 19E.

Since ODD and EVEN are inverted, the signal of the ODD field among the signals of FIG.
Video decoding circuit 1 in synchronization with the synchronization of the EVEN field
3 is output. Therefore, as shown in FIG. 19C, the center of gravity is lowered by 0.5 lines (0.5H). This signal is supplied to the vertical filter block 14, and the coefficients a1 to a shown in the above-mentioned column (b) of FIG.
5 is used for vertical filtering and the center of gravity is 0.5H
Lowered (FIG. 19B). Further, this signal is switched by the selector 63 from the delay circuit 56D to the delay circuit 56B, so that the center of gravity is 1 as shown in FIG. 19A.
H, I can raise it. As a result, the signal of the ODD field is returned to the original, that is, the line position of the reproduced signal shown in FIG. 19D.

On the other hand, the EVEN field is similarly output from the video decoding circuit 13 in synchronization with the ODD field. Since the EVEN field is adjusted to the ODD field, in this case, the center of gravity increases by 0.5H as shown in FIG. 19E. The signal whose center of gravity has risen by 0.5H is lowered by 0.5H by the vertical filtering using the coefficients a1 to a5 shown in the column (b) of FIG. 15 described above, and as shown in FIG. 19F. , EVEN field is lowered to the original line position.

The signal subjected to the vertical filter processing is supplied to the delay circuits 56A to 56D, the phases thereof are adjusted, and the center of gravity is selected by the center of gravity selection circuits 61A and 61B. In the processing from FIG. 19D to FIG. 19A, the delay circuit 56
The output of B is selected, and in the processing from FIG. 19D to FIG. 19F, the output of the delay circuit 56D is selected.

Next, the configuration and processing of the system conversion circuit 20 will be described. The system conversion circuit 20 performs the P / I conversion and the I / P conversion as described above. Outputs of the delay circuits 56A, 56B and 56C are respectively extracted and supplied to the selector 57. Therefore, the selector 57 receives three systems of signals that are shifted by 32 μs, that is, 1H in the 480P format. The selector 57 selectively outputs these three signals and supplies them to the time axis conversion circuits 58 and 59. The selector 57 selects a signal to be output according to the output format instruction signal, and selects a signal to be output based on the field polarity of the reproduced video signal output from the video decoding circuit 13 and the reference signal.

The time axis conversion circuits 58 and 59 are composed of, for example, FIFO memories, and read the input digital video signal on a different time axis from that at the time of input to convert the time axis, and perform P / I conversion or I / O conversion. Perform P conversion. Outputs of the time axis conversion circuits 58 and 59 are supplied to a selector 60, and are selected and output based on a reproduction format instruction signal and an output format instruction signal.

First, the case of normal reproduction will be described.
In the selector 57, the output of the delay circuit 56B is selected. FIG. 20 is a time chart showing an example of the normal reproduction. 20 and FIG. 22 and FIG.
3 and FIG. 24, the hatched portion indicates a horizontal blanking period.

FIG. 20A shows a reference signal. The reference signal corresponds to an interlaced scanning signal in this example, and 1H = 64 μs. The video signal of the 480I format shown in FIG. 20B is input to the vertical filter block 14 in synchronization with the reference signal. From this signal, 480
A line in P format is generated (FIG. 20C). As described above, in the vertical filter, the coefficient selection circuit 53A
By 53E, data for two pixels is combined in one pixel data period, and 2H signals of 480P format are multiplexed in 1H period of 480I format. This signal is delayed by 32 μs by delay circuits 56A and 56B, respectively (FIGS. 20D and 20E), and supplied to time axis conversion circuits 58 and 59 via selector 57.

In the time axis conversion circuit 58, the delay circuit 56B
480I format 1H
Of 2H of 480P format multiplexed in the period,
The signal of the first half line is selectively written into the FIFO memory (FIG. 20F). This signal is, as shown in FIG.
The signal is read in the latter half of 1H when the signal is written to the FO memory. On the other hand, in the time axis conversion circuit 59, the signal output from the delay circuit 56B is converted into the 480P format multiplexed in the 480I format 1H period.
H, the signal of the latter half line is selectively written into the FIFO memory (FIG. 20H). This signal is read in the first half of 1H following 1H when the signal is written in the FIFO memory, as shown in FIG. 20I.

The signals subjected to the time axis conversion by the time axis conversion circuits 58 and 59 are converted into one signal by the selector 60 and output as the converted output of FIG. 20J. By controlling the time axis conversion circuits 58 and 59 in this manner, a signal whose center of gravity is shifted by 0.5H, which is generated by the vertical filter, and
A signal having no change in the center of gravity is output every 1H, and a correctly interpolated 480P format signal is obtained.

The converted output is delayed by 3H from the input signal, as shown in FIG. 20J. On the other hand, the output from the selector 63 described above is
As shown by 0K, the output of the adder 52 is delayed by 3H with respect to the input signal through delay circuits 56A to 56D. Further, the non-converted output is supplied to the delay circuit 5
Since it is extracted from the third stage of 0A to 50D, it is delayed by 3H with respect to the input signal. That is, the outputs of the system conversion circuit 20, the vertical filter circuit 21, and the delay adjustment circuit 22 are in phase with each other.

A case in which variable speed reproduction, for example, 1/2 speed reproduction is performed, will be described. In this case, as described above, the field polarities of the reproduced video signal output from the video decoding circuit 13 and the reference signal are inverted.

FIG. 21 shows ODD and E during variable speed reproduction.
This is a field where the VEN field is inverted, and shows a change in the center of gravity in the case of progressive scanning, that is, output in the 480P format. FIG. 21D shows a video signal reproduced at 480I, and this signal is output in the ODD field as shown in FIG. 21A through the processing of FIGS. 21C and 21B. Similarly, the signal of FIG.
21F through the processing of FIG. 21F and EV as shown in FIG. 21G.
Output in EN field.

Since ODD and EVEN are inverted, the signal in the ODD field among the signals in FIG.
Video decoding circuit 1 in synchronization with the synchronization of the EVEN field
3 is output. Therefore, as shown in FIG. 21C, the center of gravity is lowered by 0.5H. Then, in the vertical filter block 14, lines are interpolated by the vertical filter processing using the coefficients a1 to a5 and b1 to b5 shown in the column (a) in FIG. Next, a line corresponding to the progressive scan is generated. This video signal of 480P format is supplied to delay circuits 56A to 56D at the subsequent stage of the vertical filter, and by controlling the reading of the memory, the center of gravity is 1H as shown in FIG. 21A.
Raised and output.

On the other hand, the signal in the EVEN field is OD
The data is output from the video decoding circuit 13 in synchronization with the D field. Therefore, as shown in FIG. 21E, the center of gravity increases by 0.5H. Then, in the vertical filter block 14, lines are interpolated by the vertical filter processing using the coefficients a1 to a5 and b1 to b5 shown in the column (a) in FIG.
, A line corresponding to the progressive scan is created. This video signal in the 480P format is supplied to delay circuits 56A to 56D, and the center of gravity is lowered by 1H as shown in FIG. Since the second line of the 480P format is formed from the first line of the EVEN field in the 480I format, the line position on the EVEN field side becomes the same as the line position on the ODD field side in FIG. 21A by lowering the 1H center of gravity.

As described above, when the field polarity of the reproduced video signal reproduced by the variable speed reproduction and the field polarity of the reference signal are reversed, the center of gravity is shifted by 0.5H (32 μs) of the 480I format with respect to the original center of gravity. Is shifted. Therefore, by changing the number of stages of the delay circuits 56A to 56C in the selector 57, this 0.5
H, that is, the displacement of the center of gravity of 32 μs is restored. Thereafter, as in the case of the above-described normal reproduction, the time axis conversion is performed by the time axis conversion circuits 58 and 59, whereby a correctly interpolated 480P format signal is obtained.

FIG. 22 shows an ODD field signal as an EV signal.
FIG. 23 is a timing chart illustrating an example of a case of outputting at the timing of the EN field, and FIG. 23 is a timing chart illustrating an example of a case of outputting the signal of the EVEN field at the timing of the ODD field. When outputting the signal of the ODD field at the timing of the EVEN field, the selector 57 selects the output of the delay circuit 56A. On the other hand, the signal of the EVEN field is set to OD
When the output is performed at the timing of the D field, the selector 57 selects the output of the delay circuit 56C. By switching the number of delay stages in this way, 0.5
The shift of the center of gravity for H is restored. Time axis conversion circuit 58
The operations of steps 59 and 59 are the same as the timings of FIG. 20 described above, and a detailed description thereof will be omitted.

Next, a case where a signal reproduced from the video decoding circuit 13 in the 480P format is processed will be described. The signal flow is the same as in the case of reproducing the 480I format signal described above. In the vertical filter, the values of column (c) in FIG. 15 can be used for the coefficients a1 to a5 and b1 to b5. A 480P format signal has a data rate of 480I format 2
Since the number is doubled, it is not necessary to consider switching of coefficients by the vertical filter and switching by the center-of-gravity selection circuits 61A and 61B as described with reference to FIGS. The 480P format is originally a non-interlaced scan that does not perform an interlaced scan.
Field = 1 frame. Therefore, the phenomenon of inversion of the field polarity between the reproduced video signal output from the video decoding circuit 13 and the reference signal during variable speed reproduction does not occur. Therefore, the selector 57 and the selector 6
In 3, the signal of the delay circuit 56A is always selected.

FIG. 24 is a time chart showing an example of processing of a signal of the 480P format. The reference signal is a signal corresponding to the 480P format as shown in FIG. 24A, and 1H is 32 μs. The 480P format video signal output from the video decoding circuit 13 is input to the vertical filter block 14 as shown in FIG. This signal is delayed by 64 μs by the vertical filter and input to the delay circuit 56A (FIG. 24C). The signal (FIG. 24D) delayed by 864 words in the delay circuit 56A is
8 and 59.

In time axis conversion circuits 58 and 59, FIG.
0, and performs the reverse process in the process of the 480I format described above with reference to FIGS. 21 and 23. That is, FIG.
As shown in FIG. 24F and FIG. 24F, and FIG. 24H and FIG. 24I, the signal of 480P format in which 1H is 32 μs written in the FIFO memory is read out in 64 μs. In the time axis conversion circuits 58 and 59, as shown in FIGS. 24G and 24J, reading is performed with a shift of 1H in the 480P format. In this example, the output of the time axis conversion circuit 58 is the first field (ODD field).
The output of the time axis conversion circuit 59 is used as a second field (EVEN field). Thus, P / I
At the time of conversion, the signals are thinned out by 1H at the time axis conversion circuits 58 and 59 and output, whereby 48
An output signal corresponding to the 0I format is obtained.

In this example, FIGS. 24G, 24J, 24
K and the system conversion circuit 2 as shown in FIG.
0, the outputs of the vertical filter circuit 21 and the delay adjustment circuit 22 are in phase with each other.

In the above description, the vertical filter block 1
4, that is, an example in which the luminance signal component Y of the video signal is mainly described, and an example in which the number of lines of the video signal is converted has been described. By applying this to the color signal component C of the video signal, Can be converted. For example, a signal having a chroma format of 4: 2: 2 can be converted into a signal having a chroma format of 4: 2: 0. For example, as described above, when the coefficients of columns (a) and (c) of the coefficients shown in FIG. 15 are used in the vertical filter, the frequency characteristic of the signal is reduced to half, Chroma format conversion can be performed. Also, the vertical filter block 1
Since 4 and 15 are controlled independently of each other, both the number of lines and the chroma format can be converted.

Further, in the above, one embodiment of this embodiment is described as follows.
Although described as applying to conversion between the 480I format and the 480P format, this is not limited to this example. For example, in the configuration of this embodiment, the HD (H
igh Definition) format and SD (Standard Definit)
(ion) format.
The HD format increases the number of lines and the number of samples per line compared to the SD format.
Higher resolution than format.

Further, in the above description, the present invention is described as being applied to a VTR that processes a signal reproduced from a magnetic tape using a magnetic tape as a recording medium, but the present invention is not limited to this example. For example, the present invention can be applied to an apparatus that uses a recording medium as a disk-shaped recording medium and converts a video signal reproduced from the disk-shaped recording medium. Further, for example, this embodiment can be applied to a case where not only a video signal reproduced from a recording medium but also a video signal supplied via a wired or wireless transmission path is converted.

In the above description, the VTR according to the embodiment is described as being compatible with the two-system format. However, the present invention is not limited to this example, and the VTR can be further adapted to the multi-system format.

[0128]

As described above, according to the present invention, the reproduction video format information recorded on the magnetic tape and the output format information specified in advance are
There is an effect that the operation mode of the system converter that performs the P / I conversion and the I / P conversion can be automatically changed.

Further, since the vertical filter and the output circuit are provided independently for the luminance component signal Y and the chrominance signal component C, there is an effect that it is possible to cope with a difference in chroma frequency characteristics at the time of output.

Furthermore, in this embodiment, there is an effect that two or more kinds of different formats of output are provided, and these two or more kinds of different formats of video signals can be output in phase with each other.

Further, according to this embodiment,
The output circuit independently adds synchronization based on the external synchronization signal to the output signal, so that even when the magnetic tape to be reproduced is replaced with a tape of a different format, synchronization can be added continuously. There is. Further, when the format is changed, the output signal is muted for a predetermined period and replaced with, for example, a gray signal, so that an error screen at the time of the format change is not displayed.

Further, according to this embodiment, there is an effect that formats of two or more systems can be freely selected in a matrix.

Further, according to this embodiment, the filter processing for variable speed reproduction and the filter processing for system conversion are performed with a common configuration, so that the circuit scale can be reduced.

Furthermore, since two types of filter coefficients having substantially the same frequency characteristics are used as filters for system conversion, flicker caused by a difference in field polarity between a reproduced signal and a reference signal during variable speed reproduction is reduced. be able to.

[Brief description of the drawings]

FIG. 1 is a schematic diagram illustrating an example of a track format formed on a magnetic tape.

FIG. 2 is a schematic diagram illustrating an arrangement of sectors on a tape.

FIG. 3 is a schematic diagram illustrating an example of a bit assignment of ID0 and ID1.

FIG. 4 is a schematic diagram illustrating a plurality of formats of a video signal.

FIG. 5 is a schematic diagram illustrating an example of an arrangement of audio data in one error correction block.

FIG. 6 is a schematic diagram illustrating an example of an arrangement of audio data in one error correction block.

FIG. 7 is a schematic diagram illustrating an example of an arrangement of audio data in one error correction block.

FIG. 8 is a schematic diagram illustrating an example of the content of AUX data.

FIG. 9 is a schematic diagram illustrating an example of a track format for recording video data and audio data.

FIG. 10 shows a digital V according to an embodiment of the present invention.
FIG. 2 is a block diagram illustrating a configuration of an example of a reproduction system of a TR.

FIG. 11 shows a signal format of 480I and 480P.
FIG. 3 is a schematic diagram illustrating a positional relationship between digital video signal lines.

FIG. 12 is a schematic diagram schematically showing an output order of ODD and EVEN fields in interlaced scanning during 1/2 × speed reproduction.

FIG. 13 is a block diagram illustrating an example of a configuration of a vertical filter block in more detail.

FIG. 14 is a block diagram illustrating a coefficient multiplier in further detail.

FIG. 15 is a block diagram showing examples of coefficients a1 to a5 and b1 to b5.

FIG. 16 is a time chart showing an operation of an example of the coefficient selection circuit.

FIG. 17 is a time chart illustrating an operation of an example of a center of gravity selection circuit.

FIG. 18 is a schematic diagram illustrating an example in which a reference ODD and an EVEN field are not inverted with respect to an input reproduced video signal.

FIG. 19 shows a field where the ODD and EVEN fields are inverted, and interlaced scanning, ie, 48
FIG. 11 is a schematic diagram illustrating an example of outputting in the 0I format.

FIG. 20 is a time chart of an example at the time of normal reproduction.

FIG. 21 is a diagram showing a field in which the ODD and EVEN fields are inverted at the time of variable-speed playback, and in the case of outputting in progressive scan, that is, in the 480P format.
It is a schematic diagram which shows the change of a center of gravity.

FIG. 22 is a timing chart illustrating an example of a case where a signal of an ODD field is output at a timing of an EVEN field.

FIG. 23 is a timing chart illustrating an example of a case where a signal of an EVEN field is output at a timing of an ODD field.

FIG. 24 is a time chart showing an example of processing of a signal in the 480P format.

[Explanation of symbols]

11: SYNC / ID detection circuit, 13: video decoding circuit, 14, 15: vertical filter block, 1
6, 17 ... output circuit, 18 ... output control circuit, 2
0, 23 ... system conversion circuit, 21, 24 ... vertical filter circuit, 22, 25 ... delay adjustment circuit, 30, 3
1, 34, 35 ... input switching circuit, 32, 36 ...
Mute circuits, 33, 37: synchronization signal generation / addition circuits, 50A to 50D: delay circuits, 51A to 51E
..Coefficient multiplication circuits, 52... Adders, 53A to 53E
... Coefficient selection circuit, 54A to 54E ... Multiplication circuit
56A to 56D: delay circuit, 57: selector,
58, 59: time axis conversion circuit, 60: selector, 61A, 61B: center of gravity selection circuit, 63: selector

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5C053 FA03 FA22 GA08 GA19 GB05 GB38 HA33 JA07 JA21 KA08 KA11 5C055 AA01 AA03 BA01 CA04 DA01 DA02 DA07 EA02 EA04 EA23 FA22 GA09 HA21 HA31 5D044 AB07 BC01 CC03 DE04 DE15 DE42 DE49 G

Claims (32)

[Claims] 1. A reproducing apparatus capable of reproducing video signals of a plurality of signal formats and converting and outputting the format of the reproduced video signal, wherein a video signal recorded with embedded format information is recorded. Reproducing means for reproducing from a medium; format detecting means for detecting the format information from the video signal reproduced by the reproducing means; output format instructing means for instructing a format of a video signal to be outputted; Format converting means for converting the format of the reproduced video signal. The format is automatically detected based on the format information detected by the format detecting means and the output format instruction by the output format instructing means. Switch the operation of the conversion means Reproducing apparatus being characterized in that the. 2. The reproducing apparatus according to claim 1, wherein said format conversion means is capable of mutually converting between interlaced scanning and progressive scanning. 3. The reproducing apparatus according to claim 2, wherein said format conversion means has a filter means for generating a progressive scan scan line by interpolating an interlaced scan scan line by a filter process. A reproducing apparatus wherein the means performs the interpolation using two types of filter coefficients having substantially equal frequency characteristics. 4. The reproducing apparatus according to claim 3, wherein the filter means switches between the two types of filter coefficients during a data period of one pixel of the input video signal. 5. The reproducing apparatus according to claim 3, wherein said format conversion means performs first interlaced scanning.
A reproducing apparatus characterized in that the shift of the center of gravity when outputting the field in synchronism with the second field is corrected by the filter means using the two types of filter coefficients. 6. The reproducing apparatus according to claim 1, wherein said format conversion means includes an HD format and an SD format.
A playback device characterized by being able to convert between formats. 7. The reproducing apparatus according to claim 1, further comprising output control means for muting an output for a predetermined period when a format of the reproduced video signal is changed. 8. The reproduction apparatus according to claim 1, wherein a synchronization signal corresponding to the output format specified by the output format instruction means is added to the output video signal based on the instruction of the output format instruction means. A reproducing apparatus further comprising an output control means for performing the operation. 9. A reproducing method capable of reproducing a video signal of a plurality of signal formats and converting and outputting the format of the reproduced video signal, wherein a video signal recorded with embedded format information. From the recording medium, a format detection step for detecting the format information from the video signal reproduced in the reproduction step, and an output format instruction step for instructing a format of the output video signal. And a format conversion step of converting the format of the video signal reproduced in the reproduction step. The format information detected in the format detection step and the output format in the output format instruction step Based on instructions , Playback method characterized by automatically and to switch the operation in the step of the format conversion. 10. A reproducing device for reproducing video signals recorded on a recording medium in a reproducing apparatus capable of reproducing video signals of a plurality of signal formats and simultaneously outputting the reproduced video signals in a plurality of formats. Format conversion means for converting the format of the video signal reproduced by the reproduction means; and the phase of the video signal reproduced and converted by the format conversion means, And a plurality of output means for selecting and outputting a video signal output from the format conversion means and a video signal output from the bypass means, and outputting the plurality of outputs. A reproducing device for simultaneously outputting a video signal from the means. 11. The playback device according to claim 10, wherein said format conversion means and said bypass means
The video signal is provided for a luminance component and a color component, respectively, and the plurality of output units select the format conversion unit and the bypass unit independently of the luminance component and the color component. A reproducing apparatus characterized by the above-mentioned. 12. The reproducing apparatus according to claim 10, further comprising a filter means for performing a filtering process on the video signal reproduced by the reproducing means, wherein the filter means performs format processing by the format converting means. Along with outputting the converted video signal in phase with the video signal and outputting the video signal, the plurality of output means includes a video signal output from the format conversion means, a video signal output from the bypass means,
A reproducing apparatus characterized in that a video signal output from the filter means is selected and output. 13. The reproducing apparatus according to claim 12, wherein said filter means, said format conversion means and said bypass means are respectively provided for a luminance component and a color component of said video signal, and said plurality of output means are A reproducing apparatus wherein the filter means, the format conversion means and the bypass means are independently selected for the luminance component and the color component. 14. The reproducing apparatus according to claim 10, wherein each of the plurality of output units mutes an output for a predetermined period when a format of the reproduced video signal is changed. apparatus. 15. The reproducing apparatus according to claim 10, further comprising output format instructing means for instructing a format of a video signal to be output, wherein each of said plurality of output means is instructed by said output format instructing means. A reproducing apparatus for adding a synchronization signal corresponding to the output format specified by the output format specifying means to an output video signal based on the output format. 16. A reproducing method capable of reproducing video signals of a plurality of signal formats and simultaneously outputting the reproduced video signals in a plurality of formats, wherein a video signal recorded on a recording medium is reproduced. A format conversion step for converting a format of the video signal reproduced in the reproduction step; and a format conversion in the format conversion step for the video signal reproduced in the reproduction step. A bypass step of outputting the video signal in phase with the output video signal, a plurality of video signals output from the format conversion step, and a video signal output by the bypass step. And an output step. Reproducing method characterized in that during performing output of the video signal. 17. A signal processing apparatus capable of inputting video signals of a plurality of signal formats and converting the format of the input video signal and outputting the converted video signal. Format detecting means for detecting, output format instructing means for instructing the format of the video signal to be output, and format converting means for converting the format of the input video signal, wherein the format is detected by the format detecting means. A signal processing apparatus wherein the operation of the format conversion means is automatically switched based on format information and an output format instruction by the output format instruction means. 18. The signal processing device according to claim 17, wherein said format conversion means is capable of mutually converting between interlaced scanning and progressive scanning. 19. The signal processing apparatus according to claim 18, wherein the format conversion unit has a filter unit that generates a progressive scan scan line by interpolating an interlace scan scan line by a filter process. A signal processing apparatus, wherein the filter means performs the interpolation using two types of filter coefficients having substantially equal frequency characteristics. 20. The signal processing apparatus according to claim 19, wherein said filter means switches between the two types of filter coefficients during a data period of one pixel of the input video signal. Signal processing device. 21. The signal processing apparatus according to claim 19, wherein said format conversion means performs first interlaced scanning.
A signal processing device, wherein the shift of the center of gravity when the field is output in synchronization with the second field is corrected by the filter means using the two types of filter coefficients. 22. The signal processing device according to claim 17, wherein said format conversion means includes an HD format and an SD format.
A signal processing device capable of mutually converting formats. 23. The signal processing apparatus according to claim 17, further comprising output control means for muting an output for a predetermined period when a format of the input video signal is changed. . 24. The signal processing device according to claim 17, wherein a synchronization signal corresponding to the output format specified by the output format instruction means is converted into an output video signal based on the instruction of the output format instruction means. A signal processing device further comprising output control means for adding. 25. A signal processing method capable of reproducing video signals of a plurality of signal formats and converting and outputting the format of the reproduced video signal, wherein a format embedded in the input video signal is provided. A format detection step of detecting information; an output format instruction step of instructing a format of an output video signal; and a format conversion step of converting the format of the input video signal. A signal processing method, wherein the operation of the format conversion step is automatically switched based on the format information detected in the step and the output format instruction in the output format instruction step. 26. A signal processing apparatus capable of inputting video signals of a plurality of signal formats and simultaneously outputting the input video signals in a plurality of formats, wherein the format conversion for converting the format of the input video signal is performed. Means, by-pass means for outputting the input video signal in phase with the video signal converted and output by the format conversion means, and outputting the video signal from the format conversion means; and A plurality of output means for selecting and outputting a video signal output from the means, and outputting the video signal from the plurality of output means simultaneously. 27. The signal processing device according to claim 26, wherein said format conversion means and said bypass means
The video signal is provided for a luminance component and a color component, respectively, and the plurality of output units select the format conversion unit and the bypass unit independently of the luminance component and the color component. A signal processing device characterized by the above-mentioned. 28. The signal processing apparatus according to claim 26, further comprising: a filter unit that performs a filtering process on the video signal reproduced by the reproduction unit, wherein the filter unit is configured by the format conversion unit. While outputting a video signal in phase with the video signal output by format conversion, the plurality of output means includes a video signal output from the format conversion means, and a video signal output from the bypass means. ,
A signal processing apparatus characterized in that a video signal output from the filter means is selected and output. 29. The signal processing device according to claim 28, wherein said filter means, said format conversion means and said bypass means are provided for a luminance component and a color component of said video signal, respectively, and said plurality of output means are provided. The signal processing device according to claim 1, wherein said filter means, said format conversion means and said bypass means are independently selected for said luminance component and said color component. 30. The signal processing apparatus according to claim 26, wherein each of the plurality of output units mutes an output for a predetermined period when a format of the reproduced video signal is changed. Signal processing device. 31. The signal processing device according to claim 26, further comprising output format instruction means for instructing a format of an output video signal, wherein each of the plurality of output means is provided by the output format instruction means. A signal processing device for adding a synchronization signal corresponding to an output format specified by the output format specifying means to an output video signal based on the specification. 32. A signal processing method capable of inputting video signals of a plurality of signal formats and simultaneously outputting the input video signals in a plurality of formats, wherein the format of the input video signal is converted. And a bypass step of outputting the input video signal in phase with the video signal that has been format-converted and output in the format conversion step, and output by the format conversion step. And a plurality of output steps for selecting and outputting the video signal and the video signal output by the bypass step, wherein a video signal is output simultaneously from the plurality of output steps. Signal processing method.