JP2001282753A - Fine grain pci slot controller for partitioned system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a system and a method for partitioning and assigning an individual PCI slot inside a primary host bridge(PHB) in a partitioned computer system. SOLUTION: This system includes an epoch-making PHB system for reducing the competition of system devices among plural operating systems to compete for the same resource by assigning the PCI slot to only one block within a given time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates generally to microprocessor computer systems, and more particularly, to resource allocation among processors in a partitioned multiprocessor system. More particularly, the preferred embodiment relates to a system for partitioning and allocating individual PCI slots in a multiprocessor computer system.

[0002]

2. Description of the Related Art Multiprocessor computer systems are well known in the art and provide increased processing power by allowing processing tasks to be divided among several different system processors.
In a conventional system, each processor has access to all system resources. That is, all system resources, memory devices, input / output devices, etc.
Shared between all system processors. Typically, some of the system resources can be partitioned between processors. For example, each processor can access a shared memory, while at the same time dividing this memory so that each processor has its own working space.

Recently, symmetric multiprocessors (SM)
P) The system is partitioned so that it behaves as multiple independent computer systems. For example,
A single system with eight processors can be configured to treat each of the eight processors (or multiple groups of one or more processors) as a separate system for processing. Each of these "virtual" systems will have its own copy of the operating system and can be independently assigned work, and together act as a processing cluster providing faster processing and increased reliability. You can also. Typically, a multi-processor system also has a "service" processor, which includes system configuration and data routing to and from specific processors on shared buses and devices. , Manages the startup and operation of the entire system.

When several virtual systems are configured to operate as a cluster in a single SMP system, each cluster node communicates with each other in the SMP and uses a constant (Quorum)
Software support must be provided in order to be able to perform negotiations and validations, send "heartbeats", and perform other quorum functions. When this is done, if one of the processors fails, the node becomes unavailable to the cluster, but the job assigned to that node is transferred to the remaining processors (nodes) using standard cluster technology. A) can be re-assigned between.

Typically, when an SMP system is divided into multiple virtual systems, each virtual system has its own copy of the operating system, and the same operating system is used for each virtual system. Implementing resource allocation between processors is relatively easy because each processor is running the same operating system.

[0006] However, there is currently a market demand for the ability to run multiple operating systems between several virtual systems. For example, a user runs a UNIX® variant operating system in one compartment,
A second partition may wish to run a Windows® based operating system. This desire raises certain issues related to resource allocation. That is, the partitioning of memory between partitions in an SMP system is generally supported by hardware,
The allocation of other resources, such as peripheral component interconnect (PCI) slots, is managed by the operating system. Since multiple partitions may be running different operating systems, a means is needed to allocate system resources that are not based on the operating system. Specifically, there is a need for an operating system independent solution that allows system resources, such as PCI slots, to be allocated among multiple partitions in an SMP computer system.

[0007]

SUMMARY OF THE INVENTION It is, therefore, one object of the present invention to provide a system for operating a multiprocessor computer system.

Another object of the present invention is to provide a multiprocessor system.
A system for improving resource allocation in a computer system.

It is yet another object of the present invention to provide a system for partitioning and allocating individual PCI slots in a multiprocessor computer system.

[0010]

The above-mentioned object is achieved as described below. Primary Host Bridge in a partitioned computer system
A system for partitioning and allocating individual PCI slots within a (PHB) is provided. Allow a PCI slot to be assigned to only one partition at a given time,
Includes an innovative PHB system that thereby reduces system device contention between multiple operating systems competing for the same resources.

[0011]

Referring now to the drawings, and more particularly to FIG. 1, there is shown a block diagram of a data processing system in which a preferred embodiment of the present invention may be implemented. The data processing system 100 may be, for example, one of the desktop model personal computers available from International Business Machines Corporation of Armonk, NY, USA. Data processing system 100 includes processors 101 and 102, which in this exemplary embodiment are connected to level two (L2) caches 103 and 104, respectively, which are connected to system bus 106.

The system bus 106 includes a system memory 108 and a primary host bridge (PHB) 12.
2 is also connected. PHB 122 couples I / O bus 112 to system bus 106 and relays and / or transfers data transactions from one bus to another. In the exemplary embodiment, data processing system 100 includes input / output bus 112
A graphics adapter 118 connected to the
Receive user interface information for display 120. Peripheral devices such as a non-volatile storage device 114, which may be a hard disk drive, and a keyboard / pointing device 116, which may also include a conventional mouse, trackball, etc.,
stry Standard Architecture (ISA) Bridge 121
Is connected to the input / output bus 112 via the. PHB122
Are also connected to the PCI slot 124 via the input / output bus 112.

The exemplary embodiment shown in FIG. 1 is provided merely to illustrate the invention, and those skilled in the art will appreciate that numerous variations in both form and function are possible. There will be. For example, the data processing system 100
Is a compact disk read-only memory (CD-R
OM) or digital video disk (DVD) drive, sound card, audio speaker,
And many other optional components. All such variations are considered to be within the spirit and scope of the present invention. The data processing system 100 and the following exemplary partitioned computer system are merely illustrative for purposes of illustration and are not meant to imply architectural limitations.

Referring to FIG. 2, there is shown a high level block diagram of a partitioned computer system according to a preferred embodiment of the present invention. This figure shows a computer including three microprocessors (μP) 204-206 and five PCI slots 208-212.
A system 200 is shown. PCI subsystem 20
7 comprises five PCI slots and a PCI host bridge 201. In this figure, the system is divided into two compartments, and compartment 202 includes microprocessor 20
4 and 205 and PCI slots 208 and 209
And PHB201. The partition 203 includes a microprocessor 206, PCI slots 210 to 212,
PHB201. Note that both partitions share the same PHB, which controls the partitioning of PCI slots.

Referring now to FIG. 3, there is shown a more detailed block diagram of an eight processor partitionable computer system according to a preferred embodiment of the present invention. In this figure, eight processors 301 to 308 include an address bus 323, 325 and a data bus 324, 3
It is shown connected to a symmetric multi-processor configuration using a core chipset 320 including an address controller 321 and a data controller 322 connected to processors 301-308 via 26 crossbars.
In a preferred embodiment, these processors are Intel ^(R)
It is a Pentium II ^(R) class processor.

Core logic 320 includes a front side bus of each processor for memory subsystems 330, 331 and an input / output bus 350, including an address bus 327 and a data bus 328.
Interface. The core logic implements a snoop filter 329 designed to limit the amount of snoop transactions between any two processor buses.
Including. Central memory subsystems 330, 331
Are shown as two separate ports that can be accessed independently and simultaneously.

The input / output bus 350 is used to support a high-numbered PCI bus to support a scalable high-performance system.
Provides the ability to attach slots 314-317. Up to four PCI host bridges 310, all interfacing with peer PCI bus segments
313 are supported.

In a preferred embodiment, all PCI slots have hot plug capability. PHB 310-3
13, the PCI hot plug control logic and the partition control logic are integrated in the preferred embodiment
An external isolation circuit, T, can be used to separate PCI slots for each transaction and implement fine-grained input / output partitioning. Each partition can own from one to all system processors and zero to all PCI slots.

This figure also shows various input / output devices connected via the PHB 310. These include
Includes a SCSI controller 340, LAN connection 341, and graphics adapter 342. The ISA bridge 343 may include, among other things, a keyboard, mouse, serial port, parallel port, audio device, floppy disk, CDROM, and any legacy input / output device 34 that may include a real-time clock.
4 is used to connect.

Referring to FIGS. 4-6, there is shown an improved PCI host bridge that provides the ability to partition PCI by slot in accordance with a preferred embodiment of the present invention.

PHB 400 provides separate request queues for outbound and inbound transactions that occur simultaneously in both directions. Outbound transactions are performed by agents on the I / O bus 401, ie, from core logic (instead of one of the eight processors), or by another PCI memory transaction in peer-to-peer applications. Start from PHB. An inbound transaction is initiated by an agent on PCI bus 403 and directed to system memory, or PCI memory on a peer PCI bus segment behind another PHB. Among other important features, PHB provides PCI arbitration, support for hot-plug PCI live insertion / removal, and partitioning of PCI slots for all initiator agents on that bus segment. Bring.

The PHB performs posted write and deferred responses for outbound transactions initiated from the I / O bus, and performs post-write and deferred transactions for inbound transactions initiated from the PCI bus. Outbound memory writes are always posted,
I / O writes are optionally posted or deferred, and both I / O reads and memory reads cause a deferred response. A deferred response is a transaction that is removed from the processor's in-order queue and placed in a deferred transaction queue, notifying the processor that the transaction will be completed later. Means PHB 400 defers the deferred transaction to its outbound request queue 42.
6, when a read or write transaction is completed on the PCI bus, a deferred reply that the transaction is completed will be delivered to the initiating processor. Inbound memory writes are always posted, and memory reads are delayed. A deferred inbound read transaction means that the PHB places the transaction in its PCI inbound buffer 429 and terminates the PCI-initiated transaction with a retry. The transaction is transferred to the I / O bus 401 for reading data, and until the PCI transaction is retried.
It is placed in the inbound request queue 428. After the transaction has been retried, the PHB completes the transaction with the data.

I / O Bus Transaction An I / O bus transaction initiated from one of the eight processors includes a resource address (input / output or memory), bus transaction type information, and an initiator partition ID. Called sideband signal 450
including. These sideband signals are generated in the core logic based on which processor on the front side bus initiated the transaction targeted for that PCI, and the partition whose initiator is a member is assigned to the PHB 40
Identify for 0. Front Side Bus (FS
B) The requesting agent is a distributed rotational priority bus arbiter.
ation scheme), and the core logic accordingly identifies the initiator of any front side bus transaction. Each processor is assigned to one partition defined by the partition ID. The partition ID is a new programmable register file built into the core logic to support sideband signal generation, which enables the innovative partitioning technique of the present invention.

The partition ID register file is configured and static at or before system initialization. That is, there is no change unless the system is rebooted. The core logic concatenates the generated initiator partition ID sideband signal with the normal transaction on the I / O bus. The number of partitions supported is equal to the number of processors supported, so the partition ID register file contains 3 to support 8-split SMP.
Any width of bits is sufficient, and the initiator partition ID sideband bus is three coded signals that identify one of the eight partitions.

PHB 400 receives the initiator partition ID sideband signal along with the I / O bus transaction and determines which PCI on its peer PCI bus segment.
Determine if slot resources should be made available as members of the targeted partition. The PHB includes a PCI slot partition descriptor as part of its PCI configuration space,
This descriptor contains the following programmable information and is configured at or after system initialization.

Target Partition ID for PCI Slots The target partition ID supports 0 to "n" partitions, where "n" is the number of processors supported in the system. Each partition can be assigned a minimum of 0 and a maximum of all PCI slots. The PCI slot and all of its target resources may be members of only one partition in this embodiment.

I / O and memory for PCI slots
Address Resource Decode Range Registers The PHB uses these range registers to positively decode address resources requested from PCI slots as transaction targets. Each set of range registers will include a start (base) address and an end address. The I / O registers will support an allocatable range of at least 256 bytes from the system address map, and the memory registers will support an allocatable range of at least 1MB from the system address map. The number of discrete address resources supported per PCI slot requires a minimum of two I / O and two memory range register pairs. These registers are used to positively decode the PHB so that the PHB receives a transaction targeted at a particular I / O partition initiated on the I / O bus.

Before the PHB can positively accept and respond as the target of an outbound transaction initiated on the I / O bus, the following conditions must occur: The following is the positive partition response of an outbound transaction
(PPR). 1. The I / O bus initiator partition ID sideband for the current transaction must match one of the target partition IDs supported by the PHB. 2. The I / O bus transaction resource address (I / O or memory) must be within the address range of the positive decode resource target associated with its matching target partition.

If one of the above conditions is not met for a positive partition response, the PHB ignores the I / O bus transaction and assumes that another PHB residing on the I / O bus is the intended target. Will do. The core logic must implement a bus transaction watchdog timer if the software or hardware fails and does not receive a response. If the bus transaction times out, the core logic will return a target abort hard failure response
d fail response) to the initiating processor on the front side bus.

The following summarizes various responses issued by the PHB for transactions initiated on an outbound I / O bus with a positive partition response, in connection with FIG.

Outbound Memory Writes Memory writes are posted to the outbound request queue 426 and then after the entry is available.
Move to PCI outbound buffer 427. The transaction is now removed from the outbound request queue 426. The PCI initiator / target control logic 425 indicates when a transaction has been placed in the PCI outbound buffer 427
Request ownership of the PCI bus via arbiter 421,
It also forwards the PCI outbound initiator partition ID to partition control logic 423 to determine which PCI slot resources are members of this partition and make their corresponding PCI slots available. While some devices may not be the intended goal, others may need to snoop transactions on a particular device and shadow its contents,
All slots in a partition on the same PCI bus are made available. The PCI partition control logic 423 is configured for each PCI attached to the PHB PCI peer bus segment.
For each slot, the PCI outbound initiator partition ID and the target partition ID are compared and compared. P
No cycles are wasted due to CI arbitration. The arbiter grants the bus to the next owner during the current transaction, but the next owner does not take ownership until it detects that its PCI bus is idle. .

In the presently preferred embodiment, the PCI bus guarantees that no contention will occur and, if fast back-to-back transactions can be performed, at least one idle bus state between transactions Note that this requires There are two types of fast back-to-back transactions defined by the PCI specification, the first being when the master's goal for the current transaction is the same as the goal of the previous write transaction. The second type, implemented, requires that the fast back-to-back possible goal ensure that there is no contention in the target response signal. The PCI specification requires that this second mechanism can be supported only via configuration bits in the PCI command register. In a presently preferred embodiment, for the same device, the second mechanism is not enabled and the fast back-to-
It needs to be able to support back transactions.

A PCI idle clock is required as a turnaround cycle to prevent contention when one PCI agent stops driving one signal and another starts driving the signal. During this turnaround cycle, the FET isolation switch 41
0-414 are enabled / disabled, so the fine-grain PCI of the slot on the same peer PCI bus segment
To implement partitioning, the preferred embodiment requires an idle bus clock during every bus transaction. Partition control logic 423 indicates to the PCI hot plug control logic which PCI slots to make available for each transaction. After the FET switch is enabled during the idle turnaround clock cycle, the PHB takes ownership of the PCI bus. The PHB initiates a memory write transaction and the target device on the available PCI slot receives the data. If data is not successfully delivered to the PCI target due to PCI target abort or parity error, a machine check abort (Machine
Check Abort (MCA) is generated.

Outbound I / O writes, which are optionally posted, have the same P as outbound memory writes.
Has HB response.

Outbound I / O writes are optionally deferred I / O writes are optionally deferred in the outbound request queue 426 and then the PCI outbound buffer after the entry becomes available. 427
Will be moved to. The transaction is not removed from the outbound request queue 426 at this point, the write on PCI bus 403 is complete, and PHB 40
0 stays in the queue until it delivers a deferred reply transaction on I / O bus 401. The PCI initiator / target control logic 425 communicates with the PCI bus 40 via the PCI arbiter 421 when a transaction is placed in the PCI outbound buffer 427.
3 and transfers the PCI outbound initiator partition ID to the partition control logic 423,
Determine which PCI slot resources are members of this partition and their corresponding PCI slots 440-44
Enable 4 The PCI partition control logic 423 determines whether P
For each of the PCI slots 440-444 attached to the HB PCI peer bus segment, the PCI outbound initiator partition ID and the target partition ID are matched and compared. PCI arbiter 421 is PHB
, And the PHB takes ownership when it detects that its PCI bus is idle. F
After ET switches 410-414 are enabled during an idle turnaround clock cycle, the PH
B400 obtains ownership of PCI bus 403. PH
B initiates an I / O write transaction and the target device on the available PCI slot receives the data. If the data was successfully delivered to the PCI target, successful completion by a deferred reply transaction is returned. If data is not successfully delivered to the PCI target due to PCI target abort or parity error, the response phase of the deferred reply transaction will indicate a hard failure response and a machine check abort (MCA) will be generated.

Outbound memory or input reads are deferred All read transactions are deferred in the outbound request queue 426, and then, after the entry becomes available, the PCI outbound buffer 4
27. The transaction is not removed from the outbound request queue 426 at this point, and the read on PCI bus 403 is complete and PHB4
Until 00 issues a deferred reply transaction with the read data provided on I / O bus 401
Stay in the queue. PCI initiator / target control 425 logic requires ownership of PCI bus 403. PCI initiator / target control logic 425 determines whether a transaction is to be processed by PCI outbound buffer 427.
When it is entered, it requests ownership of the PCI bus 403 via the PCI arbiter 421 and provides the PCI outbound initiator partition ID with the partition control logic 42.
3 to determine which PCI slot resources are members of this partition and make their corresponding PCI slots 440-444 available. The PCI partition control logic 423 compares and compares the PCI outbound initiator partition ID with the target partition ID for each of the PCI slots 440-444 attached to the PHB PCI peer bus segment. The PCI arbiter 421 authorizes the bus to PHB,
Acquires ownership when it detects that the CI bus is idle. The PHB takes ownership of the PCI bus after the FET switches 410-414 are enabled during the idle turnaround clock cycle. P
The HB initiates a read transaction and the target device on the available PCI slot provides the data. If the data was successfully read from the PCI target, the deferred reply transaction has completed successfully and the read data is provided during the data phase. If data is not successfully read from the PCI target due to a PCI target abort or parity error, the response phase of the deferred reply transaction will indicate a hard failure response and a machine check abort (MCA) will be generated. .

Positive Partition Response (PPR) as the target of an inbound transaction initiated on the PCI bus
Is much simpler than for outbound transactions. The PCI bus initiator section ID is
Generated internally in the PHB PCI arbiter 421.
PCI arbiter 421 is point-to-point, ie, intermediate logic or isolation FETs 410-414.
Without, it has signals REQ0: 4 and GNT0: 4 connected to PCI slots 440-444, respectively.
REQ0: 4 is a PCI bus request line for each of the slots 440 to 444, and GNT0: 4 is a PCI bus grant signal for these slots. The arbiter receives the request, grants ownership, and otherwise checks the status of each slot when a given slot is turned off and otherwise separated from the PHB. These signals must be neither bus connected nor separated. The arbiter grants the bus to the next owner during the current transaction, but the PCI agent
It does not take ownership until it detects that the PCI bus has gone idle. The PCI bus initiator partition ID is simply the name of any PCI slot 440.
444 are granted ownership of the bus, and
It is generated based on which I / O partition is a member of the CI slot partition descriptor. Partition control logic 4
23 receives the PCI bus initiator partition ID,
Compare it to all target partition IDs supported by PHB. When supporting peer-to-peer transaction communication, all slots in a partition on the same PCI bus are enabled. Partition control logic 423
Which PC to the PCI hot plug control logic
Indicates whether the I slot is enabled. After the FET switches 410-414 are enabled during the idle clock cycle, the PCI bus initiator takes ownership of the PCI bus.

Inbound memory writes are posted Memory writes are posted in the PCI inbound buffer 429 and will then be moved to the inbound request queue 428 after the entry is available. The transaction is now removed from PCI inbound buffer 429. I / O bus or initiator / target control 424 logic requests ownership of I / O bus 401 when a transaction is placed in inbound request queue 428. PHB
Initiates a memory read transaction on the I / O bus, targeting system memory or PCI memory on another PHB after ownership of the bus is granted.

Inbound memory reads are delayed In this embodiment, the memory reads are PCI SIG,
2575 NE Kathryn St # 17 Hillsboro, OR 97124
And is supported by a deferred transaction mechanism defined by the PCI 2.1 specification, which is incorporated herein by reference. The PHB will latch all PCI bus transaction information, place the inbound memory read into its PCI inbound buffer 429, and terminate the PCI transaction with a retry. The transaction then moves to the inbound request queue 428 after the entry becomes available, at which point the PCI transaction is removed from the PCI inbound buffer 429. I / O bus initiator / target control logic 42
4 indicates that the transaction is an inbound request queue 4
28, it requests ownership of the I / O bus 401. After the PHB is granted ownership of the bus, it initiates a memory read transaction on the I / O bus that targets either system memory or PCI memory. When read data is returned, the PHB will maintain coherency of the data in the inbound request queue 428. The agent of the PCI bus
When retrying to read the same memory location as the deferred transaction, the PHB moves the data into the PCI inbound buffer 429 and responds with that data to complete the deferred transaction on the PCI bus.

System Initialization and Configuration The preferred method of initializing and configuring a partitioned computer system is for the system's service processor to establish partitioning. The partition descriptor is programmed during basic system configuration. In the preferred method shown in FIG. 6, after a power-on reset or hard boot (step 610), the service processor begins system initialization and the processors are still held in reset (step 620). ). Among the tasks performed by the service processor is the establishment of system partitioning. Depending on whether it is configured to use the default partitioning configuration (step 6
30), the service processor uses the stored information (step 640) or obtains segmentation information from the operator by interaction (step 650). The service processor establishes a basic memory map for the system containing the locations of the PHBs (step 660) and programs the partitioning information into partition descriptor registers (step 670). The system processors are then started (step 680), after which each processor operates in its assigned partition using its assigned PCI slot (step 690).

Partition Descriptor The partition descriptor shown in FIG. 5 includes partition membership information. In this table, each slot entry contains the number of the partition to which the slot belongs. In this embodiment, each slot belongs to one (and only one) partition.

Referring now to FIGS. 7 and 8, there is shown a simplified flowchart of an exemplary PHB process according to a preferred embodiment of the present invention (a more detailed process has been described above). FIG. 7 shows a processor-initiated PC
This shows I writing. After the processor has begun writing (step 700), the PHB receives a write request (step 705) and receives the partition identifier of the initiating processor (step 710). The PHB then compares the partition identifier and the partition descriptor for each of its slots (step 715). The PHB uses each PCI with a partition descriptor indicating that it belongs to the same partition as the initiating processor.
Turn on (make available) the slot (step 72)
0), disable each PCI slot that does not belong to this partition (step 725). In the preferred embodiment, this is done using the FET shown in FIG. Finally,
The write request is passed to the target PCI device (step 730).

FIG. 8 illustrates a memory write initiated by a PCI device. In this figure, the PH starts after the PCI device starts writing (step 750).
B receives the request (step 755), reads the partition descriptor for the PCI slot (step 760), and determines if it belongs to the partition. After doing this,
The PHB enables all PCI slots belonging to the partition (step 765) and disables all slots not belonging to the partition (step 770). Finally, a write request is passed from the PHB to the I / O bus (step 775).

Of course, many modifications and variations can be made to the disclosed system without departing from the spirit and scope of the invention. For example, in the above description
Although particular emphasis is placed on the allocation of Peripheral Component Interconnect (PCI) connections, these techniques, including the technique of exclusive partitioning and selective isolation of slot connections, apply to several different computer architectures and systems. Can be applied.
Of course, other variations are within the capabilities of those skilled in the art and are intended to be included within the scope of the appended claims.

In summary, the following is disclosed regarding the configuration of the present invention.

(1) a plurality of system processors divided into a plurality of processing partitions each having at least one system processor and a unique partition descriptor;
At least one memory operatively connected to be written and read by the processor; an input / output controller connected to communicate with the system processor; and at least one processing partition. A plurality of input / output connections managed by the input / output control device, and a plurality of input / output devices connected to the input / output connections.
A computer system, wherein only the I / O controller permits communication between a system processor and I / O connections belonging to the same processing partition. (2) The system according to (1), wherein when a processor belonging to a given processing partition is communicating with an I / O device, all I / O connections not belonging to the partition are separated from the processor. (3) The system according to (1), wherein the separation is performed using a field effect transistor. (4) at least one system processor; a memory connected to be written and read by the system processor; an input / output controller connected to communicate with the memory and the processor; A computer system comprising at least one peripheral device communicatively connected to the input / output controller via one of the device connections of the input / output controller. Receiving from the system processor a request to write to the I / O controller; receiving at the I / O controller a partition identifier corresponding to the system processor; and determining whether the connection belongs to a group corresponding to the partition identifier. Turn on at least one of the plurality of connections according to whether System performing the steps, the step of passing said write request to said device. (5) The system according to (4), wherein the device connection is a PCI slot. (6) The system according to (4), wherein the device connection is separated from the input / output control device by a field effect transistor when the device connection is turned off. (7) The system according to (4), wherein all the connections that do not belong to the group are turned off. (8) a plurality of system processors;
At least one memory connected to be written and read by a processor, an input / output controller connected to communicate with the memory and the processor, and via one of a plurality of device connections A computer system including at least one peripheral device communicatively connected to the input / output controller, wherein the input / output controller receives a request from the device to write to memory. Reading a partition descriptor corresponding to the device connection with the input / output control device, and turning on at least one of the device connections according to whether the device connection belongs to a group corresponding to the partition descriptor. And connecting all the device connections that do not belong to the group. System performing the steps of the off; and passing said write request to said memory from said device. (9) The system according to (8), wherein the device connection is a PCI slot. (10) The system according to (8), wherein the device connection is separated from the input / output control device by a field effect transistor when the device connection is turned off. (11) a plurality of system processors, at least one memory connected to be written and read by the system processor, and an input / output controller connected to communicate with the memory and the processor. , A computer system including at least one peripheral device communicatively connected to the input / output controller via one of a plurality of device connections, each of the plurality of system processors. Assigning each of the device connections to one of the processing partitions; identifying to which processing partition each device connection belongs; Storing information to be stored in a memory;
Passing communication between the system processor and device connections belonging to the same processing partition, and disallowing communication between the system processor and device connections not belonging to the same processing partition. (12) When the system processors belonging to a given processing partition are communicating via a device connection belonging to the same processing partition, all device connections not belonging to the processing partition are turned off. System. (13) The system according to (11), wherein the device connection is separated from the input / output control device by a field effect transistor when the device connection is turned off.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an exemplary computer system according to a preferred embodiment of the present invention.

FIG. 2 is a high-level block diagram illustrating a partitioned computer system according to a preferred embodiment of the present invention.

FIG. 3 is a detailed block diagram illustrating an eight-processor computer system according to a preferred embodiment of the present invention.

FIG. 4 is an improved PC according to a preferred embodiment of the present invention.
FIG. 3 illustrates an I-host bridge.

FIG. 5 illustrates a partition descriptor according to a preferred embodiment of the present invention.

FIG. 6 is a flowchart illustrating a system configuration process according to a preferred embodiment of the present invention.

FIG. 7 illustrates a processor initiated PCI write according to a preferred embodiment of the present invention.

FIG. 8 illustrates a memory write initiated by a PCI device according to a preferred embodiment of the present invention.

[Explanation of symbols]

 301 CPU 310 PCI Host Bridge 314 32-bit 33 MHz PCI Slot 320 Core Logic 321 Address Control 322 Data Control 323 Address Bus 324 Data Bus 329 Snoop Filter 330 Memory 342 Graphics Adapter 343 ISA Bridge 344 Legacy I / O 350 I / O bus

 ────────────────────────────────────────────────── ─── Continued on front page (72) Inventor Richard Bearkovski 98052 Redmond, Washington One Hundred Fifty Eights Place Northeast 8336 (72) Inventor Patrick M. Brand United States 27613 Raleigh, North Carolina Willow Wood Wood Coat 8904 F term (reference) 5B014 EB01 FB04 GD05 GD22 GD37 HA04 HA05 HB06 HB13 5B045 EE08 EE11 KK06 5B098 AA10 GA02 GD03 GD06 GD14

Claims (13)

[Claims] A system processor divided into a plurality of processing partitions each having at least one system processor and a unique partition descriptor, operable to be written and read by the processor. At least one memory connected thereto, an input / output controller connected to communicate with the system processor, and a plurality of the input / output controllers managed by the input / output controller, each assigned to at least one of the processing partitions. A computer system comprising: an input / output connection; and a plurality of input / output devices connected to the input / output connection, wherein only the input / output controller is a system processor;
A computer system that allows communication between I / O connections belonging to the same processing partition. 2. The system of claim 1, wherein when a processor belonging to a given processing partition is communicating with an I / O device, all I / O connections not belonging to that partition are separated from the processor. . 3. The system of claim 1, wherein said isolation is performed using a field effect transistor. At least one system processor; a memory connected to be written and read by the system processor; and an input / output controller connected to communicate with the memory and the processor. A computer system comprising: at least one peripheral device communicatively connected to the input / output controller via one of a plurality of device connections. Receiving from a system processor a request to write to a peripheral device; receiving, at the I / O controller, a partition identifier corresponding to the system processor; At least one of the plurality of connections according to whether
Turning on one, and passing the write request to the device. 5. The system of claim 4, wherein said device connection is a PCI slot. 6. The system of claim 4, wherein said device connection is isolated from said input / output controller by a field effect transistor when said device connection is turned off. 7. The system of claim 4, wherein all the connections that do not belong to the group are turned off. 8. A plurality of system processors, at least one memory connected to be written and read by the system processor, and an input / output control connected to communicate with the memory and the processor. A computer system, comprising: an apparatus; and at least one peripheral device communicatively coupled to the input / output controller via one of a plurality of device connections. Receiving a request to write to memory from the device; reading a partition descriptor corresponding to the device connection at the input / output controller; and setting the device connection to a group corresponding to the partition descriptor. Turn on at least one of the device connections according to whether they belong System performing the steps, a step of turning off all the devices connected which do not belong to the group, the step of passing said write request to said memory from said device. 9. The system of claim 8, wherein said device connection is a PCI slot. 10. The system of claim 8, wherein said device connection is isolated from said input / output controller by a field effect transistor when turned off. 11. A plurality of system processors, at least one memory connected to be written and read by the system processor, and an input / output control connected to communicate with the memory and the processor. A computer system comprising: an apparatus; and at least one peripheral device communicatively connected to the input / output controller via one of a plurality of device connections, the plurality of system processors. Assigning each of the device connections to a processing partition; assigning a respective partition identifier to the processing partition; assigning each of the device connections to one of the processing partitions; and to which processing partition each device connection belongs Storing information identifying the System running allow communication between the device connection belonging to the same processing compartment the-time processors (pass), and a step that does not allow communication between the device connection not belonging to the same processing compartment the system processor. 12. When a system processor belonging to a given processing partition is communicating via a device connection belonging to the same processing partition, all device connections not belonging to that processing partition are turned off. 12. The system according to 11. 13. The system of claim 11, wherein said device connection is isolated from said input / output controller by a field effect transistor when turned off.