JP2001273338A - Operation timing verification method for semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily and accurately verify the operation timing of a semiconductor integrated circuit containing a macro. SOLUTION: This method includes step S21 to acquire the configuration information on a semiconductor integrated circuit and where this circuit includes a macro having an external terminal and an external circuit connected to the external terminal and to provide a boundary delay table, steps S22 and S23 where the boundary delay table shows dependency defined between the physical value given to the external terminal and the boundary delay time and the physical value is calculated from the characteristic of the external circuit, step S24 to calculate the boundary delay time from the physical value and by referring to the boundary delay table and steps S21, S25, S26 and S27 to verify the operation timing of the semiconductor integrated circuit by consindering that the signals passing through the external terminals (DIN, CLKIN, DOUT) are delayed by a degree equivalent to the boundary delay time when they pass through these terminals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for verifying operation timing of a semiconductor integrated circuit. The present invention particularly relates to a method of generating delay information at an input / output terminal of a macro and a method of using the method in a method of verifying operation timing of a semiconductor integrated circuit.

[0002]

2. Description of the Related Art It is desired to efficiently and accurately perform timing simulation of a semiconductor integrated circuit. Efficient timing simulation and
A timing simulation method for a semiconductor integrated circuit aiming at high accuracy is disclosed in Japanese Patent Laid-Open Publication No.
-319776).

FIG. 20 is a flowchart showing a known timing simulation method. The known timing simulation method includes a procedure (S101) of performing a circuit simulation. In the procedure for executing the circuit simulation (S101), the netlist 11
The simulation of the circuit is performed based on 1 and a simulation result 112 is generated.

In circuit simulation S101, FIG.
A circuit simulation is performed based on the circuit model shown in FIG. In FIG. 21, reference numeral 120 denotes an inverter. The inverter 120 is a cell in which the delay parameter is characterized. 121 is
This is an input node of the inverter 120. Reference numeral 122 denotes an output node of the inverter 120. Reference numeral 123 denotes an input waveform at the input node 121. 124 is an approximate waveform. The approximate waveform 124 is obtained by approximating the output waveform at the output node 22 to a straight line. Reference numeral 125 denotes a load capacitance connected to the output node 22.

[0005] The netlist 111 is stored in the inverter 120
And information on the load capacity 125. In the procedure for executing the circuit simulation (S101), the simulation result 10 based on the netlist 111 is used.
2 is calculated. The simulation result 112 is the first
Delay time including _{T pd0} and second delay time _{T pd1.} The first delay time T _pd0 is, as shown in FIG. 21, from the rising start edge of the input waveform 123,
This is a delay time until the falling start edge of the approximate waveform 124. The second delay time T _pd1 is a delay time from the rising start edge of the input waveform 123 to the falling end edge of the approximate waveform 124.

The procedure for executing a circuit simulation (S
101), coefficient fitting is performed (S
102). In the coefficient fitting (S102), a coefficient included in a predetermined delay model formula is calculated from the simulation result 102. The predetermined delay model formula is
The inclination T _i of the input waveform is a function of the capacitance value C of the load capacitance. The coefficient of each term represented by the product of T _i and C is
It is calculated based on the first delay time _{T pd 0} and the second delay time _{T pd1.}

[0007] The calculated coefficient is a delay parameter 114
Is registered in the delay library. Circuit simulation S10 for all cells used in circuit design
1 and coefficient fitting S102 are performed.

After the coefficient fitting (S102), a timing simulation (S102) is performed. At a timing simulation (S103), first, the inclination T _i of the input waveform of each cell included in the circuit to be timing simulation, and the capacitance value C of the load capacitance, and a coefficient included in the delay parameter 114, above , The first delay time T _pd0 and the second delay time T
Delay time _{T pd1} of is calculated. First delay time T
_{From the pd0} and the second delay time _Tpd1 , the delay time inside the cell and the slope of the output waveform of each cell are calculated.

In recent years, macros are sometimes used in the layout of semiconductor integrated circuits. A macro is composed of a group of cells. A group of cells constituting a macro constitutes a large-scale circuit having a predetermined function. The macro is
For example, it includes circuits such as a CPU and a RAM. The use of macros is based on the recent increase in the scale of semiconductor integrated circuits and the demand for more efficient design of semiconductor integrated circuits. By connecting macros having required functions, a large-scale semiconductor integrated circuit can be easily designed.

As described above, in the case of designing a large-flowered semiconductor integrated circuit using a macro, in order to perform a timing simulation of the circuit, the method disclosed in the above-mentioned publication uses the method disclosed in the above-mentioned publication. To characterize the delay parameters (extract characteristics) for the cells, calculate the delay time for each cell, and calculate the delay time of the entire semiconductor integrated circuit including the macro based on these. Become.

At this time, since the macro itself is used independently for various semiconductor integrated circuits, the circuit information on the internal side including the cell closest to the input / output terminal in the macro is considered as the delay parameter of the macro. In a semiconductor integrated circuit in which a macro is actually arranged, the specific wiring of the semiconductor integrated circuit, such as the wiring from the cell closest to the input / output terminal in the macro to the outer part, and the resistive and capacitive components attached to the terminal. There is a problem that circuit information depending on a simple circuit configuration cannot be represented in a general form in a macro delay parameter.

As a result, when a delay time is evaluated by timing simulation after designing a large-scale semiconductor integrated circuit using a macro, a portion surrounding the macro cannot be evaluated. There is a problem that the accuracy of the method is insufficient.

[0013] Therefore, as an alternative method, a large-scale semiconductor integrated circuit including a macro is obtained by assuming that one macro is to be loaded and determining the delay time between its input and output terminals in advance when forming the macro. When designing the circuit, a method of calculating the delay time of the entire circuit using the inter-terminal delay time can be considered.

However, in this method, when only a normal logic circuit is included in the macro, the delay time can be obtained without any problem.
Alternatively, if there is a RAM, their states are not uniquely determined, so the path between input and output is not uniquely determined, and therefore the delay time is not uniquely determined. As a result, there is a problem that an enormous list of paths and delay times according to conditions must be prepared in order to obtain the inter-terminal delay time.

It is desired to accurately and simply verify the operation timing of a semiconductor integrated circuit including a macro.

[0016]

SUMMARY OF THE INVENTION An object of the present invention is to accurately and simply verify the operation timing of a semiconductor integrated circuit including a macro.

[0017]

Means for solving the problem are expressed as follows. The technical items appearing in the expression are appended with numbers, symbols, and the like in parentheses (). The numbers, symbols, and the like refer to technical matters constituting at least one of the embodiments of the present invention, particularly, technical matters expressed in the drawings corresponding to the embodiments. The reference numbers, reference symbols, and the like attached to are the same. Such reference numbers,
Reference symbols clarify the correspondence and bridging between the technical matters described in the claims and the technical matters in the embodiments. Such correspondence / bridge does not mean that the technical matters described in the claims are interpreted as being limited to the technical matters of the embodiments.

According to the method for verifying operation timing of a semiconductor integrated circuit of the present invention, a step (S21) of obtaining circuit configuration information of a semiconductor integrated circuit (70) is provided. Here, the semiconductor integrated circuit (70) is connected to an external terminal (DIN, CLKIN, DOU
T) and external terminals (DIN, C
LKIN, DOUT) (71a, 7
1b, 72a, 72b, 74a to 74d) for providing a boundary delay table (2, 3) (S21), wherein the boundary delay table (2, 3)
Is a physical quantity (t rf DIN ) given to external terminals (DIN, CLKIN, DOUT).
trf CLKIN , CDOUT ) and the boundary delay time (t
pd D IN, t pd CLKIN, shows the dependence between t pd DOUT), an external circuit (71a, 71b, 72
a, 72b, based on the characteristics of 74a-74d), with reference physical quantity (t rf DIN, t rf CLKIN , and the step (S22, S23) for calculating the C DOUT), a border delay table (2,3), Physical quantity (t rf DIN , t
rf CLKIN, C DOUT) boundaries delay time based on (t pd DIN, t p d CLKIN, t pd DOUT)
(S24) and an external terminal (DIN,
CLKIN, the signal passing through the DOUT), the external terminals (DIN, CLKIN, DOUT) the boundary time delay in passing through (t pd DIN, t pd CLKI N, t pd
(S21, S25, S26, S27) for verifying the operation timing of the semiconductor integrated circuit (70), assuming that the delay is delayed by DOUT ).

External terminals (DIN, CLKIN, DOU)
Physical quantity given to ^{_{T) (t r f DIN,}} t rf
The operation timing of the semiconductor integrated circuit (70) is verified in consideration of the influence of ^CLKIN , _CDOUT ) on the delay time generated in the macro (11).

Further, physical quantities (t _rf ^DIN , t _rf)
^CLKIN , _CDOUT ) are external terminals (DIN, CL
KIN) input waveform dull values (t _rf ^DIN , t) indicating the delay in the timing at which the voltage of the input signal changes
_rf ^CLKIN ). At this time, the boundary delay table (2, 3) stores the input waveform dullness value (t _rf).
^DIN , _trf ^CLKIN ) and the boundary delay time ( _tpd
^DIN , t _pd ^CLKIN ) including an input waveform dullness-boundary delay table (3) indicating the dependency. The operation timing of the semiconductor integrated circuit (70) is verified in consideration of the influence of the input waveform dullness values (t _rf ^DIN , t _rf ^CLKIN ) on the delay time generated in the macro (11).

Here, the input waveform dullness value (t _rf ^DIN ,
_trf ^CLKIN ) is an external terminal (DIN, CLKI
N), either the time (t _dif , t _rf ) required for the voltage of the input signal input from the first voltage to reach the second voltage, or the time change rate (α) of the voltage of the input signal. It can be represented.

Further, physical quantities (t _rf ^DIN , t _rf)
^CLKIN , _CDOUT ) may include a load capacitance ( _CDOUT ) connected to an external terminal (DOUT). At this time, the boundary delay tables (2, 3) store the load capacity (C
_DOUT ) and a load capacitance-boundary delay table (2) indicating the dependency between the boundary delay time (t _{p D} ^DOUT ). The operation timing of the semiconductor integrated circuit (70) is verified while considering the effect of the load capacitance (C _DOUT ) on the delay time generated in the macro (11).

And a step of verifying operation timing.
(S21, S25, 26, S27) is the load capacity (C
_DOUT) And the output waveform dullness value (t_rf ^DOUT’)
Capacity-output waveform dullness table showing the dependence between
Step (S21) for providing (4) and load capacity
Amount-output waveform dullness value Refer to table (4) and load capacity
(C_DOUT) Based on the output waveform dullness value (t_rf
^DOUT′) And the output wave (S25)
Shape bluntness value (t_rf ^DOUT’)
(71a, 71b, 72a, 72b, 74a to 74d)
External delay time (T_dStep for calculating)
(S26) and the boundary delay time (t_pd ^DIN, T_pd
^CLKIN, T_pd ^DOUT) And the external delay time (T_d)
Timing of the semiconductor integrated circuit (70) based on
(S27). This
Here, the output waveform dullness value (t_rf ^DOUT’) Is the outer end
Child (DOUT) to external circuit (74c, 72b)
Indicates the delay in the timing at which the output signal voltage changes
You.

The output waveform of the signal output from the external terminal (DOUT) of the macro (11) becomes dull (t _rf ^DOUT ')
Is calculated. External terminal (DOUT) of macro (11)
While considering the output waveform blunting (t _rf ^DOUT ′) of the signal output from the external circuit (7
The delay time (t _pd ^72b ) of 2b) is calculated.

Operation timing of the semiconductor integrated circuit according to the present invention
The verification method is based on the circuit configuration information of the semiconductor integrated circuit (70).
Obtaining information (S21) and input boundary delay time
(T _pd ^DIN, T_pd ^CLKINStep to calculate
(S21, S22, S24) and output boundary delay time
(T_pd ^DOUT) (S21, S2)
3, S24) and the first external circuit (71a, 72a, 73)
a, 73b) to calculate the first external circuit delay time
Steps (S21, S26) and the second external circuit (71
b, 72b, 73c, 73d)
Step of calculating delay time (S21, S25, S2
6) and a circuit (16) included inside the macro (11).
a, 16b, 16c, 12b, 13a, 13b)
Calculating the macro internal delay time to be executed (S27)
And the input boundary delay time t_pd ^DIN, T _pd ^CLKIN
And the output boundary delay time (t_pd ^DOUT) And the first
An external circuit delay time, the second external circuit delay time,
From the macro internal delay time, the semiconductor integrated circuit (70)
Verifying the operation timing of (S27).
Be prepared.

Here, the semiconductor integrated circuit (70) includes a macro (11) having an input terminal (DIN, CLKIN) and an output terminal (DOUT), and an input terminal (DIN, CLKI).
N) to the first external circuit (71a, 72a, 73)
a, 73b) and a second terminal connected to the output terminal (DOUT).
External circuits (71b, 72b, 73c, 73d). Input boundary delay time (t _pd ^DIN , t _pd
^CLKIN ) is a delay time virtually assumed to occur at the input terminals (DIN, CLKIN). The output boundary delay time (t _pd ^DOUT ) is equal to the output terminal (DOUT)
Is a delay time virtually assumed to occur in

At this time, the input boundary delay time (t_pd
^DIN, T_pd ^CLKIN) (S2)
1, S22, S24) are the input waveform dullness-boundary delay te
Step (S21) for providing a cable (3);
Features of the first external circuit (71a, 72a, 73a, 73b)
The input waveform dullness value (t_rf ^DIN, T_rf
^{C LKIN}) Is calculated (S22), and the input wave
It is calculated with reference to the shape blunt value-boundary delay table (3).
Input waveform dullness value (t_rf ^DIN, T_rf ^{CLKI N})
Calculating the input boundary delay time based on
(S24). Where input waveform dullness-boundary delay
Table (3) shows the input waveform dullness value (t_rf ^DIN, T
_rf ^CLKIN) And input boundary delay time (t_pd ^DIN,
t_pd ^{CLK IN}), And here
And the input waveform dullness value (t_rf ^DIN, T _rf ^CLKIN)
Means that the voltage of the input signal input to the input terminal (DIN) is
This shows the delay of the changing timing.

At this time, the output boundary delay time (t _pd
^DOUT ) (S21, S23, S2)
4) Step (S21) for providing the load capacity-boundary delay table (2), and the second external circuit (71b,
72b, 73c, 73d), calculating the load capacitance (C _DOUT ) based on the characteristics (C23), and referring to the load capacitance-boundary delay table (2) to calculate the calculated load capacitance (C _DOUT ). Calculating the output boundary delay time on the basis of the output boundary delay time (S24). Here, the load capacitance-boundary delay table (2) is connected to an output terminal (DOU).
A load capacitance connected to T) _{(C DOUT),} shows the dependence between the output boundary delay ^{_(t pd DOUT).}

The input waveform dullness values (t _rf ^DIN , t _rf)
^CLKIN ), the operation timing of the semiconductor integrated circuit (70) is verified in consideration of the influence on the delay time generated in the macro (11). Further, the load capacity (C
The operation timing of the semiconductor integrated circuit (70) is verified in consideration of the effect of _DOUT ) on the delay time generated in the macro (11).

Further, the second external circuit delay time is calculated.
(S21, S25, S26) is the load capacity minus
Step for providing output waveform dullness table (4)
(S21) and load capacity-output waveform dullness table
Referring to (4), the load capacity (C _DOUT) Based out
Force waveform blunt value (t_rf ^DOUT’)
(S25) and the output waveform dullness value (t_rf ^DOUT’)
Calculating the second external circuit delay time based on the
(S26). Where load capacity-output
The force waveform dullness table (4) shows the load capacity
(C_DOUT) And the output waveform dullness value (t_rf ^DOUT’)
And the output waveform dullness value (t_rf
^DOUT') Is output from the output terminal (DOUT).
This shows a delay in the timing at which the signal changes.

The output waveform of the signal output from the external terminal (DOUT) of the macro (11) becomes dull (t _rf ^DOUT ').
Is calculated. External terminal (DOUT) of macro (11)
While considering the output waveform blunting (t _rf ^DOUT ′) of the signal output from the external circuit (7
The delay time (t _pd ^72b ) of 2b) is calculated.

A semiconductor integrated circuit operation timing verification apparatus according to the present invention comprises a structure obtaining means (64) for obtaining circuit configuration information of a semiconductor integrated circuit (70), a boundary delay table (2, 3), and an external circuit (71a). , 71b, 72a, 7
2b, 74a to 74d), the physical quantity (t
_rf ^DIN, _t ^rf _CLKIN, a physical quantity calculating means for calculating the _{C DOUT)} (61a), with reference to the boundary delay table (2,3), a physical quantity ^_(t rf _{DIN, t rf}
^CLKIN , _CDOUT ), the boundary delay time (t
_pd ^DIN , t _pd ^CLKIN , t _pd ^DOUT ) and signals passing through external terminals (DIN, CLKIN, DOUT)
External terminals (DIN, CLKIN, DOUT) the boundary time delay in passing through ^{_{(t pd DIN, t pd CLKIN}} ,
t _pd ^DOUT ), assumed to be delayed by
Operation timing verification means (61b) for verifying the operation timing of the semiconductor integrated circuit (70). Here, the semiconductor integrated circuit (70) has external terminals (DIN, CLK
Macro (11) having IN, DOUT) and external circuits (71a, 71b, 72a, 72b, 74a-74d) connected to external terminals (DIN, CLKIN, DOUT)
And The boundary delay tables (2, 3) include physical quantities (t _rf ^DIN , t _rf ^CLKIN , and t _rf ^DIN ) given to external terminals (DIN, CLKIN, DOUT).
C _DOUT) and boundary delay time _{^(t pd DIN,} ^t pd
^{CLK IN} , t _pd ^DOUT ).

External terminals (DIN, CLKIN, DOU)
Physical quantity given to ^{_{T) (t r f DIN,}} t rf
The operation timing of the semiconductor integrated circuit (70) is verified in consideration of the influence of ^CLKIN , _CDOUT ) on the delay time generated in the macro (11).

The macro delay information library of the present invention
Field delay tables (2, 3) are provided. Where the boundary delay
Tables (2, 3) are external ends of macro (11).
Child (DIN, CLKIN, DOUT)
Physical quantity (t_rf ^DIN, T _rf ^CLKIN, C
_DOUT) And the boundary delay time (t_pd ^DIN, T_pd
^{CLKI N}, T_pd ^DOUT).
Boundary delay time (t_pd ^DIN, T _pd ^CLKIN, T
_pd ^DOUT) Are external terminals (DIN, CLKIN, DIN
OUT) passes through external terminals (DIN, CLK)
IN, DOUT)
The delay time. External terminal of macro (11)
(DIN, CLKIN, DOUT)
Physical quantity (t_rf ^DIN, T_rf ^CLKIN,
C_DOUT), The boundary delay time (t_pd ^DIN,
t_{p d} ^CLKIN, T_pd ^DOUT) Can be calculated
A library of possible macro delay information is provided.

The physical quantities (t _rf ^DIN , t _rf)
^CLKIN , _CDOUT ) are external terminals (DIN, CL
KIN) input waveform dull values (t _rf ^DIN , t) indicating the delay in the timing at which the voltage of the input signal changes
_rf ^CLKIN ) and boundary delay tables (2, 3)
Is the input waveform dullness value (t _rf ^DIN ,
t _rf ^CLKIN ) and the boundary delay time (t _pd ^DIN , t
_pd ^CLKIN , t _pd ^DOUT ) may be included. Input waveform dullness values (t _rf ^DIN , t _rf ) of signals input to input terminals (DIN, CLKIN)
^CLKIN) is a macro (11) bounding the delay time while taking into account the influence on the delay time generated by ^{_{(t pd DIN, t pd CLKIN}} ) can calculate the macro delay information library is provided.

The physical quantity (t)_rf ^DIN, T_rf
^CLKIN, C_DOUT) Are external terminals (DIN, CL
KIN) and the load capacity (C_DOUT)
There is. At this time, the boundary delay tables (2, 3) are negative.
Load capacity (C_DOUT) And boundary delay time
(T_pd ^DOUTLoad capacity that indicates a dependency between
Field delay table (2). Output terminal (DOUT)
Connected load capacity (C_DOUT) Is a macro (11)
Boundary delay considering the effect on delay time
Time (t_pd ^DOUT) Macro that can calculate
A delay information library is provided.

In some cases, the apparatus further comprises a load capacitance-output waveform dullness table (4) indicating the dependence between the load capacitance (C _DOUT ) and the output waveform dullness value (t _rf ^DOUT '). The output waveform dullness value (t _rf ^DOUT ′) indicates a delay in the timing at which the voltage of the output signal output from the external terminal (DOUT) changes. Output terminal (DOUT)
And a macro delay information library capable of calculating an output waveform dull value (t _rf ^DOUT ′) according to a load capacitance (C _DOUT ) connected to the macro delay information library.

Further, a macro internal delay table (30) may be further provided. Macro internal delay table (3
0) indicates a delay time generated inside the macro (11). A macro delay information library capable of calculating a delay time generated inside a macro (11) is provided.

At this time, the macro (11)
(16a-16c). Boundary block (16a-
16c), the boundary block delay time (t_pd
^16a’-T_pd ^16c′) Are external terminals (DIN, C
LKIN, DOUT) (t)_rf
^DIN, T_rf ^CLKIN, C_DOUT) Depends.
The macro internal delay table (30) has a boundary block
Considered to occur virtually in (16a-16c)
Reference delay time (t_pd ^16a~ T_pd ^16c) Is written
Has been described. Reference delay time (t_pd ^16a~ T_pd
^16c) Is the physical quantity (t_rf ^DIN,
t_rf ^CLKIN, C_DOUT) Independent.
Reference delay time (t_pd ^16a~ T_pd ^16c) And late border
Delay time (t_pd ^DIN, T_pd ^{CLKI N}, T_pd
^DOUT) Is substantially equal to the boundary block delay time.
Equal. Physical quantity (t_rf ^DIN,
t_rf ^CLKIN, C_DOUT) Is the boundary block (1
6a to 16c), the boundary block delay time (t
_pd ^16a’-T_pd ^{16 c}’)
Considering the behavior of the semiconductor integrated circuit including the macro (11),
Macro delay information that can verify operation timing
An library is provided.

Method of Generating Macro Delay Information Library of the Present Invention
The method is a step of obtaining circuit configuration information of the macro (11).
(S01) and the macro (11) is connected to an external terminal (D
IN, CLKIN, DOUT) and a macro (11)
Are selected as boundary blocks (16a to 16c)
Steps (S03, S06) and physical quantity (t_rf ^D
IN, T_rf ^CLKIN, C_DOUT) Of multiple values
The boundary block delay time (t_pd ^16a
~ T_pd ^16c) (S05, S0)
8) and here, the boundary blocks (16a to 16c)
The boundary block delay time (t_pd ^16a~ T_pd
^16c) Is the external terminal (t_rf ^DIN, T_rf
^CLKIN, C_DOUTDepends on the physical quantity given to
Then, the calculated boundary block delay time (t_pd ^16a’
~ T_pd ^16c’)
(T_rf ^{D IN}, T_rf ^CLKIN, C_DOUT) And the border
Field delay time (t_pd ^DIN, T_pd ^CLKIN, T_pd
^DOUTGenerates a boundary delay table showing the dependencies between
(S04, S05, S07, S08)
Is provided. Here, the boundary delay time (t_pd ^DIN, T
_pd ^CLKIN, T_pd ^DOUT) Is the external terminal (t_r
f ^DIN, T_rf ^CLKIN, C_DOUTDeparts at)
This is a delay time that is virtually considered to occur.

The external terminal (DI) of the macro (11)
N, CLKIN, a physical quantity given to _{^{DOUT) (t rf DIN, t}} rf CLKIN, depending on the _{C DOUT),} border delay ^{_(t pd DIN,}
t _pd ^CLKIN, it is possible to generate a _t ^{pd DOUT)} macro delay information library which can be calculated.

The physical quantity (t)_rf ^DIN, T_rf
^CLKIN, C_DOUT) Are external terminals (DIN, CL
KIN) when the voltage of the input signal changes
Input waveform dullness value (t_rf ^DIN)
Can be At this time, the boundary delay table (2, 3)
Is the input waveform dullness value (t_rf ^DIN) And the boundary delay time
(T _rf ^DINInput waveform dullness value indicating the dependence between
-Include the boundary delay table (3).

The physical quantities (t _rf ^DIN , t _rf)
^CLKIN , _CDOUT ) may include a load capacitance ( _CDOUT ) connected to an external terminal (DOUT). At this time, the boundary delay tables (2, 3) store the load capacity (C
_DOUT ) and a load capacitance-boundary delay table (2) indicating the dependency between the boundary delay time (t _{p D} ^DOUT ).

The steps (S04, S05, S07, S08) for generating the boundary delay tables (2, 3) are as follows:
Reference delay time ^{_(t pd} _16a ^~t pd ^16c) step of determining the (S04, S07), wherein the reference delay time _{^{(t pd 16a ~t pd 16 c}} ) , the physical quantity _{(t rf}
^DIN, when _t ^rf _{CLKIN, C DOUT)} is a predetermined value (0 ns, 0 pF), the boundary block (16
a to ^16c ). The reference delay time (t _pd ^{16a to} t _pd ^16c ) is subtracted from the boundary block delay time (t _pd ^16a ′ to t _pd ^16c ′) to obtain the boundary delay time (t _pd ^{16a to} t _pd ^16c ). t _pd ^DIN , t _pd
^CLKIN , t _pd ^DOUT ) (S
05, S08).

The method may further include a step (S11) of generating a macro internal delay table (30). The macro internal delay table (30) stores the macro (11
And the reference delay time (t _pd ) in the boundary blocks (16a to 16c).
^{16a to} t _pd ^16c ).

The macro delay information library of the present invention
The generation device acquires circuit configuration information of the macro (11).
The structure acquisition means (44) and here the macro (11)
Unit terminals (DIN, CLKIN, DOUT)
B) Part of (11) is defined as boundary blocks (16a to 16c)
Selecting means (41) for selecting a boundary block.
Boundary block delay time that occurs in steps (16a-16c)
(T_pd ^16a’-T _pd ^16c′) Is an external terminal (D
(T, IN, CLKIN, DOUT)
_rf ^DIN, T_rf ^CLKIN, C_DOUT)dependent upon
And the physical quantity (t_{r f} ^DIN, T_rf ^CLKIN, C
_DOUTBoundary block delay time corresponding to multiple values of
(T_pd ^16a’-T_pd ^16c’)
Step (41) and the calculated boundary block delay time (t
_pd ^16a’-T_pd ^16c’)
(T_rf ^DIN, T_rf ^CLKIN, C_DOUT) And the border
Field delay time (t_pd ^DIN, T_pd ^CLKIN, T_pd
^DOUTBoundary delay table showing dependencies between
Generating means (41) for generating (2, 3).
Boundary delay time (t_pd ^DIN, T_pd ^CLKIN, T
_pd ^DOUT) Are external terminals (DIN, CLKIN, DIN
OUT) when it is virtually assumed to occur at
Between.

[0047]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment: A first embodiment of a macro boundary delay library according to the present invention will be described with reference to the drawings.
The embodiment has a macro information table. As shown in FIG. 1, the macro information table 1 comprises a macro boundary delay library 10 together with a load capacity-output boundary delay table 2, an input waveform blunting-input boundary delay table 3, and a load capacity-output waveform blunting table 4. Is configured.

The macro boundary delay library 10 is stored in a storage device or recorded on a recording medium. The macro boundary delay library 10 is read and used by a computer (not shown).

The macro boundary delay library 10 according to the first embodiment is a library for calculating the delay time of the macro 11 shown in FIG. The macro 11 includes cells 12a to 12d and cells 13a and 13b, as shown in FIG. Each of the cells 12a to 12d has an input terminal and an output terminal. Cells 12a-12
c is a cell of type BUF_A.

Each of the cells 13a and 13b has an input terminal, an output terminal, and a clock terminal. Cells 13a, 1
3b are cells of type FF_A.

The macro 11 includes an input terminal DIN and an output terminal DOUT. Input terminal DIN of macro 11 is wiring 1
4a to the input terminal of the cell 12a. Cell 1
The output terminal 2a is connected to the input terminal of the cell 13a via the wiring 14b. The output terminal of the cell 13a is connected to the wiring 14
and c to the input terminal of the cell 12b. Cell 12
The output terminal of b is connected to the input terminal of the cell 13b via the wiring 14d. The output terminal of the cell 13b is connected to the wiring 14e.
To the input terminal of the cell 12c. Cell 12c
Is connected to the output terminal DOUT of the macro 11 via the wiring 14f.

The macro 11 further includes a clock input terminal CL
Includes KIN. Clock input terminal CLKI of macro 11
N is connected to the input terminal of the cell 12d via the wiring 14g. The output terminal of the cell 12d is connected to the node 15 via the wiring 14h. The node 15 is connected to the clock terminal of the cell 13a via the wiring 14i. Node 15
Is further connected to the clock terminal of the cell 13b via the wiring 14j.

The contents of the macro boundary delay library 10 will be described below. As described above, the macro boundary delay library 10 includes the macro information table 1, the load capacity-delay time table 2, the input waveform blunt-delay time table 3, and the load capacity-output waveform blunt table 4.

First, the macro information table 1 will be described.
Is done. FIG. 3 shows the contents of the macro information table 1.
The macro information table 1 contains the size of the macro 11 in the x direction.
Z _size, The size y of the macro 11 in the y direction_size
Is described. The size x of the macro 11 in the x direction
_size, The size y of the macro 11 in the y direction_sizeIs
Described in line 1-1 of the macro information table 1.
You. x_size= 100 (um), y_size= 100
(Um).

The macro information table 1 further describes the capacity of each output terminal of the macro 11. The macro information table 1, the capacitance _{C D OUT} of the output terminal DOUT is described. Capacitance _{C DOUT} output terminal DOUT is described in the line 1-2. C
_DOUT = 0.500752 (pF).

The macro information table 1 further describes the capacity of each input terminal of the macro 11. The macro information table 1, and the capacitor _{C DI N} input terminals DIN, the capacity of the clock input terminal CLKIN C
_CLKIN is described. The capacitance C of the input terminal DIN
_DIN is described in lines 1-3. C _DIN =
0.004042. Clock input terminal CLKIN
The capacitance C _CLKIN is described in lines 1-4. C _CLKIN = 0.004042.

The macro information table 1 further describes the threshold voltage of each input terminal of the macro 11. The threshold voltage of the input terminal is a voltage used as a reference when determining whether a signal input to the input terminal is at the HI level or the LO level. The macro information table 1 contains the threshold voltage V _{T of the} input terminal DIN.
_-DIN and a clock input terminal _{VT -CLKIN} are described. The threshold voltage V of the input terminal DIN
_{The T-DIN} and the clock input terminal _VT-CLKIN may have variations. The threshold voltage VT _-DIN of the input terminal _DIN and the clock input terminal V
_T-CLKIN is represented by a range it can take and a standard value.

The threshold voltage V of the input terminal DIN
_T-DIN is described in lines 1-5. V
The minimum value, standard value, and maximum value of _T-DIN are each 0.
8 (V), 0.84 (V), and 0.88 (V). Threshold voltage V of clock input terminal CLKIN
_T-CLKIN is described on lines 1-6. V
The minimum value, standard value, and maximum value of _T-CLKIN are 0.8 (V), 0.84 (V), and 0.88 (V), respectively.

The macro information table 1 further describes the output resistance of each output terminal of the macro 11. Output resistance _{R d} of the output terminal DOUT is line 1
7 is described. Output resistance R _d of output terminal DOUT
Is represented by a range that can be taken and a standard value. Output resistance _{R d} of output terminal DOUT, the output terminal DO
It differs between when the voltage of the signal output from the UT rises and when it falls. When the voltage of the signal output from the output terminal DOUT rises, the minimum value of the output resistance _{R d} of the output terminal DOUT, a standard value, maximum value, respectively 0.808457 (Ω), 1.26791 (Ω ), 2.
0475 (Ω). When falling the voltage of the signal output from the output terminal DOUT is, the minimum value of the output resistance _{R d} of the output terminal DOUT, a standard value, maximum value, respectively 0.383117 (Ω), 0.621179 (Ω ),
1.12142 (Ω).

Next, the load capacity-output boundary delay table 2 will be described. The load capacity-output boundary delay table is a table for calculating the output boundary delay time of each output terminal included in the macro. The load capacitance-output boundary delay table 2 of the present embodiment has an output terminal D
A table for calculating an output boundary delay time t _pd ^DOUT of OUT is included.

The output boundary delay time of an output terminal is a time when a signal is output from the output terminal and the signal is considered to be delayed at the output terminal. The output boundary delay time is a virtual delay time introduced when verifying the operation timing of the semiconductor integrated circuit.

The signal generated by the cell 12c is output from the output terminal DOUT as shown in FIG. When the delay time of the macro 11 is calculated using the macro boundary delay library 10, the signal output from the cell 12c is virtually regarded as being delayed by the output boundary delay time t _pd ^DOUT when passing through the output terminal DOUT. It is.

The output boundary delay time of a certain output terminal depends on the load capacitance connected to that output terminal. Output terminal D
The output boundary delay time t _pd ^DOUT of OUT depends on the load capacitance _CDOUT connected to the output terminal DOUT.

The load capacity-output boundary delay table 2 includes:
A plurality of different load capacities C_{DO UT}About it
Output boundary delay time t of output terminal DOUT corresponding to each
_pd ^DOUTIs described. Also, the output terminal DOU
Output boundary delay time t of T_pd ^DOUTIs the output terminal DO
When the voltage of the signal output from the UT rises,
It is different from when it falls. Output boundary delay time t_pd
^DOUTIs the power of the signal output from the output terminal DOUT.
Both when the pressure rises and when it falls
Is described.

FIG. 4 shows the contents of the load capacity-output boundary delay table 2. Load capacity-output boundary delay table 2
Includes lines 2-1 to 2-6. Line 2-1 to 2-
3 is an output boundary delay time t _pd of the output terminal DOUT when a signal output from the output terminal DOUT rises.
A table for determining ^DOUT is configured.

The output boundary delay time t _pd ^DOUT is represented by a range that can be taken and a standard value. Line 2-
1, 2-2, and 2-3 have output boundary delay times t, respectively.
_The minimum value, standard value, and maximum value of _pd ^{D OUT} that can be taken are described. Each line 21, 22 and 23, the output boundary delay time _t ^{pd DOUT} corresponding to each of the plurality of load capacitance _{C DOUT} is described.

[0067] the column 2-7, the output boundary delay time _t ^{pd DOUT} is described when the load capacitance _{C L} is connected to the output terminal DOUT is 0.01 (pF). Similarly, columns 2-8, 2-9, 2-10, 2-11, 2-
12 has a load capacitance C connected to the output terminal DOUT.
_DOUT is 0.05 (pF) and 0.1 (p
F), 0.2 (pF), 0.5 (pF), and 1 (pF), the output boundary delay time t _pd ^DOUT is described.

Lines 2-4 to 2-6 are output terminals DOU
The output terminal D when the signal output from T falls
A table for determining the output boundary delay time t _pd ^DOUT of OUT is configured. Lines 2-4, 2-5, 2-6
Describes the minimum value, standard value, and maximum value of the output boundary delay time t _pd ^DOUT , respectively. Each line 2-4,2-5,2-6, a plurality of load capacitance _C output boundary delay time t corresponding to the respective _DOUT
pd ^DOUT is described.

Column 2-13 describes an output boundary delay time t _pd ^DOUT when the load capacitance C _DOUT connected to the output terminal DOUT is 0.01 (pF). Similarly, columns 2-14, 2-15, 2-16, 2
The -17,2-18, load capacitance _{C DOUT} connected to the output terminal DOUT, respectively 0.05 (pF), 0.
1 (pF), 0.2 (pF), 0.5 (pF), 1 (p
F), the output boundary delay time t _pd ^DOUT is described.

Next, the input waveform blunting-input boundary delay table 3 will be described. The input waveform dullness-input boundary delay table is a table for calculating the input boundary delay time of each input terminal included in the macro.
As shown in FIG. 5, the input waveform dullness-input boundary delay table 3 stores the input boundary delay time t of the input terminal DIN.
Table 3-1 for calculating _pd ^DIN, and input boundary delay time t _{pd of} clock input terminal CLKIN
^And a table 3-2 for calculating ^CLKIN .

The input boundary delay time of a certain input terminal is a time when a signal is considered to be delayed when a certain signal is input to the macro via the input terminal. The input boundary delay time is a virtual delay time introduced when verifying the operation timing of the semiconductor integrated circuit.

When the delay time of the macro 11 is calculated using the macro boundary delay library 10, the input terminal DIN
Is virtually assumed to be delayed by the input boundary delay time t _pd ^DIN of the input terminal DIN when passing through the input terminal DIN. A clock signal input to the macro 11 via the clock input terminal CLKIN is a clock signal input to the macro 11.
When passing through LKIN, the clock input terminal CLKIN
_Is virtually assumed to be delayed by the input boundary delay time t _pd ^CLKIN .

The input boundary delay time of a certain input terminal is
Depends on input waveform dullness of input signal input to input terminal
You. Here, the waveform blunting of a certain signal t_rfIs that signal
A parameter that indicates the speed of rising or falling.
It is. Waveform dull t_rfHas a time dimension. Ah
If the rising speed of the signal
The signal is approximated when rising at a constant voltage change rate α.
It is. Similarly, the speed at which a certain signal falls is
When represented, the signal rises at a constant voltage change rate α.
When it falls, it is approximated. Waveform dull t_rfIs entered
Signal is 0 to V _DDThe time it takes to get up,
Means that the input signal is V_DDRequired to fall from 0 to 0
Time is defined as Input at an input terminal
When a signal is input, the waveform of the input signal
This is called waveform dulling.

The definition of the waveform blunt _trf will be explained with reference to FIG. Waveform dullness when signal rises t
The definition of _rf is explained. When defining the waveform blunt _trf of the signal 21, the signal 21 is approximated to an approximation signal 22 composed of a broken line, as shown in FIG.

The time required for the signal 21 to change from the voltage _VL to the voltage _VH is _defined as t _dif . Voltage _VH is a predetermined voltage higher than threshold voltage _VTH . Voltage _VL is a predetermined voltage lower than threshold voltage _VTH . here,
The threshold voltage V _TH is a reference voltage for identifying the logic of the signal. The voltage _VH is set to, for example, 0.9 × _VDD . The voltage _VL is, for example, 0.1 × V _DD .

The voltage change rate α of the signal input to the input terminal of the cell is approximated to be constant. α = (V _H −
_VL ) / t _dif . The waveform blunting t _rf when a certain signal rises is defined as t _rf = V _DD / α.
Also, the waveform blunting t _rf when a certain signal falls is
Under conditions that the time required for the signal consists of a voltage V _H to the voltage V _L and t _dif, it is defined as t _rf waveform blunting when the certain signal rises.

The waveform blunting of a signal can be defined by the voltage change rate α of the signal. At this time, the waveform blunt has a dimension of V / s.

The input boundary delay time t _{pd of the} input terminal DIN
^DIN depends on the input waveform dullness _trf ^DIN of the input signal input to the input terminal DIN. Clock input terminal C
The input boundary delay time t _pd ^CLKIN of LKIN depends on the input waveform blunting t _rf ^CLKIN of the clock signal input to the clock input terminal CLKIN.

Input Waveform Dull-Input Boundary Delay Table 3
Represents a plurality of different input waveform dullnesses t_rf ^DINNoso
Input boundary delay time t corresponding to each_pd ^DINIs described
Have been. Also, input waveform dullness-input boundary delay table
3 has a plurality of different input waveform dullnesses t._rf
^CLKINInput boundary delay time t corresponding to
_pd ^CLKINIs described.

The input boundary delay time t _pd ^DIN of the input terminal ^DIN and the input boundary delay time t _pd ^{CLKIN of} the clock input terminal CLKIN are respectively defined by the input terminal D
The time when the voltage of the signal input to IN and the clock input terminal CLKIN rises differs from the time when it falls.
The input waveform dulling-input boundary delay table 3 has an input boundary delay time t _pd ^DIN of the input terminal ^DIN and an input boundary delay time t _pd ^{CLKIN of the} clock input terminal ^CLKIN.
Are the input terminal DIN and the clock input terminal C, respectively.
When the voltage of the signal input to LKIN rises,
Both falling and falling cases are described.

FIG. 5 shows an input waveform dullness-input boundary delay table.
The contents of Bull 3 are shown. As described above, input waveform dullness-slow
The delay time table 3 indicates that the input terminal DIN has an
Interval t _pd ^DINTable 3-1 for calculating
Input boundary delay time t of lock input terminal CLKIN_pd
^CLKINAnd a table 3-2 for calculating.

Input boundary delay time t of input terminal DIN_pd
^DINThe table 3-1 for calculating the value
3 to 3-8. Lines 3-3 to 3-8 are input terminals
Input terminal when the signal input to DIN rises
DIN input boundary delay time t _pd ^DINTo determine
Configure the table.

The input boundary delay time t _pd ^DIN is represented by a range that can be taken and a standard value. Line 3-3,
3-4 and 3-5 respectively show the output boundary delay time t _pd
Minimum possible value of ^{DI N,} standard values are described maximum value. Each of the lines 3-3, 3-4, and 3-5 has
Input Boundary delay time _t ^{pd DIN} corresponding to each of the plurality of input waveform blunting _t ^{rf DIN} is described.

[0084] the column 3-9, the input waveform of the signal inputted to the input terminal DIN blunting _t ^{rf D IN} is 0.01 (n
s), the input boundary delay time t _pd ^DIN is described. Similarly, columns 3-10, 3-11, 3-
The 12,3-13, the input waveform blunting _t ^{rf DIN} of the signal input to the input terminal DIN, respectively 0.4 (n
s), 1 (ns), 3 (ns), the input boundary delay time _{t p} ^{d DIN} is written when a 5 (ns).

Lines 3-6 to 3-8 are connected to input terminals DIN
Input terminal DI when the signal output from
N input boundary delay time t_pd ^DINTo determine the
Make up the bull. Lines 3-6, 3-7, 3-8
Input boundary delay time t _pd ^DINThe smallest possible
Values, standard values, and maximum values are described. Line 3-6,
Each of 3-7 and 3-8 has a plurality of input boundary delays.
Interval t_rf ^DINInput boundary delay time corresponding to each of
t_pd ^DINIs described.

In column 3-14, the input terminal DIN
Input waveform blunting t of the input signal_rf ^DINIs 0.01
(Ns) input boundary delay time t_pd ^DINBut
It has been described. Similarly, columns 3-15, 3-16,
3-17 and 3-18 are input to the input terminal DIN
Signal input waveform dullness t_rf ^DINBut 0.4 each
(Ns), 1 (ns), 3 (ns), 5 (ns)
Input boundary delay time t _pd ^DINIs described
You.

Table 3 for calculating input boundary delay time t _pd ^CLKIN of clock input terminal CLKIN
2 is the input boundary delay time t _pd ^DIN of the input terminal ^DIN
Has the same contents as in the table 3-1 for calculating. Input boundary delay time t of clock input terminal CLKIN
The description of the contents of Table 3-2 for calculating _pd ^CLKIN is omitted.

Next, the load capacity-output waveform dullness table 4 will be described. The load capacity-output waveform blunting table is a table for calculating waveform blunting of a signal output from each output terminal included in the macro. The blunted waveform of the signal output from the output terminal is called the blunted output waveform. The blunt output waveform of a signal output from an output terminal depends on the load capacitance connected to the output terminal.

The load capacity-output waveform dullness table 4
Output waveform dullness t of the signal output from the input terminal DIN_rf
^DOUTIs included. Different from each other
Load capacity C_DOUTAbout each
Output waveform dull t_rf ^{DO UT}Is described. Ma
The output waveform dullness t_rf ^DOUTIs the output terminal DIN
When the output signal rises and falls
And different. Output waveform dullness t_rf ^DOUTIs the output terminal
When the signal output from DIN rises and falls
It is calculated for each of the times when it falls. Calculated
Output waveform dullness t _rf ^DOUTIs the load capacity minus the output waveform
Described in Table 4.

FIG. 7 shows the contents of the load capacity-output waveform dullness table 4. Load capacity-output waveform dullness table 4
Includes lines 4-1 to 4-6. Lines 4-1 to 4-
Reference numeral 3 denotes a table for determining the output waveform blunting t _rf ^DOUT of a signal output from the output terminal DOUT when the signal rises.

The output waveform dullness t _rf ^DOUT is represented by a range that can be taken and a standard value. Lines 4-1 and 4
The -2,4-3 each output waveform distortion _{t rf}
^The minimum, standard, and maximum values that ^DOUT can take are described. Each line 4-1, 4-2, and 4-3, the output waveform distortion _t ^{rf DOUT} corresponding to each of the plurality of load capacitance _{C DOUT} is described.

[0092] the column 4-7, the output waveform distortion _t ^{rf DOUT} is described when the load capacitance _{C L} is connected to the output terminal DOUT is 0.01 (pF). Similarly,
Columns 4-8, 4-9, 4-10, 4-11, 4-12
Has a load capacitance C _DOUT connected to the output terminal _DOUT.
Are 0.05 (pF), 0.1 (pF), 0.
The output waveform dullness _trf ^{D OUT at} 2 (pF), 0.5 (pF), and 1 (pF) is described.

Lines 4-4 to 4-6 are output terminals DOU
When a signal output from T falls, a table for determining an output waveform dullness t _rf ^DOUT of the signal is formed. The line 4-4,4-5,4-6, minimum possible value of each output waveform distortion _t ^{rf DOU T,} the standard value, the maximum value is described. Lines 4-4, 4-5,
Each of 4-6, the output waveform distortion _t ^{rf DOUT} corresponding to each of the plurality of load capacitance _{C DOUT} is described.

[0094] the column 4-13, the output waveform distortion _t ^{rf DOUT} is described when the load capacitance _{C DOUT} connected to the output terminal DOUT is 0.01 (pF).
Similarly, columns 2-14, 2-15, 2-16, 2-1
The 7,2-18, the load capacitance _{C DOUT} connected to the output terminal DOUT, respectively 0.05 (pF), 0.1
(PF), 0.2 (pF), 0.5 (pF), 1 (p
The output waveform dull _trf ^DOUT when F) is described.

Next, the macro internal delay information library according to the first embodiment will be described. The macro internal delay information library 30 according to the first embodiment
When verifying the operation timing of a semiconductor integrated circuit including
Used with the macro boundary delay library 10. As shown in FIG. 8, the macro internal delay information library 30 includes a wiring delay table 31 and a cell / boundary block delay table 32.

In the wiring delay table 31, delay times of the wirings 14b to 14e and 14h to 14j included in the macro 11 are described. In the wiring delay table 31, ranges where delay times of the wirings 14b to 14e and 14h to 14j can be taken and standard values thereof are shown.

FIG. 9 shows the contents of the wiring delay table 31. The wiring delay table 31 has lines 31-1 to 31-1.
31-6. Lines 31-1, 31-2, 31-
Reference numerals 3 and 31-4 denote wiring 14e and wiring 14 respectively.
d, the delay time of the wiring 14c and the wiring 14b are described. The line 31-5 describes the sum of the delay times of the wiring 14h and the wiring 14i. Line 31-6 describes the sum of the delay times of the wirings 14h and 14j.

The delay times of the wiring 14e, the wiring 14d, the wiring 14c and the wiring 14b are the same. Wiring 14
e, the minimum value, the standard value, and the maximum value of the delay time of the wiring 14d, the wiring 14c, and the wiring 14b are 0 (ps),
0 (ps) and 1 (ps).

The sum of the delay times of the wires 14h and 14i is equal to the sum of the delay times of the wires 14h and 14j. The minimum, standard, and maximum values of the sum of the delay times of the wirings 14h and 14i and the sum of the delay times of the wirings 14h and 14j are 0 (ps), 0 (ps),
1 (ps).

In the cell / boundary block delay table 32, the cells 12b, 13a, 13b
Is described. The cell / block boundary delay table 32 further includes boundary blocks 16a to 16c.
Is described.

Here, the boundary block 16a is a portion of the macro 11 whose delay time depends on the input waveform dulling _trf ^DIN of the input signal input from the input terminal DIN. As shown in FIG. 2, the boundary block 16a includes a cell 12a and a wiring 14a. The boundary block 16a is connected to the input terminal DIN. The input terminal of the boundary block 16a is the input terminal DIN.
The output terminal of the boundary block 16a is the output terminal of the cell 12a.

The boundary block 16b is a portion of the macro 11 whose delay time depends on the load capacitance _CDOUT connected to the output terminal DOUT. The boundary block 16b includes a cell 12c and a wiring 14f. The boundary block 16b is connected to the output terminal DOUT. The input terminal of the boundary block 16b is the input terminal of the cell 12a. The output terminal of the boundary block 16b is the output terminal D
OUT.

The boundary block 16c is a portion of the macro 11 whose delay time depends on the input waveform blunting _trf ^CLKIN of the clock signal input to the clock input terminal CLKIN. The boundary block 16c includes a cell 12d and a wiring 14g. Boundary block 16c
Is connected to the clock input terminal CLKIN. The input terminal of the boundary block 16c is a clock input terminal CLKIN
It is. The output terminal of the boundary block 16b is the cell 12d
Output terminal.

In the macro 11, the boundary blocks 16a,
The delay time of portions other than the boundary block 16b and the boundary block 16c is represented by the input waveform dullness t _rf ^DIN and the load capacitance C
_{DOUT T} and input waveform blunting t _rf ^CLKIN do not substantially depend on either.

The virtual delay time of the boundary blocks 16a to 16c will be described. The delay time generated in the boundary block 16a depends on the input waveform dullness _trf ^DIN . However, the cell / boundary block delay table 32 describes that the delay time generated in the boundary block 16a is a constant value that does not depend on the input waveform dullness t _rf ^DIN . When a delay time inside the macro 11 is calculated using the macro internal delay information library 30, it is considered that a virtually constant delay time occurs in the boundary block 16a. The fixed delay time is hereinafter referred to as a reference delay time. That is, the boundary block 16a has the reference delay time t _pd ^16a .

Similarly, the delay times generated in the boundary blocks 16b and 16c depend on the load capacitance _CDOUT and the input waveform dull _trf ^CLKIN , respectively. But the cell /
In the block delay table 32, the boundary block 16b,
The delay time occurring at 16c is virtually the load capacity C
It is described as a constant value that does not depend on _OUT or the input waveform dull _trf ^CLKIN . That is, the boundary block 16b, the boundary block 16c includes each reference delay time _t ^pd _16b, the ^{t pd 16c.}

The delay time of the cells 12b, 13a and 13b differs between when the signal output from the output terminal rises and when it falls. The cell / boundary block delay table 32 describes the delay times of the cells 12b, 13a, and 13b both when the signal output from each output terminal rises and when it falls.

Similarly, the boundary blocks 16a, 16b, 1
The reference delay time of each signal 6c differs between when the signal output from its output terminal rises and when it falls. The cell / boundary block delay table 32 stores the boundary block 16 when the signal output from each output terminal rises and when it falls.
Reference delay times of a, 16b, and 16c are described.

FIG. 10 shows the contents of the cell / boundary block delay table 32. The cell / boundary block delay table 32 includes a part 32-1 related to the boundary block 16b. The part 32-1 related to the boundary block 16b includes lines 32-1a and 32-1b.

An output terminal DOUT is connected to the line 32-1a.
The reference delay time t _pd ^16a of the boundary block 16a when the voltage of the signal output from the terminal rises is described. The reference delay time t _pd of the boundary block 16a when the voltage of the signal output from the output terminal DOUT rises
The minimum, standard, and maximum values of ^16a are 43
(Ps), 68 (ps), and 115 (ps).

An output terminal DOUT is connected to the line 32-1b.
The reference delay time t _pd ^16a of the boundary block 16a when the voltage of the signal output from the falling edge falls is described. The reference delay time t _pd of the boundary block 16a when the voltage of the signal output from the output terminal DOUT falls
The minimum value, standard value, and maximum value of ^16a are 48
(Ps), 83 (ps), and 143 (ps).

The cell / boundary block delay table 32 is
Further, a portion 32-2 related to the cell 13b is included. Cell 13
The portion 32-2 relating to b is a line 32-2a, 32-2
b. The line 32-2a describes the delay time from the clock terminal to the output terminal of the cell 13b. The line 32-2a describes the delay time when the voltage of the signal output from the output terminal of the cell 13b rises and when it falls.

The minimum value, standard value, and maximum value of the delay time from the clock terminal to the output terminal of the cell 13b when the voltage of the signal output from the cell 13b rises are respectively
135 (ps), 222 (ps), and 385 (ps). The minimum value, the standard value, and the maximum value of the delay time from the clock terminal to the output terminal of the cell 13b when the voltage of the signal output from the cell 13b falls are 138, respectively.
(Ps), 235 (ps), and 419 (ps).

The line 32-2b describes the delay time from the input terminal to the output terminal of the cell 13b. The line 32-2b describes the delay time when the voltage of the signal output from the output terminal of the cell 13b rises and when it falls.

When the voltage of the signal output from the cell 13b rises, the minimum value, the standard value, and the maximum value of the delay time from the input terminal to the output terminal of the cell 13b are 19, respectively.
5 (ps), 389 (ps) and 582 (ps).
The minimum value, standard value, and maximum value of the delay time from the clock terminal to the output terminal of the cell 13b when the voltage of the signal output from the cell 13b falls are 202 (p
s), 391 (ps) and 580 (ps).

The cell / boundary block delay table 32 is
Further, a portion 32-3 related to the cell 12b is included. Cell 12
The part 32-3 relating to the line b is composed of lines 32-3a and 32-3.
b. The line 32-3a is connected to the cell 1 when the voltage of the signal output from the output terminal of the cell 12b rises.
The delay time t _pd ^{12b of} 2b is described. Cell 1
The minimum value, standard value, and maximum value of the delay time t _pd ^12b of the cell 12b when the voltage of the signal output from the output terminal 2b rises are 51 (ps) and 94 (p, respectively).
s) and 138 (ps).

The line 32-3b describes the delay time t _pd ^12b of the cell 12b when the voltage of the signal output from the output terminal of the cell 12b falls. The minimum value of the delay time t _pd ^12b of the cell 12b when the voltage of the signal output from the output terminal of the cell 12b falls;
The standard value and the maximum value are 56 (ps) and 108, respectively.
(Ps) and 160 (ps).

The cell / boundary block delay table 32 is
Further, it includes a portion 32-4 related to the cell 13a. Cell 13
The part 32-4 related to the cell 13b is a part 32-4 related to the cell 13b.
It has the same contents as 2. Portion 32 of cell 13a
The description of 4 is omitted.

The cell / boundary block delay table 32 is
It includes a portion 32-5 related to the boundary block 16a and a portion 32-6 related to the boundary block 16c. Boundary block 1
The portion 32-5 of the boundary block 16c and the portion 32-5 of the boundary block 16c correspond to the portion 32-5 of the boundary block 16b.
It has the same contents as 1. Portion 32-5 of boundary block 16a and Portion 32-6 of boundary block 16c
Is omitted.

Macro Boundary Delay Library 1 for Macro 11
0 and the macro internal delay library 30 are generated by the macro delay library generation device of the first embodiment.

The macro delay library generation device of the first embodiment is a central processing unit (hereinafter referred to as a “CPU”).
Is provided together with the storage unit. The CPU 41 is shown in FIG.
As shown in FIG. 1, a storage unit 43 is connected via a bus 42.
Connect to The CPU 41 includes a boundary delay calculation tool 41a.
And a delay calculation tool 41b. The storage unit 43
It includes a cell library storage unit 43a, a macro net list storage unit 43b, a macro boundary delay library storage unit 43c, a reference delay time storage unit 43d, and a macro internal delay library storage unit 43e. The CPU 41 is further connected to an input unit 44 and an output unit 45 via a bus 42.

The process of generating the macro boundary delay library 10 and the macro internal delay library 30 of the macro 11 by the macro delay library generation device of the first embodiment is divided into steps S01 to S11 with reference to FIG. Explained.

Step S01: The cell library 50 is input to the input section 44. The cell library 50 includes the bus 4
2 to the storage unit 43. Cell library 50
Are stored in the cell library storage unit 43a.

In the cell library 50, characteristics of all types of cells constituting the macro are described. The cell library 50 includes cells of type BUF_A and type FF_
The characteristics of A with the cell are described. Cell library 5
0 includes a portion 51 related to a cell of type BUF_A and a portion 52 related to a cell of type FF_A, as shown in FIG.

The part 51 relating to a cell of type BUF_A is
It includes a cell information table 51a, a delay time table 51b, and an output waveform dullness table 51c. Cell information table 5
1a has a size x in the x direction of a cell of type BUF_A.
_size, size _{y s ize} the y direction, the capacitance _{C in} the input terminal, the resistance _{R d} of the capacitor _{C out} and output terminals of the output terminal itself is described. The delay time table 51b is
It is a table for calculating the delay time _{t pd} of the cell types BUF_A. Output waveform distortion table 51c is a table for calculating an output waveform distortion _t ^{rf out} of the cell types BUF_A.

FIG. 14 shows the contents of the cell information table 51a. The cell information table 51a has a line 51a-1.
To 51a-5. The type BU is included in the line 51a-1.
Cell in the x direction of the size _{x size} of F_A, y-direction dimensions _{y size} is described. x _size = 3.3
6 (um), y _size = 3.92 (um).

[0127] The line 51a-2, the capacitance _{C in} the input terminal of the cell types BUF_A is described. C _in
= 0.004042 (pF). Line 51a-3
The, are described possible range threshold voltage V _T of the input terminals of the cell types BUF_A. Threshold voltage V
The minimum, standard, and maximum values of _T are 0.8
(V), 0.84 (V), and 0.88 (V). The line 51a-4 describes the capacitance C _out of the output terminal of the cell of type BUF_A. C _out = 0.499
691 (pF).

[0128] The line 51a-5, the resistance _{R d} of the output terminal of the cell types BUF_A is described. Type BU
Resistance R _d of the output terminal of the cell of F_A includes a range where it can take, is represented by the standard value. Resistance R _d of the output terminal of the cell types BUF_A is different between when the voltage of the signal output from the output terminal rises, and when the fall.

When the voltage of the signal output from the output terminal rises, the resistance R of the output terminal of the cell of type BUF_A
The minimum, standard, and maximum values of _d are 0.8108, respectively.
01 (Ω), 1.27482 (Ω), 2.06138
(Ω). When want of falling voltage of the signal output from the output terminal DOUT is, the minimum value of the resistance _{R d} of the output terminal of the cell types BUF_A, standard value, maximum value, respectively 0.38163 (Ω), 0.616605 (Ω ), 1.
1556 (Ω).

FIG. 15 shows the contents of the delay time table 51b.
Is shown. The type BUF_A is stored in the delay time table 51b.
Cell delay time t_pdIs described. Type BUF
_A cell delay time t_pdIs input to the cell input terminal
Input waveform blunting t of the input signal_rfDepends on. type
BUF_A cell delay time t_pdIs the cell exit
Load capacitance C connected to the force terminal_LDepends on. Delay time
In table 51b, delay of cell of type BUF_A
Time t_pdIs described in the form of a matrix. So
Different input waveform dullness t for each row of the matrix_rf
Delay time t corresponding to_pdIs described. That mat
Different load capacity C for each row of ricks _LCorresponding to late
Delay time t_pdIs described.

The delay time t of a cell of type BUF_A
_pd differs between when the voltage of the signal output from the output terminal of the cell rises and when it falls. The delay time table 51b describes the delay time t _pd of the cell of the type BUF_A in both cases when the voltage of the signal output from the output terminal of the cell rises and when it falls.

The delay time table 51b, as shown in FIG.
1 and a fall delay time table 51b-2. The rise delay time table 51b-1 describes the delay time t _pd of the cell of type BUF_A when the voltage of the signal output from the output terminal of the cell of type BUF_A rises.

[0133] the rise delay time table 51b-1 is possible range of the delay time _{t pd} of the cell types BUF_A is described. Rise delay time table 5
1b-1 includes matrices 51b-1 to 51b-3. Matrix 51b-1, the minimum value of the delay time _{t pd} of the cell types BUF_A is described.

The matrix 51b-1 has a line 51b
-4 to 51b-8. A line 51b-4 has a type BUF_A when the input waveform dullness is 0.01 (ns).
The minimum value of the delay time t _pd of the cell is described. Similarly, lines 51b-5, 51b-6, 51b-7, 5
1b-8 has an input waveform dullness of 0.4 (n
s), 1 (ns), 3 (ns), 5 (ns)
Minimum value of the delay time _{t pd} of the cell types BUF_A is described.

Further, column 5 of matrix 51b-1
The 1b-9, when the load capacitance _{C L} is 0.01 (pF), the minimum value of the delay time _{t pd} of the cell types BUF_A is described. Similarly, columns 51b-10, 5
1b-11, 51b-12, 51b-13, 51b-1
The 4, respectively the load capacitance _{C L} is 0.05 (pF),
0.1 (pF), 0.2 (pF), 0.5 (pF), 1
When it is (pF), the minimum value of the delay time _{t pd} of the cell types BUF_A is described.

Matrix 51b-4, Matrix 5
The 1b-5, a typical value of the delay time _{t pd} of cells in each type BUF_A, the maximum value is described. The matrices 51b-4 and 51b-5 have the same contents as the matrix 51b-3. Matrix 5
The description of the contents of the matrix 1b-4 and the matrix 51b-5 is omitted.

The falling delay time table 51b-2 describes the delay time t _pd of the cell of type BUF_A when the voltage of the signal output from the output terminal of the cell of type BUF_A falls. The fall delay time table 51 b-2 is a rise delay time table 5.
It has the same contents as 1b-1. The description of the fall delay time table 51b-2 is omitted.

FIG. 16 is a diagram showing the contents of the output waveform blunting table 51c. The output waveform distortion table 51c, being described _{t rf} 'blunting the output waveform of the cell types BUF_A. Output waveform dullness t of cell of type BUF_A
_rf ′ depends on the input waveform dullness t _rf of the input signal input to the input terminal of the cell. Output waveform distortion t _rf cell types BUF_A _'further depend on the load capacitance C _L connected to the output terminal of the cell. Output waveform dullness table 5
1c, the output waveform dullness t of the cell of type BUF_A
_rf ′ is described in the form of a matrix. As each row of the matrix, t _{rf 'blunting} output waveform corresponding to the t _rf dullness different input waveforms are described. As for each column of the matrix, t _{rf 'blunting} output waveform corresponding to the different load capacitance C _L is described.

The output waveform dullness t _rf ′ of a cell of type BUF_A differs between when the voltage of the signal output from the output terminal of the cell rises and when it falls. The output waveform distortion table 51c, and when the voltage of the signal output from the output terminal of the cell rises, the case of both when falling, being described t _{rf 'blunting} the output waveform of the cell types BUF_A.

As shown in FIG. 15, the output waveform dulling table 51c has a rising output waveform dulling table 51c-1 and a falling output waveform dulling table 51c.
-2. Rise output waveform dullness table 51c
The -1, when the voltage of the signal output from the output terminal of the cell types BUF_A rises, Type Output waveform distortion t _rf cells of BUF_A _'is described.

The rising output waveform blunting table 51c-
The 1, output waveform distortion _{t rf} cell types BUF_A '
The possible range is described. The rising output waveform dullness table 51c-1 includes the matrices 51c-1 to 51c-1.
51c-3. The minimum value of the output waveform dullness t _rf ′ of the cell of the type BUF_A is described in the matrix 51c-1.

The matrix 51c-1 has a line 51c
-4 to 51c-8. The line 51c-4 has a type BUF_A when the input waveform dullness is 0.01 (ns).
The minimum value of the output waveform dullness t _rf ′ of the cell is described. Similarly, lines 51c-5, 51c-6, 51c-
7 and 51c-8 each have an input waveform dullness of 0.4
(Ns), 1 (ns) , 3 (ns), the time of 5 (ns), the minimum value of the output waveform blunting _{t rf} 'cell types BUF_A is described.

In addition, column 5 of matrix 51c-1
The 1c-9, when the load capacitance _{C L} is 0.01 (pF), the output waveform distortion _{t rf} cell types BUF_A '
Is described. Similarly, column 51c-1
0, 51c-11, 51c-12, 51c-13, 51
c-14 has a load capacitance _CL of 0.05 (p
F), 0.1 (pF), 0.2 (pF), 0.5 (p
F) describes the minimum value of the output waveform dullness t _rf ′ of the cell of type BUF_A when it is 1 (pF).

Matrix 51c-4, Matrix 5
In 1c-5, the standard value and the maximum value of the output waveform dullness t _rf ′ of the cell of type BUF_A are described. The matrices 51c-4 and 51c-5 have the same contents as the matrix 51c-3. The description of the contents of the matrices 51c-4 and 51c-5 is omitted.

Falling output waveform blunting table 51c-
The second, when the fall of the voltage of the signal output from the output terminal of the cell types BUF_A, type output waveform distortion t _rf cells of BUF_A _'is described. The falling output waveform blunting table 51c-2 has the same contents as the rising output waveform blunting table 51c-1. The description of the falling output waveform dullness table 51c-2 is omitted.

The portion 52 related to the type FF_A flip-flop includes a cell information table 52a, a delay time table 52b, and an output waveform dullness table 52c. Each of the cell information table 52a, the delay time table 52b, and the output waveform dulling table 52c has the same contents as the cell information table 51a, the delay time table 51b, and the output waveform dulling table 51c included in the portion 51 relating to the cell of type BUF_A. Have. Description of the portion 52 related to the flip-flop of the type FF_A is omitted.

[0147] By referring to the portion 51 of the cell types BUF_A cell library 50, when the input waveform blunting _{t rf} and the load capacitance _{C L} is given the type BUF
And the delay time of the cell _{t pd} of _A, the output waveform distortion _{t rf} '
Can be determined. Similarly, by referring to the portion 52 of the cell types FF_A cell library 50, when the input waveform blunting _{t rf} and the load capacitance _{C L} is given the type and delay time of a cell _{t pd} of FF_A, output The waveform dull _trf 'can be determined.

As shown in FIG. 12, step S
After step 01, step S02 is performed.

Step S02 The macro net list 53 is read. The macro netlist 53 describes how circuits included in the macro are connected to each other. The macro netlist b further describes how circuits included in the macro and external terminals of the macro are connected to each other.

The macro netlist 53 according to the present embodiment describes how the cells 12a to 12d and the cells 13a and 13b included in the macro 11 are connected to each other. The macro netlist b of the present embodiment further describes which of the cells 12a to 12d is connected to the input terminal DIN, the output terminal DOUT, or the clock input terminal CLKIN of the macro 11.

The macro net list 53 is input from the input unit 44. The macro net list c is output from the input unit 44 to the storage unit 43. Macro netlist 53
Are stored in the macro net list storage unit 43b. Step S03 is performed after step S02.

Step S03: The boundary blocks corresponding to the respective input terminals are defined by the CPU 41.
The boundary block corresponding to a certain input terminal is a macro 11
Of these, the delay time depends on the dull input waveform of the input signal input to the input terminal.

A boundary block 16a is defined corresponding to the input terminal DIN. At this time, the delay time of the boundary block 16a depends on the input waveform dullness _trf ^DIN of the input signal input from the input terminal DIN. The portion of the macro 11 other than the boundary block 16a has the input waveform dullness t.
_It does not depend on _rf ^DIN .

According to the clock input terminal CLKIN,
A boundary block 16c is defined. Boundary block 16c
Is dependent on the input waveform blunting t _rf ^CLKIN of the input signal input from the clock input terminal CLKIN. The delay time of the portion other than the boundary block 16c in the macro 11 does not depend on the input waveform dulling t _rf ^CLKIN .

In the present embodiment, the boundary block 1
Although each of 6a and 16c includes only one cell, the boundary block can include a plurality of cells connected in series. Subsequent to step S03, step S04 is performed.

Step S04: The reference delay time of the boundary block corresponding to each of the input terminals is calculated. The reference delay time t _rf ^{16a of} the boundary block ^16a is calculated corresponding to the input terminal DIN. Clock input terminal CL
The reference delay time t _rf ^{16c of} the boundary block ^16c is calculated corresponding to KIN.

Reference delay time t _rf of boundary block 16a
^16a is calculated as the delay time of the boundary block 16a when the input waveform dullness _trf ^{DIN of the} input signal input from the input terminal DIN is 0 (ns). The reference delay time t _rf ^16a is calculated both when the voltage of the signal output from the output terminal of the boundary block 16a rises and when it falls.

Reference delay time t _rf of boundary block 16a
^16a is determined as follows.

First, the load capacitance _C12a connected to the output terminal of the cell _12a is determined. The load capacity C _12a is calculated from the cell library 50 and the macro netlist 53. Referring to the macro net list 53, the load capacitance C _12a is determined by the capacitance of the input terminal of the cell 13a and the wiring 14
It is determined that this is the sum of the wiring capacitances of a. The capacity of the input terminal of the cell 13a is described in a cell information table 52a included in the cell library 50. The load capacitance C _12a connected to the output terminal of the cell _12a is
0 is uniquely determined from the macro netlist 53.

Subsequently, referring to the cell library 50,
Dull input waveform of input signal input from input terminal DIN
t_rf ^DINOf the cell 12a when is 0 (ns)
Delay time is determined. Input from the input terminal DIN
Input signal dullness t_rf ^DINIs 0 (ns)
When the input wave of the signal input to the input terminal of the cell 12a
Deformation is also 0 (ns). Included in cell library 50
With reference to the delay time table 51b to be
Of input signal is 0 (ns)
The delay time of the cell 12a at that time is calculated. At this time,
Calculated load capacity C_12aIs the delay time of cell 12a
Used to calculate.

The sum of the delay time of the cell 12a and the delay time of the wiring 14a when the input waveform of the signal input to the input terminal of the cell 12a is 0 (ns) is the boundary block 16
This is the reference delay time t _pd ^16a of a.

Similarly, the reference delay time t _rf ^16c of the boundary block 16c is set such that the input waveform bluntness of the input signal input from the clock input terminal CLKIN t _rf ^CLKIN is zero.
(Ns) is calculated as the delay time of the boundary block 16c. The reference delay time t _rf ^16c is calculated both when the voltage of the signal output from the output terminal of the boundary block 16c rises and when it falls.

Reference delay time t _rf of boundary block 16c
^The process of calculating ^16c is the same as the process of calculating the reference delay time t _rf ^16a of the boundary block 16a.
Description of the process of the reference delay time _t ^{rf 16c} of the boundary block 16c is calculated is omitted.

The calculated reference delay time t_rf ^16aAnd the border
Reference delay time t of the field block 16c _rf ^16cMeans
It is stored in the quasi-delay time storage unit 43d. Step S04
Then, step S05 is performed.

Step S05: The input waveform dullness-input boundary delay table 3 is stored in the boundary delay calculation tool 41 of the CPU 41.
a.

In step S05, first, an input boundary delay time is calculated for each of the input terminals. For one input terminal, an input boundary delay time corresponding to each of a plurality of input waveform dullness values is calculated.

Input boundary delay time t _{pd of} input terminal DIN
^DIN is calculated. The input waveform dullness of the signal input from the input terminal DIN t _rf ^DIN is 0.01 (ns),
0.4 (ns), 1 (ns), 3 (ns) and 5 (n
input boundary delay time t when each value of s) is taken
_pd ^DIN is calculated.

Similarly, input of clock input terminal CLKIN
Force boundary delay time t_pd ^CLKINIs calculated. Clock
Input waveform of the signal input from the input terminal CLKIN
Ri _rf ^CLKINAre 0.01 (ns), 0.4 (n
s), 1 (ns), 3 (ns) and 5 (ns)
Input boundary delay time t when this value is taken_pd ^CLKIN
Is calculated.

Input boundary delay time t _{pd of} input terminal DIN
^DIN is calculated as follows. First, the input waveform blunting _t ^{rf DIN} input terminal DIN is determined to a predetermined value. The input waveform dull _trf ^DIN is 0.01 (n
s), 0.4 (ns), 1 (ns), 3 (ns) and 5
(Ns). Boundary block 16a corresponding to a predetermined input waveform dull _trf ^DIN
Is calculated.

The delay time of the boundary block 16a depends on the wiring 1
4a and the sum of the delay times of the cells 12a.
The delay time of the wiring 14a is determined by the length of the wiring 14a. On the other hand, the delay time of the cell 12a is equal to the cell library a
Is calculated from the input waveform blunting of the input signal input from the input terminal of the cell 12a and the load capacitance connected to the output terminal of the cell 12a. The input waveform blunting of the input signal input from the input terminal of the cell 12a is equal to the input waveform blunting _trf ^DIN . The load capacity of the output terminal of the cell 12a is calculated from the cell library 50 and the macro netlist 53. The delay time of the cell 12a can be uniquely calculated. Therefore, the input waveform dullness _trf
The delay time of the boundary block 16a when ^DIN takes a predetermined value can also be uniquely calculated.

A value obtained by subtracting the reference delay time t _pd ^{16a of} the boundary block 16a from the delay time of the boundary block 16a when the input waveform dullness t _rf ^DIN takes a predetermined value is used as the input waveform dullness _trf ^DIN . The corresponding input boundary delay time t _pd ^DIN .

That is, the input waveform dullness t_rf ^DINPlace
The delay time of the boundary block 16a when a constant value is taken is t
_pd ^16a’, Then t_pd ^DIN= T_pd ^16a'-T_pd ^16a  It is. Where t_pd ^DINIs the input waveform dullness t_rf
^DINOf the input terminal DIN when takes the predetermined value.
This is the force boundary delay time. Also, t_pd ^16aIs the boundary
This is a reference delay time of the lock 16a.

The input waveform dullness t _rf ^DIN is 0.01 (n
s), 0.4 (ns), 1 (ns), 3 (ns) and 5
For each case of (ns), the input boundary delay time t _pd ^DIN is calculated.

The process of calculating the input boundary delay time t _pd ^{CLKIN of the} clock input terminal CLKIN is the same as the process of calculating the input boundary delay time t _pd ^DIN of the input terminal DIN. Description of the process of the input boundary delay time _t ^{pd CLKIN} clock input terminal CLKIN is calculated is omitted.

The input boundary delay time t _{pd of the} input terminal DIN
^{From DIN} , input boundary delay time t _pd ^{DIN of} input terminal DIN in input waveform dulling-input boundary delay table 3
Is generated according to the table 3-1 for calculating. From the input waveform dulling-input boundary delay time t _pd ^{CLKIN of the} clock input terminal CLKIN, the clock input terminal CLK of the input waveform dulling-input boundary delay table 3
A portion according to Table 3-2 for calculating the input boundary delay time t _pd ^CLKIN of IN is generated. An input waveform blunt-input boundary delay table 3 is generated.

The generated input waveform blunt-input boundary delay table 3 is stored in the boundary delay library storage unit 43c. Step S06 is performed subsequent to step S05.

Step S06: The CPU 41 determines a boundary block corresponding to each output terminal. The boundary block corresponding to a certain output terminal is a portion of the macro 11 whose delay time depends on the load capacitance connected to the output terminal. The boundary block corresponding to the output terminal DOUT is the boundary block 16b. The delay time of the boundary block 16b depends on the load capacitance _CDOUT connected to the output terminal DOUT. The delay time of the part of the macro 11 other than the boundary block 16b is represented by the load capacitance C
_It does not depend on _DOUT .

The number of cells included in one boundary block is always one. This is because the number of cells connected to one output terminal is limited to one. The one cell is hereinafter referred to as a boundary cell. The boundary cell of the boundary block 16b is cell 12
c. Step S07 is performed subsequent to step S06.

Step S07: The reference delay time of the boundary block corresponding to each of the output terminals is calculated by the CPU 41. The reference delay time of the boundary block corresponding to a certain output terminal is such that the load capacitance connected to that output terminal is zero.
It is calculated as the delay time of the boundary block when (pF). The reference delay time t _rf ^16b of the boundary block 16b is a delay time of the boundary block 16b when the load capacitance connected to the output terminal DOUT is 0 (pF). The reference delay time t _rf ^16b is calculated both when the voltage of the signal output from the output terminal of the boundary block 16b rises and when it falls. The reference delay time of the boundary block corresponding to each of the output terminals is calculated in the following process.

In the following description, the input terminal of the boundary cell
The cell to which the output terminal connects is called the first preceding cell. The cell whose output terminal is connected to the input terminal of the first preceding cell is called the second preceding cell. Similarly, the k-th
The cell whose output terminal is connected to the input terminal of the preceding cell is called the (k + 1) th preceding cell. k is a natural number.

First, N is selected such that the output waveforms of the output signals output from the respective output terminals of the Nth preceding cell and the (N + 1) th preceding cell become substantially equal. Subsequently, the load capacitance connected to the (N-1) th output terminal is calculated. The load capacity connected to the (N−1) th output terminal is calculated from the cell library 50 and the macro netlist 53.

The output waveform dullness of the Nth preceding cell is reduced by the (N
-1) The output waveform blunting of the (N-1) th preceding cell is calculated as the blunting input waveform of the preceding cell. The output waveform dullness of the (N-1) -th preceding cell is calculated based on the load capacitance connected to the (N-1) -th output terminal while referring to the output waveform dulling table 51c of the cell library 50.

Similarly, the output waveform blunting of the j-th preceding cell is defined as the blunting of the input waveform of the (j-1) -th preceding cell, and the (j-th)
1) The output waveform dullness of the preceding cell is calculated. The (j-
1) The output waveform dullness of the preceding cell is calculated from the load capacitance connected to the (j-1) th output terminal while referring to the output waveform dulling table 51c of the cell library 50. Here, j is a natural number equal to or less than N. The above process is sequentially performed for all natural numbers equal to or less than N, and the output waveform dullness of the first preceding stage cell is calculated.

In this embodiment, the first preceding cell is cell 1
3b. The second preceding cell includes a cell 12b and a cell 12b.
d. Here, the blunt output waveforms of the cells 12b and 12d and the blunt output waveform of the cell 13b are substantially the same. The output waveform dullness of the cell 13b is calculated from the load capacitance connected to the output terminal of the cell 13b, using the dull output waveforms of the cells 12b and 12d as the input waveform dullness of the cell 13b. The output waveform dullness of the cell 13b is calculated with reference to the output waveform dulling table 51c of the cell library 50.

Subsequently, the delay time of the boundary cell when the load capacitance connected to a certain output terminal is 0 (pF) is calculated. At this time, the input waveform of the boundary cell is dulled by the output waveform of the first preceding stage cell. The delay time of the boundary cell when the load capacitance connected to the output terminal DOUT is 0 (pF) is determined by the delay time table 51b of the cell library 50.
Is calculated with reference to.

In the present embodiment, the output waveform of the cell 13b is made to be the dull input waveform of the cell 12c, and the output terminal DO
The delay time of the cell 12c when the load capacitance connected to the UT is 0 (pF) is calculated. The delay time of the cell 12c when the load capacitance connected to the output terminal DOUT is 0 (pF) is obtained by referring to the delay time table 5 of the cell library 50.
1b with reference to FIG.

At this time, the input waveform dullness of the signal input to the input terminal of the boundary cell included in the boundary block 16b can be determined to have a predetermined value. For example, the input waveform blunting of the signal input to the input terminal of the cell 12c which is the boundary cell included in the boundary block 16b can be determined to be 0.4 (ns).

The load capacitance connected to the output terminal is 0 (pF)
The sum of the delay time of the boundary cell and the delay time of the wiring from the boundary cell to the output terminal is defined as the reference delay time of the boundary block.

In this embodiment, the sum of the delay time of the cell 12c and the delay time of the wiring 14f when the load capacitance connected to the output terminal DOUT is 0 (pF) is equal to the reference delay time t of the boundary block 16b. _pd ^16b .

The calculated reference delay time t _pd ^16b of the boundary block ^16b is stored in the reference delay time storage section 43d. Step S08 is performed subsequent to step S07.

Step S08: The load capacity-output boundary delay table 2 is generated by the boundary delay calculation tool 41 of the CPU 41.

In step S08, first, an output boundary delay time is calculated for each of the output terminals. An output boundary delay time t _pd ^{DOUT of the} output terminal DOUT is calculated. For one output terminal, an output boundary delay time corresponding to each of a plurality of load capacitance values is calculated. Load capacitance _{C DOUT} connected to the output terminal DOUT is 0.0
1 (pF), 0.05 (pF), 0.1 (pF), 0.
2 (pF), 0.5 (pF ) and 1 (pF) of the output boundary delay time _t ^{pd DO UT} when taking each value is calculated.

Output boundary delay time t of output terminal DOUT
_pd ^DOUT is calculated as follows. First,
Load capacitance _{C DOUT} output terminal DOUT is determined to a predetermined value. The load capacitance _CDOUT is 0.01 (pF),
0.05 (pF), 0.1 (pF), 0.2 (pF),
For the cases of 0.5 (pF) and 1 (pF), the delay time of the boundary block 16b is calculated, respectively.

The delay time of the boundary block 16b depends on the wiring 1
4f is the sum of the delay time of the cell 12c.
The delay time of the wiring 14f is determined by the length of the wiring 14f. On the other hand, the delay time of the cell 12 c
Referring to 0, it is calculated from the input waveform blunting of the input signal input from the input terminal of the cell 12c and the load capacitance connected to the output terminal of the cell 12c. The input waveform of the input signal input from the input terminal of the cell 12c is blunted by the cell 13b.
Output waveform is dull.

The output waveform of the cell 13b becomes blunt at step S
The same value as the value calculated in 07 is used. Cell 12
The load capacitance at the output terminal c is calculated by referring to the output delay time table 51b of the cell library 50. The load capacitance connected to the output terminal DOUT, the wiring capacitance of the wiring 14f, and the delay time of the cell 12c are calculated. The delay time of the boundary block 16a is calculated from the delay time of the cell 12c and the wiring delay of the wiring 14f.

From the delay time of the boundary block 16b when the load capacitance _CDOUT takes a predetermined value, the boundary block 1
Value reference delay time _t ^{pd 16b} is play reduction of 6b is, the load capacitance _{C DOUT} corresponding to the output boundary delay time _{t pd}
^DOUT .

That is, the load capacity C_DOUTIs a given value
The delay time of the boundary block 16b when_pd
^16b’, Then t_pd ^DOUT= T_pd ^16b'-T_pd ^16b  It is. Where t_pd ^DOUTIs the load capacity C
_DOUTIs the output terminal DOUT when takes the predetermined value.
Is the output boundary delay time.

When the load capacitance _CDOUT is 0.01 (ns),
0.4 (ns), 1 (ns), 3 (ns) and 5 (n
In each case of s), the output boundary delay time t _pd ^DOUT is calculated.

A load capacity-output boundary delay table 2 is generated from the calculated output boundary delay time t _pd ^{DOUT of} the output terminal DOUT. The generated load capacity-output boundary delay table 2 is stored in the boundary delay library storage unit 43c. Following step S08, step S09
Is performed.

Step S09: The load capacity-output waveform dullness table 4 is generated by the CPU 41.

In step S09, first, the output waveform dullness of the output signal output from each output terminal of the macro 11 is calculated. The output waveform dullness t _rf ^{DOUT of the} output signal output from the output terminal DOUT is calculated. The load capacitance _CDOUT is 0.01 (ns), 0.4 (ns),
For each of the cases of 1 (ns), 3 (ns), and 5 (ns), the output waveform dull _trf ^{DOUT of the} output signal output from the output terminal ^DOUT is calculated.

The output waveform blunting of the output signal output from the output terminal DOUT, _trf ^DOUT, is equal to the output waveform blunting of the output signal output from the output terminal of the cell 12c. The output waveform blunting of the output signal output from the output terminal of the cell 12c is performed by the output waveform blunting table 5 of the cell library 50.
1c. At this time, the input waveform dullness of the cell 12c required to calculate the output waveform dullness of the cell 12c is assumed to be equal to the one calculated in step S07. The load capacitance of the output terminal of the cell 12c required for calculating the output waveform dullness of the cell 12c is the sum of the load capacitance connected to the output terminal DOUT and the wiring capacitance of the wiring 14f.

A load capacity-output waveform dullness table 4 is generated from the calculated output waveform dullness t _rf ^DOUT .
The load capacity-output waveform dullness table 4 is stored in the macro boundary delay library storage unit 43c. Step S08
Then, step S10 is performed.

Step S10: The macro information table 1 is generated by the CPU 41. The size x _{size of} the macro 11 in the x direction and the size y of the macro 11 in the y direction
_{The size} is determined from the cell library 50 and the macro netlist 53. The capacitance of each output terminal of the macro 11 is described. The capacitance of the output terminal DOUT is the sum of the capacitance of the output terminal itself of the cell 12c and the wiring capacitance of the wiring 14f. The capacity of the output terminal itself of the cell 12c is described in the cell information table 51a of the cell library 50.

The capacitance of each input terminal of the macro 11 is calculated. And the capacitance _{C DIN} input terminal DIN, the capacitance _{C CLKIN} clock input terminal CLKIN is calculated. Capacitance _{C DIN} input terminal DIN is the sum of the wiring capacitance of the capacitor and the wiring 14a of the input terminal of the cell 12a. Capacitance _{C CLKIN} clock input terminal CLKIN is a capacitance of the input terminal of the cell 12c, is the sum of the wiring capacitance of the wiring 14 g. The capacity of the input terminal of the cell 12a and the capacity of the input terminal of the cell 12c are described in the cell information table 51a of the cell library 50.

Further, the threshold voltage of each input terminal of the macro 11 is calculated. The threshold voltage of the input terminal DIN is the threshold voltage of the input terminal of the cell 12a. The threshold voltage of the clock input terminal CLKIN is the threshold voltage of the input terminal of the cell 12c. The threshold voltage of the input terminal of the cell 12a and the threshold voltage of the input terminal of the cell 12c are described in the cell information table 51a of the cell library 50.

Further, the output resistance of each output terminal of the macro 11 is calculated. Output resistance _{R d} of the output terminal DOUT is an output resistance of the output terminal of the cell 12c. The output resistance of the output terminal of the cell 12c is
Is described in the cell information table 51a.

As described above, all information described in the macro information table 1 is calculated. Macro information table 1
Is generated. The generated macro information table 1 is stored in the macro boundary delay library storage unit 43c.

The macro boundary delay library 10 is generated by the processes of steps S01 to S10 and stored in the macro boundary delay library storage section 43c. Step S11 is performed after step S10.

Step S11: The macro internal delay library 30 is generated by the delay calculation tool 41b of the CPU 41. Cell library 50 and macro netlist 53
From this, the delay times of the cells 12b, 13a, and 13b are calculated. The calculated delay time of the cell 12b, the cell 13a, and the cell 13b, and steps S04 and S0
Reference delay time _t ^pd 16a of the boundary block 16a~16c calculated in ^{_{7, t pd 16b, t p}} d 16c is described as contents of the intra-macro delay library 30.
The generated macro internal delay library 30 is stored in the macro internal delay library storage unit 43e.

Step S12: If necessary, the macro boundary delay library 10 and the macro internal delay library 3
0 is output from the output unit 44.

The macro boundary delay library 10 and the macro internal delay library 30 may be stored in a storage unit of a computer and used. The macro boundary delay library 10 and the macro internal delay library 30 may be recorded on a recording medium and provided to a user.

Subsequently, the macro boundary delay library 10
And the macro 1 using the macro internal delay library 30
The process of verifying the operation timing of the semiconductor integrated circuit including No. 1 will be described.

The operation timing of the semiconductor integrated circuit including the macro 11 is verified by the semiconductor integrated circuit operation timing verification device of the first embodiment. The operation timing verification device for a semiconductor integrated circuit according to the first embodiment includes a central processing unit (hereinafter, referred to as a “CPU”) together with a storage unit. The CPU 61 is connected to the storage unit 63 via the bus 62 as shown in FIG.

The CPU 61 includes a delay calculation tool 61b,
It includes a delay analysis tool 61b. The storage unit 63 includes a cell library storage unit 63a, a circuit net list storage unit 63b,
It includes a macro boundary delay library storage unit 63c, a macro internal delay library storage unit 63d, and a macro external delay time storage unit 63e. The CPU 61 is further connected to an input unit 64 and an output unit 65 via a bus 62.

A process in which the operation timing of the semiconductor integrated circuit 70 including the macro 11 is verified by the operation timing verification apparatus for a semiconductor integrated circuit according to the first embodiment will be described. As shown in FIG. 18, the semiconductor integrated circuit 70 includes a macro 11, cells 71a and 71b, a cell 72a,
72b. The cells 71a and 71b are of the type FF-A. Each of the cells 71a and 71b has an input terminal, an output terminal, and a clock terminal. The cells 72a and 72b are cells of type BUF_A. Each of the cells 72a and 72b has an input terminal and an output terminal.

The output terminal of the cell 71a is connected to the input terminal of the cell 72a via the wiring 73a. The output terminal of the cell 72a is connected to the input terminal D of the macro 11 via the wiring 73b.
Connect to IN. The output terminal DOUT of the macro 11 is connected to the input terminal of the cell 72b via the wiring 73c. The output terminal of the cell 72b is connected to the cell 71b via a wiring 73d.
Connect to the input terminal of

A clock signal CLK is input to the clock terminals of the cells 71a and 71b and the clock input terminal CLKIN of the macro 11.

The process of verifying the operation timing of the semiconductor integrated circuit 70 by the semiconductor integrated circuit operation timing verification device of the first embodiment will be described by dividing into steps S21 to S27 with reference to FIG. Is done.

Step S21: The cell library 50, the macro boundary delay library 10, the macro internal delay library 30, and the circuit net list 54 are inputted from the input section 64. The contents of the cell library 50, the macro boundary delay library 10, and the macro internal delay library 30 are as described above. The configuration of the semiconductor integrated circuit 70 is described in the circuit netlist 54. The circuit netlist 54 includes cells 71 included in the semiconductor integrated circuit 70.
It describes how a, 71b, 72a, 72b and macro 11 are connected to each other. Subsequent to step S21, step S22 is performed.

Step S22: When the input waveform of the input signal input from each of the input terminals of the macro 11 becomes dull,
It is calculated by the delay calculation tool 61a of the PU 61. Input signal dullness of input signal input from input terminal DIN
_rf ^DIN and an input waveform blunting t _rf ^{CLKIN of the} clock signal input from the clock input terminal ^CLKIN are calculated.

The input waveform dullness _trf ^DIN of the input signal input from the input terminal DIN is calculated as follows.

The output waveform dullness _trf ^71a 'of the signal output from cell 71a is calculated. The input waveform blunting t _rf ^71a of the signal input to the cell 71a is a waveform blunting of the clock signal CLK. The waveform bluntness of the clock signal CLK is a given given value.

The load capacitance C _71a connected to the output terminal of the cell 71a is the sum of the wiring capacitance of the wiring 73a, the capacitance of the output terminal of the cell 71a itself, and the capacitance of the input terminal of the cell 72a. The capacity of the output terminal itself of the cell 71a is described in a cell information table 52a included in the cell library 50. The capacity of the input terminal of the cell 72a is described in the cell information table 51a included in the cell library 50.

The input waveform dull _trf ^71a and the load capacitance C
Based on _71a, the cell 71a with reference to the output waveform distortion delay table 52c included in the cell library 50
Is calculated, the output waveform dull _trf ^71a 'of the signal output from the.

Subsequently, the output waveform dullness _trf ^72a 'of the signal output from the cell 72a is calculated. Cell 72a
Input waveform blunting _t ^{rf 72a} of the signal input is equal to _t ^{rf 71a} 'blunting output waveform of the signal outputted from the cell 71a to.

The load capacitance C _72a connected to the output terminal of the cell 72a is the sum of the wiring capacitance of the wiring 73b and the capacitance of the input terminal DIN of the macro 11. The capacity of the input terminal DIN of the macro 11 is described in the macro information table 1 included in the macro boundary delay library 10.

The input waveform dull _trf ^72a and the load capacitance C
Based on _72a, the cell 72a with reference to the output waveform distortion delay table 51c included in the cell library 50
Is calculated, the output waveform dullness _trf ^72a 'of the signal output from is calculated.

The input waveform dullness t _rf ^DIN of the input signal input from the input terminal DIN is equal to the output waveform dullness t _rf ^72a ′ of the signal output from the cell 72a. Through the above process, the input waveform dullness _trf ^{DIN of the} input signal input from the input terminal ^DIN is calculated.

On the other hand, input from clock input terminal CLKIN
Input waveform blunting t of the input signal_rf ^CLKINIs
Equal to the dull waveform of the clock signal CLK. Clock input terminal
Input waveform blunting t of signal input from CLKIN_rf
^CLKINIs calculated. Subsequent to step S22,
Step S23 is performed.

Step S23: The load capacity connected to each output terminal of the macro 11 is calculated by the delay calculation tool 61a of the CPU 61. Load capacitor _{C D OUT} connected to the output terminal DOUT is calculated. Load capacity C
_DOUT is equal to the sum of the wiring capacitance of the wiring 73c and the capacitance of the input terminal of the cell 72b. The capacity of the input terminal of the cell 72b is described in the cell information table 51a of the cell library 50. Following step S23, step S23
24 is performed.

Step S24: The input boundary delay time of each input terminal of the macro 11 and the output boundary delay time of each output terminal are calculated by the delay calculation tool 6 of the CPU 61.
1a. Input terminal DIN of the input boundary delay time _t ^{pd DIN,} output boundary delay time _t ^{pd DIN} input boundary delay time _t ^{pd CLKIN} and the output terminal DOUT of the clock input terminal CLKIN is calculated.

[0233] Dullness of input waveform at input terminal DIN _trf
^DIN has been calculated in step S22. The input boundary delay time t _pd ^DIN of the input terminal DIN is calculated based on the input waveform dullness t _rf ^DIN with reference to the input waveform dullness-input boundary delay table 3.

The input waveform of the clock input terminal CLKIN becomes dull.
Ri_rf ^CLKINIs calculated in step S22.
You. Input boundary delay time t of clock input terminal CLKIN
_pd ^CLKINIs the input waveform dullness t_rf ^CLKINBased on
Input waveform blunt-input boundary delay table 3
It is calculated while.

Load capacitance C connected to output terminal DOUT
_DOUTIs calculated in step S23. Output end
Output boundary delay time t of child DOUT_pd ^DOUTIs the load
Capacity C _DOUTBased on the load capacitance-output boundary delay
Calculated with reference to Table 2. In step S24
Subsequently, step S25 is performed.

Step S25: The output waveform of the output signal output from each of the output terminals of the macro 11 becomes C
It is calculated by the delay calculation tool 61a of the PU 61. The output waveform dullness t _rf ^DOUT ′ of the output signal output from the output terminal DOUT is calculated. Load capacity C
_{D OUT} is equal to the sum of the wiring capacitance of the wiring 73c and the capacitance of the input terminal of the cell 72b. Based on the load capacitance _CDOUT , the output waveform dullness t _rf ^DOUT ′ is calculated with reference to the load capacitance-output waveform dullness table 4 included in the macro boundary delay library 10. Step S25 is performed following step S24.

Step S26: The delay time of the portion other than the macro 11 in the semiconductor integrated circuit 70 is calculated by the delay calculation tool 61a of the CPU 61. Cell 71a,
The delay times of 71b and 72a are calculated respectively.

The input waveform dullness t of the cell 71a
_rf ^71a is equal to the blunt waveform of the clock signal CLK. The load capacitance C _71a of the cell 71a is equal to the sum of the wiring capacitance of the wiring 73a and the capacitance of the input terminal of the cell 72a.
Based on the input waveform blunting _t ^{rf 71a} and the load capacitance _{C 7 1a,} the delay time _{t pd} of the cell 71a with reference to the delay time table 52a included in the cell library 50
^71a is calculated.

The input waveform blunting t of the cell 72a
_rf ^72a is the cell 71a calculated in step S22.
The output waveform of the signal output from is equal to _trf ^71a '. The load capacitance C _72a of the cell 72a is equal to the sum of the wiring capacitance of the wiring 73b and the capacitance of the input terminal DIN of the macro 11. Input waveform dull _trf ^72a and load capacitance C
Based on the _72a, the delay time _t ^{pd 72a} of cell 72a is calculated with reference to the delay time table 51a included in the cell library 50.

Input waveform blunting t of cell 72b
_rf ^72bIs output from the output terminal DOUT of the macro 11
Output waveform blunting t of the output signal_rf ^DOUT’
No. Output waveform dullness t_rf ^DOUT’In step S24
It has been calculated. Load capacity C of cell 72a _72aIs
Of the capacitance of the line 73c and the capacitance of the input terminal of the cell 71b
Equal to the sum. The capacity of the input terminal of the cell 71b is
Described in the cell information table 52a included in the library 50.
Have been. Input waveform dullness t_rf ^72bAnd load capacity C
_72b, The delay included in the cell library 50
When the cell 72a is delayed while referring to the time table 51a
Interval t_pd ^72aIs calculated. Following step S26
Step S27 is performed.

Step S27: The input boundary delay time and the output boundary delay time calculated in step S24, the delay time of the part outside the macro 11 calculated in step S26, and the macro 11 described in the macro internal delay library 30 The operation timing of the semiconductor integrated circuit 70 is verified based on the internal delay time. Verification of the operation timing of the semiconductor integrated circuit 70 is performed by the delay analysis tool 61b of the CPU 61.

At this time, a signal passing through the input terminal DIN of the macro 11, that is, a signal input to the input terminal DIN is virtually regarded as delayed by the input boundary delay time t _pd ^DIN . The signal passing through the clock input terminal CLKIN, that is, the clock signal CLK input to the clock input terminal CLKIN has an input boundary delay time t _pd ^C
A delay of ^LKIN is considered virtually. Further, a signal passing through the output terminal DOUT, that is, the output terminal DOU
Signal output from the T is output boundary delay time t _{p d}
^A delay of ^DOUT is virtually assumed.

In step S27, a delay time _Td until the signal output from the output terminal of cell 71a reaches the input terminal of cell 71b is calculated. Delay time T
_d is the delay time of the cells 72a, 72b,
3b is the sum of the wiring delay, the input boundary delay time t _pd ^DIN , the output boundary delay time t _pd ^DOUT and the delay time from the input terminal DIN to the output terminal DOUT of the macro 11. From the input terminal DIN to the output terminal DOUT of the macro 11
The delay time until is calculated from the macro internal delay library 30.

Further, based on the delay time _Td , the cell 71
It is determined whether the timing at which the signal output from the output terminal a reaches the input terminal of the cell 71b and the timing of the clock signal CLK are appropriate. Delay time T _d
From the result of the timing judgment, report file 5
5 is generated. The report file 55 is stored in the report file storage unit 63f. Step S28 is performed following step S27.

Step S28: The report file 55 is output from the output section 65. The verification of the operation timing of the semiconductor integrated circuit 70 ends.

The operation timing verification apparatus and method for a semiconductor integrated circuit according to the present embodiment comprises: an input boundary delay time;
The operation timing of the semiconductor integrated circuit 70 is verified based on the output boundary delay time. The input boundary delay time indicates a portion of the delay time generated inside the macro 11 that depends on the input waveform dullness of the signal input to the input terminal. The output boundary delay time indicates a portion of the delay time generated inside the macro 11 that depends on the load capacitance of the output terminal. The input boundary delay time and the output boundary delay time are calculated with reference to the macro boundary delay library 10.

The operation timing verification apparatus and verification method for a semiconductor integrated circuit according to the present embodiment uses the macro boundary delay library 10 and the macro internal delay library 30 to reduce the input waveform blunting of the signal input to the input terminal and the output terminal. The operation timing of the semiconductor integrated circuit 70 including the macro 11 is verified while considering the effect of the load capacitance on the delay time.

In this manner, the operation timing of the semiconductor integrated circuit 70 including the macro 11 is simply and accurately verified.

[0249]

According to the present invention, the operation timing of a semiconductor integrated circuit including a macro can be accurately and simply verified.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a macro boundary delay library according to a first embodiment;

FIG. 2 is a diagram illustrating a configuration of a macro 11 corresponding to a macro boundary delay library according to the first embodiment;

FIG. 3 is a diagram illustrating a macro information table 1;

FIG. 4 is a diagram illustrating a load capacity-output boundary delay table 2;

FIG. 5 is a diagram showing an input waveform dullness-input boundary delay table 3;

FIG. 6 is a diagram showing a definition of waveform dullness _trf .

FIG. 7 is a diagram showing an output waveform dullness-output boundary delay table 4;

FIG. 8 is a diagram illustrating a macro internal delay library 30;

FIG. 9 is a diagram illustrating a wiring delay table 31;

FIG. 10 is a diagram showing a cell / boundary block delay table 32;

FIG. 11 is a diagram illustrating a macro boundary delay library generation device according to the first embodiment;

FIG. 12 is a flowchart illustrating a process of generating a macro boundary delay library according to the first embodiment by the macro boundary delay library generation device according to the first embodiment;

FIG. 13 is a diagram showing the contents of a cell library 50;

FIG. 14 is a diagram showing the contents of a cell information table 51a.

FIG. 15 is a diagram showing the contents of a delay time table 51b.

FIG. 16 is a diagram showing the contents of an output waveform dulling table 51c.

FIG. 17 is a diagram illustrating an operation timing verification device of the semiconductor integrated circuit according to the first embodiment;

FIG. 18 is a diagram illustrating a configuration of a semiconductor integrated circuit 70 whose operation timing is verified by the operation timing verification device for a semiconductor integrated circuit according to the first embodiment;

FIG. 19 is a flowchart showing a process of verifying the operation timing of the semiconductor integrated circuit 70;

FIG. 20 is a diagram illustrating a conventional timing simulation method.

FIG. 21 is a diagram showing a circuit model used in a conventional timing simulation method.

[Explanation of symbols]

S01-S12, S21-S28: Step 1: Macro information table 2: Load capacity-output boundary delay table 3: Input waveform dullness-Input boundary delay table 4: Load capacitance-Output waveform dullness table 10: Macro boundary delay library 11: Macros 12a-12b, 13a, 13b, 71a, 71b, 7
2a, 72b: cells 14a to 14j, 73a to 73d: wiring 70: semiconductor integrated circuits 41, 61: CPU 42, 62: buses 43, 63: storage units 44, 64: input units 45, 65: output units

Claims (22)

[Claims] 1. A step of obtaining circuit configuration information of a semiconductor integrated circuit, wherein the semiconductor integrated circuit includes a macro having an external terminal, and an external circuit connected to the external terminal, and provides a boundary delay table. The boundary delay table indicates a dependency between a physical quantity given to the external terminal and a boundary delay time, and calculates the physical quantity based on characteristics of the external circuit. Referring to the boundary delay table, calculating the boundary delay time based on the physical quantity, a signal passing through the external terminal is delayed by the boundary delay time when passing through the external terminal. Verifying the operation timing of the semiconductor integrated circuit. 2. The input signal according to claim 1, wherein the physical quantity includes an input waveform dullness value indicating a delay of a timing at which a voltage of an input signal input to the external terminal changes. A method for verifying operation timing of a semiconductor integrated circuit including an input waveform dullness-boundary delay table indicating a dependency between a value and the boundary delay time. 3. The physical quantity according to claim 1, wherein the physical quantity includes a load capacity connected to the external terminal, and wherein the boundary delay table indicates a load capacity indicating a dependency between the load capacity and the boundary delay time. An operation timing verification method for a semiconductor integrated circuit including a boundary delay table. 4. The method according to claim 3, wherein the step of verifying the operation timing includes the step of providing a load capacitance-output waveform dullness table indicating a dependency between the load capacitance and an output waveform dullness value. Here, the output waveform blunt value indicates a delay in timing at which a voltage of an output signal output from the external terminal to the external circuit changes, and the load capacitance-output waveform blunt value table is referred to, and the load capacitance is reduced. Calculating the output waveform blunt value based on the following: calculating the external delay time generated in the external circuit based on the output waveform blunt value; based on the boundary delay time and the external delay time Verifying the operation timing of the semiconductor integrated circuit by performing the operation timing verification. 5. A step of acquiring circuit configuration information of a semiconductor integrated circuit, wherein the semiconductor integrated circuit includes: a macro having an input terminal and an output terminal; a first external circuit connected to the input terminal; Calculating an input boundary delay time, wherein the input boundary delay time is a delay time virtually assumed to occur at the input terminal; Calculating a delay time, wherein the output boundary delay time is a delay time virtually assumed to occur at the output terminal, and calculating a first external circuit delay time generated in the first external circuit. Calculating a second external circuit delay time generated in the second external circuit; calculating a macro internal delay time generated in a circuit included in the macro And a signal passing through the input terminal is delayed by the input boundary delay time when passing through the input terminal, and a signal passing through the output terminal is passed through the output terminal. , The input boundary delay time, the output boundary delay time, the first external circuit delay time, the second external circuit delay time, and the macro internal delay time. Verifying the operation timing of the semiconductor integrated circuit on the basis of the above, wherein calculating the input boundary delay time comprises: providing an input waveform dullness-boundary delay table; and The input waveform dullness-boundary delay table indicates the dependency between the input waveform dullness and the input boundary delay time, and wherein the input waveform dullness is: A delay of a timing at which a voltage of an input signal input to the input terminal changes; calculating the input waveform blunt value based on characteristics of the first external circuit; and the input waveform blunt value-boundary delay Referring to a table and calculating the input boundary delay time based on the calculated input waveform dullness value. The step of calculating the output boundary delay time provides a load capacity-boundary delay table. And the load capacitance-boundary delay table indicates a dependency between the load capacitance connected to the output terminal and the output boundary delay time, based on a characteristic of the second external circuit. Calculating the load capacity, and referring to the load capacity-boundary delay table, calculating the output boundary delay time based on the calculated load capacity. And an operation timing verification method for a semiconductor integrated circuit. 6. The method according to claim 5, wherein the step of calculating the second external circuit delay time comprises: providing a load capacitance-output waveform dullness table; and wherein the load capacitance-output waveform dullness value is provided. The table shows a dependency between the load capacitance and an output waveform blunting value, and the output waveform blunting value shows a delay in a timing at which a signal output from the output terminal changes, and the load capacitance − A semiconductor comprising: a step of calculating the output waveform dull value based on the load capacitance with reference to an output waveform dull value table; and a step of calculating the second external circuit delay time based on the output waveform dull value. An operation timing verification method for an integrated circuit. 7. A structure obtaining means for obtaining circuit configuration information of a semiconductor integrated circuit, wherein the semiconductor integrated circuit includes a macro having an external terminal, and an external circuit connected to the external terminal, wherein a boundary delay table Where the boundary delay table is
A physical quantity calculation unit that calculates the physical quantity based on the characteristics of the external circuit, and indicates a dependency between the physical quantity given to the external terminal and the boundary delay time; A boundary delay time calculating means for calculating the boundary delay time based on a physical quantity, a signal passing through the external terminal is virtually regarded as being delayed by the boundary delay time when passing through the external terminal, An operation timing verification device for a semiconductor integrated circuit, comprising: operation timing verification means for verifying operation timing of the semiconductor integrated circuit. 8. The physical delay according to claim 7, wherein the physical quantity includes an input waveform blunting value indicating a delay of a timing at which a voltage of an input signal input to the external terminal changes, and the boundary delay table stores the input waveform blunting. An operation timing verification device for a semiconductor integrated circuit including an input waveform dullness-boundary delay table indicating a dependency between a value and a boundary delay time. 9. The physical quantity according to claim 7, wherein the physical quantity includes a load capacity connected to the external terminal, and wherein the boundary delay table indicates a load capacity indicating a dependency between the load capacity and the boundary delay time. An operation timing verification device for a semiconductor integrated circuit including a boundary delay table. 10. The method according to claim 9, wherein the boundary delay table includes a load capacitance-output waveform dullness table indicating a dependency between the load capacitance and an output waveform dullness value, wherein the output waveform dullness value is: The operation timing verification unit indicates a delay of a timing at which a voltage of an output signal output from the external terminal to the external circuit changes, and the operation timing verification unit refers to the load capacitance-output waveform blunt value table, based on the load capacitance. An output waveform blunt value calculating means for calculating the output waveform blunt value; an external delay time calculating means for calculating an external delay time generated in the external circuit based on the output waveform blunt value; the boundary delay time and the external delay Verification means for verifying an operation timing of the semiconductor integrated circuit based on time. 11. A boundary delay table, wherein the boundary delay table indicates a dependency between a physical quantity given to an external terminal of a macro and a boundary delay time, and the boundary delay time is: A macro delay information library indicating a delay time that is virtually regarded as a signal passing through the external terminal being delayed at the external terminal. 12. The physical quantity according to claim 11, wherein the physical quantity includes an input waveform blunting value indicating a delay in timing at which a voltage of an input signal input to the external terminal changes, and the boundary delay table stores the input waveform blunting. A macro delay information library including an input waveform dullness-boundary delay table indicating a dependency between a value and the boundary delay time. 13. The physical quantity according to claim 11, wherein the physical quantity includes a load capacity connected to the external terminal, and wherein the boundary delay table indicates a load capacity indicating a dependency between the load capacity and the boundary delay time. Macro delay information library including boundary delay tables. 14. The apparatus according to claim 13, further comprising a load capacitance-output waveform dullness value table indicating a dependency between the load capacitance and an output waveform dullness value, wherein the output waveform dullness value is output from the external terminal. A macro delay information library showing a delay in the timing at which the voltage of the output signal changes. 15. The macro delay information library according to claim 11, further comprising a macro internal delay table, wherein the macro internal delay table indicates a delay time generated inside the macro. 16. The macroblock according to claim 15, wherein the macro includes a boundary block, and a boundary block delay time generated in the boundary block is:
The macro internal delay table describes a reference delay time considered to virtually occur in the boundary block, and the reference delay time is dependent on the physical quantity given to the external terminal. A macro delay information library that is independent, wherein the sum of the reference delay time and the boundary delay time is substantially equal to the boundary block delay time. 17. A step of obtaining circuit configuration information of a macro, wherein the macro has an external terminal, and selecting a part of the macro as a boundary block, wherein the macro block information is generated in the boundary block. Calculating a boundary block delay time corresponding to each of a plurality of values of the physical quantity, the boundary block delay time being dependent on a physical quantity given to the external terminal; and Generating a boundary delay table indicating the dependence between the physical quantity and the boundary delay time, wherein the boundary delay time is a macro delay that is virtually regarded as occurring at the external terminal. Information library generation method. 18. The method according to claim 17, wherein the physical quantity includes an input waveform blunting value indicating a delay in timing at which a voltage of an input signal input to the external terminal changes, and the boundary delay table stores the input waveform blunting. A method for generating a macro delay information library including an input waveform dullness-boundary delay table indicating a dependency between a value and the boundary delay time. 19. The physical quantity according to claim 17, wherein the physical quantity includes a load capacity connected to the external terminal, and the boundary delay table indicates a load capacity that indicates a dependency between the load capacity and the boundary delay time. A method for generating a macro delay information library including a boundary delay table. 20. The method according to claim 17, wherein the step of generating the boundary delay table includes the step of determining a reference delay time, wherein the reference delay time is determined when the physical quantity is a predetermined value. A macro delay information library generating method, comprising calculating the boundary delay time by subtracting the reference delay time from the boundary block delay time, the delay time occurring in a block. 21. The macro internal delay table according to claim 20, further comprising the step of generating a macro internal delay table, wherein the macro internal delay table indicates a delay time generated inside the macro, and the reference time is used in the boundary block. A method for generating a macro delay information library describing that a delay corresponding to a delay time occurs. 22. A structure acquiring unit for acquiring circuit configuration information of a macro, wherein the semiconductor integrated circuit includes: a macro having an external terminal; and an external circuit connected to the external terminal; A boundary block delay time generated in the boundary block depends on a physical quantity given to the external terminal, and the boundary block delay time corresponding to a plurality of values of the physical quantity. And calculating means for calculating a boundary delay table indicating a dependency between the physical quantity and the boundary delay time based on the calculated boundary block delay time. Is a macro delay information library generation device that is a delay time virtually regarded as occurring at the external terminal.