JP2001267851A - Distortion compensating amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the accuracy of distortion compensation by using inexpensive and highly accurate A/D converters for a distortion compensating amplifier for compensating distortion generated in the amplifier on the basis of the digital level value of a signal acquired by using the A/D converters and allowed to be amplified. SOLUTION: An analog level detection means 2 detects the analog level of a signal to be amplified by an amplifier, n (=2) A/D converters 5, 6 respectively acquire digital level values from the detected result in a period nT (=1/40 MHz) corresponding to n times of prescribed period T (=1/80 MHz) at timing mutually shifted from the prescribed period T, a synthesis means 7 generates a digital level value of the prescribed period T from the acquired digital level values, and a distortion compensation means 8 controls the amplitude and phase of the signal amplified by the amplifier 9 on the basis of the generated digital level value to compensate distortion generated from the amplifier 9.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a distortion compensating amplifier for compensating for distortion generated in an amplifier based on a digital level value of a signal to be amplified acquired by using an A / D converter. The present invention relates to a distortion compensation amplifier that improves the accuracy of distortion compensation as a configuration using a high-precision A / D converter.

[0002]

2. Description of the Related Art For example, W-CDMA (Wide-band Code D)
The prior art will be described by taking a mobile communication system adopting the ivision Multiple Access (ivision Multiple Access) system as a mobile communication system as an example. In such a W-CDMA mobile communication system, a base station apparatus (CDMA base station apparatus) and a mobile station apparatus (CDM)
A mobile station device) performs wireless communication of a wideband signal by the CDMA method. In such wireless communication, for example, in a base station apparatus, a signal to be wirelessly transmitted needs to reach a physically distant mobile station apparatus. Therefore, a signal to be transmitted is greatly amplified by an amplifier (amplifier). It is necessary to amplify the signal and transmit the signal from the antenna.

However, since the amplifier is an analog device, the amplifier has an amplification limit. This amplification limit is also called a saturation point. If the power level of the signal input to the amplifier exceeds the power level at the saturation point, even if the power of the signal input to the amplifier increases, Is constant, that is, a non-linear output is obtained.

As an example, as a distortion generated in a power amplifier (PA), which is an amplifier having a relatively large output power, for example, when the level of the input signal is large, the phase of the output signal fluctuates (AM). -PM conversion), and similarly, when the level of the input signal is large, the relationship between the amplitude (level) of the input signal and the amplitude (level) of the output signal deviates from a straight line (AM- Amplitude (level) distortion due to AM conversion).

[0005] The nonlinear characteristics of such an amplifier cause nonlinear distortion when amplifying a signal with the amplifier. Here, FIG. 6 shows an example of a spectrum of a transmission signal before being input to an amplifier, for example.
FIG. 7 shows an example of a spectrum of a transmission signal output from the amplifier (after amplification) when, for example, distortion compensation is not performed. The horizontal axis of the graphs in these figures indicates frequency (unit: [KHz]), and the vertical axis indicates power ratio (unit: [dB]).

As shown in FIG. 6, in a transmission signal before being amplified by an amplifier, a signal component outside a band of a signal to be transmitted (transmission desired signal) is reduced to a low level by using, for example, a band limiting filter. It is suppressed. On the other hand, as shown in FIG. 7, in the transmission signal amplified by the amplifier, the signal is distorted due to the nonlinear distortion, and the signal component leaks out of the band of the desired transmission signal. I will.

Here, the magnitude of the power leaked to a band (adjacent channel) adjacent to the band of the desired transmission signal is strictly defined, for example, for a base station device having a high power of a radio transmission signal. Therefore, the adjacent channel leakage power (ACP: Adjacent Channel)
A major issue is how to reduce leak power.

[0008] In the W-CDMA system shown in this example, for example, each antenna is spaced apart at a frequency interval of 5 MHz, and each is 5 MHz (± 2.5 MHz).
It is assumed that wireless communication is performed using signals of four different frequencies (four carrier signals) having a bandwidth of z). However, in FIGS. 6 and 7 and FIG. 10 described below, for convenience of description, 2 shows the spectrum for only one frequency signal (one carrier signal).

[0009] From the above, for example, a transmission power amplifier of a base station apparatus is configured using an amplifier (distortion compensation amplifier) having a function of performing distortion compensation.
Thereby, the distortion generated in the amplifier that amplifies the transmission signal is reduced.

Here, FIG. 8 shows an example of such a distortion compensation amplifier, and an operation example of the distortion compensation amplifier will be described below. That is, the transmission signal generated by the baseband unit (not shown) is input to this distortion compensation amplifier as a signal to be amplified (amplified signal), and the amplified signal is distributed to the delay unit 51 and the envelope. The signal is output to the line detector (level information converter) 52.

The envelope detector 52 detects the power level (analog power level) of the analog signal to be amplified, and obtains (sampling) the analog power level from the analog value at a predetermined conversion rate by the A / D converter 54. Is converted to a digital value (digital power level value). The conversion rate of the A / D conversion is determined, for example, by the frequency of the clock signal supplied from the clock generation unit 53 to the A / D converter 54.

In this example, as described above, each of the 5 MHz
Since it is assumed that four carrier signals having a bandwidth of z are input to the distortion compensation amplifier, the bandwidth of the entire amplified signal is 20 MHz (= 5 [MHz] × 4 [carrier]). Here, in general, in order to convert the analog signal into a digital signal without losing the information of the analog signal, when the bandwidth of the analog signal is Q, a time interval of 1 / (2 · Q) (ie, , (2 · Q) conversion rate), it is known from the sampling theorem that it is necessary to acquire a digital signal value.

For this reason, generally, in the A / D converter 54 as described above, a value twice or four times the bandwidth of the input signal (here, the above-described analog power level) is converted. Used as In this example, the value is 4 times the bandwidth of the analog power level (20 MHz).
The conversion rate is 0 MHz, and the above-described clock generation unit 53 generates an 80 MHz clock signal and
It is supplied to a D converter 54.

That is, in this example, a digital power level value obtained at a conversion rate of 80 MHz (that is, a conversion cycle of (1/80 MHz)) is output from the A / D converter 54 to the pre-distortion section 55. The digital power level value is information for specifying the level of the signal to be amplified.

In the pre-distortion section 55, A / D
Based on the digital power level value input from the converter 54, a distortion compensation process is performed on the amplified signal input from the delay unit 51. The delay unit 51 has a function of delaying the amplified signal input from the baseband unit and outputting the delayed signal to the predistortion unit 55.
The delay time is set so that distortion compensation performed on the signal to be amplified at a certain time in the pre-distortion section 55 is performed based on the power level of the signal to be amplified at the time.

FIG. 9 shows a detailed configuration example of the pre-distortion section 55. The pre-distortion section 55 includes two memories 61 and 63, a variable phase shifter 62, and a variable attenuator. (Attenuator) 64. The amplified signal output from the delay means 51 is input to the variable phase shifter 62, and the digital power level value output from the A / D converter 54 specifies an address in each of the memories 61 and 63. Entered as information.

Each of the memories 61 and 63 stores information on the content of distortion compensation corresponding to the digital power level value corresponding to each address specified by each digital power level value of the signal to be amplified. Specifically, one memory 61
Stores the amount of phase compensation (the amount corresponding to the inverse characteristic of the AM-PM conversion of the amplifier 56) corresponding to each address specified by each digital power level value. The memory 61 reads the phase compensation amount stored at the address specified by the digital power level value input from the A / D converter 54, and obtains information on the phase compensation amount (instruction information on the phase compensation amount). Is output to the variable phase shifter 62.

The other memory 63 stores an amplitude compensation amount (amplifier 5) corresponding to each digital power level value corresponding to each address specified by each digital power level value.
6 is stored in the memory 63. The memory 63 stores the amplitude compensation stored in the address designated by the digital power level value input from the A / D converter 54. It has a function of reading the amount and outputting the information of the amplitude compensation amount (instruction information of the amplitude compensation amount) to the variable attenuator 64.

The variable phase shifter 62 receives the signal to be amplified from the delay means 51, receives instruction information on the amount of phase compensation from the memory 61, and adjusts the phase of the signal to be amplified by an amount corresponding to the amount of phase compensation. And outputs the amplified signal to the variable attenuator 64 with only the change. That is, the variable phase shifter 62 compensates for the phase distortion generated in the amplifier 56. Further, since the magnitude of the phase distortion generated in the amplifier 56 changes according to the level of the signal to be amplified input to the amplifier 56, as described above, the level of the signal to be amplified is used as an address for one of the memories 61.
By storing the amount of phase compensation corresponding to the level, it is ensured that distortion compensation is performed according to the level of the signal to be amplified.

The variable attenuator 64 receives the signal to be amplified from the variable phase shifter 62, receives instruction information on the amount of amplitude compensation from the memory 63, and converts the input signal to be amplified into an attenuation rate corresponding to the amount of amplitude compensation. And outputs the amplified signal to the amplifier 56. That is, the variable attenuator 64 compensates for the amplitude distortion generated in the amplifier 56. In addition, since the magnitude of the amplitude distortion generated in the amplifier 56 changes according to the level of the signal to be amplified input to the amplifier 56, the level of the signal to be amplified is used as an address in the other memory 63 as described above. By storing the amplitude compensation amount according to the level, it is ensured that the distortion compensation according to the level of the signal to be amplified is performed.

As described above, the pre-distortion section 55
In accordance with the power level of the signal to be amplified input from the delay means 51, the inverse component of the phase distortion and the inverse component of the amplitude distortion expected to be generated in the amplifier 56 are read out from the memories 61 and 63, and , And a distortion-compensated signal is output to the amplifier 56. The information of the distortion compensation contents (that is, the amount of phase compensation and the amount of amplitude compensation) stored in each of the memories 61 and 63 corresponding to each address can be rewritten, for example, by the control unit 58 described later.

The amplifier 56 is composed of, for example, a power amplifier.
Is amplified to the required power by the amplifier 56, and the amplified signal is output to an antenna (not shown) and wirelessly transmitted from the antenna. Here, for example, distortion (amplitude distortion or phase distortion) according to the power level of the input amplified signal is generated in the amplifier 56, but the distortion compensation processing is performed on the amplified signal by the pre-distortion unit 55 as described above. Is applied to cancel the distortion generated in the amplifier 56.
The distortion included in the amplified signal output from is reduced (ideally, to zero).

The distortion compensating amplifier shown in FIG. 8 monitors whether or not distortion compensation by the pre-distortion section 55 has been properly performed by detecting the residual distortion amount. Is provided with a feedback system that controls the distortion compensation processing based on the residual distortion amount. By performing such feedback control, it is possible to guarantee that the distortion compensation processing in the pre-distortion unit 55 is appropriately performed, and an efficient transmission power amplification unit is realized.

More specifically, in the feedback system, a part of the signal output from the amplifier 56 to the antenna is obtained by the coupler and input to the error detection unit 57, where the distortion amount (amplitude distortion of the signal) included in the signal is included. (The amount of phase distortion) is detected by the error detection unit 57 as the residual distortion amount. Then, the control unit 58 including, for example, a DSP (Digital Signal Processor) reduces the amount of distortion detected by the error detection unit 57 based on the detection result (ideally,
The contents of the distortion compensation stored in each of the memories 61 and 63 are rewritten so as to be set to zero.

FIG. 10 shows an example of the spectrum of the transmission signal (after amplification) output from the amplifier 56 when the distortion compensation is performed in the pre-distortion section 55 as described above. . Note that the horizontal axis of the graph in the figure indicates frequency (unit is [KHz]), and the vertical axis indicates power ratio (unit is [dB]). As shown in the figure, when the inverse component of the distortion (amplitude distortion or phase distortion) generated in the amplifier 56 is added to the amplified signal by distortion compensation, compared with the spectrum shown in FIG. Adjacent channel leakage power can be reduced.

[0026]

However, in the conventional distortion compensating amplifier as shown in FIG. 8, for example, an A / D converter having the ability to perform A / D conversion at a high conversion rate of, for example, 80 MHz. Since the A / D converter 54 is required, the price of the A / D converter becomes extremely expensive, and the accuracy of the A / D conversion (that is, the number of quantization bits of the A / D converter) is ensured to be high. There was a problem that it was difficult.

In other words, the A / D converter generally becomes more expensive as the conversion rate increases, and the number of quantization bits of a digital value (digital power level value in the above-described conventional example) obtained by A / D conversion. A / D
Conversion accuracy will be poor. As a specific example, at present, a 10-bit A / D converter at 80 MHz is very expensive, and is about three times as expensive as a 12-bit A / D converter at 40 MHz.

As described above, the high price of the A / D converter is a fatal problem in manufacturing a product having a distortion compensation amplifier. In the distortion compensation processing performed by the distortion compensation amplifier as shown in FIG.
Although it is essential to use an A / D converter, for example, it is often the case that the number of quantization bits of the A / D converter is not enough to be 10 bits, and such a small number of quantization bits (that is, A / Poor accuracy of D / D conversion) directly affects the distortion compensation result, resulting in extremely poor distortion compensation accuracy.

In the above description, the base station device of the W-CDMA mobile communication system has been described as an example. However, the above-described disadvantages are caused by the base station device of various wireless communication systems including the W-CDMA system and the relay amplifier. It also occurs in devices and the like, and also occurs in various devices in which a distortion compensation amplifier is used.

The present invention has been made to solve such a conventional problem. For example, a low-cost, high-precision A / A
An object of the present invention is to provide a distortion compensating amplifier that can perform accurate distortion compensation by using a D converter to compensate for distortion generated in the amplifier.

[0031]

In order to achieve the above object, a distortion compensating amplifier according to the present invention has the following features.
Using an A / D converter, a digital level value of a predetermined period T is obtained, and distortion generated in the amplifier is compensated. That is, first, the analog level detecting means detects the analog level of the signal to be amplified by the amplifier. Also, n is 2
As the above integers, there are provided n A / D converters for acquiring digital level values from the detection result of the analog level detecting means at a period nT which is n times the predetermined period T, respectively, and these n A / D converters are provided. A digital level value is obtained from the detection result of the analog level detecting means at a timing shifted by the predetermined period T from each other.

The combining means combines the digital level values obtained by the n A / D converters to generate a digital level value of the predetermined period T, and the distortion compensating means is generated by the combining means. The distortion generated in the amplifier is compensated by controlling at least one of the amplitude and the phase of the signal amplified by the amplifier based on the digital level value.

Therefore, the configuration in which the digital level value of the predetermined period T is obtained from the detection result of the analog level by using the A / D converter is obtained at a period nT which is n times the predetermined period T (that is, (1 / ( n) It is realized by using an A / D converter that obtains a digital level value (at a conversion rate of twice), so that the cost of the A / D converter can be reduced, and high accuracy (ie, A / D converters (with a large number of quantization bits) can be used,
Accurate distortion compensation can be realized using a low-cost A / D converter.

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described with reference to the drawings. In the following embodiment, for example, a case is shown in which the present invention is applied to a distortion compensation amplifier provided in a base station apparatus of a W-CDMA mobile communication system similar to that shown in the above conventional example. In this example, a transmission signal output from a baseband unit is input as a signal to be amplified (amplified signal), and the amplified signal is amplified by an amplifier and wirelessly transmitted from an antenna.

First, a distortion compensation amplifier according to a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows an example of the distortion compensating amplifier of the present embodiment.
Delay means 1, envelope detector 2, clock generator 3
, An inverter (inverter) 4, two A / D converters 5 and 6, a multiplexer 7, a pre-distortion unit 8, an amplifier 9, an error detection unit 10, and a control unit 11. ing. Here, in the distortion compensation amplifier of this example,
The amplified signal input from a baseband unit (not shown) is distributed and output to the delay unit 1 and the envelope detection unit 2.

The delay means 1 is composed of, for example, a delay line and has a function of delaying an input amplified signal by a predetermined time and outputting the amplified signal to the pre-distortion section 8. The predetermined time to be delayed (delay time) will be described later. The envelope detector 2 detects an analog power level (analog power level) of the amplified signal by detecting an envelope of the input amplified signal, and converts the detected analog power level into each A signal.
It has a function of outputting to the / D converters 5 and 6.

The clock generator 3 generates a signal in which, for example, two values (for example, “1 value” and “0 value”) alternately change at a predetermined frequency as a clock signal, and outputs the clock signal to one A / A It has a function of outputting to the D converter 5 and the inverter 4. In this example, 40 MHz is used as the predetermined frequency of the clock signal. The inverter 4 has a function of inverting two values constituting a clock signal input from the clock generation unit 3 and outputting the inverted clock signal (inverted clock signal) to the other A / D converter 6. are doing.

The A / D converter 5 has a timing according to the clock signal input from the clock generation unit 3,
It has a function of converting an analog power level input from the envelope detection unit 2 from an analog value to a digital value (digital power level value), and outputting the digital power level value to the multiplexer 7. Similarly, the other A / D converter 6 changes the analog power level input from the envelope detector 2 from an analog value to a digital value (digital power level) at a timing according to the inverted clock signal input from the inverter 4. ) And outputs the digital power level value to the multiplexer 7.

Here, each of the A / D converters 5 and 6 in this example has a conversion rate of 40 MHz (that is,
An A / D converter having an ability to convert an analog signal to a digital signal (with a conversion cycle of 1/40 MHz) is used, and a timing (sample timing) for obtaining a digital power level value from an analog power level is determined. One half of the conversion period (that is, (８)
0 MHz).

The multiplexer 7 has a function of outputting the digital power level values input from the two A / D converters 5 and 6 to the pre-distortion unit 8 at timings corresponding to the input timings of the respective digital power level values. are doing. With this function, the pre-distortion unit 8
These two A / D converters 5 and 6 provide a multiplexer 7
The result obtained by combining the digital power level values output to the multiplexing by multiplexing is input. The digital power level value input from the multiplexer 7 to the pre-distortion unit 8 is information for specifying the level of the signal to be amplified.

Here, the processing performed by the A / D converters 5 and 6 and the multiplexer 7 of the present embodiment will be specifically described with reference to FIG. FIG. 3 shows a waveform of an analog power level detected by the envelope detection unit 2 (analog signal waveform).
FIG. 3A shows an example of the sample timing when a digital power level value is obtained from the analog power level at a conversion rate of 80 MHz (sample timing of 80 MHz) required in the present example. Are shown by arrows.

FIG. 3B shows an example of a sample timing when a digital power level value is obtained by one of the A / D converters 5 by arrows. An example of the sample timing when the digital power level value is obtained by the other A / D converter 6 is indicated by an arrow.

As described above, the respective sample timings of the two A / D converters 5 and 6 operating according to the inverted clock signals are (1/80 MHz).
z) The time is shifted. In each of the A / D converters 5 and 6 in this example, the timing of the rising position of the input clock signal or inverted clock signal is used as the sample timing.

As described above, the multiplexer 7 multiplexes the digital power level values input from the two A / D converters 5 and 6 and multiplexes the digital power level values into the pre-distortion section 8.
The output is performed. That is, specifically, the multiplexer 7 alternately outputs the 40 MHz digital power level value input from each of the A / D converters 5 and 6 to the pre-distortion unit 8, whereby
The pre-distortion unit 8 receives, for example, a digital power level value of 80 MHz as shown in FIG.

The pre-distortion section 8 has a function of performing distortion compensation processing on the amplified signal input from the delay means 1 based on the digital power level value input from the multiplexer 7. Here, the configuration and operation of the pre-distortion unit 8 of this example are the same as, for example, the configuration and operation of the pre-distortion unit shown in FIG. For this reason, in the present example, the two memories 61 and 63, the variable phase shifter 62 and the variable attenuator 64 are indicated using the same reference numerals as those shown in FIG. 9, and the configuration example of the pre-distortion unit 8 of the present example. And an operation example will be briefly described.

That is, the pre-distortion section 8 of the present embodiment stores the phase compensation amount corresponding to each digital power level value of the signal to be amplified corresponding to each address specified by the digital power level value in the memory 61. A variable phase shifter 62 for changing the phase of the signal by an amount corresponding to the phase compensation amount specified by the memory 61; and a digital phase shifter 62 corresponding to each address specified by each digital power level value of the signal to be amplified. A memory 63 storing an amplitude compensation amount corresponding to the power level value, and a variable attenuator 64 for attenuating a signal at an attenuation rate corresponding to the amplitude compensation amount specified by the memory 63 are provided. In this example,
The amplified signal output from the delay means 1 is a variable attenuator 62
And the digital power level value output from the multiplexer 7 is input to each of the memories 61 and 63.

Then, in the pre-distortion section 8,
One of the memories 61 instructs the variable attenuator 62 on the phase compensation amount stored at the address specified by the digital power level value input from the multiplexer 7, and the variable attenuator 62 is input from the delay unit 1. The phase of the signal to be amplified is changed according to the instruction and the signal to be amplified is output to the variable attenuator 64, and the other memory 63 is stored in the address specified by the digital power level value input from the multiplexer 7. The variable amplitude attenuator 63 instructs the variable amplitude attenuator 63 to attenuate the amplified signal input from the variable phase shifter 62 according to the instruction, and outputs the signal to the amplifier 9.

As described above, in the pre-distortion section 8, the phase and the amplitude of the signal to be amplified inputted from the delay means 1 are compensated for in accordance with the power level of the signal to be amplified. Each memory 6 corresponds to each address.
The information of the distortion compensation contents (that is, the amount of phase compensation and the amount of amplitude compensation) stored in the storage units 1 and 63 is, for example, a control unit 11 described later.
And so on. The delay time of the delay unit 1 may be, for example, the power level of the signal to be amplified at the time when the distortion compensation applied to the signal to be amplified at each time in the variable phase shifter 62 or the variable attenuator 64 is performed. It is set to be performed based on.

The amplifier 9 is composed of, for example, a power amplifier, and amplifies the distortion-compensated signal input from the predistortion unit 8 to a predetermined power (in this example, required transmission power). It has a function of outputting the amplified signal to an antenna (not shown). Note that the amplified signal output to the antenna is wirelessly transmitted from the antenna.

Here, in the amplifier 9, for example, distortion (amplitude distortion or phase distortion) corresponding to the power level of the input amplified signal occurs, but the amplified signal is distorted by the pre-distortion section 8 as described above. Due to the compensation process,
The distortion included in the amplified signal output from the amplifier 9 is reduced (ideally, zero). That is, the amplifier 9
As the amplified signal output from the, an amplified signal with reduced adjacent channel leakage power can be obtained, for example, as in the spectrum shown in FIG.

The distortion compensating amplifier of the present embodiment monitors whether or not the distortion compensation by the pre-distortion section 8 has been properly performed by detecting the residual distortion amount. A feedback system that controls the processing based on the residual distortion amount is provided,
This feedback system includes, for example, a coupler (not shown), an error detection unit 10, and a control unit 11.

The coupler has a function of obtaining a part of the amplified signal output from the amplifier 9 to the antenna, and outputting the obtained signal to the error detector 10. Error detector 10
Detects the amount of distortion (the amount of amplitude distortion and the amount of phase distortion) contained in the signal input from the coupler as the remaining amount of distortion,
It has a function of notifying the control unit 11 of the detection result.

The control unit 11 is composed of, for example, a DSP, and reduces the amount of distortion detected by the error detection unit 10 based on the detection result notified from the error detection unit 10 (ideally, zero). As described above, a function of rewriting the distortion compensation contents (that is, the amount of phase compensation and the amount of amplitude compensation) stored in each of the memories 61 and 63 is provided.

In the present embodiment, by performing such feedback control, it is ensured that the distortion compensation processing in the predistortion section 8 is appropriately performed, and an efficient transmission power amplifying section can be realized. . Specifically, in a configuration in which such feedback control is performed, a residual error (distortion component that cannot be compensated) occurs in an amplified signal output from the amplifier 9 due to, for example, a temperature change or some abnormality. However, since the content of the distortion compensation in each of the memories 61 and 63 is rewritten so that the residual error (distortion residual amount) detected by the error detection unit 10 can be canceled, a highly accurate distortion A compensation process is realized.

As described above, in the distortion compensation amplifier of this embodiment,
A configuration in which a digital power level value of a predetermined cycle (1/80 MHz) is obtained from the analog power level detection result using the A / D converter is changed to a cycle (1/1 /
A / D converter 5, which obtains a digital power level value at 40 MHz) (ie, at (１ ／) times the conversion rate),
6 is realized.

Therefore, in the distortion compensation amplifier of this embodiment, the A / D
The cost of the converters 5 and 6 can be reduced, and the conversion can be performed with high accuracy (that is, a large number of quantization bits).
A / D converters 5 and 6 can be used, whereby
Even without using an A / D converter operating at a high speed of, for example, 80 MHz, accurate distortion compensation can be realized using the low-cost A / D converters 5 and 6. Specifically, the distortion compensating amplifier of the present example is different from the conventional distortion compensating amplifier shown in FIG.
The cost required for the converters 5 and 6) can be reduced to about (2/3).

In this embodiment, the function of the envelope detector 3 for detecting the analog power level of the signal to be amplified by the amplifier 9 (amplified signal) constitutes analog level detecting means according to the present invention. ing. As the analog level in the present invention, the power level does not necessarily need to be detected as in the present embodiment, and for example, a current or voltage level may be detected.

In this example, the case where n in the present invention is 2 and the predetermined period T in the present invention is 80 MHz is shown, and each of them has a period nT which is n times the predetermined period T. The two A / D converters 5 and 6 that acquire the digital power level value from the analog power level detection result at the timing shifted by the predetermined period T are referred to as n in the present invention.
A / D converters. Note that, like the analog level described above, the power level value does not necessarily have to be used as the digital level value in the present invention as in the present embodiment.

In this embodiment, the multiplexer 7 combines the digital power level values obtained by the two A / D converters 5 and 6 by multiplexing and multiplexes the digital power level values in the predetermined period T.
The function for generating the digital power level value constitutes the synthesizing means according to the present invention. Further, in this example, the pre-distortion unit 8 controls the phase and amplitude of the signal amplified by the amplifier 9 based on the digital power level value of the predetermined period T generated by the multiplexer 7 to generate the signal in the amplifier 9. The function of compensating for this distortion constitutes a distortion compensating means according to the present invention.

In this embodiment, as a preferred embodiment, the distortion is compensated by adjusting both the amplitude and the phase of the signal amplified by the amplifier 9. For example, only one of the amplitude and the phase is adjusted. The adjustment may be performed. Even in such a case, it is possible to reduce the influence of distortion generated in the amplifier 9 according to the degree of the adjustment.

In the present embodiment, as a preferred embodiment, the distortion compensation (pre-distortion) is performed on the signal before being amplified by the amplifier 9. However, for example, the signal after being amplified by the amplifier is subjected to distortion compensation. It is also possible to use a configuration. Further, as the degree of compensating for the distortion generated in the amplifier, for example, it is preferable to make the distortion zero, but if the distortion can be reduced to a practically effective degree, the distortion is not necessarily made zero. May be.

Next, a distortion compensation amplifier according to a second embodiment of the present invention will be described with reference to the drawings. The distortion compensating amplifier of this embodiment is obtained by further modifying the distortion compensating amplifier shown in FIG. 1 of the first embodiment, for example. Even if an error occurs in the sample timing of the D converters 5 and 6,
This guarantees the accuracy of sampling.

That is, in the first embodiment, one A /
It has been described that the timing is adjusted so that no time error occurs between the timing of the clock signal input to the D converter 5 and the timing of the inverted clock signal input to the other A / D converter 6. However, in an actual circuit, a subtle delay time difference may occur between the clock signal and the inverted clock signal due to, for example, a difference in a signal path or the presence or absence of the inverter 4.

If such a delay time difference occurs, oversampling is performed at a conversion rate that is a multiple (in this example, four times) of the bandwidth of the analog signal to be A / D converted. The condition is not satisfied, and as a result, the digital value after the A / D conversion does not represent the analog value before the A / D conversion, so that accurate distortion compensation may not be performed. Further, if accurate distortion compensation is not performed, the device may not be able to be established without satisfying the condition of adjacent channel leakage power strictly defined for the output of the amplifier.

The distortion compensating amplifier of the present embodiment ensures that accurate sampling is performed and accurate distortion compensation is performed even in the case where a delay time difference between clock signals occurs as described above. This is guaranteed, and a configuration example and an operation example of the distortion compensation amplifier of this example will be described below. FIG. 3 shows an example of the distortion compensating amplifier of this embodiment. The configuration of the distortion compensating amplifier is such that the frequency of the clock signal generated by the clock generation unit 21 is 80 MHz and the frequency divider 22 and the sample hold Except that a circuit 23 is provided, the configuration is the same as that of the distortion compensation amplifier shown in FIG. 1 of the first embodiment.

For this reason, in this example and FIG. 3, the delay means 1 having the same configuration as that shown in the first embodiment,
The envelope detector 2, the inverter 4, the two A / D converters 5, 6, the multiplexer 7, the predistortion unit 8, the amplifier 9, the error detector 10, the control unit 11
Are denoted by the same reference numerals as those described in the first embodiment, and in this embodiment, the description of the same components as those in the first embodiment is omitted.

Hereinafter, the clock generator 21, the frequency divider 22, and the sample-and-hold circuit 23, which are characteristic parts of the present embodiment, will be described in detail. That is, in the distortion compensation amplifier of this example, the analog power level detected by the envelope detection unit 2 is set to 2 via the sample / hold circuit (S / H) 23.
The A / D converters 5 and 6 receive the clock signal. The clock signal generated by the clock generator 21 is input to the sample and hold circuit 23.
The clock signal is input to one of the A / D converter 5 and the inverter 4 via the frequency divider 22.

The clock generator 21 of the present embodiment has a frequency of 80 MHz.
Has the function of generating a clock signal having a frequency of .times. And outputting the clock signal to the sample-and-hold circuit 23 and the frequency divider 22. The frequency divider 22 sets the frequency of the clock signal input from the clock generator 21 to (１ ／)
It has a function of outputting the clock signal of 40 MHz generated by this to one A / D converter 5 and the inverter 4. That is, also in this example, as in the case of the first embodiment, one A / D converter 4 has 40M
Hz clock signal is input, and the other A / D converter 6
Is supplied with an inverted clock signal of 40 MHz.

The sample hold circuit 23 holds the analog power level input from the envelope detector 2 for a predetermined time at each timing according to the 80 MHz clock signal input from the clock generator 21 (ie, a predetermined time). For a certain period of time), and the level held in this way is
It has a function of outputting to the / D converters 5 and 6.

The predetermined time for holding is as follows.
Various times may be set. The point is that accurate sampling is performed by the two A / D converters 5 and 6 even when a delay time difference occurs between clock signals. The time that can be guaranteed is set. Specifically, in the present example, for example, a predetermined time of (1/80 MHz) or less and a fixed time of about (1/80 MHz) is set. Further, as the sample-and-hold circuit 23, for example, a generally known existing circuit can be used.

Here, with reference to FIG. 4, the effect of the sample and hold processing performed by the sample and hold circuit 23 of this embodiment will be specifically described. FIG. 2 shows an example of a waveform (analog signal waveform) of an analog power level detected by, for example, the envelope detection unit 2, and an example of a waveform (sample-hold waveform) held by the sample-and-hold circuit 23. Is shown.

In FIG. 11A, an example of the timing at which the analog power level is held by the sample and hold circuit 23 is indicated by an arrow. As shown in FIG. In the circuit 23, (1 /
At 80 MHz), the analog power level is held. In other words, the waveform held by the sample and hold circuit 23 of the present example is a straight line that holds the analog power level at that instant for a predetermined time every (1/80 MHz) time. In practice, the sample and hold circuit 23
Is composed of analog devices, so the sample-and-hold waveform does not become an exact straight line but slowly attenuates, but for example, it is a straight line that is practically effective compared to the case without sample and hold. Can be considered.

In FIG. 3B, an example of a sample timing when a digital power level value is obtained by one of the A / D converters 5 is indicated by an arrow, and FIG. For example, when a subtle delay time occurs in the inverted clock signal and a subtle delay time difference occurs between the clock signal and the inverted clock signal, the digital power level value is acquired by the other A / D converter 6. An example of the sample timing at this time is indicated by an arrow.

When a configuration is used in which the analog power level is converted into a linear sample-and-hold waveform and input to each of the A / D converters 5 and 6 as shown in FIG.
As shown in (2), even when a delay time occurs in the inverted clock signal, the same level value as when no such delay time occurs can be obtained as the digital power level value. In the case where the sample and hold circuit 23 is not provided as in this example, if such a delay time occurs, a different level value from the case where the delay time does not occur is set as a digital power level value. Will be obtained.

As described above, in the distortion compensation amplifier of this embodiment,
A means for holding the analog power level detected by the envelope detection unit 2 for a predetermined period of time at a predetermined period T referred to in the present invention (in this example, a sample and hold circuit 23) is provided, and the A / D converter 5, 6 obtains the digital power level value from the held level.

Therefore, in the distortion compensating amplifier of this embodiment, for example, a delay time difference is generated between clock signals indicating the acquisition timing (sample timing) of the digital power level value by each of the A / D converters 5 and 6. Even in such a case, it is possible to obtain the same digital power level value as in the case where such a delay time difference does not occur, thereby performing, for example, a work of finely adjusting the delay time difference between clock signals. At least, it is possible to guarantee that accurate sampling is performed and accurate distortion compensation is performed.

Next, a distortion compensation amplifier according to a third embodiment of the present invention will be described with reference to FIG. The distortion compensating amplifier of the present embodiment is obtained by further improving the distortion compensating amplifier shown in FIG. 3 of the second embodiment, for example. This is applied not only to the A / D converters 5 and 6 but also to the memory provided in the pre-distortion section.

That is, for example, the first embodiment or the second
In the distortion compensation amplifier shown in the embodiment, since the digital power level values input to the two memories 61 and 63 provided in the pre-distortion unit 8 fluctuate at 80 MHz, these memories 61 and 63 are respectively 80M
A memory operating at Hz is used. However, the problem that a device that operates at high speed is expensive occurs not only for the A / D converter but also for the memory. Therefore, in the distortion compensation amplifier of the present example, as described below, a device is devised so that distortion compensation is realized using a memory that operates at a low speed.

FIG. 5 shows an example of the distortion compensating amplifier of the present embodiment. The configuration of this distortion compensating amplifier is provided in, for example, the distortion compensating amplifiers shown in the first and second embodiments. For example, the configuration is the same as that of the distortion compensating amplifier shown in FIG. 3 of the second embodiment except that the multiplexer 7 is not provided and the configuration of the predistortion section 31 is different.

For this reason, in this example and FIG. 5, the delay means 1 having the same configuration as that shown in the second embodiment,
The envelope detection unit 2, the inverter 4, the two A / D converters 5, 6, the amplifier 9, the error detection unit 10, the control unit 1,
1, the clock generator 21, the frequency divider 22, and the sample-and-hold circuit 23 are denoted by the same reference numerals as those used in the second embodiment. The description of the same components as those shown in the example is omitted.

In the following, a configuration example and an operation example of the pre-distortion unit 31 which is a characteristic part of the present embodiment will be described in detail. As described above, in this example, the multiplexer 7 shown in the first embodiment and the second embodiment is used.
Is not provided, and the digital power level value obtained by each of the A / D converters 5 and 6 is output to the pre-distortion unit 31.

As shown in the figure, four memories 41, 42, 4
5, 46, two multiplexers 43 and 47, a variable phase shifter 44, and a variable attenuator 48 are provided. Here, the two memories 41 and 42, the one multiplexer 43 and the variable phase shifter 44 are components for performing a phase compensation process on the signal to be amplified, and the two memories 45, 46 and 1
The multiplexers 47 and the variable attenuators 48 are components for performing amplitude compensation processing on the signal to be amplified.

Further, in this example, the amplified signal output from the delay means 1 is input to the variable phase shifter 44, and the A / A
The digital power level value output from the D converter 5 is input to the memories 41 and 45 as information specifying an address, and the digital power level value output from the other A / D converter 6 is stored in the memories 42 and 46. Is input as information for specifying an address.

First, components for performing the phase compensation processing will be described. That is, the memory 41 and the memory 4
2 stores a phase compensation amount corresponding to each digital power level value corresponding to each digital power level value of the signal to be amplified. Then, the one memory 41 reads out the phase compensation amount stored at the address specified by the digital power level value input from the one A / D converter 5 and stores information on the phase compensation amount (phase compensation amount). Multiplexer 4)
3, the other memory 42 reads out the phase compensation amount stored in the address specified by the digital power level value input from the other A / D converter 6 in the same manner. In addition, a function of outputting the information of the phase compensation amount (instruction information of the phase compensation amount) to the multiplexer 43 is provided.

Here, each of the memories 41 and 42 has a rate of 40 MHz (that is, (1)
/ 40 MHz). Further, in each of the memories 41 and 42, corresponding to the shift provided at the timing when the digital power level value is inputted from the A / D converters 5 and 6 in the preceding stage, the memory 41 and 42 correspond to the inputted digital power level value. The timing of outputting the phase compensation amount instruction information is shifted from each other by a time that is (1/2) times the period (that is, a time of (1/80 MHz)).

The multiplexer 43 includes two memories 4
It has a function of outputting instruction information of the amount of phase compensation input from 1, 42 to the variable phase shifter 44 at a timing corresponding to the input timing of each instruction information. In other words, the variable phase shifter 62 receives the result of multiplexing of the instruction information input to the multiplexer 43 from the two memories 41 and 42 by multiplexing.

More specifically, the multiplexer 43 outputs to the variable phase shifter 44 the instruction information alternately input at 40 MHz from each of the memories 41 and 42 in the input order. Instruction information is input to 44 at an 80 MHz rate. In addition,
Although not shown, the same clock signal as the 80 MHz clock signal supplied to the sample and hold circuit 23 is supplied to the multiplexer 43, for example.

The variable phase shifter 44 receives the signal to be amplified from the delay means 1, receives the instruction information of the amount of phase compensation from the multiplexer 43, and adjusts the phase of the signal to be amplified by an amount corresponding to the amount of phase compensation. And outputs the amplified signal to the variable attenuator 48 with only the change.

Next, the components for performing the amplitude compensation processing will be described. That is, the memory 45 and the memory 4
6 stores an amplitude compensation amount corresponding to the digital power level value corresponding to each address specified by each digital power level value of the signal to be amplified. Then, the one memory 45 reads out the amplitude compensation amount stored at the address specified by the digital power level value input from the one A / D converter 5, and reads information on the amplitude compensation amount (amplitude compensation amount). Multiplexer 4)
7, and similarly, the other memory 46 reads the amplitude compensation amount stored at the address specified by the digital power level value input from the other A / D converter 6. In addition, the multiplexer 47 has a function of outputting the information of the amplitude compensation amount (instruction information of the amplitude compensation amount) to the multiplexer 47.

Here, each of the memories 45 and 46 has a rate of 40 MHz (that is, (1)
/ 40 MHz). Then, in each of the memories 45 and 46, the A / D
Corresponding to the shift provided at the timing at which the digital power level value is input from the converters 5 and 6, the timing at which the instruction information of the amplitude compensation amount corresponding to the input digital power level value is output is equal to the period. (Ie, a time of (1/80 MHz)).

The multiplexer 47 includes two memories 4
It has a function of outputting the instruction information of the amplitude compensation amount input from 5, 46 to the variable attenuator 48 at a timing corresponding to the input timing of each instruction information. That is, the variable attenuator 48 receives the result of multiplexing of the instruction information input from the two memories 45 and 46 to the multiplexer 47 by multiplexing.

More specifically, the multiplexer 47 outputs to the variable attenuator 48 the instruction information which is alternately input at 40 MHz from the memories 45 and 46 in the order of the input. The instruction information is input to 48 at a rate of 80 MHz. In addition,
Although not shown, the multiplexer 47 is supplied with the same clock signal as the 80 MHz clock signal supplied to the sample and hold circuit 23, for example.

The variable attenuator 48 receives the signal to be amplified from the delay means 1 and receives instruction information on the amount of amplitude compensation from the multiplexer 47, and attenuates the amplitude of the signal to be amplified corresponding to the amount of amplitude compensation. It has a function of outputting the amplified signal to the amplifier 9 at an attenuated rate.

As described above, the pre-distortion section 31
Then, according to the power level of the signal to be amplified input from the delay means 1, the inverse components of the phase distortion and the amplitude distortion expected to be generated in the amplifier 9 are stored in the memories 41, 42, 4 and 4.
A distortion compensation process (pre-distortion) of reading from the signals 5 and 46 and adding the signal to the amplified signal in advance is performed, and the amplified signal subjected to the distortion compensation is output to the amplifier 9. In addition,
Each memory 41, 42, 45, 46 corresponding to each address
Can be rewritten by the control unit 11 for example.

As described above, in the distortion compensation amplifier of this example,
The same number of memories 41 and 42 as the A / D converters 5 and 6 are stored in each A / D converter.
A phase compensation amount corresponding to the digital power level value is stored in each of the memories 41 and 42 provided for the D converters 5 and 6, and the memories 41 and 42 are acquired by the A / D converters 5 and 6, respectively. Means for outputting the phase compensation amount instruction information stored corresponding to the digital power level value to be output at a timing corresponding to the acquisition timing (sample timing) of each digital power level value, and synthesizing the instruction information. In the example, the multiplexer 43) includes the plurality of memories 41,
The instruction information output from 42 is combined to generate instruction information of a predetermined period T (80 MHz in this example) according to the present invention, and the phase compensating means (variable phase shifter 44 in this example) is generated. Distortion compensation is performed by controlling the phase of the signal amplified by the amplifier 9 based on the instruction information of the predetermined cycle T.

Similarly, in the distortion compensation amplifier of this embodiment, the A / D
The same number of memories 45, 46 as the converters 5, 6 are provided for the respective A / D converters 5, 6, and the amplitude compensation amounts corresponding to the digital power level values are stored in the memories 45, 46, respectively. The memories 45 and 46 use the amplitude compensation amount instruction information stored corresponding to the digital power level values acquired by the A / D converters 5 and 6 at the acquisition timing (sample timing) of each digital power level value. The instruction information is output at a timing corresponding thereto, and the instruction information synthesizing means (in this example, the multiplexer 47) synthesizes the instruction information output from the plurality of memories 45 and 46 to generate a predetermined period T (in this example, the present invention). , 80 MHz), and the amplitude compensating means (in this example, the variable attenuator 48) controls the amplitude of the signal amplified by the amplifier 9 based on the generated instruction information of the predetermined period T. To distortion compensation.

As described above, in the distortion compensation amplifier of this example, the distortion compensation content (that is, the phase compensation amount and the amplitude compensation) of the predetermined cycle (1/80 MHz) corresponding to the detection result of the digital power level value of the predetermined cycle (1/80 MHz). The amount of information is notified to the means for performing distortion compensation (that is, the variable phase shifter 44 and the variable attenuator 48) using a memory in a cycle (1/40 MHz) twice as long as the predetermined cycle (that is, This is realized by using memories 41, 42, 45, and 46 that operate (at a rate of (1/2) times).

Therefore, in the distortion compensating amplifier of this embodiment, the cost of the memory can be reduced by using the low-speed memories 41, 42, 45, and 46 without using, for example, an expensive device with a small number of bits. Thus, for example, it is possible to configure the circuit of the pre-distortion unit and the distortion compensation amplifier at low cost without deteriorating the characteristics of the distortion compensation at all. Further, even in the configuration using the low-speed operation A / D converters 5 and 6 and the low-speed operation memories 41, 42, 45 and 46 as in the distortion compensation amplifier of this example,
Since the distortion compensation process is performed at a predetermined cycle originally required (80 MHz in this example), it is possible to sufficiently cope with, for example, a case where high-speed distortion compensation is required.

Here, the configuration of the distortion compensating amplifier according to the present invention is not necessarily limited to the one described above, and various configurations may be used. For example, various methods may be used as the amplifier, the signal to be amplified, and the method of distortion compensation by the distortion compensation unit (pre-distortion unit in the above embodiment).

Further, in the above embodiments, the case where n is 2 in the present invention has been described as a preferred embodiment, but a configuration in which n is an integer of 3 or more may be used. Further, in the above embodiment, as a preferable mode, the feedback system that detects the amount of distortion included in the amplified signal output from the amplifier 9 and controls the distortion compensation process based on the detection result is provided. A feedback system need not always be provided.

As various processes such as a distortion compensation process performed by the distortion compensation amplifier according to the present invention, for example, the processor executes a control program stored in a ROM in a hardware resource including a processor and a memory. For example, each functional means for executing the processing may be configured as an independent hardware circuit. In addition, the present invention can be understood as a computer-readable recording medium such as a floppy disk or a CD-ROM storing the above-mentioned control program. Thereby, the processing according to the present invention can be performed.

Further, in the above embodiment, as a preferred embodiment, the case where the present invention is applied to a distortion compensation amplifier provided in a base station apparatus of a W-CDMA mobile communication system has been described. The present invention can be applied to base stations and relay amplifiers of various wireless communication systems including a CDMA system, and can be applied to various devices using a distortion compensation amplifier. is there.

[0103]

As described above, according to the distortion compensating amplifier according to the present invention, the analog level of the signal to be amplified by the amplifier is detected, and n (n is 2
A digital level value is acquired at a timing shifted by the predetermined period T from each other by n A / D converters that acquire a digital level value from the detection result at a cycle nT times the above integer) times. A digital level value of the predetermined cycle T is generated from the digital level value obtained by the D converter, and the amplitude and phase of the signal amplified by the amplifier are controlled based on the generated digital level value of the predetermined cycle T. Since the distortion generated in the amplifier is compensated for, accurate distortion compensation can be realized using a low-cost and high-precision A / D converter.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an example of a distortion compensation amplifier according to a first embodiment of the present invention.

FIG. 2 shows an A / D conversion value of 40 MHz to an A of 80 MHz.
FIG. 4 is a diagram for explaining a method of generating a / D conversion value.

FIG. 3 is a diagram illustrating an example of a distortion compensation amplifier according to a second embodiment of the present invention.

FIG. 4 shows a case where a sample hold is used, and 40M is used.
FIG. 6 is a diagram for explaining a method of generating an A / D converted value of 80 MHz from an A / D converted value of Hz.

FIG. 5 is a diagram illustrating an example of a distortion compensation amplifier according to a third embodiment of the present invention.

FIG. 6 is a diagram illustrating an example of a spectrum of a signal before being input to an amplifier.

FIG. 7 is a diagram illustrating an example of a spectrum of a signal output from an amplifier when distortion compensation is not performed.

FIG. 8 is a diagram illustrating an example of a distortion compensation amplifier according to a conventional example.

FIG. 9 is a diagram illustrating a configuration example of a pre-distortion unit.

FIG. 10 is a diagram illustrating an example of a spectrum of a signal output from an amplifier when distortion compensation is performed.

[Explanation of symbols]

1. Delay means, 2. Envelope detector, 3, 21
・ Clock generation unit, 4 ・ ・ Inverter, 5, 6 ・ ・ A
/ D converter, 7, 43, 47 ··· multiplexer,
8, 31 pre-distortion section, 9 amplifier,
10. Error detection unit, 11 Control unit, 22
Frequency divider, 23 ... sample hold circuit, 41, 42,
45, 46, 61, 63 .. memory, 44, 62 .. variable phase shifter, 48, 64 .. variable attenuator,

Continued on the front page F-term (reference) 5J090 AA01 AA41 CA21 CA87 FA19 GN03 HN08 HN10 HN12 KA00 KA04 KA15 KA16 KA19 KA23 KA32 KA33 KA34 KA55 SA14 TA01 TA03 TA06 5J091 AA01 AA41 CA21 CA87 KA15 KA14 KA04 KA00 TA01 TA03 TA06

Claims (1)

[Claims] An analog level of a signal to be amplified by an amplifier is detected, a digital level value of a predetermined cycle T is obtained from the detection result using an A / D converter, and based on the obtained digital level value. Analog level for detecting the analog level of a signal to be amplified by the amplifier in a distortion compensation amplifier that compensates for distortion generated in the amplifier by controlling at least one of the amplitude and the phase of the signal amplified by the amplifier Detecting means, n is an integer of 2 or more, and n of the predetermined period T
N A / D converters for obtaining a digital level value from the detection result of the analog level detection means at a timing shifted by the predetermined period T from each other at a double cycle nT, and obtained by the n A / D converters Synthesizing means for synthesizing a digital level value of the predetermined period T by synthesizing the digital level value, and at least one of an amplitude and a phase of a signal amplified by an amplifier based on the digital level value generated by the synthesizing means. A distortion compensating means for compensating for distortion generated in the amplifier by controlling one of them.