JP2001267351A - Wire-bonding structure - Google Patents
Wire-bonding structureInfo
- Publication number
- JP2001267351A JP2001267351A JP2000075359A JP2000075359A JP2001267351A JP 2001267351 A JP2001267351 A JP 2001267351A JP 2000075359 A JP2000075359 A JP 2000075359A JP 2000075359 A JP2000075359 A JP 2000075359A JP 2001267351 A JP2001267351 A JP 2001267351A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- wire bonding
- land
- substrate
- wire
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H—ELECTRICITY
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- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
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- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明はワイヤボンディング
構造に係り、半導体のベアチップをワイヤボンディング
実装するものに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wire bonding structure, and more particularly, to a method for mounting a semiconductor bare chip by wire bonding.
【０００２】[0002]
【従来の技術】半導体のベアチップを基板にワイヤボン
ディング実装する場合、例えば、図３に示すように、ベ
アチップ１のパッド２と基板31上のランド32とではベア
チップ１の高さ分の差があるため、ワイヤ33がベアチッ
プ１に接触する恐れがあるため、ボンディングができな
い。このため、ランド32とベアチップ１のパッド２との
間に所定の間隔（スパン）Ｂを設けている。また、基板
31のランド32にはワイヤボンディングのため金メッキが
必要である。2. Description of the Related Art When a semiconductor bare chip is mounted on a substrate by wire bonding, for example, as shown in FIG. 3, there is a difference between the pad 2 of the bare chip 1 and the land 32 on the substrate 31 by the height of the bare chip 1. Therefore, bonding may not be performed because the wire 33 may come into contact with the bare chip 1. For this reason, a predetermined interval (span) B is provided between the land 32 and the pad 2 of the bare chip 1. Also, the substrate
The lands 32 of the 31 require gold plating for wire bonding.
【０００３】[0003]
【発明が解決しようとする課題】上述のように、従来の
ワイヤボンディングでは、ベアチップのパッドと基板の
ワイヤボンディング用のランドとの間に所定のスパンが
必要で、ベアチップを高密度実装する場合の障害になっ
ていた。本発明は、ベアチップのパッドと基板のランド
とのスパンを狭める手段を設けてベアチップの高密度実
装を可能にし、また、基板のランドの金メッキを不要に
して基板の製作コストを低減することを目的とする。As described above, in the conventional wire bonding, a predetermined span is required between the pad of the bare chip and the land for wire bonding of the substrate, and when the bare chip is mounted at high density. Had been an obstacle. An object of the present invention is to provide a means for narrowing the span between the pad of the bare chip and the land of the substrate to enable high-density mounting of the bare chip, and to reduce the manufacturing cost of the substrate by eliminating the need for gold plating on the land of the substrate. And
【０００４】[0004]
【課題を解決するための手段】上記目的を達成するた
め、本発明のワイヤボンディング構造では、半導体のベ
アチップを基板にワイヤボンディング実装するものにお
いて、上面にワイヤボンディング用のランドを形成する
と共に、上面のランドと導電接続される導電部を側面に
形成したＷ／Ｂチップ（ワイヤボンディングチップ）
を、基板のワイヤボンディング箇所のランドに導電させ
て取付け、ベアチップのパッドをＷ／Ｂチップにワイヤ
ボンディングするように構成する。In order to achieve the above object, in a wire bonding structure according to the present invention, a semiconductor bare chip is mounted by wire bonding on a substrate. W / B chip (wire bonding chip) with a conductive part formed on the side surface that is conductively connected to the land
Is electrically conductively attached to the land of the wire bonding portion of the substrate, and the pad of the bare chip is wire-bonded to the W / B chip.
【０００５】Ｗ／Ｂチップは、基板に取付けたとき上面
がベアチップと略同じ高さになるように形成する。[0005] The W / B chip is formed such that the upper surface thereof is substantially the same height as the bare chip when mounted on a substrate.
【０００６】そして、Ｗ／Ｂチップは、上面のランドに
金メッキを施し、側面に上面の金メッキ層と導電する導
電メッキを施す。The W / B chip is provided with gold plating on the lands on the upper surface and with conductive plating on the side surfaces to conduct with the gold plating layer on the upper surface.
【０００７】または、上面のランドに金メッキを施し、
側面に半スルーホールを形成してもよい。この場合、Ｗ
／Ｂチップの複数の側面、例えば、対向する二側面にそ
れぞれ半スルーホールを形成するようにする。Alternatively, gold on the land on the upper surface is applied,
A half through hole may be formed on the side surface. In this case, W
A half through hole is formed on each of a plurality of side surfaces of the / B chip, for example, two opposing side surfaces.
【０００８】あるいは、Ｗ／Ｂチップは、両面基板の上
面のランドに金メッキを施すと共にスルーホールを形成
し、該スルーホールを二分割するように切断して形成す
るようにしてもよい。Alternatively, the W / B chip may be formed by plating a land on the upper surface of the double-sided substrate, forming a through hole, and cutting the through hole into two parts.
【０００９】なお、Ｗ／Ｂチップは側面の導電部を基板
のワイヤボンディング箇所のランドに半田付けで取付け
る。The W / B chip has a conductive portion on the side surface attached to a land at a wire bonding portion of the substrate by soldering.
【００１０】[0010]
【発明の実施の形態】発明の実施の形態を実施例に基づ
き図面を参照して説明する。図１は本発明によるワイヤ
ボンディング構造の一実施例の要部の上面図および側面
図である。図において、１は半導体のベアチップ、２は
ベアチップ１のパッド（電極）、３は基板、４は基板３
のランド、５はＷ／Ｂ用チップ、６はワイヤボンディン
グ用のワイヤである。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described based on embodiments with reference to the drawings. FIG. 1 is a top view and a side view of a main part of an embodiment of a wire bonding structure according to the present invention. In the figure, 1 is a semiconductor bare chip, 2 is a pad (electrode) of the bare chip 1, 3 is a substrate, 4 is a substrate 3
, 5 are W / B chips, and 6 is a wire for wire bonding.
【００１１】Ｗ／Ｂ用チップ５は、例えば、図２（イ）
に示すように、図１の基板３と同様のセラミック等の基
材11で四角形に形成し、上面に金メッキ12を施し、側面
に金メッキ12層と導電する導電メッキ、例えば、半スル
ーホール13を形成する。半スルーホール13はＷ／Ｂチッ
プ５の少なくとも二側面、例えば、左右両側面に形成す
る。このＷ／Ｂチップ５を基板３のワイヤボンディング
箇所のランド４に乗せ、半田付けでランド４に半スルー
ホール13を取付け、このＷ／Ｂチップ５にベアチップ１
のパッド２をワイヤボンディングする。Ｗ／Ｂチップ５
の高さ（厚み）をベアチップ１と同程度にすることによ
り、ワイヤボンドのツールはベアチップ１と略同じ高さ
の位置でＷ／Ｂチップ５にボンディングできるので、ワ
イヤ６がベアチップ１に接触するという従来の障害を排
除でき、ベアチップ１のパッド２とランド４（Ｗ／Ｂチ
ップ５）との間隔Ｂを狭めることができ、ベアチップ１
の実装密度を上げることができる。The W / B chip 5 is, for example, as shown in FIG.
As shown in FIG. 1, a rectangular plate is formed of a base material 11 such as ceramics similar to the substrate 3 of FIG. 1, gold plating 12 is applied to the upper surface, and conductive plating that conducts with the gold plating 12 layer on the side surface, for example, a half through hole 13 is formed. Form. The half through holes 13 are formed on at least two side surfaces of the W / B chip 5, for example, on both left and right side surfaces. The W / B chip 5 is placed on the land 4 of the wire bonding portion of the substrate 3 and a half through hole 13 is attached to the land 4 by soldering.
Is bonded by wire bonding. W / B chip 5
By making the height (thickness) of the bare chip 1 approximately the same as that of the bare chip 1, the wire bonding tool can bond to the W / B chip 5 at a position at substantially the same height as the bare chip 1, so that the wire 6 comes into contact with the bare chip 1. And the distance B between the pad 2 of the bare chip 1 and the land 4 (W / B chip 5) can be reduced.
Mounting density can be increased.
【００１２】Ｗ／Ｂチップ５は、図２（ロ）に示すよう
に、長方形の基材21（両面基板）の上面のランドに金メ
ッキ22を施し所定の間隔でスルーホール23を形成し、こ
のスルーホール23を二分割する位置24で基材21を切断し
て形成してもよい。このように、Ｗ／Ｂチップ５を用い
ることにより、基板３のランド４には直接ワイヤボンデ
ィングをしないので基板３に金メッキを施す必要がな
く、形状の小さいＷ／Ｂチップにのみ金メッキを施せば
よいので基板の製作コストを低減することができる。As shown in FIG. 2B, the W / B chip 5 is provided with gold plating 22 on lands on the upper surface of a rectangular base material 21 (double-sided substrate) to form through holes 23 at predetermined intervals. The base material 21 may be cut at a position 24 where the through hole 23 is divided into two. In this way, by using the W / B chip 5, the land 4 of the substrate 3 is not directly wire-bonded, so that the substrate 3 does not need to be gold-plated, and only the small-sized W / B chip is plated with gold. Since it is good, the manufacturing cost of the substrate can be reduced.
【００１３】[0013]
【発明の効果】以上に説明したように、本発明によるワ
イヤボンディング構造によれば、基板のワイヤボンディ
ング用のランドにＷ／Ｂ用チップを導電的に取付け、こ
こにベアチップのパッドをワイヤボンディングするもの
であるから、Ｗ／Ｂ用チップをベアチップと同じ位の高
さにすることにより、ワイヤがベアチップに接触する可
能性がなくなるので、ベアチップのパッドと基板のワイ
ヤボンディング用のランドとの間隔を従来より狭めるこ
とができ、ベアチップの実装密度を上げることができ
る。また、基板はランドの金メッキが不要になるので、
基板の製作コストを低減することができる。As described above, according to the wire bonding structure of the present invention, the W / B chip is conductively attached to the wire bonding land of the substrate, and the bare chip pad is wire-bonded thereto. Since the W / B chip is at the same height as the bare chip, there is no possibility that the wire comes into contact with the bare chip. Therefore, the space between the pad of the bare chip and the land for wire bonding of the substrate is reduced. It can be narrower than before, and the mounting density of bare chips can be increased. Also, since the substrate does not require gold plating on the land,
The manufacturing cost of the substrate can be reduced.
【図１】本発明によるワイヤボンディング構造の一実施
例の要部上面図および側面図である。FIG. 1 is a top view and a side view of a main part of an embodiment of a wire bonding structure according to the present invention.
【図２】本発明のワイヤボンディングに用いるＷ／Ｂチ
ップの例を示す図である。FIG. 2 is a diagram showing an example of a W / B chip used for wire bonding of the present invention.
【図３】従来のワイヤボンディング構造の一例の要部上
面図および側面図である。FIG. 3 is a top view and a side view of a main part of an example of a conventional wire bonding structure.
１ ベアチップ ２ パッド ３、31 基板 ４、32 ランド ５ Ｗ／Ｂ用チップ ６、33 ワイヤ 11、21 Ｗ／Ｂ用チップの基材 12、22 金メッキ 13 半スルーホール 23 スルーホール 24 切断箇所 Reference Signs List 1 bare chip 2 pad 3, 31 substrate 4, 32 land 5 W / B chip 6, 33 wire 11, 21 W / B chip base material 12, 22 gold plating 13 half through hole 23 through hole 24 cut point
Claims (8)
ディング実装するものにおいて、上面にワイヤボンディ
ング用のランドを形成すると共に、上面のランドと導電
接続される導電部を側面に形成したＷ／Ｂチップ（ワイ
ヤボンディングチップ）を、前記基板のワイヤボンディ
ング箇所のランドに導電させて取付け、前記ベアチップ
のパッドを前記Ｗ／Ｂチップにワイヤボンディングする
ようにしたワイヤボンディング構造。1. A W / B chip (1) in which a semiconductor bare chip is mounted on a substrate by wire bonding, wherein a land for wire bonding is formed on an upper surface, and a conductive portion electrically connected to the land on the upper surface is formed on a side surface. A wire bonding structure in which a wire bonding chip is electrically conductively attached to a land of a wire bonding portion of the substrate, and a pad of the bare chip is wire-bonded to the W / B chip.
き上面が前記ベアチップと略同じ高さになるように形成
するようにした請求項１記載のワイヤボンディング構
造。2. The wire bonding structure according to claim 1, wherein said W / B chip is formed such that an upper surface thereof is substantially the same height as said bare chip when attached to a substrate.
メッキを施し、側面に上面の金メッキ層と導電する導電
メッキを施してなる請求項１または２記載のワイヤボン
ディング構造。3. The wire bonding structure according to claim 1, wherein the W / B chip is provided with gold plating on a land on an upper surface and a conductive plating on a side surface of the W / B chip with a gold plating layer on the upper surface.
メッキを施し、側面に半スルーホールを形成してなる請
求項１または２記載のワイヤボンディング構造。4. The wire bonding structure according to claim 1, wherein the W / B chip is formed by applying gold plating to a land on an upper surface and forming a half through hole on a side surface.
施し、複数の側面にそれぞれ半スルーホールを形成して
なる請求項１または２記載のワイヤボンディング構造。5. The wire bonding structure according to claim 1, wherein the W / B chip is formed by applying gold plating on an upper surface and forming half through holes on each of a plurality of side surfaces.
施し、対向する二側面にそれぞれ半スルーホールを形成
してなる請求項１または２記載のワイヤボンディング構
造。6. The wire bonding structure according to claim 1, wherein the W / B chip has a gold plating on an upper surface and a half through hole formed on each of two opposing side surfaces.
ランドに金メッキを施すと共にスルーホールを形成し、
該スルーホールを二分割するように切断して形成するよ
うにした請求項１または２記載のワイヤボンディング構
造。7. The W / B chip is provided with a gold plating on a land on an upper surface of a double-sided board and a through hole,
3. The wire bonding structure according to claim 1, wherein said through hole is formed by cutting said through hole into two parts.
板のワイヤボンディング箇所のランドに半田付けで取付
けるようにした請求項３、４、５、６または７記載のワ
イヤボンディング構造。8. The wire bonding structure according to claim 3, wherein the W / B chip has a conductive portion on a side surface attached to a land of a wire bonding portion of the substrate by soldering.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000075359A JP2001267351A (en) | 2000-03-17 | 2000-03-17 | Wire-bonding structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000075359A JP2001267351A (en) | 2000-03-17 | 2000-03-17 | Wire-bonding structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001267351A true JP2001267351A (en) | 2001-09-28 |
Family
ID=18593268
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000075359A Pending JP2001267351A (en) | 2000-03-17 | 2000-03-17 | Wire-bonding structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001267351A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1387603A1 (en) * | 2002-07-30 | 2004-02-04 | Agilent Technologies, Inc. - a Delaware corporation - | Electronic assembly and method of manufacture thereof |
| KR101046379B1 (en) | 2008-02-14 | 2011-07-05 | 주식회사 하이닉스반도체 | Semiconductor package and manufacturing method thereof |
| JP2015076576A (en) * | 2013-10-11 | 2015-04-20 | パナソニックＩｐマネジメント株式会社 | Electric device and manufacturing method of the same |
-
2000
- 2000-03-17 JP JP2000075359A patent/JP2001267351A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1387603A1 (en) * | 2002-07-30 | 2004-02-04 | Agilent Technologies, Inc. - a Delaware corporation - | Electronic assembly and method of manufacture thereof |
| KR101046379B1 (en) | 2008-02-14 | 2011-07-05 | 주식회사 하이닉스반도체 | Semiconductor package and manufacturing method thereof |
| JP2015076576A (en) * | 2013-10-11 | 2015-04-20 | パナソニックＩｐマネジメント株式会社 | Electric device and manufacturing method of the same |
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