JP2001256119A - Self-destruction type semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To quickly detect voltage change including the short-circuit/opening of a power supply source. SOLUTION: A differential amplifier circuit block 52a is constituted of the two stages of differential amplifier circuits 54-1 and 54-2. A referential voltage setting circuit 51 is constituted of a capacity circuit. A digital output buffer circuit block 53a is constituted of the two stages of CMOS inverters 55-1 and 55-2 and a control circuit or element 4 is constituted of a CMOS selector circuit. When the detachment or short-circuit of the power supply source 6 occurs, voltage decline is detected by a voltage change detection circuit 5a. Thus, the control circuit or element 4 is ON-operated, a destruction circuit 2 and a capacitor 3 for destruction are connected and the memory data of a semiconductor integrated circuit 1 are destroyed by the destruction circuit 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a physical security technique for falsification of memory contents of a semiconductor integrated circuit having a function of storing and processing important information with high confidentiality, and more particularly to an IC (Integrated Circuits) card. The present invention relates to a self-destructive semiconductor device in which a thin power supply source suitable for mounting on a thin semiconductor device such as the above is used as a detector of a physical attack by an unauthorized analyst.

[0002]

2. Description of the Related Art At present, an IC card used as a credit card or electronic money has various functions for storing and processing important information such as personal privacy and money in a semiconductor integrated circuit (IC chip). The IC chip is sealed in a plastic card. Therefore, in some cases, after removing the IC chip from the body of the plastic card, observe the surface of the IC chip with an optical microscope or the like, and illegally analyze the function, operation method, circuit method, circuit pattern, stored data, etc. of the integrated circuit. And modify the contents (illegal analysts, hereafter,
Attackers).

Therefore, it is necessary to provide the IC card for storing and processing such important information with some kind of defense means for preventing such illegal acts. For example, a high-end class IC card is equipped with a coprocessor for performing signal processing using encryption to prevent tampering of digital data, and a tamper-resistant (Tamper resistance) circuit to prevent unauthorized access to digital data. Or a built-in illegal operation prevention circuit. Examples of the tamper-resistant circuit include a frequency detection circuit, a temperature detection circuit, and a power supply voltage detection circuit.

[0004] Regarding the frequency detection circuit, the attacker uses C
It is conceivable to adopt a method of analyzing the clock while inputting it to the PU for each instruction. To prevent this analysis, a low-frequency detection circuit for detecting the clock of the CPU is built in.
Further, an integrated circuit on an IC chip does not operate at any temperature, and there is always an optimum operating temperature. Since operation cannot be guaranteed when the temperature becomes other than the operating temperature, the operation of the integrated circuit is stopped by the temperature detection circuit when the temperature becomes out of the standard. Similarly, if a voltage other than the standard voltage is applied, the operation of the integrated circuit becomes unstable. Therefore, the power supply voltage detection circuit is designed so that the integrated circuit does not operate when the voltage becomes a voltage other than the normal voltage. .

[0005] By the way, fraudulent acts by attackers include:
There are two main types: a method for analyzing the inside by breaking the IC chip and a method for nondestructive analysis. The above-described tamper-resistant circuit is mainly for preventing the analysis of the electrical signal data of the IC chip via the external connection electrode, and can be said to be a defense measure against the latter non-destructive analysis method. On the other hand, the physical dissection and analysis of an IC chip cannot be prevented by an IC card having a conventional structure.

FIG. 10 shows a contact type IC currently used.
FIG. 3A shows a schematic configuration example of the card 13, in which FIG. 4A is a plan view showing a circuit block arrangement in a semiconductor integrated circuit mounted on the IC card 13, and FIG.
FIG. 3C is a cross-sectional view of the C module, and FIG. As shown in FIG. 10C, an IC card 13 made of plastic includes an IC chip 12
An IC module 11 composed of a hot melt adhesive 34 and a contact electrode base is mounted. The contact electrode base is obtained by printing a contact pattern 35 corresponding to an electrode of the contact type IC card 13 on a glass epoxy substrate 36 with a copper foil or the like. In the IC module 11, the IC chip 12 is die-bonded to the glass epoxy substrate 36 on which the contact pattern 35 is formed, and the external connection electrode pad 7 and each contact pattern 35 are wire-bonded by the gold wire 37. , And is fixed and sealed by a mold resin 38.

[0007] As shown in FIG.
2, a data memory (flash memory, EEPROM, etc.), which is composed of a nonvolatile memory capable of electrically writing and collectively erasing a plurality of bits of data, which stores particularly important information such as an encryption code and an authentication code. (Electrically
Erasable and Programmable ROM) or Ferroelectric Thin Film Memory (FRAM)
4, a peripheral circuit 15 including a voltage booster circuit for writing and erasing, a read-only program memory (configured with a ROM or the like) 16 storing a predetermined control program, and a program memory 16 A central processing unit (CPU) 17 that reads a control program, performs processing in accordance with the control program, and controls arithmetic operations and rewriting of data stored in a nonvolatile memory;
Random access memory (RAM) 1 composed of volatile memory as working memory for temporary data storage
8. Security authentication microprocessor (MP
U) 19 are formed on the same semiconductor substrate. A data bus and power supply electrode wiring (not shown) are provided around these components.

A reader / writer separate from the IC card 13
In order to supply an electric signal and a driving voltage from the writer to the IC chip 12, a total of eight external connection electrode pads 7 made of a metal such as aluminum are formed near two opposite ends of the IC chip 12. Have been. Therefore, the external connection electrode pads 7 on the IC chip 12 exchange electric signals with the outside of the IC chip via the contact pattern 35 on the card surface. Note that when reading or writing an electric signal from the outside, encryption processing of the electric signal is performed by the microprocessor 19 for authentication or encryption to enhance security.

The data memory 14 and the program memory 16 in the IC chip 12 store important data such as a protocol required for communication, a number code for authentication, and a password required for security. .
Therefore, these codes and data, as well as information such as circuit blocks and circuit patterns constituting the semiconductor device, are used to prevent forgery and tampering of the IC card.
It must be prevented from being read by an attacker.

However, in the semiconductor device as shown in FIG. 10, the circuit configuration blocks, the functional element circuits, the data memory 14 and the program memory 16 and the authentication microprocessor 1 are started by optical observation from above.
9 can be seen, and furthermore, the probing measurement using an electron beam can be used to easily read out the stored contents of the memory element, or cause the authentication microprocessor 19 to malfunction due to a runaway trigger, thereby skipping the authentication process itself. It was possible to make it.

Therefore, in recent high-density mounting technology, the IC module 11 has a semiconductor integrated circuit, which has a purpose of reducing the thickness by physically grinding the IC module 11 itself and preventing optical observation from above. A flip electrode for forming a bump electrode for obtaining electrical connection on the element forming surface side on which the IC chip is formed, turning the IC chip upside down, and connecting to a mounting substrate (electrode substrate) on which a contact electrode for external connection is formed Implementation is frequently adopted.

However, a technique for observing a circuit near the surface of the semiconductor substrate in a non-destructive manner from the back surface of the semiconductor substrate on which the semiconductor integrated circuit is formed has been developed in response to a demand for a failure analysis technique or the like. In this method, the transparency of the semiconductor substrate is enhanced by using infrared light having a wavelength that is hardly absorbed by the semiconductor substrate as an observation light source, and a wiring pattern or the like mainly made of metal is observed from the back side of the semiconductor substrate. Thus, the pattern of the lowermost transistor and the wiring pattern of the first layer can be observed nondestructively. Therefore, in the flip chip mounting method, since the chip back surface is exposed to the outside, pattern observation from the back surface side rather than the element formation surface side of the IC chip becomes easy.

In order to solve the above-mentioned problem, the present inventors have incorporated a thin power supply source and mounted the thin power supply source on the back side of an IC chip, so that optical observation from the back side is possible. Proposed a self-destructive type semiconductor device for preventing a semiconductor device (JP-A-11-306786, JP-A-2000-306786)
0222093, Japanese Patent Application No. 10-243444.
issue). The conceptual reason for adopting such a mounting structure is as follows. There are many physical analysis methods using attackers, and it is technically difficult to apply effective defense measures to all of them, and it is irrational in cost. A more proactive defense is to limit attacks by attackers and incorporate effective defenses within the limited attack range.

In other words, by adopting a structure in which the thin power supply is stacked and mounted on the back surface of the flip-chip mounted IC chip, the thin power supply must be removed first in order to proceed with the analysis of the IC chip with an attacker. Drive to. When an attack on the thin power supply source is detected, a mechanism of self-destruction that securely erases confidential information is incorporated in advance, so that information required by an attacker is not provided.

In the self-destructive semiconductor device proposed above, the thin power supply itself mounted and stacked is used as the tamper detection sensor, and its voltage change is constantly monitored. Then, the power of the thin power supply is stored in a large-capacity capacitor connected in parallel with the power supply, so that the power supply is attacked first and malfunctions, so that it is used as a destruction power supply. . Naturally, the connection between the power supply source and the destruction capacitor and the connection between the destruction capacitor and the destruction circuit are simultaneously switched by a detection signal from the voltage change detection circuit.

The functions required of such a self-destruct system are as follows. There are two possible attacks by the attacker, such as (1) removing the thin power supply for shielding, and (2) short-circuiting the thin power supply for shielding in advance. Memory must be erased.

Therefore, a self-destructive function required for a self-destructive semiconductor device is to erase secret important information in a memory when an attack on a power supply source is detected. Furthermore, it is impossible to predict when an attack by the attacker will occur, and it is necessary to constantly monitor the attack by the attacker during the operation guarantee period of the IC chip. Therefore, the tamper-resistant circuit continuously detects the tamper action during the operation guarantee period of the IC chip within the limited battery capacity of the thin power supply source, and immediately detects the attack by the attacker. You have to erase the secret important information in the memory.

FIG. 11 shows a basic circuit block diagram of a self-destructive semiconductor device having such a self-destructive function. FIG. FIG. 12 shows a mounting structure in which a thin power supply source is mounted on the back surface of an IC chip. FIG.
1A is a bottom view showing an example of the arrangement of a self-destructive semiconductor device disclosed in Japanese Patent Application Laid-Open No. 2000-022093, FIG. 13B is a cross-sectional view of the self-destructive semiconductor device, and FIG.
FIG. 4 is a diagram showing a state of flip-chip mounting. In addition,
FIG. 13A shows a state before flip-chip mounting. As shown in FIG.
On the semiconductor integrated circuit 2a, a data memory 14, a program memory 16, a central processing unit 17, a random access memory 18, and an authentication microprocessor 19 necessary for the original IC card function shown in FIG. Have been.

In this configuration, in addition to the above configuration, a destruction circuit for destructing memory information is added as the destruction circuit 2. Further, on the IC chip 12a, a destruction capacitor 3, a control circuit or an element are provided. 4 and a voltage change detection circuit 5 are formed. A thin power supply 6 is connected to a terminal 10 whose terminal voltage is constantly monitored by the voltage change detection circuit 5. As a power supply for driving the destruction circuit 2, electric charges accumulated in a large-capacity destruction capacitor 3 formed on the IC chip 12a are used. In the normal operation state, this capacitor 3
A power supply 6 is connected via a control circuit or an element 4, and an output voltage of the power supply 6 is applied to a voltage change detection circuit 5.
Is constantly monitored.

As shown in FIG. 13 (b), the thin power supply source 6 is formed by laminating a positive electrode current collector / terminal plate 21, a positive electrode 22, a solid electrolyte 23, a negative electrode 24, and a negative electrode current collector / terminal plate 25. The periphery thereof is thermally sealed by a sealing material 26. In addition, the external dimensions of the positive electrode current collector / terminal plate 21 and the negative electrode current collector / terminal plate 25 are designed differently so that even if the battery end surface comes into contact with a conductive material such as a metal, the external short circuit is prevented. I have. Usually, the positive electrode current collector / terminal plate 21 is configured to be smaller than the negative electrode current collector / terminal plate 25.

In order to ensure the back surface shielding effect by the thin power supply source 6 stacked and mounted on the back surface side of the IC chip 12,
Until now, a thin power supply source mounting structure having 2n connection leads (Japanese Patent Laid-Open No. 2000-022093) or a power supply source is covered with a metal foil in order to hide the connection leads from an attacker. Thin power supply I
Mounting structure to be mounted on the back side of C chip (Japanese Patent Application No. 10-24)
No. 3444).

For example, FIG.
3A shows a state in which a thin power supply source 6 having connection leads made of metal foil is mounted on an electrode substrate 32a on which a is flip-chip mounted. FIG. 13A shows a configuration example of the lower surface of the self-destructive semiconductor device corresponding to the IC chip 12a in FIG.
13 (b) is a sectional view of the self-destructive semiconductor device. In these figures, components equivalent to those in FIG. 10 are denoted by the same reference numerals. Power supply source 6 having 2n connection leads 28 shown in FIG.
13A, the IC chip 12a shown in FIG. 13A has eight external connection electrode pads 7 (7-1 to 7-8) necessary for operation as an IC card, 2n electrode pads 10 for connection with the supply source 6a,
That is, n power supply sources 6a are added for a positive electrode lead, and n power supply sources are added for a negative electrode lead.

The external connection electrode pads 62 corresponding to the external connection electrode pads 7-1 to 7-8 of the IC chip 12a are provided on the IC chip mounting surface of the corresponding electrode base 32a.
-1 to 62-8 are formed, and the respective electrode pads 62-1 to 6-8 are formed.
Reference numerals 2-8 are respectively connected to the contact patterns 35-1 to 35-8 by through holes or the like. Further, on the IC chip mounting surface of the electrode base 32a, 2n power supply source connection electrodes corresponding to the 2n power supply source connection electrode pads 10 of the IC chip 12a (n for each of the positive electrode and the negative electrode) are provided. The pads 63 are formed, and 2n power supply source connection electrode pads 64 corresponding to the 2n connection leads 28 of the power supply source 6 (n for the positive and negative electrode leads) are formed. And the electrode pad 6
Each of 3 is connected to the corresponding electrode pad 64 by wiring.

As shown in FIG. 13B, the electrode substrate 32
a through the anisotropic conductive adhesive resin 61 applied to the entire IC chip mounting surface of the IC chip 12a.
It is flip-chip mounted on top. Further, the electrode base 32
The power supply source 6 is mounted on the back surface of the IC chip 12a which is flip-chip mounted on the IC chip 12a via the adhesive film 20, and the connection leads 28 thereof and the power supply source connection electrode pads 64 of the electrode base 32a are connected by the bumps 27. Electrically connected. In this manner, a mounting structure having an effect of shielding the back surface of the IC chip 12a by the thin power supply source 6 can be realized.

A system circuit for enabling these mounting structures to function as expected as a physical tamper-resistant structure is described below.
Hereinafter, a description will be given using a circuit block diagram 11 and FIG. 12 which is an example of a specific circuit configuration using MOS transistors. The power supply to the entire circuit is performed by the electric charge accumulated in the destruction capacitor 3 connected in parallel to the power supply source 6. The control circuit or the element 4 is constituted by a CMOS selector circuit combining a CMOS transmission gate. In a normal state, the CMOS transmission gate between the destruction capacitor 3 and the power supply source 6 is in an ON state, and the power supply source 6 is brought into conduction through the destruction capacitor 3 and the voltage change detection circuit 5, while the destruction capacitor 3 is turned on. The CMOS transmission gate provided between 3 and the destruction circuit 2 is kept in a non-conductive state.

The voltage change detection circuit 5 mainly includes a one-stage modified current mirror type differential amplifying circuit 52 (see FIG. 15) having high detection sensitivity. Is connected to an open / short detection circuit 50 (see FIG. 16) composed of a capacitance-divided RC time constant circuit, and the voltage supplied from the destruction capacitor 3 is capacitance-divided on the reference voltage input Vref side. A reference voltage setting circuit 51 for setting a reference voltage is connected, and a digital output buffer circuit 53 (see FIG. 17) composed of a single-stage CMOS inverter is arranged on the output side of the differential amplifier circuit 52.

The DC leakage current of the entire voltage change detection circuit 5 includes a sub-threshold leakage current ILK1 flowing through the transistor used in the RC time constant circuit of the open / short detection circuit 50, a current ILK2 flowing through the differential amplifier circuit 52,
And the current ILK3 flowing through the digital output buffer circuit 53
It consists of three components. Among them, the current ILK3 flowing through the digital output buffer circuit 53 has a CMOS switch configuration, so that the DC current component is extremely small, and the current ILK2 flowing through the differential amplifier circuit 52 controls the total leakage current.

The reason why the RC time constant circuit is provided in the open / short detection circuit 50 is that the power supply connection electrode pads 10a,
When the portion between the terminals 10b is opened due to the removal of the power supply source or the like, charge is extracted from the capacitance due to the leak current flowing through the resistance of the RC time constant circuit, and the detection-side differential voltage input Vin of the differential amplifier circuit 52 is used as a reference. This is for detecting a voltage change by lowering the voltage input before the voltage input Vref. The RC time constant circuit is connected to the power supply connection electrode pad 10.
This gives a delay time for detecting the open state between a and 10b. On the other hand, the power supply source connection electrode pad 10
When the short circuit between the terminals a and b is detected, the detection voltage input Vin of the differential voltage input immediately decreases.
Immediately detects the voltage difference.

The detection signal is converted to a 0-Vdd signal by a digital output buffer circuit 53 in the output stage,
The signal is output to a control circuit or element 4 composed of a transmission gate. Control voltage Vout before and after the inverter
The control circuit or the element 4 receiving the complementary voltage bar Vout disconnects the conduction of the transmission gate connecting the destruction capacitor 3 with the voltage change detection circuit 5 and the power supply source 6, and also sets the destruction capacitor 3 And the transmission gate connecting the destruction circuit 2 with the transmission gate. In this manner, the removal of the power supply source 6 or an attack on the power supply source 6 such as a needle stick is detected by the voltage change detection circuit 5, and the power stored in the destruction capacitor 3 is transmitted to the destruction circuit 2 by the signal output. As a result, the secret memory information was erased, and the prevention of data tampering was realized as a minimum function.

[0030]

However, FIG.
In the voltage change detection circuit 5 using the single-staged differential amplifier circuit 52 shown in (1), there is a problem that it takes time to detect a voltage drop when the power supply source 6 is opened. As a result, connection switching by the control circuit or the element 4 is not performed quickly,
In some cases, before the charge stored in the destruction capacitor 3 is supplied to the destruction circuit 2 and used for erasing the memory, it is consumed as power for driving the voltage change detection circuit 5 and discharged. As a result, there is a problem that the self-destruction mechanism does not operate. Further, in the voltage change detection circuit 5 using the one-stage differential amplifier circuit 52 and the one-stage digital output buffer circuit 53, when the circuit optimization is insufficient, the low potential Vss ( 0V)
There is a problem that an intermediate potential between the high potential and the high potential Vdd is easily generated. As a result, there is a problem that the transmission gate connecting the destruction capacitor 3, the voltage change detection circuit 5, and the power supply source 6, which is a component of the control circuit or the element 4, is not completely turned off. . The present invention has been made to solve the above-described problem, and can operate for a required period with a limited battery capacity of a power supply source and quickly detect a voltage change including a short circuit / open of the power supply source. It is an object of the present invention to provide a self-destructive semiconductor device that can be used. Another object of the present invention is to provide a self-destructive semiconductor device capable of outputting a detection signal required for operation of a self-destruction mechanism (switching operation of a control circuit or an element) at a high speed and without dulling a signal waveform. With the goal.

[0031]

A self-destructive semiconductor device according to the present invention comprises a semiconductor memory element, a central processing element for processing data stored in the memory element, and at least one of memory information of the semiconductor memory element. A destruction circuit (2) for self-destruction by erasing a portion, at least one or more destruction capacitors (3) for storing charges for self-destruction by the destruction circuit; The voltage between the connection terminals (10a, 10b) provided for the positive and negative electrodes of the power supply source for accumulating electric charges and the voltage between the connection terminals for the positive and negative electrodes is monitored, and a detection signal is output according to the voltage drop. A voltage change detection circuit (5a);
During normal operation, a control circuit that connects the power supply source and the destruction capacitor via the connection terminal, and disconnects the connection and connects the destruction capacitor and the destruction circuit when the detection signal is output from the voltage change detection circuit. And the element (4) on the same semiconductor substrate and a power supply source (6) connected to the connection terminal. Voltage change detection circuit (5a)
Includes an open / short detection circuit (50a) for detecting open / short of a power supply source, a reference voltage setting circuit for generating a predetermined reference voltage (Vref), and a first and second two-stage differential amplifier. The output voltage of the open / short detection circuit is compared with the reference voltage of the reference voltage setting circuit, and a detection signal is output when a decrease in the output voltage of the open / short detection circuit is detected. And a differential amplifier circuit block (52a) for outputting, and each circuit is constituted by a MOS transistor circuit. The control circuit or element (4) is composed of a CMOS selector circuit. When the power supply source (6) is removed or short-circuited, a voltage drop is detected by the voltage change detection circuit (5a). The control circuit or element (4) is turned on by this detection signal, and the destruction circuit (2) is connected to the destruction capacitor (3). Thereby, the electric charge accumulated in the destruction capacitor (3) is supplied to the destruction circuit (2). Therefore, the essential non-volatile memory data of the integrated circuit to be falsified is destroyed, so that falsification becomes impossible.

The self-destructive semiconductor device according to the present invention
As a configuration example, the first amplifier of the differential amplifier circuit block (52a)
Is a first differential amplifier composed of first and second p-channel MOS transistors (Q20, Q21), and a first differential amplifier connected to the first differential amplifier. A first current mirror type load including two n-channel MOS transistors (Q22, Q23), and a third n for power control connected to the first current mirror type load.
A channel MOS transistor (Q24), and the second differential amplifier circuit of the differential amplifier circuit block
A second differential amplifier comprising p-channel MOS transistors (Q25, Q26) and fourth and fifth n-channel MOS transistors (Q27, Q28) connected to the second differential amplifier. A second current mirror type load connected to the second current mirror type load,
A sixth n-channel MOS transistor (Q29) for timing adjustment when the connection terminals are short-circuited;
The source electrode of the p-channel MOS transistor is connected to the high potential side of the power supply via the connection terminal,
The drain electrode of the second p-channel MOS transistor is connected to the drain electrode of the first and second n-channel MOS transistors, respectively, and the first p-channel MOS transistor
The first of the open / short detection circuit for the gate electrode of the transistor
Output voltage (Vin1) is input to the second p-channel M
The reference voltage (Vref) of the reference voltage setting circuit is input to the gate electrode of the OS transistor, and the source electrodes of the first and second n-channel MOS transistors are connected to the drain electrode and the gate electrode of the third n-channel MOS transistor. The source electrode of the third n-channel MOS transistor is connected to the lower potential side of the power supply via the connection terminal, and the source electrodes of the third and fourth p-channel MOS transistors are connected via the connection terminal. The third p-channel MOS transistor is connected to the high potential side of the power supply source, and the drain electrodes of the third and fourth p-channel MOS transistors are connected to the drain electrodes of the fourth and fifth n-channel MOS transistors, respectively.
The second output voltage (Vin2) of the open / short detection circuit is input to the gate electrode of the channel MOS transistor, and the fourth
A second p-channel MOS transistor and a second n-channel MOS
The voltage (Vout) of the common drain electrode of the S transistor is input, the source electrodes of the fourth and fifth n-channel MOS transistors are connected to the drain electrode of the sixth n-channel MOS transistor, and the sixth n-channel MOS transistor is connected. A gate electrode of the transistor is connected to a high potential side of the power supply via a connection terminal; a source electrode of the sixth n-channel MOS transistor is connected to a low potential side of the power supply via a connection terminal; It outputs the voltage of the common drain electrode of the fourth p-channel MOS transistor and the fifth n-channel MOS transistor as a detection signal (bar Vout1). As described above, by using a combination of two stages of the modified current mirror type differential amplifying circuit operable with low power consumption as the differential amplifying circuit block, the first output voltage (Vin1) of the open / short detection circuit can be reduced. The potential difference between the reference voltage (Vref) of the reference voltage setting circuit and the second output voltage (Vref) of the open / short detection circuit are detected with high sensitivity.
By accurately detecting the potential difference between (in2) and the detection signal (Vout) of the first differential amplifier circuit, an open event between the power supply source connection terminals can be particularly detected in a short time (high speed). .

The self-destructive semiconductor device according to the present invention
As a configuration example, an open / short detection circuit (50a) includes first and second open / short detection circuits inserted in series between the positive and negative connection terminals.
And a source electrode connected to the high potential side of the power supply via the connection terminal, and a drain electrode connected to the low potential of the power supply via the connection terminal. P-channel MOS connected to the potential side and having a gate electrode connected to a connection point of the first and second capacitors
A transistor (Q1), and outputs a divided voltage obtained at a connection point between the first and second capacitors to a first output voltage (Vin).
1), and outputs a voltage obtained at a connection point between the first capacitor and the high potential side of the power supply source as a second output voltage (Vin2). Thus, in the open / short detection circuit (50a), the power supply source (6) is connected to the connection terminal (10).
a, 10b), and is composed of an RC time constant circuit for detecting that the connection terminal has become an open end.
When the power supply source (6) is removed from the connection terminal, the charges stored in the capacitors (C1, C2) are discharged through a path passing through the p-channel MOS transistor (Q1), and the output voltages (Vin1, Vin2) decrease. I do. When a short circuit occurs in the power supply source (6), the output voltage (Vin1,
Vin2) drops immediately.

Further, the self-destructive semiconductor device of the present invention
The configuration example is a first and second two-stage CMOS inverter (5
5-1 and 55-2), a digital output buffer circuit block for generating a signal (Vout1) complementary to the detection signal (Vout1) of the differential amplifier circuit block and a signal (Vout2) in phase with the detection signal. The control circuit or element (4) includes p-channel MOS transistors (Q40, Q4) each having a source electrode and a drain electrode connected in common.
2) and n-channel MOS transistors (Q41, Q4)
Transmission gate composed of the pair of 3)
In each transmission gate, a substrate electrode of a p-channel MOS transistor is connected to a drain electrode, and a substrate electrode of an n-channel MOS transistor is connected to a low potential of a power supply source via a connection terminal. The detection signal is input to each gate electrode of the n-channel MOS transistor in the first transmission gate and the p-channel MOS transistor in the second transmission gate, and the p-channel MOS transistor in the first transmission gate And a signal complementary to the detection signal is input to each gate electrode of the n-channel MOS transistor in the second transmission gate, and the commonly connected drain electrode of each transistor is connected to the destruction capacitor, and the first transmission gate Commonly connected source electrodes of the transistors of the inner is connected to the connection terminal of the high-potential side, in which is commonly connected source electrodes of the transistors in the second transmission gate is connected to the breaking circuit.

Further, the self-destructive semiconductor device of the present invention
As a configuration example, a digital output buffer circuit block (5
3a) is configured by stacking two stages of CMOS inverters (55-1, 55-2) each including an n-channel MOS transistor and a p-channel MOS transistor, and includes a first n-channel MOS transistor (Q30) and a The gate electrodes of the first p-channel MOS transistor (Q31) are connected to each other, the drain electrodes are connected to each other, and the source electrode and the substrate electrode of the first p-channel MOS transistor are connected to the high power supply source via the connection terminal. The first n-channel MOS transistor and the first p-channel MOS transistor are connected to the potential side, and the source electrode and the substrate electrode of the first n-channel MOS transistor are connected to the low potential side of the power supply via the connection terminal. The detection signal (bar Vout1) of the differential amplifier circuit block is input to the commonly connected gate electrodes of the transistors. And the first n-channel MOS
A signal (Vout1) complementary to the detection signal is output from a commonly connected drain electrode of the transistor and the first p-channel MOS transistor, and a second n-channel MOS transistor (Q32) and a second p-channel MOS transistor (Q33) are output. ), The drain electrodes are connected to each other, and the source electrode and the substrate electrode of the second p-channel MOS transistor are connected to the high potential side of the power supply via the connection terminal. N channel M
A source electrode and a substrate electrode of the OS transistor are connected to the low potential side of the power supply via a connection terminal, and a detection signal is supplied to a commonly connected gate electrode of the second n-channel MOS transistor and the second p-channel MOS transistor. And a signal (Vout1) complementary to the second n-channel MO
A signal (Vout2) having the same phase as the detection signal is output from the commonly connected drain electrode of the S transistor and the second p-channel MOS transistor. in this way,
By configuring the digital output buffer circuit block (53a) with two-stage CMOS inverters, it is possible to reduce the slack in the output waveform and suppress the generation of the intermediate potential portion. As a result, a voltage change including a short circuit / open circuit of the power supply source is detected at a high speed, and a steep output waveform necessary for reliably operating the next-stage circuit is output, thereby ensuring the function as a tamper detection circuit. .

[0036]

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit block diagram of a self-destructive semiconductor device according to an embodiment of the present invention. Also in this embodiment, as in FIG.
On the semiconductor integrated circuit 1 on the IC chip 12b (semiconductor substrate 9b), a data memory, a peripheral circuit, a program memory, a central processing unit, a random access memory, and a microprocessor for security authentication necessary for the original IC card function are formed. , But omitted here.

In the present invention, in addition to the above configuration, the destruction circuit 2 for erasing the memory information of the data memory is added on the semiconductor substrate 9b, and the destruction circuit 2, the destruction capacitor 3, the control circuit, An element 4 and a voltage change detection circuit 5a are added on a semiconductor substrate 9b. Thus, a self-destructive IC chip 12b is formed.

In the present invention, a large-capacity destruction capacitor 3 formed on a semiconductor substrate 9b is used to store power for driving the destruction circuit 2. As shown in FIG. 13B, a thin power supply source 6 for accumulating electric charge in the destruction capacitor 3 includes a positive electrode current collector / terminal plate 21, a positive electrode 22, a solid electrolyte 23, a negative electrode 24, and a negative electrode collector. It is formed by a laminated structure of the electric / cum-terminal plate 25, and the periphery is thermally sealed by a sealing material 26.

The power supply source 6 supplies power to the destruction circuit 2, the destruction capacitor 3, the control circuit or element 4, and the voltage change detection circuit 5a. Is supplied with power from the outside via power supply terminals of the eight external connection electrode pads 7.

With respect to the power supply source 6 as described above, an IC
On the semiconductor substrate 9b on which the chip 12b is formed, in addition to the eight external connection electrode pads 7 necessary for operation as an IC card, a power supply source connection electrode pad 10a for connection to the positive electrode of the power supply source 6 , And at least one power supply source connection electrode pad 10 b for connecting to the negative electrode of the power supply source 6.

The voltage change detection circuit 5a monitors the voltage between the power supply source connection electrode pads 10a and 10b, that is, the output voltage of the power supply source 6 as needed. The voltage change detection circuit 5a includes an open / short detection circuit 50a for detecting the open / short circuit of the power supply source 6, a reference voltage setting circuit 51 for generating a predetermined reference voltage Vref, and a second circuit of the open / short detection circuit 50a. 1 output voltage Vin1 and reference voltage setting circuit 51
Differential amplifier circuit 54 for comparing the reference voltage Vref with
-1 and the second output voltage V of the open / short detection circuit 50a
a differential amplifier circuit block 52a composed of two stages of a second differential amplifier circuit 54-2 for comparing in2 with the output voltage Vout of the first differential amplifier circuit 54-1; It comprises a digital output buffer circuit block 53a for generating a signal Vout1 complementary to the detection signal Vout1 and a signal Vout2 in phase with the detection signal Vout1 output from the detection signal Vout1, and an n-channel MOS transistor Q50 for protection when the power supply source is short-circuited. .

The control circuit or element 4 has a switch that receives a detection signal output from the voltage change detection circuit 5a as a control input. This switch outputs the detection signal from the voltage change detection circuit 5a. In the normal operating state, the NC side shown in FIG. 1 is selected.

Next, in designing the self-destructive semiconductor device of the present embodiment, there are the following two problems to be considered. A) The amount of current consumption Ist allowed in a tamper-resistant circuit (self-destruction circuit) that realizes the self-destruction function b) The size of the capacitance value CBK required for the destruction capacitor 3

Hereinafter, the concept of such a problem will be described. First, the battery capacity of the power supply source 6 is set to CBT [mA
h], and a self-destruction circuit (destruction circuit 2, destruction capacitor 3, control circuit or element 4, and voltage change detection circuit 5a)
The operation guarantee period during which the operation must continue is defined as T [h].
And The amount of current Ist that can be always conducted in the self-destruction circuit is given by the following equation. Ist = CBT / T [A] (1)

For example, the thickness which can be obtained at present is 0.3 mm
In the case of a thin lithium battery, the battery size is 1 × 1 cm ²
In this case, the battery capacity CBT is about 3 mAh. Assuming that the operation guarantee period T of the self-destruction circuit is about three years, the steady-state current value Ist allowed for the system by simple calculation is about 11
4 nA. The operating current of the entire self-destruction circuit during normal times must be designed to be kept below this steady-state current value Ist.

In the self-destruction circuit shown in FIG.
a, the standby current ILK1 flowing through the digital output buffer circuit block 53a, the standby current ILK1 flowing through the digital output buffer circuit block 53a, and the operating current ILK2 (= ILK21 + ILK22) of the differential amplifier circuit block 52.

As described later, since the reference voltage setting circuit 51 is composed of a plurality of capacitors connected in series,
The leak current component flowing through the reference voltage setting circuit 51 does not matter. Similarly, since the destruction capacitor 3 is also a capacitor, the leakage current component flowing through the destruction capacitor 3 does not matter.

On the other hand, during normal operation, the destruction capacitor 3
Since a leakage current flowing through the destruction circuit 2 via the control circuit or the element 4 can be considered, it is important to keep the magnitude of the leakage current small. As described later, the control circuit or the element 4
Is composed of two CMOS transmission gates, the sub-threshold leakage current can be reduced to a small value by setting the threshold voltage of each transmission gate to be higher.

Therefore, in the self-destruction circuit shown in FIG. 1, the condition that the total amount of current that is always conducting is less than Ist is given by the following equation. ILK1 + ILK2 + ILK3 <Ist (2)

Next, the charge amount Q required for erasing the memory portion of the data memory which stores particularly important information is
er is the current I flowing through the voltage booster circuit constituting the destruction circuit 2
It is given by the following equation from cp and its driving time tcp. Qer = Icp × tcp (3)

Thus, the capacitance value CBK required for the destruction capacitor 3 is given by the following equation, where the output voltage of the power supply source 6 is Vdd. CBK = α × Qer / Vdd (4) In Expression (4), α is a safety coefficient, and is a positive real number larger than 1.

Specifically, operation at Vdd = 3.3 V
EEPROM for writing / erasing 4 kbit EEPROM by channel hot electron injection method manufactured by standard 0.6 μm design rule to erase EEPROM
In the case of M, it is necessary to keep the erase current of 1 mA flowing for an erase time of 10 ms. Therefore, assuming that α = 3 and using equation (4), the capacitance value CBK of the destruction capacitor 3 needs about 10 μF.

The capacitance value CBK required for the destruction capacitor 3 strongly depends on the erasing method of the nonvolatile memory employed in the data memory. EEPRO
In the case of the method of erasing by applying a Fowler-Nordheim tunnel current when a high voltage is applied to the control gate electrode between the tunnel oxide films of the floating gate elements constituting M (FN erasing method) In addition, a current for erasing is not so required, and the erasing time is shortened. Therefore, when an EEPROM using the FN erasing method is used as a data memory, the capacitance value CBK required for the destruction capacitor 3 may be smaller by one to two orders of magnitude than 10 μF.

Under the above conditions, the self-destructive semiconductor device of FIG. 1 is configured as follows. FIG. 2 is a circuit block diagram showing one specific configuration example of the self-destructive semiconductor device of FIG. The n-channel MOS transistor Q
Reference numeral 50 is inserted to prevent a sharp voltage drop when the power supply connection electrode pads 10a and 10b are short-circuited. First, opening (removing) the power supply source 6
The open / short detection circuit 50a for detecting a short circuit will be described. FIG. 3 is a circuit diagram showing one configuration example of the open / short detection circuit 50a.

The open / short detection circuit 50a shown in FIG. 3 includes a voltage dividing section between connection terminals comprising two capacitors C1 and C2 inserted in series between the power supply source connection electrode pads 10a and 10b, and a source electrode. Is the electrode pad 10a for the positive electrode
And the drain electrode is connected to the negative electrode pad 10b.
And a p-channel MOS transistor Q1 for detecting an open end, the gate electrode of which is connected to the connection point of the capacitors C1 and C2.

Open / short detection circuit 50a of this embodiment
The power supply source 6 is connected to the power supply source connection electrode pad 10.
a, 10b, and is constituted by an RC time constant circuit for detecting that the electrode pads 10a, 10b have become open ends. The output voltage Vdd of the power supply 6 is divided by the voltage dividing capacitor C1. Then, the divided voltage obtained at the connection point of the capacitors C1 and C2 is released.
It becomes the first output voltage Vin1 of the short-circuit detection circuit 50a. Further, the input voltage of the positive electrode pad 10a becomes the second output voltage Vin2 of the open / short detection circuit 50a.

Next, such an open / short detection circuit 50
The operation of a will be described. In a normal operation state, p-channel MOS transistor Q1 is biased by a divided voltage obtained at a connection point between capacitors C1 and C2, and is always on. Here, when the power supply source 6 is removed from the power supply source connection electrode pads 10a and 10b, the charges stored in the capacitors C1 and C2 are discharged through a path passing through the p-channel MOS transistor Q1 in the ON state. .

The resistance component R of the RC time constant of such a circuit
Is given by the on-resistance of p-channel MOS transistor Q1. The capacitance component C of the RC time constant is given by the capacitors C1 and C2. Therefore, when the power supply source 6 is removed from the power supply source connection electrode pads 10a, 10b, the first and second output voltages Vin1, Vin2 are obtained.
Gradually decreases according to the RC time constant.

When a short circuit occurs in the power supply source 6, the electric charge stored in the capacitors C1 and C2 is immediately discharged by the short circuit, so that the first and second output voltages Vin1 and Vin2 are reduced. Both drop immediately. The current ILK1 flowing through the open / short detection circuit 50a as described above is a subthreshold current flowing through the p-channel MOS transistor Q1, and this current value can be narrowed down to a smaller value by setting the threshold voltage of the transistor Q1. It is.

Open / short detection circuit 50a of this embodiment
In the above, the RC time constant determines the discharge time constant when the opening of the power supply source connection electrode pads 10a and 10b occurs. Therefore, in order to quickly operate the self-destruction function in response to the removal of the power supply source 6, the above R
It is necessary to make the C time constant as short as possible and quickly reduce the first and second output voltages Vin1 and Vin2.

On the other hand, in order to suppress the consumption of the battery capacity of the power supply source 6, it is necessary to reduce the subthreshold current ILK1 flowing through the p-channel MOS transistor Q1 as small as possible. Accordingly, the on-resistance R of the transistor Q1 increases. Therefore, it is desirable to set the capacitors C1 and C2 to a small capacitance in order to shorten the RC time constant.

Next, a reference voltage setting circuit 51 for generating a predetermined reference voltage Vref will be described. FIG. 4 is a circuit diagram showing one configuration example of the reference voltage setting circuit 51. The reference voltage setting circuit 51 according to the present embodiment includes capacitors C10, C
It is composed of a capacity division circuit composed of 11 capacitors. Power supply 6
The voltage Vdd from the destruction capacitor 3 connected in parallel with the voltage Vdd is divided by the capacitors C10 and C11. Then, the divided voltage obtained at the connection point between the capacitors C10 and C11 becomes the reference voltage Vref.

The charge amount Q stored in the reference voltage setting circuit 51 is given by the following equation. Q = Ctot × Vdd = C11 × Vref = C10 × (Vdd−Vref) (5) In Expression (5), Ctot is the total capacitance of the reference voltage setting circuit 51 and is given by the following expression. Ctot = C10 × C11 / (C10 + C11) (6)

Therefore, from the equations (5) and (6), the reference voltage Vre output from the connection point of the capacitors C10 and C11 is obtained.
f is as follows. Vref = (Ctot / C11) × Vdd = {C10 / (C10 + C11)} × Vdd (7) In the present embodiment, the reference voltage setting circuit 51 is configured by connecting the capacitors C10 and C11 in series. ,
There is no leak path in the current path. Therefore, the configuration is such that the limited power of the power supply source 6 is not consumed.

Next, the differential amplifier circuit block 52a, which may be called the heart of the voltage change detection circuit 5a, will be described. FIG. 5 is a circuit diagram showing one configuration example of the differential amplifier circuit block 52a. In the present embodiment, as the differential amplifier circuit block 52a, a two-stage modified current mirror type differential amplifier circuit using MOS transistors is used instead of the conventional one-stage configuration (see FIG. 15).

In the present embodiment, the first differential amplifier circuit 5
In the configuration of 4-1 usually two p-channel MOS
Where a transistor is used to form a current mirror type load,
A current mirror type load is formed by two n-channel MOS transistors Q22 and Q23, and a differential amplifier is formed by two p-channel MOS transistors Q20 and Q21 instead. Similarly, in the configuration of second differential amplifier circuit 54-2, two n-channel MOS transistors Q
27, Q28 constitute a current mirror type load, and instead use two p-channel MOS transistors Q25, Q26.
Constitute a differential amplifier.

As described above, by inverting the block configuration in the circuit of the conventional current mirror type sense amplifier,
The power consumption of each of the differential amplifier circuits 54-1 and 54-2 is reduced. As a result, the current consumption of the entire differential amplifier circuit block is reduced, and the power supply source 6 with a limited battery capacity operates for a long time. There is a possible circuit configuration.

Two p-channel MOS transistors Q2 forming a differential amplifier section of first differential amplifier circuit 54-1
The source electrodes 0 and Q21 are connected to the high potential side of the power supply 6 via the power supply connection electrode pad 10a for the positive electrode. First p-channel MOS transistor Q20
Is connected to the drain electrode of the first n-channel MOS transistor Q22 forming the current mirror type load, and the second p-channel MOS transistor Q22
The drain electrode 21 is connected to the drain electrode of the second n-channel MOS transistor Q23 forming the same load.

The source electrodes of the first and second n-channel MOS transistors Q22 and Q23 are connected to a third power control
Is connected to the drain electrode of the n-channel MOS transistor Q24. The source electrode of the third n-channel MOS transistor Q24 is connected to the lower potential side of the power supply 6 via the power supply connection electrode pad 10b for the negative electrode.

First p-channel MOS transistor Q2
The first output voltage Vin1 from the open / short detection circuit 50a is input to the zero gate electrode. On the other hand, the reference voltage Vref from the reference voltage setting circuit 51 is input to the gate electrode of the second p-channel MOS transistor Q21. Then, the second p-channel MOS transistor Q2
The voltage at the common drain electrode of the first and second n-channel MOS transistors Q23 is output as the internal detection signal Vout of the first differential amplifier circuit 54-1.

Two n-channel MOS transistors Q2
2 and Q23, the drain electrode of the transistor Q22 and the transistor Q2
The first and second gate electrodes are connected to form the first
The gate electrode of the second n-channel MOS transistor Q23 is biased such that a drain current equal to the drain current of the n-channel MOS transistor Q22 flows. Thus, the Vin1 side and the Vref side of the differential amplifier of the first differential amplifier circuit 54-1 are configured to receive the same current drive.

The potential of the internal detection signal Vout is changed by the first p-channel MOS transistor Q20 and the second p-channel MOS transistor Q21 constituting the differential amplifier.
And the ratio of the current flowing through As shown in FIG.
The second differential amplifier circuit 54-2 has the same configuration as the first differential amplifier circuit 54-1 except for a part.

That is, the source electrodes of the two p-channel MOS transistors Q25 and Q26 constituting the differential amplifier of the second differential amplifier circuit 54-2 are connected via the power supply source connection electrode pad 10a for the positive electrode. To the high potential side of the power supply 6. The drain electrode of the third p-channel MOS transistor Q25 is connected to the drain electrode of a fourth n-channel MOS transistor Q27 forming a current mirror type load, and the drain electrode of the fourth p-channel MOS transistor Q26 has the same load. The fifth that constitutes
Is connected to the drain electrode of the n-channel MOS transistor Q28.

The source electrodes of the fourth and fifth n-channel MOS transistors Q27 and Q28 are connected to the drains of the sixth n-channel MOS transistor Q29 for adjusting timing at the time of short-circuit between the power supply connection electrode pads 10a and 10b. Connected to electrodes. The source electrode of the sixth n-channel MOS transistor Q29 is connected to the low potential side of the power supply 6 via the power supply connection electrode pad 10b for the negative electrode, and the gate electrode is connected to the power supply for the positive electrode. The power supply source 6 is connected to the high potential side via the connection electrode pad 10a.

Third p-channel MOS transistor Q2
The second output voltage Vin2 from the open / short detection circuit 50a (= the high potential Vdd of the power supply source 6) is applied to the gate electrode of No. 5
Is entered. On the other hand, the gate electrode of the fourth p-channel MOS transistor Q26 is
The internal detection signal Vout from -1 is input.

Therefore, in this circuit configuration, the two p-channel MOS transistors Q25 and Q26 constituting the differential amplifier of the second differential amplifier circuit 54-2 are turned off by the high potential Vdd of the power supply source 6. Since it is in the (non-conducting) state, the resistance is sufficiently high, and the leak current ILK22 flowing through the differential amplifier circuit for power control as required by the first differential amplifier circuit 54-1 is narrowed down. N-channel MOS transistor Q29 for this purpose is not required. The n-channel MOS transistor Q29 includes a power supply source connection electrode pad 10a,
It is not required even when the space between 10b is open.

However, the power supply source connection electrode pad 10
When the short circuit between the terminals a and 10b is short-circuited, the second output voltage Vin2 from the open / short detection circuit 50a sharply drops. In this case, the internal detection from the first differential amplifier circuit 54-1 is performed. An n-channel MOS transistor Q29 is required in order to be able to time the change in the signal Vout.

Then, the fourth p-channel MOS transistor Q26 and the fifth n-channel MOS transistor Q2
8 has a common drain electrode voltage of 5
It is output as a detection signal Vout1 of 2a. Next, the operation of the differential amplifier circuit block 52a will be described. First, in the normal operation state, the first output voltage Vin1 from the open / short detection circuit 50a and the reference voltage Vref from the reference voltage setting circuit 51 are set to be equal in each circuit.

At this time, the differential amplifier circuit block 52a
Outputs an "L" level detection signal Vout1. On the other hand, when the first output voltage Vin1 of the open / short detection circuit 50a becomes lower than the reference voltage Vref of the reference voltage setting circuit 51 due to the removal or short circuit of the power supply source 6, the differential amplifier circuit block 52a becomes "H". Level detection signal bar V
Output out1. Here, the “H” level means a level that is equal to or higher than a threshold voltage of a digital output buffer circuit block 53a described later.

The differential amplifier circuit block 52a as described above
In the first differential amplifier circuit 54-1 of the first embodiment, the third p-channel MOS transistor Q24 connected in series to the commonly connected source electrode side of the current mirror type load is the same as that shown in FIG.
Is used for power down control of the whole modified current mirror type differential amplifier circuit.

Therefore, the differential amplifier circuit block 52a
Is the subthreshold current flowing through the third p-channel MOS transistor Q24. This subthreshold current can be narrowed down by setting the threshold voltage of p-channel MOS transistor Q24. As a result, the differential amplifier circuit block 52 is provided by the power supply source 6 having a limited battery capacity.
a can be driven for a long time.

Next, the detection signal Vout1 output from the differential amplifier circuit block 52a is changed to Vss (0) or Vd
The digital output buffer circuit block 53a that converts a binary voltage d will be described. FIG. 6 is a circuit diagram showing one configuration example of the digital output buffer circuit block 53a. In the present embodiment, a two-stage CMOS inverter 55-
1, 55-2 is used.

As shown in FIG. 6, a first CMOS inverter 55-1 uses a first n-channel MOS transistor Q30 as a driving element, a first p-channel MOS transistor Q31 as a load element, and transistors Q30 and Q31.
Are commonly connected to form an input terminal, and the drain electrodes are commonly connected to form an output terminal. That is, the first n-channel MOS transistor Q30 and the first
Power supply source 6 through power supply connection electrode pads 10a and 10b.
Are connected in series between the high potential Vdd and the low potential Vss.

Similarly, the second CMOS inverter 55-
Reference numeral 2 designates a second n-channel MOS transistor Q32 as a driving element, a second p-channel MOS transistor Q33 as a load element, and gate electrodes of the transistors Q32 and Q33 commonly connected as input terminals, and a drain electrode commonly connected. Output terminal.

The substrate electrodes of the first and second n-channel MOS transistors Q30 and Q32 are normally connected (grounded) to the low potential Vss, and the first and second p-channel MOS transistors Q30 and Q32 are connected to each other.
The substrate electrodes of the transistors Q31 and Q33 are connected to the high potential Vdd.
It is connected to the. The detection signal Vout1 output from the differential amplifier circuit block 52a is applied to the commonly connected gate electrodes of the transistors Q30 and Q31 forming the first CMOS inverter 55-1, and a signal Vout1 complementary to the detection signal is output. , From the commonly connected drain electrodes of the transistors Q30 and Q31.

Subsequently, the signal Vout1 is supplied to the second CMO
Transistor Q32 forming S inverter 55-2,
A signal Vout2 applied to the commonly connected gate electrode of Q33 and having the same phase as the detection signal is applied to transistors Q32 and Q32.
It is taken out from 33 commonly connected drain electrodes.

When the detection signal Vout1 is at "L" level, in the first CMOS inverter 55-1 the n-channel MOS transistor Q30 is turned off (non-conductive),
P-channel MOS transistor Q31 is turned on (conducting), and output signal Vout1 attains "H" level. As a result, in the second CMOS inverter 55-2, the n-channel MOS transistor Q32 is turned on, the p-channel MOS transistor Q33 is turned off, and the output signal Vout2 goes to "L" level.

Conversely, when the detection signal Vout1 is at the "H" level, in the first CMOS inverter 55-1, the n-channel MOS transistor Q30 is turned on, the p-channel MOS transistor Q31 is turned off, and the output signal Vout1 becomes “L” level. Thereby, the second C
In MOS inverter 55-2, n-channel MOS transistor Q32 is turned off, p-channel MOS transistor Q33 is turned on, and output signal Vout2 attains "H" level.

As described above, the differential amplifier circuit block 52a
Transistor Q3 according to the detection signal Vout1 from the
0 or Q31 becomes conductive, the other becomes non-conductive,
Further, one of the transistors Q32 and Q33 becomes conductive and the other becomes non-conductive, so that the high potential Vdd is changed to the low potential Vdd.
Current leak I through CMOS inverter towards ss
LK31 and ILK32 are few in principle. However, actual CM
In the OS inverter, even if one of the MOS transistors is turned off, there is a sub-threshold current leaking through the channel portion, and this current becomes a leak current ILK3 through the entire CMOS inverter. Regarding this subthreshold current, transistors Q30, Q3
It is possible to reduce the threshold voltages of Q1, Q32 and Q33 by setting them higher.

Next, using the parameters of the standard cell structure of the 0.5 μm rule operating at the power supply voltage of 3 V, the voltage change detection circuit 5a (30 transistor scale circuit) of the self-destructive semiconductor device shown in FIG. An example of numerical values when configured is shown.
FIG. 7 is a diagram showing a circuit operation simulation result of the voltage change detection circuit 5a of the self-destruction type semiconductor device of FIG. 1. FIG. 7A shows power supply source connection electrode pads 10a and 10a.
In the case where the space between b is open, (b) shows the electrode pads 10a and 10b.
The case where the short circuit occurs is shown.

The normal operating current of the entire circuit is 27.1.
nA, of which the open / short detection circuit 5
0a, about 7.7 nA, 18.7 nA in the first-stage modified current mirror type differential amplifier circuit 54-1 and 5.43 p in the second-stage modified current mirror type differential amplifier circuit 54-2.
A, First CMO of digital output buffer circuit block
The output is 680 pA for the S inverter 55-1 and 8.5 pA for the second CMOS inverter 55-2.

As described above, in the voltage change detection circuit 5a of the present self-destruction type semiconductor device, the largest operation current is required because the first stage differential amplifier circuit of the differential amplifier circuit block 52a. 54-1, and the leak current ILK2 (≒ ILK21) of the entire differential amplifier circuit block is a subthreshold current flowing through the third n-channel MOS transistor Q24 for power control. Therefore, by setting the threshold voltage of the third n-channel MOS transistor Q24 higher, it is possible to narrow down the operating current of the entire voltage change detection circuit 5a.

In the circuit simulation shown in FIG. 7, at time t = 0, the power supply source connection electrode pads 10a,
The first and second output voltages Vin1, Vin from the open / short detection circuit 50a after the open / short circuit between 10b
2. The reference voltage Vref by the reference voltage setting circuit 51, the detection signal Vout1 of the differential amplifier circuit block 52a, and the first differential amplifier circuit 54- in the differential amplifier circuit block 52a.
1 internal output signal Vout, the first CMOS inverter 55 forming the digital output buffer circuit block 53a.
-1 output voltage Vout1 and the second CMOS inverter 5
The change of the output voltage bar Vout2 with respect to each response time of 5-2 is shown.

As shown in FIG. 7, the detection signal Vout1 of the differential amplifier circuit block 52a and the output voltage bar Vout2 of the digital output buffer circuit block 53a change in phase with each other, and the output voltage of the output buffer circuit block 53a. Has a sharper output waveform.

According to the numerical example shown in FIG.
= 0, the power supply source connection electrode pads 10a, 10
It can be confirmed that when the interval between the terminals b is opened, the voltage change detection circuit 5a as a whole can output the detection signal Vout1 of 0-3 V after 90 μs.

Power supply source connection electrode pads 10a, 10
When b is opened, in the open / short detection circuit 50a, charges are extracted from the minute capacitors C1 and C2, and the output voltages Vin1 and Vin2 decrease gradually. On the other hand, the reference voltage Vref of the reference voltage setting circuit 51 held at the voltage Vdd by the charge supply from the destruction capacitor 3 remains unchanged. The potential difference between the second output voltage Vin2 of the open / short detection circuit 50a and the internal detection signal Vout from the first differential amplifier circuit 54-1 is detected by the second differential amplifier circuit 54-2, and a digital output buffer is provided. Circuit block 53
From (a), a digital detection signal of 0-Vdd is output.

On the other hand, in the numerical example shown in FIG. 7B, the short-circuit state between the power supply source connection electrode pads 10a and 10b is simulated by assuming that the resistance value between the electrode pads 10a and 10b is 10Ω. I have. When the power supply connection electrode pads 10a and 10b are short-circuited at time t = 0, the voltage Vdd on the left side of the protection transistor Q50 and the output voltages Vin1 and Vin2 of the open / short detection circuit 50a are all Vss (=
0V), and at the same time, the extraction of the charge from the destruction capacitor 3 occurs.

However, the extraction of the electric charge is interrupted by the protection transistor Q50, and the differential amplifier circuit block 52a driven by the remaining power of the destruction capacitor 3 operates, and the digital output buffer circuit block 53a outputs 0 from the digital output buffer circuit block 53a. A digital detection signal of -Vdd is output. As described above, the protection transistor Q50 effectively prevents a rapid voltage drop when the power supply source connection electrode pads 10a and 10b are short-circuited, and the transistor Q50
In the circuit block on the right side of 50, the destruction capacitor 3
, The high voltage Vdd before the short circuit is held.

As shown in this numerical example, the voltage change detection circuit 5a of the present invention outputs a digital detection signal having an amplitude of 0-3V 3 ns after the short circuit between the electrode pads 10a and 10b. The CMOS selector is switched in response to the output signal Vout1 and the bar Vout2 from the digital output buffer circuit block 53a, and the destruction capacitor 3 is cut off from the power supply source connection electrode pads 10a and 10b.
The connection to the destruction circuit 2 is switched.

Next, the control circuit to the element 4 will be described. FIG. 8 is a circuit diagram showing one configuration example of the control circuit or the element 4. In the present embodiment, a CMOS selector circuit combining two CMOS transmission gates is used as the control circuit or element 4.

The characteristics required for the control circuit to the element 4 are as follows. During normal operation, the power supply 6
Is applied to the destruction capacitor 3 via the control circuit or the element 4, and the destruction charge is accumulated in the destruction capacitor 3. At this time, the space between the destruction capacitor 3 and the destruction circuit 2 is in a non-conductive state.

On the other hand, when a voltage difference generated between the open / short detection circuit 50a and the reference voltage setting circuit 51 is detected by the differential amplifier circuit block 52a, the "H" level detection signal Vout1 becomes digital. The output buffer circuit block 53a converts the output signal Vout1 to an "L" level and an output signal Vout2 to an "H" level. In response to this, the control circuit or element 4 cuts off the path between the power supply source 6 and the destruction capacitor 3, and makes the path between the destruction capacitor 3 and the destruction circuit 2 conductive instead.

The transmission gate TG1 is shown in FIG.
As shown in the figure, the source electrode is commonly connected and the drain electrode is commonly connected, and is configured by a pair of a p-channel MOS transistor Q40 and an n-channel MOS transistor Q41. p channel MOS transistor Q4
The substrate electrode of 0 is connected to the drain electrode, and the substrate electrode of the n-channel MOS transistor Q41 is connected to the low potential side of the power supply 6 via the power supply connection electrode pad 10b for the negative electrode.

The detection signal bar Vout1 of the differential amplifier circuit block 52a is converted into an output signal Vout1 by the digital output buffer circuit 53 and applied to the gate electrode of the n-channel MOS transistor Q41. One output signal Vout2 is applied to the gate electrode of p-channel MOS transistor Q40. When the detection signal Vout1 is at the “L” level (the signal Vout1 is at the “H” level), the transistor Q
Both 40 and Q41 are turned on (conductive state), and the input (drain electrode) and the output (source electrode) are connected.

On the other hand, when the detection signal Vout1 is at the "H" level (the signal Vout1 is at the "L" level), the transistor Q
Both 40 and Q41 are turned off (non-conducting state), the output is disconnected from the input, and the previous output potential is held by the parasitic capacitance. Such CMOS transmission gates are symmetric with respect to input and output, and signal propagation is bidirectional.

Therefore, as shown in FIG. 8, the first transmission gate TG1 and the drain electrode of the second transmission gate TG2 having the same configuration as this TG1 are connected to each other, and the detection signal Vout2 is connected to the first transmission gate TG1. P-channel MOS transistor Q40 and second transmission gate T forming TG1
The complementary signal Vout1 is applied to the gate electrode of the n-channel MOS transistor Q43 forming the G2 and the p-channel MOS transistor forming the n-channel MOS transistor Q41 and the second transmission gate TG2 forming the first transmission gate TG1. When the voltage is applied to the gate electrode of Q42, it is possible to function as a selector switch of one input and two outputs having a connection point between the first and second transmission gates TG1 and TG2 as input, that is, a selector.

In the present embodiment, a control circuit or an element 4 having a required function is constructed by utilizing such properties of a CMOS selector circuit composed of two CMOS transmission gates. Note that the destruction capacitor 3 includes transmission gates TG1, TG
2 (drain electrode) and a power supply connection electrode pad 10a (more precisely, transistor Q50).
Of the transmission gate TG1) is connected to the first output (the source electrode of the transmission gate TG1).
(The source electrode of the transmission gate TG2).

Next, the destruction circuit 2 for erasing secret information stored in the data memory will be described. FIG. 9 is a circuit diagram showing one configuration example of the destruction circuit 2. In the present embodiment, a voltage booster circuit is used as the destruction circuit 2.

Generally, a nonvolatile memory constituting a data memory is an EEP having a floating gate element as a basic device.
ROM (Electrically Erasable and Programmable ROM)
) And flash memory. In these nonvolatile memories, a write voltage or an erase voltage Vpp higher than the power supply voltage Vdd is usually required when writing cell information to a storage cell or erasing cell information stored in the storage cell.

As described above, in the case of the non-volatile memory of the program system using hot electron injection for writing, a large current is required, so that the high voltage Vpp must be supplied from the outside. In other words, in this case, the power supply connected to the external connection electrode pad 7 causes the
Erasure has been performed.

On the other hand, F using Fowler-Nordheim tunnel current for writing / erasing is used.
In the case of the N-type non-volatile memory, the current value may be small, so that it can be covered by the boosted voltage generated by charge pumping on the chip. Therefore, the destruction circuit 2 for erasing the secret important information stored in the non-volatile memory can be configured by a voltage boosting circuit as shown in FIG. 9 which boosts the output voltage Vdd of the power supply source 6 to the high voltage Vpp. Becomes

In the destruction circuit 2 of the present embodiment, the gate electrode is connected to the drain electrode, and the substrate electrode is connected to the low voltage side of the power supply 6 via the power supply connection electrode pad 10b. N-channel MOS transistor Q
A boosting block including 3-k (k = 1, 2,..., N) and a boosting capacitor C4-k having one end connected to the source electrode of the transistor Q3-k is connected to the source electrode and the next stage. By connecting to the drain electrode of the transistor,
They are connected in n stages in series.

Further, the drain electrode of an n-channel MOS transistor Q4 is connected to the source electrode of the last transistor Q3-n, and the gate electrode of this transistor Q4 is connected to the drain electrode. One end of an output capacitor C5 is connected to the source electrode of the n-channel MOS transistor Q4, and the other end of the output capacitor C5 is connected to the low voltage side of the power supply source 6.

Further, p-channel MOS transistor Q
5 and an n-channel MOS transistor Q6.
Is connected in series with a second CMOS inverter including a p-channel MOS transistor Q7 and an n-channel MOS transistor Q8, thereby forming an output stage of the oscillator.

A clock signal CLK is input to an input terminal of the first CMOS inverter. This first CMOS
The clock signal bar φ, which is the output signal of the inverter, is input to the input terminal of the second CMOS inverter and the capacitor C4 of an even-numbered stage among the capacitors C4-k.
−i (i = 2, 4,...). The clock signal φ as the output signal of the second CMOS inverter is applied to the other end of the odd-numbered stage capacitors C4-j (j = 1, 3,...) Of the capacitors C4-k.

In the destruction circuit 2 configured as described above, when the voltage Vdd from the destruction capacitor 3 is supplied to the first transistor Q3-1, the output voltage Vpp output from the source electrode of the second transistor Q4 becomes , The level of the power supply voltage Vdd. In this state, when the clock signal CLK is input to the first CMOS inverter, the second C
First of clock signal φ output from MOS inverter
Since the drain / source terminal of the capacitor C4-1 is raised from Vss to Vdd by a pulse, the drain voltage and the gate voltage of the transistor Q3-2 are raised based on the coupling ratio between the capacitor C4-1 and the transistor Q3-2. And the potential is the output voltage Vpp
Is output from the output terminal Tout.

Then, when the clock signal φ and the bar φ are inverted according to the clock signal CLK, the same operation as described above is performed between the capacitor C4-2 and the transistor Q3-3, and the output voltage Vpp is further increased. Can be When the inversion operation of the clock signal φ and the bar φ corresponding to the clock signal CLK is repeated, the level of the output voltage Vpp rises stepwise.

As described above, the charge from the destruction capacitor 3 is transferred to the next stage every half cycle of the clock signal CLK to charge the output capacitor C5 to the level of the high voltage Vpp. High voltage Vpp can be obtained. By applying this high voltage Vpp as an erasing voltage to the control gate electrode corresponding to the memory block storing the secret information of the data memory, the entire memory block is erased and the required memory erasing function can be realized. It becomes possible.

In the present embodiment, the Fowler-Nordheim tunnel current flows from the low voltage of at most about 3.6 V supplied from the power supply source 6 to the tunnel oxide film of the floating gate element constituting the memory cell. Dozens of V required for
In order to boost the voltage to a high voltage, transistors having threshold voltages near 0 V are used as transistors Q3-k and Q4 constituting each stage of the charge pump.

The reason is to suppress the voltage drop due to the back gate effect. In order to reduce power consumption, the boosting clock signal CLK is made as slow as possible, and the power consumption at the time of writing is reduced to about 1 mA when Vdd = 3 V.
To less than about. By using the voltage boosting circuit configured as described above as the destruction circuit 2, the charge stored in the destruction capacitor 3 connected in parallel to the power supply source 6 having a limited battery capacity allows the secret information in the data memory to be stored. Can be erased.

Next, a self-destruction mechanism of the self-destruction type semiconductor device of the present embodiment will be described. A third party aiming at falsification of the IC chip 12b first removes the IC module from the plastic case, and then removes the mold resin using a chemical. And IC chip 1
The rear surface or the element surface of 2b is to be observed, but when the power supply source 6 is mounted on the back surface or the element surface of the IC chip 12b, it cannot be observed unless the power supply source 6 is removed.

Here, when the power supply source 6 is detached from the power supply source connection electrode pads 10a and 10b, as described above, the capacitor C in the open / short detection circuit 50a is removed.
1 and C2 are discharged through a path passing through the p-channel MOS transistor Q1, and both the first and second output voltages Vin1 and Vin2 of the open / short detection circuit 50a decrease.

On the other hand, the reference voltage Vref generated by dividing the voltage charged in the large-capacity destruction capacitor 3 by the reference voltage setting circuit 51 is opened between the power supply source connection electrode pads 10a and 10b. However, it does not drop immediately. Therefore, a potential difference occurs between the output voltages Vin1 and Vin2 of the open / short detection circuit 50a and the reference voltage Vref of the reference voltage setting circuit 51. The modified current mirror type differential amplifier circuit block 52a accurately detects this potential difference and outputs an "H" level detection signal Vout1.

The control circuit or element 4 connects the power supply source 6 and the destruction capacitor 3 during the normal operation in which the "L" level detection signal Vout1 is output. Here, when the "H" level detection signal Vout1 is output from the differential amplifier circuit block 52a, the control circuit or the element 4
Cuts off the connection between the power supply source 6 and the destruction capacitor 3, and connects the destruction capacitor 3 and the destruction circuit 2. Thus, the destruction circuit 2 starts operating, and the semiconductor integrated circuit 1
The secret important information stored in the data memory inside is erased.

On the other hand, when the power supply source 6 is short-circuited by the attacker piercing the power supply source 6 with a needle or the like, the electric charges stored in the capacitors C1 and C2 in the open / short detection circuit 50a become short-circuited. And the first and second output voltages Vin1 and Vin2 of the open / short detection circuit 50a.
Drops immediately.

Here, the power supply source connection electrode pad 10
a to reference voltage setting circuit 51, differential amplifier circuit block 5
2a, an n-channel MOS transistor Q50 for protection at the time of short-circuiting of a power supply source is inserted in series in a power supply line leading to the control circuit or element 4, the destruction capacitor 3, and the destruction circuit 2, and a gate electrode of the transistor Q50 is Open
The first output voltage Vin1 of the short circuit detection circuit 50a is input. Therefore, during normal operation, n-channel MOS transistor Q50 is on.

On the other hand, when the output voltage Vin1 of the open / short detection circuit 50a decreases due to the short circuit of the power supply source 6, the transistor Q50 shifts to the off state. Thereby, it is possible to prevent the electric charge stored in the destruction capacitor 3 from being discharged due to the short circuit of the power supply source 6. And finally, by the same operation as when opening,
The control circuit or element 4 cuts off the connection between the power supply source 6 and the destruction capacitor 3, and the destruction circuit 2 erases the secret important information stored in the data memory in the semiconductor integrated circuit 1.

In the present embodiment, the IC chip 12
Although the mounting method of b and the power supply source 6 is not described, the mounting method shown in FIGS. 13 and 14 may be used, or another mounting method may be used.

[0129]

According to the present invention, a power supply source is provided by differentially inputting a detection voltage from an open / short detection circuit and a reference voltage setting circuit in a voltage change detection circuit by a two-stage differential amplifier circuit. , It is possible to detect the voltage change between the connection terminals due to the short circuit and the open circuit with high sensitivity and at a high speed, and particularly to quickly detect the voltage change when the connection terminals are opened. Open / short detection circuit in voltage change detection circuit,
The reference voltage setting circuit and the differential amplifier circuit block are constituted by MOS transistor circuits, and the control circuit or element is formed by CMOS.
By using a selector circuit, the operating current can be suppressed. Further, by providing the open / short detection circuit, not only the removal of the power supply source but also the short circuit of the power supply source can be detected. As a result, during the operation guarantee period of the semiconductor integrated circuit, the physical attack is constantly monitored, and when the power supply source is removed or short-circuited, this is immediately detected and the memory information of the semiconductor integrated circuit is stored. Since it can be destroyed, it is possible to reliably prevent the contents of the memory of the semiconductor integrated circuit from being falsified or forged.

Further, the first differential amplifier circuit of the differential amplifier circuit block includes a first differential amplifier section comprising first and second p-channel MOS transistors, and first and second n-channel MOS transistors. A first current mirror type load including transistors and a third n-channel MOS transistor, and a second differential amplifier circuit of the differential amplifier circuit block,
A second differential amplifying section including third and fourth p-channel MOS transistors, a second current mirror type load including fourth and fifth n-channel MOS transistors, and a sixth
, It is possible to realize a modified current mirror type differential amplifier circuit with high detection accuracy and suppress the operating current.

Further, the open / short detection circuit includes first and second circuits.
And a p-channel MOS transistor.
Removal of the power supply source (opening of the connection terminal) and short circuit can be reliably detected, and the operating current can be suppressed.

Further, the control circuit or element is formed by a p-channel M
By using a CMOS selector circuit in which two transmission gates each composed of a pair of an OS transistor and an n-channel MOS transistor are connected in series, leakage current can be suppressed. Further, by forming the digital output buffer circuit block with two-stage CMOS inverters, a blunt binary digital detection signal capable of reliably operating a control circuit or element formed by a CMOS selector circuit is output. can do.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram of a self-destructive semiconductor device according to an embodiment of the present invention.

FIG. 2 is a circuit block diagram showing one specific configuration example of the self-destructive semiconductor device of FIG. 1;

FIG. 3 is a circuit diagram showing one configuration example of an open / short detection circuit according to the embodiment of the present invention.

FIG. 4 is a circuit diagram showing one configuration example of a reference voltage setting circuit according to the embodiment of the present invention.

FIG. 5 is a circuit diagram showing one configuration example of a differential amplifier circuit block according to the embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration example of a digital output buffer circuit block according to the embodiment of the present invention.

FIG. 7 is a diagram illustrating a circuit operation simulation result of the voltage change detection circuit according to the embodiment of the present invention.

FIG. 8 is a circuit diagram illustrating a configuration example of a control circuit or element according to an embodiment of the present invention.

FIG. 9 is a circuit diagram showing one configuration example of a destruction circuit according to an embodiment of the present invention.

FIG. 10 is an explanatory diagram showing a configuration example of a general IC card.

FIG. 11 is a circuit block diagram of a conventional self-destructive semiconductor device.

FIG. 12 is a circuit block diagram showing one specific configuration example of the self-destructive semiconductor device of FIG. 11;

13A and 13B are a plan view and a cross-sectional view illustrating an example of an arrangement configuration of the self-destructive semiconductor device in FIG.

14 is a diagram showing a state of flip-chip mounting in the self-destructive semiconductor device of FIG.

FIG. 15 is a circuit diagram showing one configuration example of the differential amplifier circuit of FIG. 11;

FIG. 16 is a circuit diagram showing one configuration example of the open / short detection circuit of FIG. 11;

FIG. 17 is a circuit diagram showing one configuration example of the digital output buffer circuit of FIG. 11;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit, 2 ... Breakdown circuit, 3 ... Breakdown capacitor, 4 ... Control circuit or element, 5a ... Voltage change detection circuit, 6 ... Power supply source, 7 ... External connection electrode pad, 9b
... Semiconductor substrate, 10a, 10b ... Electrode pad for connecting power supply source, 12b ... IC chip, 50a ... Open / short detection circuit, 51 ... Reference voltage setting circuit, 52a ... Differential amplifier circuit block, 53a ... Digital output buffer circuit Blocks, 54-1, 54-2 ... differential amplifier circuits, 55-1, 5
5-2... CMOS inverter, Q1, Q5, Q7, Q2
0, Q21, Q25, Q26, Q31, Q33, Q4
0, Q42... P-channel MOS transistor, Q3-
k, Q4, Q6, Q8, Q22, Q23, Q24, Q2
7, Q28, Q29, Q30, Q32, Q41, Q4
3, Q50... N-channel MOS transistor, C1, C
2, C4-k, C5, C10, C11 ... capacitors.

Claims (5)

[Claims] A semiconductor memory device; a central processing unit for processing data stored in the memory device; a destruction circuit for self-destruction by erasing at least a part of memory information of the semiconductor memory device; At least one or more destruction capacitors for storing charge for self-destruction by the destruction circuit, connection terminals provided for a positive electrode and a negative electrode of a power supply source for storing charge in the destruction capacitor, A voltage change detection circuit that monitors the voltage between the connection terminals for the positive electrode and the negative electrode and outputs a detection signal according to the voltage drop, and connects a power supply source and a destruction capacitor via the connection terminal during normal operation. When a detection signal is output from the voltage change detection circuit, the connection is cut off, and the control circuit or element for connecting the destruction capacitor and the destruction circuit is connected to the same semiconductor. A self-destructive semiconductor device having a power supply connected to the connection terminal and on a body substrate, wherein the voltage change detection circuit detects an open / short detection of the power supply. A reference voltage setting circuit for generating a predetermined reference voltage; and a first and second two-stage differential amplifier circuit.
A differential amplifier circuit block that compares the output voltage of the short-circuit detection circuit with the reference voltage of the reference voltage setting circuit, and outputs the detection signal when detecting a drop in the output voltage of the open / short-circuit detection circuit. A self-destructive semiconductor device comprising a MOS transistor circuit, wherein the control circuit or element comprises a CMOS selector circuit. 2. The self-destructive semiconductor device according to claim 1, wherein said first differential amplifier circuit of said differential amplifier circuit block comprises first and second p-channel MOS transistors.
A first current mirror-type load connected to the first differential amplifier, the first current-mirror load including first and second n-channel MOS transistors; and a first current-mirror load. A third n-channel MOS transistor for power control connected thereto, and the second differential amplifier circuit of the differential amplifier circuit block comprises a second and a fourth p-channel MOS transistor.
A second current mirror-type load composed of fourth and fifth n-channel MOS transistors connected to the second differential amplifier, and a second current mirror-type load. A sixth n-channel MOS transistor for adjusting timing when the connection terminals are short-circuited, wherein the source electrodes of first and second p-channel MOS transistors are connected to the power supply source via the connection terminal. , The drain electrodes of the first and second p-channel MOS transistors are respectively connected to the drain electrodes of the first and second n-channel MOS transistors, and the gate of the first p-channel MOS transistor is connected to The first output voltage of the open / short detection circuit is input to the electrode, and the gate electrode of the second p-channel MOS transistor is connected to the gate electrode of the second p-channel MOS transistor. The reference voltage is input, the source electrodes of the first and second n-channel MOS transistors are connected to the drain electrode and the gate electrode of the third n-channel MOS transistor, and the source electrode of the third n-channel MOS transistor is The third and fourth p-channel MOS transistors are connected to the high potential side of the power supply via the connection terminal, and are connected to the low potential side of the power supply via the connection terminal; The drain electrodes of the third and fourth p-channel MOS transistors are respectively connected to the drain electrodes of the fourth and fifth n-channel MOS transistors, and the gate electrode of the third p-channel MOS transistor is connected to the open / short detection circuit. The second output voltage is input, and the second p-channel MOS transistor is connected to the gate electrode of the fourth p-channel MOS transistor. The source and the voltage of the common drain electrode of the second n-channel MOS transistor are input, and the source electrodes of the fourth and fifth n-channel MOS transistors are connected to the drain electrode of the sixth n-channel MOS transistor. The gate electrode of the n-channel MOS transistor is connected to the high potential side of the power supply through the connection terminal, and the source electrode of the sixth n-channel MOS transistor is connected to the low potential of the power supply through the connection terminal. A self-destructive semiconductor device which is connected to a potential side and outputs a voltage of a common drain electrode of a fourth p-channel MOS transistor and a fifth n-channel MOS transistor as the detection signal. 3. The self-destructive semiconductor device according to claim 1, wherein the open / short detection circuit includes first and second capacitors connected in series between the positive and negative connection terminals. An inter-voltage divider, a source electrode connected to the high potential side of the power supply via the connection terminal, a drain electrode connected to the low potential side of the power supply via the connection terminal, and a gate An electrode comprising a p-channel MOS transistor connected to a connection point between the first and second capacitors; a divided voltage obtained at a connection point between the first and second capacitors is used as a first output voltage; A voltage obtained at a connection point between the capacitor and the high potential side of the power supply source is output as a second output voltage. 4. The self-destructive semiconductor device according to claim 1, comprising a first and a second two-stage CMOS inverter, a signal complementary to a detection signal of said differential amplifier circuit block and in-phase with said detection signal. A digital output buffer circuit block that generates a signal of (i), wherein the control circuit or element includes a transmission gate composed of a pair of a p-channel MOS transistor and an n-channel MOS transistor having a source electrode and a drain electrode connected in common. CMO with two connected in series
In each transmission gate, a substrate electrode of a p-channel MOS transistor is connected to a drain electrode, and a substrate electrode of an n-channel MOS transistor is connected to a low potential side of a power supply via the connection terminal. An n-channel MOS transistor in a first transmission gate and a p-channel MOS transistor in a second transmission gate
The detection signal is input to each gate electrode of the S transistor, and the p-channel M in the first transmission gate
A signal complementary to the detection signal is input to each gate electrode of the OS transistor and the n-channel MOS transistor in the second transmission gate, and a commonly connected drain electrode of each transistor is connected to the destruction capacitor. The common connection source electrode of each transistor in the transmission gate is connected to the connection terminal on the high potential side, and the common connection source electrode of each transistor in the second transmission gate is connected to the destruction circuit. A self-destructive semiconductor device, comprising: 5. The self-destructive semiconductor device according to claim 4, wherein said digital output buffer circuit block is configured by stacking two CMOS inverters each including an n-channel MOS transistor and a p-channel MOS transistor. The gate electrodes of the first n-channel MOS transistor and the first p-channel MOS transistor are connected to each other, the drain electrodes are connected to each other, and the source electrode and the substrate electrode of the first p-channel MOS transistor connect to the connection terminal. Connected to the high potential side of the power supply via
The source electrode and the substrate electrode of the n-channel MOS transistor are connected to the lower potential side of the power supply via the connection terminal, and the gates of the first n-channel MOS transistor and the first p-channel MOS transistor are connected in common. A detection signal of the differential amplifier circuit block is input to an electrode, and a signal complementary to the detection signal is output from a commonly connected drain electrode of the first n-channel MOS transistor and the first p-channel MOS transistor; The gate electrodes of the n-channel MOS transistor and the second p-channel MOS transistor are connected to each other, the drain electrodes are connected to each other, and the source electrode and the substrate electrode of the second p-channel MOS transistor are connected via the connection terminal. Connected to the high potential side of the power supply
The source electrode and the substrate electrode of the n-channel MOS transistor are connected to the low potential side of the power supply via the connection terminal, and the commonly connected gates of the second n-channel MOS transistor and the second p-channel MOS transistor A signal complementary to the detection signal is input to the electrode, and a second n
Channel MOS transistor and second p-channel MOS
A self-destructive semiconductor device, wherein a signal having the same phase as the detection signal is output from a commonly connected drain electrode of transistors.