JP2001251186A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To guarantee that a PLL is locked in a prescribed frequency range in the fluctuation range of a circuit operation condition and a manufacture condition and to shorten the locking time. SOLUTION: The PLL circuit is provided with a sampling circuit 3 supplying ground GND to a VCO 13A in an oscillation frequency band A which is selected at first, causing it to self-travel and oscillate, and generating a sampling value CO counted by sampling the VCO output signal VO for prescribed time, a comparison circuit 4 comparing the sampling value CO with an expectation value EX and outputting a switch signal SV which changes over a control voltage signal SC from ground potential GND to a control voltage signal VC in accordance with the compared result or a shift signal SS controlling the selection of the oscillation frequency, a frequency selection circuit 2 generating a selection signal S for setting a constant current circuit 131 to a oscillation frequency band B next to the oscillation frequency band A and a switch circuit 15 which changes over ground potential GND to the control voltage signal VC in response to the supply of the switch signal SV.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit,
In particular, a PL having a VCO circuit having a plurality of oscillation frequency bands
It relates to an L circuit.

[0002]

2. Description of the Related Art A first conventional PLL generally used.
Referring to FIG. 7 showing an example of the circuit, the first conventional PLL circuit compares the phase of the reference clock CKR with the frequency-divided signal DS, and corresponds to the phase difference between the reference clock CKR and the frequency-divided signal DS. A phase comparison circuit 11 that outputs a phase difference signal PD that is a DC signal, a low-pass filter (LPF) 12 that removes unnecessary high-frequency components of the phase difference signal PD and outputs a control voltage signal VC, and a voltage of the control voltage signal VC A voltage-controlled oscillation circuit (VCO) 13 whose frequency is controlled by the value to output an output signal VO;
(N is an integer) and outputs a frequency-divided signal DS having a frequency substantially equal to the reference clock signal CKR.

The frequency of the output signal VO of the VCO 3 is controlled by the voltage value of the control voltage signal VC. The relationship between the control voltage signal VC and the frequency f of the output signal VO depends on the circuit operation such as power supply voltage and ambient temperature. Variation in conditions and VC
It changes due to fluctuations in manufacturing conditions such as the process in the O manufacturing process.

Under standard circuit operating conditions and manufacturing conditions, when the control voltage signal VC is 1 V, the frequency f = 100 M
Hz, for example, the control voltage signal VC corresponding to the frequency f = 100 MHz becomes 0.5
It fluctuates in the range of ~ 1.5V. Also, it varies similarly due to the variation of the circuit operating conditions.

In order to guarantee that the PLL locks in a predetermined reference clock frequency range even in such a predetermined fluctuation range of the circuit operating conditions and the manufacturing conditions, the frequency range of the VCO is designed to be wide.

For this reason, the variable range of the constant control voltage signal VC determined by circuit conditions such as the power supply voltage, for example, the variable range of the frequency f of the output signal VO with respect to 3 V naturally increases, that is, the control voltage signal VC The slope of the graph of the frequency f (hereinafter, frequency control voltage gain) becomes steep. In other words, the frequency control voltage gain increases (increases).
As a result, the fluctuation of the frequency f of the output signal VO becomes large even for a slight fluctuation of the control voltage signal VC, which has a bad influence on characteristics such as jitter.

In order to solve the above problem, Japanese Patent Laid-Open Publication No. 7-30
The conventional second PLL circuit described in Japanese Patent No. 3041 (Document 1) divides the entire oscillation frequency range of a VCO into a plurality of oscillation frequency bands (oscillation frequency ranges) having a small (low) frequency control voltage gain and a predetermined period. Otherwise, the oscillation frequency band is sequentially shifted to lock the PLL circuit, thereby improving the jitter characteristics by using the advantage of the low frequency control voltage gain.

FIG. 8 is a block diagram of a conventional second PLL circuit which is simplified for the purpose of describing the present invention described later, and in which the same components as those of FIG.
, The second conventional PLL circuit includes a phase comparison circuit 11 common to the first first PLL circuit and an LPF.
12, a frequency range selection circuit 20 for sequentially shifting the oscillation frequency range of the VCO 13 and locking the PLL circuit when not locked within a predetermined period, in addition to the VCO 12, the VCO 13, and the frequency dividing circuit 14.

A frequency range selection circuit 20 includes a shift register 21 for generating a control voltage RC in a range corresponding to one of the five oscillation frequency bands in accordance with the value of the range selection signal. A range selection signal generation circuit for generating a range selection signal in response to various conditions such as a phase error during a steady operation and a locked / unlocked state;

Referring to FIG. 8, the operation of the second conventional PLL circuit will be described. For convenience of description, first, as an initial condition, the range selection signal generating circuit 22
It is assumed that a range selection signal RS for selecting the highest oscillation frequency range BA among the two oscillation frequency bands is generated. In response to the supply of the range selection signal RS, the shift register 21 generates a control voltage RC corresponding to the oscillation frequency range BA and supplies the control voltage RC to the VCO 13. VCO13
Oscillates at a frequency within the oscillation frequency range BA and outputs an oscillation signal VO. Hereinafter, the frequency dividing circuit 14, the phase comparing circuit 11 and the LPF 12 perform the same operation as the conventional first PLL circuit, and the LPF 12 outputs the DC control signal VC and supplies it to the shift register 21.

On the other hand, the range selection signal generating circuit 22 monitors the presence or absence of a phase error between the frequency-divided signal DS output from the frequency-dividing circuit 14 and the reference clock signal CKR. If the convergence is achieved, it is determined that the PLL circuit can be locked, and the shift register 21 is controlled to pass the input control signal VC as it is. As a result, an operation similar to that of the conventional first PLL circuit is performed.

If the phase error does not converge within a predetermined time, it is determined that locking is impossible, and the range selection signal generating circuit 22 outputs a range selection signal RS for selecting an oscillation frequency range BB immediately below the oscillation frequency range BA. Generated and supplied to the shift register 21. The VCO 13 self-oscillates at a frequency within the oscillation frequency range BB and generates an oscillation signal VO.
Is output. Hereinafter, the same operation as described above is repeated, and when the locked state is established, the stationary operation is performed in the oscillation frequency range (frequency band).

However, in the second conventional PLL circuit, a phase comparison circuit 11, an LPF 12, a VCO 13, a frequency dividing circuit 14, and a frequency range selecting circuit 20 are all connected in series to form a loop. When selecting the oscillation frequency range of the VCO, the entire PLL circuit performs a lock operation each time the oscillation frequency range is selected because all of these loop components are operated as a loop. The disadvantage is that the time is very long.

For example, assuming that the lock determination time and lock time of each frequency range are 10 ms and the number of selections (shift times) of the oscillation frequency range until locking is three, the lock time of the second conventional PLL circuit is as follows. , The lock determination time × (the number of shifts) + the lock time.
A time of 0 ms × 4 = 40 ms is required.

[0015]

The above-mentioned first conventional PLL circuit requires a VCO to ensure that the PLL locks in a predetermined reference clock frequency range even in a predetermined fluctuation range of circuit operating conditions and manufacturing conditions. The frequency control voltage gain, which is the slope of the graph of the control voltage signal vs. frequency, must be increased because of the wide frequency range of the control voltage signal. Also, there is a disadvantage that the frequency of the output signal greatly fluctuates and characteristics such as jitter deteriorate.

If the VCO has a plurality of oscillation frequency bands having a low frequency control voltage gain and the VCO is not locked within a predetermined period, the oscillation frequency band is sequentially shifted to lock the PLL circuit. In the conventional second PLL circuit which has solved the problem, when the oscillation frequency range (frequency band) of the VCO is selected, the entire PLL circuit performs the lock operation every time the oscillation frequency range is selected, so that the lock time is extremely short. Had the disadvantage of being long.

An object of the present invention is to provide a PLL circuit which guarantees that a PLL locks in a predetermined reference clock frequency range even in a predetermined fluctuation range of circuit operating conditions and manufacturing conditions, and shortens the lock time. is there.

[0018]

The PLL circuit of the present invention comprises:
A phase comparison circuit that compares the phase of the reference clock and the divided signal and outputs a phase difference signal that is a DC signal corresponding to the phase difference between the reference clock and the divided signal, and removes unnecessary high-frequency components of the phase difference signal A low-pass filter that outputs a first control voltage signal; a VCO that is a voltage-controlled oscillation circuit whose frequency is controlled by a voltage value of the first control voltage signal and outputs an output signal; And a frequency divider that outputs a frequency-divided signal. The PLL section divides a preset entire oscillation frequency range of the voltage-controlled oscillation circuit into a plurality of oscillation frequency bands. Select a frequency band to operate a phase locked loop (PLL),
Oscillation frequency band setting for setting the VCO to operate in one of a plurality of oscillation frequency bands in accordance with the setting of a first selection signal, in a PLL circuit that shifts the oscillation frequency band when not locked within a predetermined period. Means for supplying a second control voltage signal of a constant voltage to the VCO in the first oscillation frequency band selected first, causing the VCO to oscillate for free running, and sampling the VCO output signal for a fixed time to count a sampling value. A sampling circuit for generating a switching signal for comparing the sampling value with a predetermined expected value, and switching a control voltage signal of the VCO from the second control voltage signal to the first control voltage signal in accordance with the comparison result A comparison circuit for outputting one of a shift signal for controlling selection of the oscillation frequency band, and a setting circuit for setting the oscillation frequency band in response to the supply of the shift signal. A frequency selection circuit for generating a second selection signal for setting the means to a second oscillation frequency band next to the first oscillation frequency band, and the first and second control circuits in response to supply of a switching signal And a switching circuit for switching the voltage signal.

The sampling circuit counts the reference clock signal, measures time, and outputs a timer signal of a first level until a predetermined time elapses. The timer circuit includes a timer signal and a VCO output signal. AND that outputs the gate signal by passing the VCO output signal when the timer signal is at the first level.
The semiconductor device may include a gate and a counter circuit that counts the gate signal and outputs the sampling value corresponding to the count value.

The first to N-th (N is a positive integer) selection in which the frequency selection circuit sequentially shifts in response to each supply of the shift signal to select and shift the oscillation frequency band of the VCO. An N-stage shift register including a series connection of N flip-flops that sequentially output signals may be provided.

Further, the VCO is the oscillation frequency band setting means for outputting a control current signal whose value changes according to the first or second control voltage signal and the selection signal from the frequency band selection circuit. The control circuit may include a current circuit, and a current control oscillation circuit whose oscillation frequency is controlled in accordance with control of the control current and outputs the VCO output signal.

Further, the second control voltage signal is the first control voltage signal.
Alternatively, it may be the second power supply voltage.

Further, the constant current circuit of the VCO includes:
A first conductive type output MOS transistor for connecting the source to the first power supply, connecting the drain and the gate in common and outputting the control current signal, and connecting the drain to the first MOS transistor;
A control MOS transistor of a second conductivity type connected to the drain of the S transistor and receiving the first or second control voltage signal at the gate, and having one end connected to the source of the second MOS transistor Connected first
To the Nth (N is a positive integer) resistor, the source is connected to the second power supply, and the gate is connected to the first to Nth resistors.
Of the second conductivity type receiving each of the selection signals of
An Nth current source MOS transistor.

[0024] An initial setting voltage generating circuit for supplying an initial setting voltage of a third voltage intermediate between the first and second power supply voltages as the second control voltage signal may be provided. good.

[0025]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

The PLL circuit according to the present embodiment divides a preset entire oscillation frequency range of a voltage controlled oscillation circuit (VCO) into a plurality of frequency bands, selects one of the frequency bands, and selects a phase lock loop. (PLL) In a PLL circuit configured to operate and shift the oscillation frequency band of the VCO when not locked within a predetermined period, first, a constant control voltage is supplied to the VCO in the selected first oscillation frequency band. The VCO output signal frequency is sampled for a certain period of time to generate a sampling signal, the sampled signal value is compared with a predetermined expected value, and based on the comparison result, the oscillation frequency band of the VCO is determined. Shift to the next second oscillation frequency band or connect the control voltage signal of the VCO to the output of a low-pass filter (LPF) circuit to In selecting whether to PLL operation.

When the control voltage signal is connected to the output of the LPF circuit, the PLL circuit enters a normal operation state, and
The circuit locks to the predetermined frequency after a few ms.

As described above, in order to determine the output signal frequency of the VCO in the free-running oscillation state and automatically select the oscillation frequency band in which the PLL circuit locks, the lock time, which is the time until the PLL circuit locks, is set. Can be shortened.

Next, referring to FIG. 1, which shows the first embodiment of the present invention and the same components as those in FIG. The PLL circuit of the present embodiment includes a PLL unit 1 constituting a phase lock loop portion, and a frequency band for outputting a selection signal S for selecting and shifting an oscillation frequency band of a VCO 13A described later in response to the supply of the shift signal SS. A selection circuit 2; a sampling circuit 3 for supplying a ground GND to the VCO 13A in the oscillation frequency band selected first, causing the VCO 13A to oscillate for free running, sampling the VCO output signal VO for a certain period of time, and generating a sampling value CO counted; The value CO is compared with the expected value EX, and the voltage control switching signal S
A comparison circuit 4 that outputs V and a shift signal SS, and an expected value register 5 that holds an expected value EX are provided.

The PLL section 1 compares the phase of the reference clock CKR with the frequency-divided signal DS, and is a DC signal corresponding to the phase difference between the reference clock CKR and the frequency-divided signal DS, which is common to the first PLL of the related art. A phase comparison circuit 11 that outputs a phase difference signal PD; and a low-pass filter (L) that removes unnecessary high-frequency components of the phase difference signal PD and outputs a control voltage signal VC.
PF) 12 and a frequency dividing circuit 14 which divides the output signal VO by a frequency dividing ratio N (N is an integer) and outputs a frequency divided signal DS having a frequency substantially equal to the reference clock signal CKR. Instead of the (VCO) 13, the VCO 13A outputs an output signal VO with the frequency being controlled by the voltage value of the control voltage signal VC and the control voltage signal VC output from the LPF 12 in response to the supply of the voltage control switching signal SV and the ground. VCO 13 as the selection control signal SC by switching the potential
A is provided with a switching circuit 15 for supplying A.

The frequency band selection circuit 2 has a seven-stage shift register formed by connecting known flip-flops in series, and sequentially shifts in response to the supply of the shift signal SS to select the oscillation frequency band of the VCO 13A. -The shift selection signals S1 to S7 are sequentially output.

Referring to FIG. 4A, which shows an example of the configuration of the VCO 13A as a block, the VCO 13A includes a control voltage SC and selection signals S1 to S7 from the frequency band selection circuit 2.
A constant current circuit 131 that outputs a control current IC whose value changes according to the current, and an ICO circuit 132 that is a current control oscillation circuit whose oscillation frequency is controlled according to the control of the control current IC and outputs a VCO output signal VO.

The sampling circuit 3 counts the reference clock signal CKR, measures time and outputs a timer signal T of "1" level until a predetermined time elapses, a timer signal T and an output signal of the VCO 13A. The logical product with VO is taken, and when the timer signal T is present ('1'), the output signal VO is passed and the gate signal VG is output, that is, the output signal VO is sampled and gated during the period of '1' of the timer signal T. AND gate 3 for outputting signal VG
2 and a counter circuit 33 that counts the gate signal VG and outputs a sampling value CO.

FIG. 4B is a circuit diagram showing an example of the configuration of the constant current circuit 131. Referring to FIG.
Is a P-channel MOS transistor P1 having a source connected to a power supply VD, a drain and a gate commonly connected to output a control current IC as an output, and a drain connected to a drain of the transistor P1 and a gate connected to a control voltage SC. An N-channel MOS transistor N1 receiving the supply of
One end of each of the drains is connected to the other end of each of the resistors R11 to R15 having one end connected to the source of the transistor N1, the source is connected to ground GND, and the selection signal S1 is connected to the gate.
To S7 to receive N-channel MOS type transistors N11 to N17.

Next, the operation of the present embodiment will be described with reference to FIG. 1, FIG. 2 showing the waveforms of respective parts in a time chart, and FIG. 3 and FIG. 4 showing the frequency and voltage control characteristics of the VCO 13A in a graph. As shown in FIG.
The entire oscillation frequency range of A is divided from the high frequency side into seven oscillation frequency bands A, B,..., G corresponding to the selection signals S1 to S7 from the frequency band selection circuit 2, respectively. Each frequency band corresponds to the resistances R11 to R11 of the constant current circuit 131 of the VCO 13A.
The median value of the control current IC corresponding to each frequency band is set by R17.

Hereinafter, for convenience of explanation, it is assumed that the ICO circuit 132 has a characteristic that the oscillation frequency f increases in proportion to the increase of the control current IC. Therefore, by sequentially increasing the values of the resistors R11 to R17 such that R12 is larger than the resistor R11, the currents of the transistors N11 to N17 sequentially decrease, and the control current IC of the corresponding output sequentially decreases. Therefore, the control current IC (referred to as IC1 to IC7) corresponding to each of the selection signals S1 to S7 sequentially decreases, and the corresponding oscillation frequency also sequentially decreases.

As an initial condition, the control voltage signal SC of the VCO 13A is connected to the ground GND by the switching circuit 15, and at the same time, the selection signal S1 from the frequency band selection circuit 2
As a result, the transistor N11 of the constant current circuit 131 operates, and the corresponding control current IC1 is supplied to select the oscillation frequency band A. Under this condition, the VCO 13A enters a free-running state in the oscillation frequency band A. In this state, the frequency of the free-running state of the VCO 13A is sampled by the AND gate 32 only during the initialization period in which the timer signal T output from the timer circuit 31 is "1".
G is counted by the counter circuit 33. The comparison circuit 4 compares the sampling value CO, which is the count value of the counting result, with the expected value EX.

The expected value EX is a frequency at which the PLL circuit locks, that is, a value corresponding to the lock frequency. For example, the reference clock signal CKR = 25 MHz, the lock frequency of the PLL circuit = 100 MHz, the period of “1” of the timer signal T, That is, assuming that the initial setting period is 10 μs, the expected value EX = 10 ÷ 1/100 MHz = 1000.

Assuming that the frequency f1 of the self-running state of the VCO 13A at this time is 150 MHz, the initial setting period is 10 μs.
In the meantime, the sampling value CO of the counter circuit 33 corresponding to the gate signal VG is 10 ÷ 1/150 = 666, and the comparison circuit 4 outputs the shift signal SS to the frequency band selection circuit 2 because the expected value EX is larger. Send to The frequency band selection circuit 2 shifts the selection signal from the signal S1 to the signal S2 in response to the supply of the shift signal SS, and the VCO 13A changes the oscillation frequency band from A to B in response to the supply of the selection signal S2. . In the period T2, the VCO 13A selects the oscillation frequency band B. VCO1 in this oscillation frequency band B
Assuming that the frequency f2 of the self-propelled state of 3A is 130 MHz,
During the initial setting period 10 μs, the sampling value CO of the counter circuit 33 becomes 10 ÷ 1/130 = 769, and the comparison circuit 4 sends the shift signal SS again to the frequency band selection circuit 2 because the expected value EX is larger. send.

The frequency band selection circuit 2 shifts the selection signal from the signal S2 to the signal S3 in response to the supply of the shift signal SS, and in response to the supply of the selection signal S3,
The oscillation frequency band of A changes from B to C. Therefore, the period T3
In the example, the oscillation frequency band C is selected.

Assuming that the frequency f3 of the free-running state of the VCO 13A in the oscillation frequency band C is 110 MHz, the sampling value C of the counter circuit 33 during the initial setting period of 10 μs.
O is 10 ÷ 1/110 = 909. The comparison circuit 4
Since the expected value EX is larger, the shift signal SS is sent to the frequency band selection circuit 2 again. The frequency band selection circuit 2 shifts the selection signal from the signal S3 to the signal S4 in response to the supply of the shift signal SS, and changes the oscillation frequency band of the VCO 13A from C to D in response to the supply of the selection signal S4. change.
Accordingly, in the period T4, the VCO 13A operates in the oscillation frequency band D
Is selected.

Assuming that the frequency f4 of the free-running state of the VCO 13A in the oscillation frequency band D is 90 MHz, the sampling value CO of the counter circuit 33 becomes 10 ÷ 1/90 = 1111 during the initial setting period 10 μs, and the comparison circuit 4
Does not generate the shift signal SS because the sampling value CO is larger. Therefore, the selection signal remains at S4, and the oscillation frequency band D does not change. Further, since the voltage control switching signal SV is generated, the switching circuit 15
Input selection control signal SC from ground GND to LPF 1
2 is switched to the output voltage control signal VC.

In a period T5, a normal PLL operation is performed.
The number of ms required for locking (10 m here for convenience of explanation)
After that, the PLL circuit locks at 100 MHz,
After that, it continues to operate at 100 MHz.

As described above, the frequency of the VCO 13A is counted during the initial setting period of 10 μs, the sampled value CO is compared with the expected value EX, and based on the comparison result, the oscillation frequency band is switched and the optimum frequency band is automatically determined. select.
Since the PLL circuit locks in the selected oscillation frequency band, the lock time is set to 10 μm in the description example of the present embodiment.
s × 3 + 10 ms = 10.03 ms.

On the other hand, a second conventional PLL circuit having a plurality of VCO oscillation frequency bands and having a shift structure includes a phase comparison circuit 11, an LPF 12, a frequency range selection circuit 20, a VC
Since the lock is performed through the loop of O13A and the frequency dividing circuit 14, the lock is performed at the same oscillation frequency as in the present embodiment and at the fourth time after the same number of shifts (three times), and the lock determination time in each oscillation frequency range Assuming that the lock time is 10 ms, which is the same as in the present embodiment, the lock time is the lock determination time × (the number of shifts) + the lock time.
A time of 10 ms × 3 + 10 ms = 40 ms is required. Therefore, it is possible to shorten the time for locking with respect to the related art.

As described above, the PLL circuit according to the present embodiment is configured such that the VC circuit in the free-running oscillation state in the selected oscillation frequency band
Since the lock possibility is determined by comparing the output signal frequency of O with the expected value, and the oscillation frequency band to be locked by the PLL circuit is automatically selected based on the determination result.
It is possible to guarantee that the L circuit locks in a predetermined frequency range, and shorten the lock time, which is the time until the PLL circuit locks.

Next, referring to FIG. 5, which shows a second embodiment of the present invention, in which constituent elements common to FIG. The difference of the present embodiment from the above-described first embodiment is that, in the initial setting period, which is the period of “1” of the timer signal T, the ground GND in the first embodiment is replaced with a sufficient ground potential instead of the ground GND. An initial setting voltage generating circuit 6 for supplying a constant initial setting voltage VM which is set high and sufficiently lower than the power supply VDD.
It is to have.

The initial setting voltage generation circuit 6 generates the reference voltage VM
A reference voltage generating circuit 61 for generating R;
And an operational amplifier 62 for buffer-amplifying and outputting an initial setting voltage VM.

The reference voltage generating circuit 61 includes, for example, a power supply V
It can be configured by a voltage dividing circuit or the like that divides DD at a predetermined voltage dividing ratio to generate a reference voltage VMR.

The operational amplifier 62 according to the present embodiment
Since it is a% negative feedback amplifier, the gain is 1, and thus the initial setting voltage VM is equal to the reference voltage VMR.

Next, referring to FIG. 5 and the VCO 13 of this embodiment,
The operation of the present embodiment will be described focusing on the differences from the first embodiment with reference to FIG. 6 showing a graph of the frequency voltage control characteristic of A, as in the first embodiment.
If the PLL circuit is locked when the control voltage signal SC of the VCO 13A is at a voltage close to the ground GND or near the power supply VDD near the limit of the lock range, if the reference clock signal CKR changes slightly, the PLL falls out of the lock range.
There is a possibility that the circuit will be out of the locked state, that is, will be in the unlocked state. For this reason, in the present embodiment,
During the initial setting period, a voltage sufficiently higher than the ground GND, that is, an initial setting voltage VM sufficiently away from the limit of the lock range is supplied as the control voltage signal SC of the VCO 13A, and the frequency of the VCO 13A corresponding to the initial setting voltage VM (initial setting period) Is compared with the expected value EX.
By selecting the oscillation frequency band of the VCO 13A, lock near the ground GND is prevented. As the initial setting voltage VM, a voltage that can be set closest to the ground GND is a minimum voltage VMmin, and a voltage that can be set closest to the power supply VD is a maximum voltage VMmax.
n and VMmax.

When there are two or more oscillation frequency bands to be locked, an oscillation frequency band to be locked near the initial setting voltage VM is selected.
Locking in the vicinity of D or the power supply VDD is prevented.

As described above, even when the reference clock signal CKR changes slightly, the PLL circuit is not unlocked because it is sufficiently away from the limit of the lock range.

Although the embodiment of the present invention has been described above, the present invention is not limited to the above embodiment, and various modifications can be made. For example, in the first and second embodiments, the frequency band is shifted from the higher frequency to the lower frequency, and the VCO frequency is compared with the expected value. However, the frequency band is shifted from the lower frequency to the higher frequency. Even so, a similar effect can be obtained.

[0055]

As described above, in the PLL circuit of the present invention, the oscillation frequency band setting means for setting the VCO to operate in one of a plurality of oscillation frequency bands in accordance with the setting of the first selection signal. A sampling circuit that supplies a second control voltage signal of a constant voltage to the VCO in the first oscillation frequency band selected first, causes the VCO to self-run, and generates a sampling value obtained by sampling the VCO output signal for a fixed time. A comparison circuit that compares the sampling value with a predetermined expected value and outputs one of a switching signal and a shift signal according to the comparison result; and setting the oscillation frequency band in response to the supply of the shift signal. A frequency selection circuit for setting the means to a second oscillation frequency band next to the first oscillation frequency band, and a switching circuit for switching the first and second control voltage signals in response to the supply of the switching signal. By first comparing the output signal frequency of the VCO in the free-running oscillation state in the selected oscillation frequency band with an expected value, the possibility of locking is determined, and based on the determination result, the oscillation of the PLL circuit locked is determined. Since the frequency band is automatically selected, it is possible to ensure that the PLL circuit locks in a predetermined frequency range and to shorten the lock time.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a PLL circuit according to the present invention.

FIG. 2 is a time chart illustrating an example of an operation in the PLL circuit according to the present embodiment.

FIG. 3 is a graph showing a frequency voltage control characteristic of a VCO of the PLL circuit according to the present embodiment.

FIG. 4 is a block diagram showing an example of the configuration of the VCO of FIG. 1 and a circuit diagram showing an example of the configuration of a constant current circuit thereof.

FIG. 5 is a block diagram illustrating a PLL circuit according to a second embodiment of the present invention.

FIG. 6 is a graph showing a frequency voltage control characteristic of a VCO of the PLL circuit according to the present embodiment.

FIG. 7 is a block diagram showing an example of a conventional first PLL circuit.

FIG. 8 is a block diagram showing an example of a conventional second PLL circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 PLL part 2 Frequency band selection circuit 3 Sampling circuit 4 Comparison circuit 5 Expected value register 6 Initial setting voltage generation circuit 11 Phase comparison circuit 12 LPF 13, 13A VCO 14 Divider circuit 15 Switching circuit 20 Frequency range selection circuit 21 Shift register 22 Range selection signal generation circuit 31 Timer circuit 32 AND gate 33 Counter circuit 61 Reference voltage generation circuit 62 Operational amplifier 131 Constant current circuit 132 ICO circuit N1, N11 to N17, P1 Transistor R11 to R17 Resistance

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J106 AA04 CC01 CC21 CC38 CC41 CC52 DD09 DD17 DD38 DD39 DD43 DD46 EE09 EE18 GG01 HH03 JJ01 KK03 KK08 KK36 LL01

Claims (8)

[Claims] 1. A phase comparison circuit for comparing a phase between a reference clock and a frequency-divided signal and outputting a phase difference signal which is a DC signal corresponding to a phase difference between the reference clock and the frequency-divided signal. A low-pass filter that removes a high-frequency component and outputs a first control voltage signal; a VCO that is a voltage-controlled oscillation circuit whose frequency is controlled by the voltage value of the first control voltage signal and outputs an output signal; Having a frequency dividing circuit for dividing the frequency by a predetermined frequency dividing ratio and outputting a frequency divided signal
L section, which divides a preset entire oscillation frequency range of the voltage controlled oscillation circuit into a plurality of oscillation frequency bands, and selects one of the oscillation frequency bands to select a phase locked loop (PL).
L) In a PLL circuit that operates and does not lock within a predetermined period, shifts the oscillation frequency band, wherein the VCO is set to operate in one of a plurality of oscillation frequency bands according to the setting of a first selection signal. An oscillation frequency band setting means for supplying a second control voltage signal of a constant voltage to the VCO in the first oscillation frequency band selected first, causing the VCO to oscillate free-running and sampling the VCO output signal for a fixed time; A sampling circuit for generating a counted sampling value; comparing the sampling value with a predetermined expected value; and, according to a result of the comparison, converting a control voltage signal of the VCO from the second control voltage signal to the first control voltage. A comparison circuit for outputting one of a switching signal for switching to a signal and a shift signal for controlling selection of the oscillation frequency band; A frequency selection circuit for generating a second selection signal for setting the oscillation frequency band setting means to a second oscillation frequency band next to the first oscillation frequency band; And a switching circuit for switching the second control voltage signal.
LL circuit. 2. A timer circuit, wherein the sampling circuit counts the reference clock signal, measures time, and outputs a timer signal of a first level until a predetermined time elapses, the timer signal and the VCO output signal. An AND gate that takes a logical product of the AND signal and passes the VCO output signal when the timer signal is at the first level and outputs a gate signal; and a counter that counts the gate signal and outputs the sampling value corresponding to a count value. The PLL circuit according to claim 1, further comprising a circuit. 3. The first to Nth (N is a positive integer) selection in which the frequency selection circuit sequentially shifts in response to each supply of the shift signal to select and shift the oscillation frequency band of the VCO. 2. The PLL circuit according to claim 1, further comprising an N-stage shift register configured by serially connecting N flip-flops that sequentially output signals. 4. The oscillating frequency band setting means for outputting the control current signal whose value changes according to the first or second control voltage signal and the selection signal from the frequency band selection circuit. A current circuit, wherein the oscillation frequency is controlled according to the control of the control current, and
2. The PLL circuit according to claim 1, further comprising a current control oscillation circuit that outputs a CO output signal. 5. The P according to claim 1, wherein the second control voltage signal is a first or second power supply voltage.
LL circuit. 6. An initialization voltage generation circuit for supplying an initialization voltage of a third voltage intermediate between the first and second power supply voltages as the second control voltage signal. The PLL circuit according to claim 1. 7. A first conductivity type output MOS transistor for outputting the control current signal by connecting a source to a first power supply and connecting a drain and a gate in common, the constant current circuit comprising: A second conductive type control MOS transistor connected to the drain of the first MOS transistor and receiving the first or second control voltage signal at a gate, one end of which is connected to the second MOS transistor; Each of the first to Nth (N is a positive integer) resistor connected to the source of the transistor is connected to the other end of the resistor, the source is connected to the second power supply, and the gate of the first to Nth selection signals is connected to the gate. 5. The PL according to claim 4, further comprising: first to Nth current source MOS transistors of the second conductivity type receiving the respective supply.
L circuit. 8. The apparatus according to claim 1, wherein the initial setting voltage generating circuit includes a reference voltage generating circuit for generating a reference voltage, and an operational amplifier for buffer-amplifying the reference voltage and outputting the initial setting voltage. Item 6
The PLL circuit as described in the above.