JP2001237843A - Packet segment and reassembly processing section in switching system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a switching system accommodating interfaces adopting a plurality of protocols that conducts efficient packet switching. SOLUTION: The packet segment and reassembly processing section (SAR) of this invention is provided with a CPU, an interface control section that controls input output of a POS framer, an IP header check section that checks the normality of a received packet, a destination retrieval interface section that applies input/output of header information or the like to/from a destination retrieval section as to a normal IP packet, a buffer that stores received data, a buffer that stores information acquired from the destination retrieval section and an output control means that writes the acquired destination information to the received data and provides an output of data with a fixed length for each priority class.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM (Asyn)
coronous Transfer Mode) or S
ONET (Synchronous Optical)
Network) and SDH (Synchronous)
Assembly and disassembly function unit (Segment and Release) mounted on a line card accommodating a plurality of communication interfaces such as Digital Hierarchy
mbly: SAR) relates to a SAR that assembles fixed-length data received from the switch side into an IP packet by hardware autonomously and outputs the IP packet to the network interface side.

[0002]

2. Description of the Related Art A conventional SAR is disclosed in
There is a technique described in Japanese Patent Laid-Open No. 05344. According to the technology described in the above publication, in the ATM cell assembling / disassembling function unit (SAR), conventionally, a received cell is once assembled into a frame, and the processing is entrusted to upper software through a CPU interface. In order to deal with the problem that processing delay occurs due to the bus speed for transferring data, a plurality of processing units having the same processing function are provided, and a plurality of interfaces other than the CPU bus are provided between the processing units and the processing unit. An SAR that improves processing performance and reduces delay time by providing an appropriate processing device and distributing the load by referring to necessary information such as a protocol type is provided.

The technology disclosed in the network connection device described in Japanese Patent Application Laid-Open No. 11-122307 is an invention relating to a network connection device provided between a communication network having an Internet protocol and another communication network. In order to effectively utilize communication resources, packet assembling means for accommodating information signals of a plurality of calls having the same destination network connection device in one IP packet, and transmitting the IP packet received from the Internet for the destination network connection device. Packet decomposing means for decomposing into information signals of a plurality of calls.

[0004]

However, in the above-mentioned prior art, there is no interface capable of directly accommodating the IP packet. Therefore, when the IP packet is delivered to the CPU, the fixed data such as the ATM cell is transferred from the received data. There is a problem in that long data cannot be extracted and further assembled into an IP packet from the ATM cell data before it can be passed. Especially, in networks handling multimedia protocols, ATM, SON
In a switching system that handles various protocols such as ET, the length of data output to the switch varies depending on the protocol interface to be accommodated, and processing for each protocol is required in the input / output unit. However, there is a problem that a large amount of processing loss for switching occurs. For this reason, there is a problem that it is necessary to increase the speed of the switch itself and prepare expensive hardware in order to increase the processing efficiency.

[0005]

A packet assembling / disassembling processing unit in a switching system of the present invention extracts an IP packet from a received physical frame, performs assembling / disassembling of the extracted packet, and transfers the packet to a predetermined destination. A packet assembling / disassembling processing unit in the system, wherein the packet assembling / disassembling processing unit decomposes the IP packet extracted from the physical frame into a fixed-length data packet,
Means for performing a switching operation with the fixed-length data packet.

The switching system further includes a line interface unit for transmitting and receiving data of a plurality of communication protocols, a switch unit for switching data output from the line interface to a predetermined destination, and attribute information of the received data. Therefore, when it is determined that processing for each protocol is necessary, a multi-protocol processing unit that performs necessary processing for the data for each protocol is included.

[0007] Further, the line interface unit includes a POS for extracting an IP packet from the received physical frame.
A framer, a destination search unit for searching for a transfer destination for the extracted IP packet, and a transfer destination switch port are determined from the information searched by the destination search unit, and the received IP packet data is divided into fixed length data. And a packet assembling / disassembling unit for outputting the packet to the switch side.

The fixed-length data includes a transfer destination switch port number, a processing priority class, and CPU pick-up instruction information for designating a CPU for processing the data.

The SAR comprises the CPU and a PO.
An interface control unit for controlling input / output to / from the S framer; an IP header check unit for checking the normality of a received packet; and a destination for inputting / outputting header information and the like to the destination search unit for a normal IP packet. A search interface unit, a buffer for storing the received data, a buffer for storing information obtained from the destination search unit, and the obtained destination information are written in the received data and output as fixed-length data for each priority class. Output control means.

Further, the SAR includes a switch interface unit for receiving fixed-length data from a switch, a distribution unit for determining a buffer for reading and storing a source switch port number and a priority class from the received fixed-length data, When the data is stored in the predetermined buffer by the distribution unit, the data is written to the packet buffer for each source switch port number and priority class, and the data belonging to the same group as the received fixed-length data is stored in the same storage order. While receiving the final data while instructing storage in the same storage area, a packet buffer interface unit instructing an output instruction unit to output, and an output instruction received from the packet buffer interface unit are used for each priority class. Allocate bandwidth and output to network And a force controlling section.

[0011]

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an ATM (Asynco).
RON (Transfer Mode) and SON
In a disassembly / disassembly function (SAR) mounted on a line card accommodating an interface such as ET or SDH, fixed-length data received from the switch side is autonomously IP-hardened.
It is characterized in that it is assembled into packets and output to the network interface side. Also, the present invention is characterized in that a transfer destination switch port of an IP packet received from a network is determined autonomously by hardware, and the IP packet data is divided into fixed-length data and output to the switch. Hereinafter, embodiments of the present invention will be described.

FIG. 1 shows the configuration of a switching system in which the SAR of the present invention is mounted. A switching system 10 accommodates line interfaces 100 to 102 each accommodating a plurality of protocol types. Each of these line interfaces 100 to 102 is a line card having a CPU and an interface such as SONET, SDH or ATM, connected to the switch 103, and mounted with the SAR of the present invention.

The switching system 10 further includes a multi-protocol processing unit 104 and a central processing unit 105. A maintenance bus 106 for monitoring the status of the line card and the multi-protocol processing unit 104. Have been. The multi-protocol processing device 104
It is mounted on the trunk of the switch 103. The central processing unit 105 performs control such as device management. Usually,
The central processing unit 105 includes a processor, a memory, and a secondary storage device, and operates according to a program stored in the memory.

Here, the embodiment of the present invention is described as SONE.
T interface and POS (Packet Ov
The operation will be described with an example of a line card (hereinafter, this will be referred to as a line card 100) that processes er.

Line card 1 having a line interface
00 extracts the IP packet from the received SONET frame, determines the port number of the transfer destination switch from the IP address, divides the IP packet into fixed-length data in the SAR section, and uses the switch port as an internal header. A number or the like is added to each fixed-length data and output to the switch 103.

The switch 103 sets the I
Data is switched according to the switch port number determined from the P address.

The multi-protocol processing device 104 performs a process according to each protocol type on data input from each of the different types of line cards 100 to 102 via a switch. For example, in the case of an ATM, a signaling process is performed. In the case of an IP packet, a packet of a routing protocol is received, a routing calculation is performed, a latest routing table is created, and an interface required to be transferred in the IP layer is provided. Processing such as distributing the forwarding table to the line card is performed.

Conversely, the line card 100 that has received the fixed length data as data to be transmitted to the network from the switch 103 deletes the fixed length data in the SAR unit while deleting the port number assigned inside the device. ,
It assembles the original IP packet autonomously by hardware and sends it to the network side.

Here, the IP address is addressed to oneself,
If the protocol type of the IP packet is a protocol that can be processed in the line card (for example, ICMP processing), the SAR passes the data to the CPU, executes the processing by the CPU described later, Will be returned.

Next, the processing operation of the line interface will be described in more detail with reference to the functional block diagram of the line interface of FIG.

The line interface 100 shown in FIG.
This is a line card having a SONET interface and having a POS function for extracting an IP packet from a SONET frame.

A line card 100 for processing this POS
Is a POS framer 204, a SAR unit 205 that divides an IP packet into fixed-length data or assembles an IP packet from fixed-length data, a destination search unit 206 that searches for a transfer destination switch port number from a destination address of the IP packet, Packet memory 203 for storing packet data, CP for managing line cards and performing protocol processing
U202, main memory 201 and the like.

In addition, a bus 211 for the CPU to access each component block of the line card, an interface 212 for the POS framer to receive / transmit STM-1 frames, and an SAR for IP packet reception / transmission.
It has an interface 213 for transmission, an interface 214 between the SAR and the switch, and an interface 215 for the SAR and the destination search unit.

When a physical frame is received from the network, the POS framer 204 extracts an IP packet from the SONET frame,
A P packet pickup request signal is output. SAR205
Receives the IP request signal, and receives the IP packet.

When the SAR 205 receives the IP packet, it checks the normality of each field of the IP header.
The IP header of the normal IP packet and the TCP port number are output to the destination searching unit 206, and the destination searching unit 206
Performs a destination search of the IP packet by hardware.
Here, the destination search unit 206 previously stores information of the received packet, for example, destination information such as an IP header and a protocol type of an IP packet, a port number of a transfer destination for the packet, and a processing type. Is retrieved and output.

When an error is detected by the IP packet normality check, the error packet is
Discarded at 205. The destination search unit 206 extracts the destination information, and performs a hardware IP address destination search based on the extracted destination information.

Here, the SA according to the output destination information
The processing operation in R205 is different. The following can be summarized: (I) The case where the destination of the IP packet is addressed to itself and the protocol can be processed in the line card. (II) When transferring to a multi-protocol processing device or another line interface via a switch. In the above case, the flow of each process will be described. (I) When the received data is data processed in the own line interface.

If the received data is a protocol that can be processed in the line card, such as ICMP, addressed to the own device, the data received by the line interface is returned,
Output to own line interface. This data flow corresponds to (A) shown in FIG.

As a result of the search by the destination search unit 206, the IP packet is addressed to itself, and a protocol (for example, ICM) that can be processed by the line card based on the protocol type of the IP packet.
P), the SAR 205 stores the IP packet in the memory 203, and stores the stored address in the CPU 203.
At 202, a request for taking in an IP packet is made.

When the CPU 202 receives the data collection request from the SAR 205, it receives the IP packet from the storage address indicated by the SAR 205, for example, ICMP.
If this is the case, processing such as adding the IP address information of the own apparatus is performed, and after these processings are completed, this IP packet is stored in the packet memory 203. And SAR
The storage address is indicated to 205, and an output request is made.

Upon receiving the output request from the CPU, the SAR 205 reads the IP packet from the memory and transmits the IP packet to the network. (II) Case of Line Interface → Multiprotocol Processing Device or Line Interface Next, a case where data received by the line interface is transferred to the multiprotocol processing device or the line interface will be described. These are shown in FIG.
And (C).

In the destination search process, the SAR 205
CPU 202 determines from the received packet address and the protocol type that the packet cannot be processed by its own line interface card, and determines that processing for each protocol is necessary. Instruct the SAR 205 to transfer.

At this time, the SAR 205 is
In order to perform the switching as shown in FIG. 3 so that the switching can be performed, switch header information added inside the device is added, and the IP packet is output to the switch while being divided into fixed length data.

The switch header information internally given to the fixed-length data includes a transfer destination switch port number 30
1. Source switch port number 302, CPU takeover instruction 303, priority class 304, head data / final data identifier 305 (hereinafter referred to as switch header A), data length 306, protocol identifier 307 (hereinafter referred to as switch header B) ).

The switch header A is added to all the fixed-length data, and the switch header B is added to the switch fixed-A only in the case of the first fixed-length data.

The fields of the switch header will be described in detail with reference to FIG. 3. The destination switch port number 301 indicates the port number at which fixed-length data is to be switched, and the source switch port number 302
Indicates the switch port number to which the line interface that has transmitted the fixed-length data is connected. The CPU takeover instruction 303 indicates an identifier indicating whether the received fixed-length data is to be passed to the CPU or output to the network. An identifier 307 is a field indicating a protocol type of the divided data, a priority class 304 is a field indicating a priority class when transferring received data, and a data length 306 is a field indicating a data length actually received by the SAR from the line side. , The first / last word data identifier 305 indicates an identifier indicating whether the fixed-length data is the first or last fixed-length data. When the CPU transmits data, the field of the switch header information is set by the CPU.

The received IP packet received by the line interface 100 and transferred from the POS framer 204 to the SAR 205 has been transferred to the multiprotocol processing device 104 or another line interface as a result of search by the destination search unit 206. In this case, the destination search unit 206
Transfers the transfer destination switch port number 301 and the priority class information 304 to the SAR from the stored information.

The other fields are as follows: (1) The source switch port number 302 is set by referring to the information set in the SAR register at the time of initial setting of the line interface. (2) The CPU pickup instruction 303 is set to be output to the network side. (3) The protocol identifier 307 is a PPP (Point)
The protocol field value of “to Point Protocol” is inserted autonomously by hardware. (4) For the data length 306, the SAR counts the data length actually received from the POS framer, and inserts the count value. (5) The first data / last data identifier 305 is (4)
It is set autonomously by hardware based on the data length 306 of.

In this way, the necessary header information for the fixed-length data can be set autonomously by hardware.
The SAR internally has a high priority class I according to the priority class.
While dividing the P packet into fixed-length data, switch header information is added and output to the switch 103.

The transfer destination is the multi-protocol processing device 104
To give a concrete example, I of the received IP packet
This is the case where the protocol number in the P header indicates a routing protocol, or when the destination is not found as a result of the search by the destination search unit 206, or when the destination is the multi-protocol processing device 104.

The switch 103 switches the fixed-length data output from the line interface according to the transfer destination port number 301 and the priority class 304 in the switch header information.

The line card that has received the fixed-length data from the switch assembles the fixed-length data into an IP packet in a hardware autonomous manner while deleting the switch header information added internally in the SAR 205 and sends the IP packet to the network side. Send a packet. At this time, the SAR compares the data length actually received from the switch with the data length of the switch header B.
Discard the packet.

When the data lengths match and the CPU takeover instruction is enabled, the SAR delivers the assembled packet to the CPU. If the CPU takeover instruction is disabled, the instruction is output to the network side.

The multi-protocol processing device 104 performs a process such as a routing function on the IP packet received from the switch, and performs processing for each of the different types of line cards 100 to
Processing corresponding to each protocol is performed on data input from 102 via the switch. That is, as described above, for an ATM, a signaling process is performed. For an IP packet, a packet of a routing protocol is received, a routing calculation is performed, a latest routing table is created, and a transfer in the IP layer is requested. Processing such as distributing a forwarding table to a line card having a specified interface.

When mounted on a line interface accommodating an ATM, the SAR of the present invention outputs an ATM cell to the switch side with header information as in the case of an IP packet. The header information is the VPI and VCI of the ATM header.
The destination search unit 206 determines from the value and transfers the switch header information to the SAR. The receiving SAR deletes the switch header information and outputs the ATM cell to the network side.

Description of the operation of the embodiment (1) Operation at the time of packet division processing Next, a detailed functional configuration of the SAR will be described. First, the operation of the SAR 205 at the time of IP packet division will be specifically described with reference to FIGS.

FIG. 4 is a functional block diagram of the SAR dividing process according to the embodiment of the present invention. As shown in FIG.
The unit divides the IP packet into fixed-length data, adds a port number of the switch as an internal header for each fixed-length data, and outputs the result to the switch 103.

In FIG. 4, the CPU interface unit (C
The PU INF) 402 performs an interface process with the CPU 202 in FIG. The POS framer interface (POS Framer INF) 403 is a POS
The interface processing with the framer 204 is performed.

Interface control unit (ARB0) 401
Are CPU INF402 and POSFramer IN
The control unit when an input / output conflict occurs in F403. IP header check unit (IPH CHK) 404
Is a block for checking the normality of the IP header when the received data is an IP packet.

The destination search INF 407 is a destination search unit 20
6 is performed.

A buffer TB 405 stores received data until the processing of the destination search unit 206 is completed.
The SAR connection is realized by an external memory or an internal memory. The TB controller (TB CNT) 406
This block writes / reads data received from the PH CHK 404 to / from the TB 405, extracts an IP header, and transfers the extracted IP header to the destination search INF 407.

The PB 408 is a buffer for storing data to which the information of the destination search unit 206 has been added, and is realized by an external memory or an internal memory like the TB.

PB controller (PB CNT) 409
Is a block for writing / reading data from the TB CNT 406 to the PB 408.

SW interface (SW INF0) 4
Reference numeral 10 denotes an interface unit with the switch.

Hereinafter, the packet division operation of the SAR unit will be described with reference to the configuration of FIG. 4 and FIGS. 2 and 6.

The POS framer 204 extracts an IP packet from the STM-1 frame, and
5 is transmitted. FIG. 6 shows an example of the format of a frame extracted from the extracted STM-1.
In this example, a PPP (Point to Point) in which an IP packet is mounted in the data area of the STM-1 frame.
Protocol frame), and the extracted PPP frame has a fixed value FF0 as its header information.
3, a protocol field indicating the type of protocol of the data part, and a data part including an IP packet.

The protocol field is a field referred to when hardware inserts a value autonomously into the protocol field portion of the switch header B.

Next, a case where the POS Framer INF receives data will be described. This case is a case where a physical frame is received from the network side.

When the POS framer INF 403 receives the frame shown in FIG. 6, it deletes the fixed value FF03 and
When the P packet is extracted, the protocol field is converted into a value to be used in the device, and the value to be put in the protocol field of the switch header B is determined.

Also, the head and the end of the received data are recognized, and when the data is received up to the end, the IPHCHK unit is notified.
When the received data is an IP packet, the IPH CHK unit checks the IP packet. If the check result is normal, the data is transferred to the TB CNT 406 by the final data reception notification from the POS framer INF unit. If the result of the check is an error, all received data up to the final data reception notification is discarded.

The TB CNT 406 extracts the IP header from the received data and transfers it to the destination search INF 407,
Write the received data to TB.

Upon receiving the information of the switch port number to be transferred and the priority class as a result of the search by the destination search unit 206, the TB CNT reads the data from the TB and adds the information (the fixed length data of FIG. 3). Is transferred to the PB CNT 409. PB CNT
Reference numeral 409 extracts priority class information, writes data to the PB according to the priority class, and outputs a request signal to the switch 103 for each priority class.

When the output permission signal is received from the switch,
The PB CNT 409 determines the priority class of the output permission signal, reads the PB 408, and transmits data to the SW INF 410. SW INF410 is switch header A
And outputs the data to the switch 103 by adding the switch header A while dividing the data from the PB CNT into fixed-length data.

If the result of the search by the destination search unit 206 indicates that the processing is for the own line card, the SAR 205 is instructed to deliver it to the CPU 202. At this time, SAR
205 notifies the CPU of the storage address of the packet memory 203, and the CPU 203 reads the packet from the notified address and receives the IP packet.

When outputting the data after the processing on the own line to the other line interface, the CPU stores the data in the memory 203 and sets an address and a data size in the CPU INF 402. As a result of the contention control of ARB0, when the output permission to the IPH CHK unit is received, the data is read from the memory 202 by the data size,
Output to H CHK section.

(2) Operation at the time of packet assembling processing Next, an operation of assembling an IP packet from fixed length data received from the switch unit in the line card will be described with reference to FIG. FIG. 5 is a functional configuration diagram of the SAR assembly processing unit according to the embodiment of the present invention.

SW interface (SW INF) 50
9 is an interface with the switch. The distribution unit 508 uses the source switch port number and the priority class,
This is a block for determining a FIFO to be stored.

The FIFO unit 507 has a priority class FIFO of # 0 to #n for each of the source switch port numbers # 0 to #M.
When receiving fixed-length data, the packet buffer interface unit (PKTBUF INF) 505
Is a block for making a request for collection. The POS framer INF 503 is a block that receives data from the PKTBUF INF 505 and outputs the data to the POS framer.

The CPU INF 502 has a switch header A
Is an interface that transfers the enabled data to the packet memory 203 and notifies the CPU of the storage address.

SW interface (SW INF) 50
9, when the fixed length data is received from the switch, the distribution unit 508 determines the FIFO for reading and storing the source switch port number and the priority class of the packet. When data is stored in the FIFO unit 507, the FIFO
The unit sends a pick-up request to PKTBUF INF 505.

Next, PKTBUF INF 505 sets F
The fixed length data is read from the IFO unit 507, and the PKT is
Write to BUFF 504.

The PKTBUF INF 505 is the PKT B
The free address of the UF 504 is managed, and when writing the received fixed-length data, the address where the next fixed-length data is stored (hereinafter referred to as a next pointer) is added and written.

When the last data is received, an identifier indicating the last data (hereinafter referred to as an end pointer) is added and written. When receiving the final fixed-length data, the PKTBUF INF 505 transmits the storage address and the priority class information to the output instruction unit 506 to the output instruction unit 506.

The output instructing unit 506 performs band control, and allocates a large band to data of a high priority class so as to output the data to the network side.
The storage address is transmitted to the F INF 505 to instruct output.
The PKTBUF INF 505 receives the PKT BU according to the storage address received from the output instruction unit 506 and the output instruction.
Data is read from the FF 504. When the next pointer is added to the read fixed-length data, the next fixed-length data is read from the address indicated by the next pointer. This operation is continued until the fixed-length data to which the end pointer is added is output.

[0075]

According to the present invention, the following effects can be obtained.

The first effect is that the SAR has an interface capable of directly accommodating the IP packet, and the IP packet can be delivered to the CPU without assembling the IP packet from fixed-length data such as ATM cells. That is, the processing capability of the SAR is not suppressed by the delivery of the IP packet to the CPU.

The second effect is that since the SAR has an interface capable of directly accommodating the IP packet, the IP packet can be divided into fixed length data by the hardware autonomous and output to the switch. High-speed processing can be performed at the same input speed. Similarly, even when assembling an IP packet from fixed-length data, the assembling into an IP packet can be performed autonomously by hardware, so that high-speed processing can be performed at the input speed of the input fixed-length data.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a switching system equipped with an SAR according to an embodiment of the present invention.

FIG. 2 is a functional block diagram of a line interface according to the embodiment of the present invention.

FIG. 3 shows a format of fixed-length data according to the embodiment of the present invention.

FIG. 4 is a functional configuration diagram of SAR division processing according to the embodiment of this invention.

FIG. 5 is a functional configuration diagram of an SAR assembling process according to the embodiment of the present invention.

FIG. 6 shows a format of an extracted frame.

[Explanation of symbols]

 100, 101, 102 Line interface 103 Switch 104 Multiprotocol processing unit 105 Central processing unit (CPU) 201 Main memory 202 CPU 203 Packet memory 204 POS framer 205 SAR 206 Destination search unit 211 System bus 212 Frame transmission / reception interface 213 IP packet transmission / reception interface 214 Interface with Switch 215 Interface of SAR and Destination Search Unit 301 Destination Switch Port Number 302 Source Switch Port Number 303 CPU Pickup Instruction 304 Priority Class 305 First Data / Last Data Identifier 306 Data Length 307 Protocol Identifier 401, 501 ARB 402 , 502 CPU INF 403, 503 POS FRAMER INF 40 IPH CHK 405 TB 406 TB CNT 407 destination search INF 408 PB 409 PB CNT 410,509 SW INF 504 PKT BUFF 505 PKT BUFF INF 506 output control unit 507 FIFO 508 distribution unit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5K030 GA03 HA08 HB12 HB14 HB17 HB18 HD09 JA06 KA01 KA03 LA01 LB11 LB13 LE02 LE05 LE14 5K034 AA07 EE11 HH12 HH42 HH63 MM01 MM18 MM25 9A001 BB04 CC06 DD10 JJ18

Claims (6)

[Claims] A packet assembling / disassembling unit (SAR) provided at a line interface provided corresponding to each communication protocol in a stage preceding a switch of a switching system, comprising: a physical frame received from a network; Packet decomposing means for extracting the IP packet into fixed-length data packets that can be exchanged by the switch and inputting the data to the switch; fixed-length data exchanged and output by the switch A packet assembling means for receiving a packet, assembling the fixed-length data packet into a physical frame according to a protocol of a corresponding line interface, and outputting the physical frame to the network. 2. The line interface unit comprising: a POS framer for extracting an IP packet from a received physical frame; a destination search unit for searching a transfer destination of the extracted IP packet; and a search performed by the destination search unit. From the information, the transfer destination switch port is determined.
2. The packet assembling / disassembling unit in the switching system according to claim 1, further comprising a packet assembling / disassembling unit for dividing the P packet data into fixed-length data and outputting the divided data to the switch side. 3. The fixed-length data according to claim 2, wherein the fixed-length data includes a transfer destination switch port number, a processing priority class, and other CPU pick-up instruction information for designating a CPU that processes the data. Packet assembling / disassembling processing unit in the switching system. 4. The SAR includes an interface control unit for controlling input / output between the CPU and a POS framer, an IP header check unit for checking the normality of a received packet, and the destination search for a normal IP packet. For the unit, a destination search interface unit that inputs and outputs header information and the like, a buffer that stores the received data, and a buffer that stores information acquired from the destination search unit,
4. The packet assembling / disassembling processing unit in the switching system according to claim 3, further comprising output control means for writing the acquired destination information in the received data and outputting the destination information as fixed-length data for each priority class. 5. A switch interface unit for receiving fixed length data from a switch, a distribution unit for determining a source switch port number and a buffer for reading and storing a priority class from the received fixed length data, When the data is stored in the predetermined buffer by the distribution unit, the data is written to the packet buffer for each source switch port number and priority class, and the data belonging to the same group as the received fixed-length data is stored in the same storage order. While receiving the final data while instructing storage in the same storage area, a packet buffer interface unit instructing an output instructing unit to output, and an output instruction received from the packet buffer interface unit are used for each priority class. Output system that allocates a suitable bandwidth and outputs it to the network Packet exploded processing unit in the switching system according to claim 4, characterized in that it comprises a part. 6. A switching system, comprising: a line interface unit for transmitting and receiving data of a plurality of communication protocols; a switch unit for switching data output from the line interface to a predetermined destination; and attribute information of the received data. And a multi-protocol processing unit for performing necessary processing for the data by protocol when it is determined that processing for each protocol is necessary. 6. The switching system according to claim 1, further comprising: A packet assembling / disassembling processing unit.