JP2001236305A - Semiconductor integrated circuit and data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve data transfer efficiency. SOLUTION: The circuit is provided with an internal circuit and a bus control controller 70 which can change the correspondence relation of connection with an external bus(BUS) according to data transferred through the external bus when an input/output port(IOP) which enables the transfer of signals between the internal circuit and external bus is included. Since the correspondence relation of connection with the external bus can be changed according to the data transferred through the external bus, a data processor to which this semiconductor integrated circuit is applied is able to partially use the external bus, which can be used divisionally to transfer data by plural bus masters in parallel, so that the data transfer efficiency is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit technology, and more particularly to a technology effective when applied to a computer system.

[0002]

2. Description of the Related Art As a data processing device, there is a data processing device having a plurality of bus masters, for example, a microprocessor (hereinafter simply referred to as a "processor"). For example, a first processor, a second processor, a semiconductor memory, and an I / O
Consider a data processing device in which (input / output) units are mutually connected by a bus so that signals can be exchanged. The semiconductor memory and the I / O unit are shared resources of the first processor and the second processor. Since the first processor and the second processor cannot use the shared resources at the same time, bus arbitration is performed.

When the bus is not used by the first processor or the second processor, an I / O port in the processor is put into a high impedance state with respect to the bus to avoid a signal collision. When the first processor acquires the bus right and accesses the semiconductor memory, the second processor cannot use the bus. In this case, the second processor waits for the first processor to release the bus, acquires the bus right, and
Access the O section.

[0004] As an example of a document describing bus arbitration, there is a "Microcomputer Handbook (pages 676-)" issued by Ohm Co., Ltd. on December 25, 1985.

[0005]

While the first processor acquires the bus right and accesses a device such as a semiconductor memory as described above, the second processor cannot use the bus. Even when it is desired to exchange signals with the I / O unit, it is necessary to wait until the first processor relinquishes the bus right. For this reason, the upper limit of the processing performance may be determined by the bus transfer speed.

In the case where a plurality of types of data need to be transferred at the same timing, in the data processing device, the first processor and the second processor cannot acquire the bus right at the same time. It is necessary to provide a plurality of buses according to the data to be transferred. However, providing a plurality of buses increases the area occupied by the mounting board, which hinders miniaturization of the system.

An object of the present invention is to provide a technique for improving data transfer efficiency.

[0008] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, when a semiconductor integrated circuit is configured to include an internal circuit and an input / output port that enables signals to be exchanged between the internal circuit and an external bus, the semiconductor integrated circuit exchanges signals via the external bus. There is provided a bus connection controller capable of changing the correspondence of connection with the external bus according to data to be transmitted.

According to the above means, the bus connection controller can change the correspondence of connection with the external bus in accordance with data exchanged via the external bus. In the data processing device to be used, the external bus can be partially used, which enables the divided use of the external bus,
Data transfer efficiency can be improved by enabling parallel execution of data transfer by a plurality of bus masters.

The input / output port includes a bus monitor for monitoring the status of the external bus, holding means for holding bus assignment information taken in through the bus monitor, and the external bus. And a switch means for selectively coupling the constituent bits of the external bus to an internal circuit based on the information held by the holding means.

At this time, the bus monitor includes an ID register capable of holding ID information preset for each chip;
An ID check unit for comparing the ID information in the register data input from the outside with the information held in the ID register; and taking in the bus allocation information into the holding means based on the check result in the ID check unit. And a bus monitoring control unit for controlling.

The data processing apparatus may include a plurality of semiconductor integrated circuits configured as described above and an external bus for coupling the plurality of semiconductor integrated circuits so that signals can be exchanged with each other. it can.

[0015]

FIG. 7 shows a configuration example of a computer system which is an example of a data processing device according to the present invention.

As shown in FIG. 7, the computer system 500 includes a first processor 101, a second processor 102, a memory 104, and an I / O (input / output) unit 1
03, which are communicably coupled to each other by a bus BUS. First processor 10
Each of the computers 1 and 102 performs a predetermined calculation process by executing a predetermined program. The memory 104 stores data and the like necessary for arithmetic processing in the first processors 101 and 102, and is accessed by the first processors 101 and 102 as needed. I /
The O unit 103 enables various data to be exchanged with a device arranged outside the data processing device, and is accessible by the first processors 101 and 102. The bus BUS basically has a 32-bit configuration, but can be divided into two, such as a two-system 16-bit bus or a 24-bit bus and an 8-bit bus, by bus connection control described later. . That is, as shown in FIG.
While the memory 104 is being accessed by the first processor 101 using the bits, the I / O unit 103 can be accessed by the second processor 102 using the lower 16 bits of the bus BUS. Also,
As shown in FIG. 7, the first processor 101 uses the upper 24 bits of the bus BUS to
Is accessed by the second processor 102 using the lower 6 bits of the bus BUS during the period when
The access of the O section 103 is enabled.

FIG. 10 shows a configuration example of the first processor 101.

The processor 101 shown in FIG. 1 includes a flash memory 20, a CPU 12, a DMAC 13, a bus controller (BSC) 14, a ROM 15, a RAM 16,
It is composed of functional blocks or modules of a timer 17, a serial communication interface (SCI) 18, an input / output port IOP, and a clock oscillator (CPG) 19, and is formed as a semiconductor integrated circuit on one semiconductor substrate by a known semiconductor manufacturing technique. You.

The processor 101 operates in synchronization with a system clock generated by the clock oscillator 19 based on a crystal oscillator (not shown) connected to the clock input terminals EXTAL and XTAL. Alternatively, an external clock may be input to the EXTAL terminal. One cycle of the system clock is called one state.

The above functional blocks are interconnected by an internal bus. The internal bus includes a control bus including a read signal, a write signal, a bus size signal, a system clock, and the like, in addition to an address bus and a data bus. IAB, PA on the internal address bus
B exists, and IDB and PDB exist on the internal data bus. IAB and IDB are flash memory 20, CPU
12, ROM 15, RAM 16, bus controller 1
4. Connected to a part of the input / output port IOP. PAB,
PDB is the bus controller 14, timer 17, SCI1
8. Connected to input / output port IOP. IAB and PA
B, IDB and PDB are connected to the bus controller 14 respectively.
Interfaced. Although not particularly limited, PAB
And PDB are exclusively used for register access in the functional block to which it is connected.

The input / output port IOP is connected to an external bus signal,
Also used for input / output with input / output signals of the input / output circuit. These functions are selected and used according to the operation mode or software setting. The external address and the external data are respectively IAB and ID via buffer circuits (not shown) included in these input / output ports.
B is connected. PAB and PDB are used to read / write internal registers such as an input / output port and the bus controller 14, and have no direct relation to an external bus.

In the processor 101, the flash memory 20 appropriately stores a user program, tuning information, a data table, and the like. The ROM 15 stores, although not particularly limited, a system program such as an OS.

The flash memory 20 has an internal bus IAB,
It is coupled to the IDB and is made accessible by the CPU 12 and the like. That is, the CPU 12 sets control information for the write / erase control register WEREG, supplies the control signal READ when instructing a read operation for reading data from the memory cell MC, supplies an address signal, and supplies write data. Control. The CPU 12 issues a read operation instruction for erase verification and write verification, and reads the read data from the CPU 1.
2 is verified.

The second processor 102 has the same configuration as described above.

FIG. 1 representatively shows a configuration example of the input / output port IOP included in the first processor 101 and the second processor 102.

As shown in FIG.
OP is an input / output unit 50, a bus state controller 6
0, and a bus connection controller 70. The input / output unit 50 enables data and address signals to be exchanged between the internal address buses IAB and PAB and the internal data buses IDB and PDB. Bus state controller 6
0 opens and closes a signal path between the input / output unit 50 and the bus connection controller 70. Bus connection controller 70
Changes the correspondence of connection with the bus BUS according to data exchanged via the bus BUS.

FIG. 2 shows an example of the configuration of the bus connection controller 70.

As shown in FIG. 2, the bus connection controller 70 includes a bus allocation register 701, a plurality of selectors 702-0 to 702-n, and a bus monitor 705. When the maximum bit width of the bus BUS is 32 bits,
Thirty-two registers are arranged correspondingly. In addition, the bus assignment register 701 includes the selector 7
There are 32 storage units corresponding to 02-1 to 702-n. Although not particularly limited, the selectors 702-1 to 702-1-7
When a logical value “1” is written in the 32 storage units corresponding to the bus state controllers 02-n, the corresponding selectors 702-1 to 702-n are turned on, and the bus state controller 60 and the bus state controller 60 The corresponding bit of BUS is combined. Further, selectors 702-1 to 702-n
When the logical value “0” is written in the 32 storage units corresponding to
2-1 to 702-n are turned off, and the bus state controller 60 and the corresponding bit of the bus BUS are cut off. Writing data to the bus allocation register 701 is performed by an output signal of the bus monitoring unit 705. The bus monitoring unit 705 monitors the state of the bus, and receives request data REQDATA from the second processor 102.
Or an acknowledge signal ACK is asserted.

FIG. 3 shows an example of the configuration of the bus monitor 705.

As shown in FIG. 3, the bus monitor 70
Reference numeral 5 denotes a FIFO (first-in first-out) buffer unit 34 capable of holding register data in a first-in first-out format, an ID register 36 capable of holding an ID number of each device, ID data input from outside, and the ID An ID check unit 36 for determining whether or not the information stored in the register 36 matches, an ACK generation unit 37 for generating an acknowledge signal ACK, and an REQ generation unit 38 for generating request data REQDATA. including.

FIG. 5 shows a configuration example of the memory 104.

The memory 104 shown in FIG. 5 is, but not limited to, a dynamic random access memory (DRAM), a memory cell array in which a plurality of dynamic memory cells are arranged in a matrix, and an external bus. By decoding a row address signal input via the BUS, a row system circuit 52 for generating a word line selection signal in the memory cell array 51 and a column address fetched via the external bus BUS are used. In addition to decoding, based on the decoding result, a column circuit 54 for selectively coupling a plurality of bit lines in the memory cell array 51 to a common line, and a row address strobe signal and a column strobe signal, Controls for generating operation control signals for each part And over La 53, output port 55 to allow exchange of various signals to and from the external bus BUS
And This input / output port 55 can be configured similarly to the input / output port IOP shown in FIG. 10 (see FIGS. 1, 2 and 3). However, since the memory 104 is not a bus master, the REQDATA generator 38 in FIG. 3 is not required.

FIG. 6 shows a configuration example of the I / O section 103.

As shown in FIG. 6, the I / O unit 103
Is an input / output circuit 62 coupled to an external device (not shown).
And an input / output port 61 coupled to the external bus BUS, are formed on one semiconductor substrate such as single crystal silicon. This input / output port 61 can be configured similarly to the input / output port IOP shown in FIG. 10 (see FIGS. 1, 2, and 3). However, since the memory 104 is not a bus master, the memory
Is unnecessary.

FIG. 4A shows the request data RE.
The format of QDATA is shown.

As shown in FIG. 4 (a), the request data REQDATA
0, ID number information 401, start bit information 402,
End bit information 403 is arranged. When the request bit 400 has the logical value “1”, the request data REQDATA is valid. The ID number information is identification information set in advance for each device,
With this ID number information, it is possible to identify which device the request is for. The start bit means the first bit of a group of bits to be used among all bits of the bus BUS. Also, the end bit 403
Means the last bit of the bit group to be used among all the bits of the bus BUS. For example, when specifying the 0th to 15th bits of the bus BUS,
The start bit is “0” and the end bit is “1”.
5 ".

Such request data REQDAT
When A is input, the ID check unit 36
A check is performed with the data held in the register 35, and the request data REQD input in this check is checked.
If the ID number information in the ATA matches the information held in the ID register 35, the ID check unit 36 asserts the check result signal CHEND to a high level. Then, the bus monitoring control unit 33 determines whether or not the device uses the bus BUS. If it is determined in this determination that the device does not use the bus, the bus monitoring control unit 33 determines whether the device uses the bus BUS. Based on the stored start bit information and end bit information, a logical value “1” is written to a corresponding storage unit in the bus allocation register 701. For example, when the start bit is “0” and the end bit is “15”, the logical value “1” is written in the storage unit corresponding to the 0th to 15th bits of the bus BUS. As a result, the selectors 702-0 to 702-0 corresponding to the logical value "1"
By conducting 702-n, the 0th to 15th bits of the bus BUS are changed to the bus state controller 6.
Combined with zero.

As shown in FIG. 4B, information 503 of the bus width from the start bit to the end bit may be set instead of the end bit information.

FIG. 11 shows how signals are exchanged between the devices.

The first processor 101 is a bus master. The second processor 102 issues request data to the first processor 101. First processor 10
1, the ID number in the request data REQDATA is stored in the ID register 3
The data is compared with the contents stored in No. 5, and if they match, it is determined that the request data is for itself, and it is determined whether or not the bus BUS is used. In this determination, if the user is not currently using the bus BUS, the request data REQDATA is sent to all other devices that will affect before and after the change in the width of the bus BUS. For example, the request data REQDATA is transmitted to the memory 104 and the I / O unit 103. Memory 10
4 and the I / O unit 103 transmit the request data REQD
After receiving the ATA, no new data transfer is performed. If any data transfer is currently being performed, after the transfer is completed, the information in the bus assignment register 701 is rewritten in the bus connection controller in each device, and the state of the selector is changed based on the rewritten information. By the resetting, the bus width is changed, for example, as shown in FIG. 8 or FIG. After this change, the acknowledgment signal ACK for the first processor 101, which is the bus master, is asserted. When the acknowledge signals ACK from all devices such as the memory 104 and the I / O 103 are asserted, the first processor 101 confirms the completion of the change of the bus width in each device.

FIG. 13 shows a change in the state of the bus width switching.

Before the change of the bus width, the first processor 101 and the I / O unit 103 are connected by the bus width A, and the second processor 102 and the memory 104 are connected by the bus width B. However, after the above bus width change, before the bus width change, the first processor 101
And the I / O unit 103 are connected by a bus width AA, and the second processor 102 and the memory 104 are connected by a bus width BB. Also, after the bus width is changed as shown in FIG. 12, data transfer is performed between the first processor 101 and the memory 104 by the bus width AA. Bus connection controller 70 in 101
The first processor 101 and the memory 104
Can be changed so that the data transfer between them is performed with the bus width BB. In this case, the request data and the acknowledge signal are not exchanged because the bus width is not changed.

FIG. 14 shows a data transfer state in a device to be compared with the data processing device according to the present invention.

As shown in FIG. 14, data transfer from A0 to A3 (32 bits × 4) requires four cycles. Normally, when the effective data width is 8 bits, FIG.
As shown in FIG. 5, 32 bits are packed, which requires shift processing and logical OR (mask processing). That is, the data transfer is completed in one cycle, but as shown in FIG. 13, the load on the arithmetic and logic operation unit in the processor increases in order to obtain the shift processing and the logical sum. In the meantime, another processor is connected to the bus BU
S cannot be used.

On the other hand, according to the present embodiment, the bus BUS is divided into two by the bus width control, so that one of the buses is used for data transfer (A0 to A3) by the first processor 101 as shown in FIG. And the other can be used for data transfer (B0-B3) by the second processor 102. That is, data transfer by both processors can be performed simultaneously. This eliminates the need for one processor to wait for the release of the bus right of the other processor, thereby improving data transfer efficiency. In addition, since the bus width is not fixed, as shown in FIG.
The optimum bus width can be set according to the data to be transferred to be performed.

According to the above-described example, the following effects can be obtained.

(1) In the data processing device, the bus BUS is set to 2 by including the bus connection controller 70 capable of changing the correspondence of connection with the external bus according to data exchanged via the external bus. Since it can be used in a divided manner, in other words, one can be used for data transfer by the first processor 101 and the other can be used for data transfer by the second processor 102.
This eliminates the need for one processor to wait for the release of the bus right of the other processor, thereby improving data transfer efficiency.

(2) Since the bus width is not fixed, the optimum bus width can be set according to the data to be transferred, so that the data transfer efficiency can be improved.

Although the invention made by the present inventor has been specifically described above, the present invention is not limited to this, and it goes without saying that various modifications can be made without departing from the gist of the invention.

For example, the bus connection controller 70 can be configured as shown in FIG.

The bus connection controller 7 shown in FIG.
0 is different from that shown in FIG. 2 in that a bus allocation table 706 is provided and the selector 703 is provided.
-0 to 703-n respectively correspond to all bits of the bus BUS. Selectors 703-0 to 703-n
Correspond to all bits of the bus BUS,
A bus assignment table 706 is formed as holding means for holding the bus assignment information. Based on the information held in the bus assignment table 706, each selector 703
In -0 to 703-n, any bit of the bus BUS can be selectively coupled to the bus state controller 60. For this reason, more complicated bus width control is possible as compared with the configuration shown in FIG.

In the memory 104 and the I / O unit 103, the bus monitoring unit included in the bus connection controller is omitted, and data is written directly from the bus master to the bus assignment register 701 and the bus assignment table 706. Is also good.

In the above description, the case where the invention made by the present inventor is mainly applied to a computer system which is a utilization field as a background has been described. However, the present invention is not limited to this, and various data processing is performed. It can be widely applied to equipment.

The present invention can be applied on the condition that it includes at least an input / output port which enables signal exchange between an internal circuit and an external bus.

[0055]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, since the correspondence of the connection with the external bus can be changed according to the data exchanged via the external bus, in the data processing device to which this semiconductor integrated circuit is applied, the external bus is partially connected. Therefore, the external bus can be divided and used, and data transfer by a plurality of bus masters can be performed in parallel, so that data transfer efficiency can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration example of an input / output port in a computer system which is an example of a data processing device according to the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a bus connection controller in the input / output port.

FIG. 3 is a block diagram illustrating a configuration example of the bus connection controller.

FIG. 4 is an explanatory diagram of a format of request data exchanged in the computer system.

FIG. 5 is a block diagram illustrating a configuration example of a memory in the computer system.

FIG. 6 is a block diagram illustrating a configuration example of an I / O unit in the computer system.

FIG. 7 is a block diagram illustrating a configuration example of the computer system.

FIG. 8 is an explanatory diagram of bus division in the computer system.

FIG. 9 is an explanatory diagram of bus division in the computer system.

FIG. 10 is a block diagram illustrating a configuration example of a processor included in the computer system.

FIG. 11 is an explanatory diagram of signal exchange in bus division in the computer system.

FIG. 12 is a diagram illustrating a change in a state of bus width switching in the computer system.

FIG. 13 is an explanatory diagram of a state change of bus width switching in the computer system.

FIG. 14 is an explanatory diagram of data transfer in a system to be compared with the computer system.

FIG. 15 is another explanatory diagram of data transfer in a system to be compared with the computer system.

FIG. 16 is an explanatory diagram of data transfer in the computer system.

FIG. 17 is another explanatory diagram of data transfer in the computer system.

FIG. 18 is a block diagram illustrating another configuration example of the bus connection controller in the computer system.

[Description of Signs] 33 Bus monitoring control unit 34 FIFO buffer unit 35 ID register 36 ID check unit 37 ACK generation unit 38 REQDATA generation unit 50 Input / output unit 60 Bus state controller 70 Bus connection controller 101 First processor 102 Second processor 103 I / O unit 104 memory 701 bus allocation register 702-0 to 702-n selector 705 bus monitoring unit BUS bus

Claims (4)

[Claims] 1. A semiconductor integrated circuit comprising: an internal circuit; and an input / output port capable of exchanging signals between the internal circuit and an external bus, wherein the input / output port is connected via the external bus. A semiconductor integrated circuit, comprising: a bus connection controller capable of changing a correspondence relationship with the external bus according to data exchanged. 2. A semiconductor integrated circuit comprising: an internal circuit; and an input / output port that enables signals to be exchanged between the internal circuit and an external bus. A bus monitoring unit for monitoring; a holding unit for holding bus allocation information taken in through the bus monitoring unit; and a holding unit provided corresponding to a maximum bit width of the external bus; Switch means capable of selectively coupling the configuration bits of the external bus to an internal circuit based on
A semiconductor integrated circuit, comprising: 3. A semiconductor integrated circuit comprising: an internal circuit; and an input / output port that enables signals to be exchanged between the internal circuit and an external bus. A bus monitoring unit for monitoring; a holding unit for holding bus allocation information taken in through the bus monitoring unit; and a holding unit provided corresponding to a maximum bit width of the external bus; Switch means capable of selectively coupling the configuration bits of the external bus to an internal circuit based on
An ID register capable of holding ID information preset for each chip; and an ID checking unit for comparing ID information in register data input from the outside with information held in the ID register. And a bus monitoring control unit for controlling loading of the bus allocation information into the holding unit based on a check result of the ID check unit. 4. A data comprising: a plurality of semiconductor integrated circuits according to claim 1; and an external bus for connecting the plurality of semiconductor integrated circuits so that signals can be exchanged with each other. Processing equipment.