JP2001231994A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine which does not generate a malfunction of a picture pattern display device in the game machine independently provided in each of a main base and the picture pattern display device. SOLUTION: In a pachinko machine 1, after a power except a main base 41 is turned on, when an I/O controller 110 for a peripheral device receives a dummy command from a sub-CPU unit 99, begins to monitor the rise of a min CPU unit 98 and detects a start signal from the main CPU unit 98 in a picture pattern display base 44 provided with the I/O controller 110 between the sub-CPU unit 99 and the main CPU unit 98, the controller informs a sub- CPU 103 of the start signal as the change of level of an ACK signal. The sub- CPU 103 sends a signal to a power base not shown to turn on the power of the main base 41. Therefore, a command from the main base 41 does not generate a malfunction on the picture pattern display base 44.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a game machine such as a pachinko machine, and more particularly, to a game machine in which a main board for controlling a main control of the game machine and a symbol display board for controlling a symbol display device are provided independently of each other. A first control means for controlling a symbol display device on the symbol display board, and a second control means for transmitting and receiving data between the first control means and receiving data from the main board. The present invention relates to a gaming machine provided with control means.

[0002]

2. Description of the Related Art Conventionally, in a game machine, for example, a pachinko machine,
A main board for controlling the gaming machine is provided, and the main board is provided with a CPU.
The control of the symbol display device of the gaming machine, the control of the light emission mode of the illumination, the control of the sound generation, the control of the payout of the game ball, and the like are performed. However, when using a liquid crystal display or the like for the symbol display device, it is necessary to process a huge amount of data on the main substrate in order to display a moving image on the liquid crystal screen. Then, the main board that controls the gaming machine is caused to perform all the controls, and the burden on the main board is increased, so that control may not be completed or the processing speed may be reduced. Therefore, in addition to the main board, a symbol display board for controlling the symbol display device, a payout control board for controlling the payout of the game balls, an electric decoration board for controlling the light emission mode of the illumination of the gaming machine, and controlling the sound generation of the gaming machine. There has been a gaming machine having a configuration in which sound boards and the like are provided independently of each other, and a part of the control performed on the main board is performed by dispersing the control on each board to reduce the burden of controlling the main board. In this case, the main board simply sends a command to identify and display a predetermined symbol to the CPU of the symbol display board, and complicated processing is processed by the CPU of the symbol display board, so that the burden on the main board is significantly reduced. You can now.

On the other hand, the CPU on the symbol display substrate provided independently of the CPU of the main substrate is, for example, a 32-bit type CPU due to the complexity and high definition of the symbol displayed on the symbol display device. A high-performance CPU capable of such high-speed processing is used, and a high-definition moving image is configured to be displayed at high speed on the symbol display device.

[0004]

However, such a 32-bit high-performance CPU has an OS (operating software) in order to process enormous data for controlling the symbol display device at high speed. The program itself becomes complicated. Therefore, a predetermined start-up time is required from when the power is turned on to when the CPU of the symbol display board is started up to a state in which the CPU can operate, because it is necessary to read the OS or the like. On the other hand, the main board with a small processing load may have a simple configuration using, for example, an 8-bit type CPU, and the CPU of the main board rises to a state where it can be operated in a short time. Therefore, immediately after the power is turned on at the same time, the main board rises first and sends a command to the CPU of the symbol display board.
PU has not yet started up. Furthermore, when only one-way traffic from the main board to the symbol display board is permitted in accordance with gaming machine standards, data cannot be transmitted from the symbol display board to the main board. The state of the symbol display substrate could not be determined from the substrate side. Therefore, the CP provided on the main substrate
When data is transmitted directly from U to the CPU provided on the symbol display board, the
When the PU is running, the C provided on the main board is
When data is transmitted from the PU, there is a problem that the activated CPU provided on the symbol display board may malfunction.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. In a gaming machine, a main board for controlling the main control of the gaming machine and a symbol display board for controlling the symbol display device are provided with independent control means. When the control means of the symbol display device is in operation, the command from the main board is not received so that the CP
It is an object of the present invention to provide a gaming machine that does not cause a malfunction of U.

[0006]

In order to achieve the above object, a gaming machine according to the first aspect of the present invention comprises a main board for controlling the main control of the gaming machine and a symbol display board for controlling the symbol display device. An independently provided gaming machine, wherein the symbol display board includes a first control unit for receiving a signal from the main substrate, and a signal from the first control unit. Second control means for transmitting a signal to a display device, wherein the first control means includes monitoring means for monitoring a rise of the second control means, and detects rise of the second control means. Until the signal is transmitted from the main board, the signal is not transmitted to the second control means.

In the gaming machine having this configuration, the main board for controlling the main control of the gaming machine and the symbol display board for controlling the symbol display device are provided with independent control means, respectively, and the symbol display device provided on the symbol display substrate is provided. When the second control means for transmitting the signal from the main board is activated, the first control means of the symbol display device for receiving the signal from the main board does not transmit the command from the main board to the second control means. Therefore, there is no possibility that the second control means malfunctions and displays an undesired screen on the display screen of the symbol display device.

A game machine according to a second aspect of the present invention is a game machine in which a main board for controlling the main control of the game machine and a symbol display board for controlling the symbol display device are provided independently of each other. The symbol display substrate includes a first control unit that receives a signal from the main substrate, a second control unit that transmits a signal for the symbol display device, the first control unit, and the second control unit. A third control means capable of transmitting and receiving signals bidirectionally with the control means, and the third control means is transmitted from the first control means after the rise of the first control means Upon receiving the start signal, the control unit starts transmitting a notification signal of a predetermined level to the first control unit, and includes a monitoring unit, and starts monitoring the rising of the second control unit by the monitoring unit. The second control means is activated by the monitoring means. When it is detected that the rose is,
Changing the level of the notification signal transmitted to the first control means, wherein the first control means, when the notification signal transmitted from the third control means has a predetermined level, Is not transmitted to the second control means.

In the gaming machine having this configuration, the main board for controlling the main control of the gaming machine and the symbol display board for controlling the symbol display device are each provided with independent control means, and the symbol display device provided on the symbol display substrate is provided. When the second control means for transmitting a signal is activated, the first control means of the symbol display board for receiving a signal from the main board transmits a command from the main board to the second control means.
Is not transmitted to the second control means, the second control means does not malfunction and an undesired screen is not displayed on the display screen of the symbol display device. Further, third control means capable of transmitting and receiving signals in both directions is provided between the first control means and the second control means, and the third control means is provided with a monitoring means, and the second control means is provided. The start of monitoring of the rising edge is started, and when this is detected, it is notified to the first control means, so that the load on the first control means can be reduced.

According to a third aspect of the present invention, in addition to the configuration of the gaming machine according to the second aspect, the start signal transmitted from the first control unit to the third control unit is the same as that of the third embodiment. A signal in the same format as a command transmitted from the first control means to the third control means for the symbol display device, and the symbol display device is received even when the signal is received by the second control means. This is a dummy command which does not affect the control of the dummy command.

In the gaming machine having this configuration, in addition to the function of the gaming machine described in claim 2, a start signal transmitted from the first control means to the third control means is transmitted from the first control means to the third control means. Since it is possible to use a signal of the same format as the command transmitted to the third control means for the symbol display device, the first control means can transmit a start signal under the same control as the normal control, and Even when the activation of the second control means is completed, no malfunction occurs.

According to a fourth aspect of the present invention, in addition to the configuration of the gaming machine according to any one of the first to third aspects, the first control means is activated until the second control means is activated.
Is displayed on the symbol display device to notify that it is on standby.

In the gaming machine having this configuration, in addition to the function of the gaming machine according to any one of claims 1 to 3, the first control means controls the symbol display board until the second control means is activated. Since a display indicating that the player is on standby can be displayed on the symbol display device, an undesired screen is not displayed to the player.

According to a fifth aspect of the present invention, in addition to the configuration of the gaming machine according to any one of the first to fourth aspects, a condition that activation of the second control means is completed is provided. The main substrate is activated.

In the gaming machine having this configuration, in addition to the operation of the gaming machine according to any one of claims 1 to 4, the main board is activated after the activation of the entire symbol display board is completed. Therefore, the signal from the main board is reliably received by the symbol display board, and no malfunction occurs.

According to a sixth aspect of the present invention, in addition to the configuration of the gaming machine according to any one of the first to fifth aspects, the first control means activates the first control means. Is completed, the reception inhibition flag provided in the first control means is turned on, the reception of the signal from the main board is inhibited based on the reception inhibition flag, and the activation of the second control means is started. The reception inhibition flag is turned off in association with the completion, and reception of a signal from the main board is permitted.

In the gaming machine having this configuration, in addition to the operation of the gaming machine according to any one of claims 1 to 5, when the activation of the first control means is completed, the reception inhibition flag provided here is reset. Is turned on, prohibits reception of a signal from the main board based on the reception prohibition flag, and turns off the reception prohibition flag in association with the completion of the activation of the second control means, thereby receiving a signal from the main board. To allow, the first control means can receive a signal from the main board at a timing at which no malfunction occurs.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a pachinko machine 1 as a preferred embodiment of a gaming machine according to the present invention will be described with reference to the drawings.

First, the mechanical configuration of the pachinko machine 1 will be described with reference to the drawings. FIG. 1 is a front view of the pachinko machine 1. As shown in FIG. 1, a substantially square game board 2 is provided in an upper half portion of the front of the pachinko machine 1, and a substantially circular game area 4 surrounded by a guide rail 3 is provided on the game board 2. Is provided. Pachinko machine 1 game board 2
A lower plate 6 for supplying a game ball to a launcher (not shown) and receiving a prize ball is provided below the lower plate, and a lower plate 6 for receiving a prize ball is provided immediately below the upper plate 5. A firing handle 7 is provided on the right side of the lower plate 6.

Next, the mechanical structure of the game board 2 is shown in FIG.
This will be described with reference to FIG. FIG. 2 is a front view of the game board 2 of the pachinko machine 1. The game board 2 is provided with a substantially circular game area 4 surrounded by a guide rail 3. At a substantial center of the game area 4, a special symbol display device 8 having a liquid crystal screen is provided. In addition, an illuminated windmill 9 is provided on the upper right of the special symbol display device 8, and an illuminated windmill 10 is also provided on the upper left. Further, a normal symbol start gate 11 is provided on the right side of the special symbol display device 8, and an ordinary symbol start gate 12 is provided on the left side.

A special symbol starting electric accessory 15 is provided below the special symbol display device 8, and a special winning opening 16 is provided below the special symbol starting electric accessory 15. . Further, a winning opening 19 is provided below the ordinary symbol starting gate 11, and a winning opening 20 is provided below the ordinary symbol starting gate 12. Further, a stage 21 on which a game ball can be temporarily mounted is provided substantially below the vertical direction in the lower part of the special symbol display device 8. A game ball passage opening 22 is provided on the right shoulder of the special symbol display device 8, and a game ball passage opening 23 is also provided on the left shoulder of the special symbol display device 8. The game balls passing through these game ball passage openings 22 and 23 appear on the stage 21 through the inside of the special symbol display device 8 (so-called warp zone). The game balls appearing on the stage 21 are temporarily placed on the stage 21 and fall toward the special symbol starting electric accessory 15 provided immediately below the stage 21.

Above the special symbol display device 8, a normal symbol display device 24 is provided so that a symbol such as a one-digit number or a one-letter alphabet can be displayed. Further, a special symbol starting reservation unit 25 composed of two LEDs is provided on each of the right and left sides of the ordinary symbol display device 24 to display the number of so-called reserved balls that have won the special symbol starting electric accessory 15. Can be. Also, between the special symbol display device 8 and the ordinary symbol display device 24, 4
There is provided a normal symbol start reservation unit 26 composed of a plurality of LEDs, and this normal symbol start reservation unit 26 can display the so-called reserved ball number of game balls that have passed the normal symbol start gates 11 and 12. In addition, in addition to the above, the game board 2 is provided with out ports, various illumination lamps, windmills, a large number of obstacle nails, and the like at predetermined positions.

Next, the structure and display screen of the special symbol display device 8 will be described with reference to FIG. FIG. 3 is a front view of the special symbol display device 8. As shown in FIG. 3, on the liquid crystal screen of the special symbol display device 8, three special symbols of a first stop symbol L1, a second stop symbol L2, and a third stop symbol L3 can be displayed side by side in a horizontal direction. ing. In addition, the special symbol display device 8 performs the above-described first stop symbol L1 and second stop symbol L
2. Not limited to the display of the special symbol of the third stop symbol L3, a moving image, a message, and the like can be displayed instead of the special symbol or together with the special symbol. In addition,
It goes without saying that the special symbol display device 8 can use not only a liquid crystal display device but also various display devices such as a CRT, an LED, and a plasma display.
In addition, the arrangement of the display of the special symbols is not limited to the horizontal direction, and the fluctuation direction is not limited to the vertical direction. .

The first stop symbol L1 and the second stop symbol L
2. In the gaming machine 1 according to the present embodiment, as the symbols displayed on the second and third stop symbols L3, "11,000" imitating a mahjong tile,
"20,000", "30,000", "40,000", "50,000", "60,000",
There are twelve types of patterns: "Seven thousand", "eight hundred", "90,000", "white (the same applies to the following text)", "Hatsu", and "medium". Wins, and three symbols of the first stop symbol L1, the second stop symbol L2, and the third stop symbol L3 are arranged in a predetermined combination, for example, the same specific number, character, symbol, or the like ( For example, FIG.
(When three "Seven thousand" shown in Fig. 3) are collected).

Of the twelve symbols, “Sanma”, “Five thousand”, “Seven thousand”, “White”, “Hatsu”, and “Medium” are probability variation symbols (specific jackpot symbols), When a particular size is won by the lottery means, any of these symbols is displayed with the same symbols aligned with the first stop symbol L1, the second stop symbol L2, and the third stop symbol L3, and the probability variation is entered. Is notified to the player, and the probability of drawing the next big hit is changed to be higher. The jackpot probability is, for example, 31/76 in the normal state, and 6 in the probability fluctuation state.
It is 8.1, but is not necessarily limited to this value. In addition, "10,000", "20,000", "40,000", "60,000", "80,000", and "90,000" are non-stochastic fluctuation symbols (non-specific jackpot symbols or normal symbols).

Next, referring to FIG. 4, the mechanism on the back of the pachinko machine 1 will be described. FIG. 4 is a rear view of the pachinko machine 1. As shown in FIG. 4, a board box 31 is provided in a lower portion of the back of the pachinko machine 1, and the board box 3 is provided.
Above 1, a center cover 32 is provided.
In the board box 31, a main board 41 for controlling the main control of the pachinko machine 1 and a power supply board 42 for supplying power to each board are provided.
And a sound board 43 for controlling sound generation of the gaming machine. Further, in the center cover 32, a symbol display board 44 for controlling the special symbol display device 8, a payout control board 45 for controlling the payout of game balls, and an illumination for controlling a light emission mode of the illumination of the gaming machine. A substrate 46 is provided. The relay board 4 is provided below the center cover 32.
7 are provided. Further, on the right side of the center cover 32, a prize ball payout device 49 is provided.

Next, an electric circuit configuration of the pachinko machine 1 according to the present embodiment will be described with reference to FIG. FIG.
FIG. 2 is a block diagram illustrating an electric circuit configuration of the pachinko machine 1. The control unit 40 of the pachinko machine 1 includes a main board 41, a power board 42, a sound board 43, a symbol display board 44, a payout control board 45, an illumination board 46, and a relay board 47. Is provided with a main board CPU unit 50 that performs various processes according to. This main board C
The PU unit 50 includes a main board C for performing various arithmetic processing.
A PU 51, a main board RAM 52 for storing flags, counter values, data, programs, and the like, and a main board ROM 53 for storing a control program, data of various initial values, table data, and the like are provided. However, in the present embodiment, one LSI
It is molded as one.

An interrupt reset circuit 57 is connected to the main board CPU unit 50.
An interrupt signal is given to the main board CPU 51 every 0.002 seconds (hereinafter abbreviated as “2 ms”). The main control, which is the overall control of, is performed. As an example of the main board CPU 51,
An 8-bit CPU is used.

The main board 41 includes a sound board 43, a symbol display board 44, a payout control board 45, an illumination board 46, and a relay board 4.
An I / O interface 54 for transmitting and receiving data signals to and from the communication device 7 is provided. The I / O interface 54 is connected to an output port 55 for outputting information of the pachinko machine 1 to a game center management computer (not shown). A main CPU 100 and a sub CPU 103 are mounted on the symbol display board 44 (see FIG. 6), and the power supply board 42, the sound board 43, and the symbol display board 4
4. Each of the payout control board 45 and the illuminated board 46 also has a CP
U (not shown) is mounted. The main board 41 controls the main control of the pachinko machine 1, the power supply board 42 supplies a direct current to each board, the sound board 43 controls the sound generation of the pachinko machine 1, and the symbol display board 44 has a special symbol display. The device 8 is controlled, the payout control board 45 controls the prize ball payout device 49, the illuminated board 46 controls the light emission mode of each illuminated device of the pachinko machine 1, and the relay board 47 is connected to the wiring of each sensor. Is relaying.

The illuminated board 46 has a normal symbol start holding section 2
6, a special symbol storage number display LED 59 constituting the special symbol start reservation unit 25.
0, other LEDs 62 and illumination lamps 63 are connected, a special symbol display device 8 is connected to the symbol display board 44, a speaker 48 is connected to the sound board 43, and a payout control board. 45 is connected to a prize ball payout device 49, and further, to the relay board 47, a normal symbol display device 24, a special winning opening opening solenoid 70, a special symbol starting electric accessory opening solenoid 71, a special symbol starting electric accessory. 15 (see FIG. 2), a starting port switch 72 for detecting a game ball that has won a prize, a normal symbol operating switch 73 for detecting a game ball passing through the normal symbol starting gates 11 and 12 (see FIG. 2), and a large winning port 16 (see FIG. 2). A V switch (prize detection mechanism) 74 for detecting a game ball that has won a V zone in the V zone (see FIG. 2).
A count switch 75 (winning detection mechanism) for counting the number of gaming balls that have won the large winning opening 16, winning openings 19 and 20
(See FIG. 2) and a winning opening switch 7 for detecting a winning ball collected in a winning ball collecting section by a guide passage (not shown).
6 (prize detection mechanism).

The power supply board 42 includes a main board 41, a sound board 4
3, symbol display board 44, payout control board 45, illumination board 4
6. Each of them is connected to the relay board 47 to supply a stabilized DC current. The main substrate 4
1, 12 V DC is supplied to the sound substrate 43, the payout control substrate 45, the illumination substrate 46, and the relay substrate 47, and 5 V DC and 12 V DC are supplied to the symbol display substrate 44. Further, 24 V AC is supplied to the power supply board 42. The power supply board 42 is provided with a rectifier composed of a silicon diode bridge (not shown), a smoothing circuit composed of an electrolytic capacitor, a stabilization circuit composed of a regulator IC, and the like.
V can be supplied. Although not particularly shown in FIG. 5, the main board 41, the power board 42, and the sound board 4
3, symbol display board 44, payout control board 45, illumination board 4
6. The relay boards 47 are all connected by ground lines. In addition, the power supply board 42 includes a switch (not shown) for each board so that a power supply current can be individually applied to each board.

As will be described later in detail, the power supply board 42 is turned on simultaneously with the symbol display board 44, the sound board 43, the payout control board 45, the illumination board 46, and the relay board 47. The sub CPU 1 of the symbol display board 44 that has detected the completion of the activation of the main CPU 100 of 44
On the basis of a predetermined signal from the control circuit 03, a switch of the main board 41 is turned on to supply a power supply current. With this configuration, the main substrate C of the main substrate 41
When the activation of the PU 51 is completed, the activation of the sound board 43, the symbol display board 44, the payout control board 45, the illumination board 46, and the relay board 47 has been completed, and the signal from the main board 41 may malfunction. You can receive without.

Next, referring to FIG.
And the connection relationship between the symbol display substrate 44, the main substrate 41 and the special symbol display device 8 will be described. FIG. 6 is a block diagram showing the structure of the symbol display substrate 44 and the connection relationship between the symbol display substrate 44, the main substrate 41, and the special symbol display device 8. As shown in FIG. 6, the symbol display substrate 44 is provided with a sub CPU 103 which is an 8-bit CPU. The sub CPU 103 includes a main board CP of the main board 41.
U51 to I / O interface 54, bus line 9
5, an address / data signal 201 for transmitting command data such as fluctuation pattern designation command data, stop symbol designation command data, symbol stop command data, and power-on (first morning) appearance setting command data, and a strobe signal 200. (See FIG. 7) is transmitted in one direction. The sub CPU 103 has a sub RAM for temporarily storing the received address / data signal 201 as data.
A sub-ROM 105 storing a control program and various data is connected. The sub CPU
The 103, the sub RAM 104, and the sub ROM 105 may have independent configurations, or may be configured on one chip. Here, a sub-CPU 103, a sub-RAM 104, and a sub-ROM 105 configured as one sub-chip as the sub-CPU unit 99 are used. Since the sub CPU 103 does not perform processing such as image data expansion, the processing load is smaller than that of the main CPU 100, and an 8-bit type CPU is used, and a program for controlling the sub CPU 103 itself is small. For this reason, the power supply is turned on immediately after the power is turned on, and the startup is completed.

The symbol display substrate 44 has an ASIC (Application) configured as a gate array.
Specific Integrated Circ
ui) peripheral I / O controller 110
Are connected to the sub CPU unit 99 via the bus line 111 so as to be capable of bidirectional transmission and reception. An I / O controller 114 is connected to the peripheral device I / O controller 110 via a low-speed bus 113 so as to be capable of bidirectional transmission and reception. Also, I / O for peripheral devices
An interrupt connection line is connected from the controller 110 to the I / O controller 114 without passing through the low-speed bus 113. This is transmitted to the controller 114. The I / O controller 114 is connected to the main CPU 100 via a high-speed bus 115 so that signals can be transmitted and received in both directions.

In the present embodiment, the main CPU 100 is constituted by a 32-bit type CPU because it is necessary to process data at high speed and in large quantities.
This is suitable for a process of displaying a color high-definition moving image on the screen of the liquid crystal 121 of FIG. However, this 32-bit main CP
In order to operate the U100, predetermined operating software (OS) that can perform complicated processing is required. At startup, it is necessary to read out the OS stored in the main ROM 102 and load it into the main RAM 101. Since the OS is complicated, the data amount is large, and therefore, even if the power is turned on, the OS cannot be operated immediately, and a predetermined startup time is required. After the power is turned on, even if a command from the main board 41 is received, processing based on the command cannot be executed until the start is completed, and a signal may be received in an unstable state during the start. Then, in some cases, a malfunction may occur. When the main CPU 100 and the sub CPU 103 are powered on at the same time, the sub CPU 1
03 is 8-bit and rises quickly, so the sub CPU1
03 rises first.

Note that the main CPU 100 requires a relatively large storage capacity of the RAM in order to execute the processing, so that the internal memory alone is insufficient and an external memory is required. In particular, an external memory is indispensable for processing image data, and includes a relatively large-capacity main RAM 101. Further, a relatively large-capacity main ROM 102 for storing an OS and image data is provided, and these are configured as microcomputers by bus lines including an address bus, a data bus, and a system bus. Note that the main CPU 10
0, the main RAM 101, and the main ROM 102 do not necessarily have to be configured in one place as long as they can exchange signals with each other, and may have independent configurations.
1 may be connected to the graphic engine 116. Of course one chip or one
It may be configured on a board. In the present embodiment, for simplicity, the main CPU
PU 100, main RAM 101, and main ROM 102
Is used for one chip.

The I / O controller 114 is connected to the high-speed bus 1
15 and also connected to the graphic engine 116. Further, the graphic engine 1 is transmitted from the I / O controller 114 without passing through the high-speed bus 115.
16 is provided with a bus line 122 which is a connection line connected to the bus 16. Therefore, the signal from the sub CPU 103 is
The data can be sent directly to the graphic engine 116 regardless of the rise of the PU 100 and without passing through the general-purpose high-speed bus 115.

The main CPU unit 98 is connected to the graphic engine 116 and sends out predetermined image data to the graphic engine 116 based on the command data sent from the main board 41. The graphic engine 116 is connected to a liquid crystal controller 120, and the liquid crystal controller 120 is connected to a liquid crystal 121 of the special symbol display device 8. The graphic engine 116 sends a control signal to a liquid crystal controller 120 which is a driver based on the image data.
Send to 1. The liquid crystal 121 displays a symbol based on this signal.

Next, control of the special symbol display device 8 will be described. In the pachinko machine 1 of the present embodiment, the control of the special symbol display device 8 is based on the main board CP of the main board 41.
The U51 does not transmit the drawing data for controlling the graphic engine 116, but the main board CPU 51 sends to the sub CPU 103 of the symbol display board 44 the variation pattern designation command data, the stop symbol designation command data, the symbol stop command. At the time of turning on the power (in the morning), each command data relating to the symbol display, such as the appearance setting command data, is transmitted by an address / data signal 201 (see FIG. 7). The information is temporarily stored in the RAM 104.

Then, the sub CPU 103 has a sub RAM
Analyzing the received command data related to the symbol display such as the fluctuation pattern designation command data, the stop symbol designation command data, the symbol stop command data, and the power setting (first morning) appearance setting command data stored in the memory 104 The information about the symbol is output to a symbol inspection device (not shown) via the peripheral device I / O controller 110, and the main CPU 100 of the symbol display board 44 stores the sub RAM1.
04, the change pattern designation command data of the symbol displayed on the first stop symbol L1, the second stop symbol L2, and the third stop symbol L3, the stop symbol designation command data,
The main CPU 100 transmits the command data such as the symbol stop command data and the power setting (first morning) appearance setting command data, and the main CPU 100 executes the main RO based on the data.
Necessary data from M102 to graphic engine 11
6 and the graphic engine 116 generates specific drawing data and outputs it as a control signal to the liquid crystal controller 1.
20, the liquid crystal controller 120 is configured to transmit a drive signal of a large current based on the control signal so that the pattern is displayed on the liquid crystal 121. That is, the pachinko machine 1 of the present embodiment is a so-called black box compatible machine.

In this embodiment, the sub CPU 10
3 corresponds to the first control means in the claims, and the main CPU 100 corresponds to the second control means.
The / O controller 110 corresponds to the third control means.

Next, the main board 41 and the sub CPU unit 9
9 and peripheral device I / O controller 110 and main CP
The exchange of signals with U100 will be described. FIG. 7 is a diagram schematically showing the exchange of signals among the main board 41, the sub CPU unit 99, the peripheral device I / O controller 110, and the main CPU 100.

First, the I / O interface 54 of the main board 41 is connected to the sub CPU unit 99 of the symbol display board 44.
And a bus line 95 (see FIG. 6).
An address / data signal 201 and a strobe signal 200 are sent from the main board 41 to the symbol display board 44 in one way. Among these, the address / data signal 201 is a signal for transmitting command data, specifically, address and data alternately. In the present embodiment, the address / data signal 201 is “00H to FFH”.
The main ROM 102 stores, in the main ROM 102, a hexadecimal digit and a letter "H" representing a hexadecimal number. The type of processing is specified by the preceding command data corresponding to the address, and the specific content is specified by the subsequent command data corresponding to the data. Specified by data. Also, the strobe signal 200
Is a synchronizing signal for synchronizing the signal transmission timing, and the sub CPU unit 99 transmits the timing at which the address / data signal 201 transmitted from the main board side 41 is transmitted.
, And a control signal for controlling the timing of reception by the sub CPU 103 (see FIG. 6). That is, the main substrate 4
In this embodiment, the symbol 1 and the symbol display board 44 cannot communicate in both directions.
Since only the transmission in the direction is possible, the handshake transfer method cannot be adopted, and the sub CPU which receives the address / data signal 201 transmitted from the main board 41 side is used.
The reception timing of the signal 103 (see FIG. 6) is controlled by the strobe signal 200.

As described above, the address / data signal 2 is adjusted while the reception timing is adjusted by the strobe signal 200.
01, the sub CPU unit 99 sends the address / data signal 3 to the peripheral device I / O controller 110.
01, address / data switching signal (A / D in FIG. 7)
The peripheral I / O controller 110 transmits an ACK (acknowledge) signal 304 and a CLK (clock) signal 305 to the sub CPU unit 99. I have. Further, the peripheral device I / O controller 110 transmits an address / data signal 401, an address / data switching signal (denoted as an A / D switching signal in FIG. 7) 402, and an enable signal 403 to the main CPU unit 98. On the other hand, the main CPU unit 98 transmits an ACK signal 404, a CLK signal 405, and a start signal 406 to the peripheral device I / O controller 110.

Address / data signals 201, 301, 4
01 is basically a common signal and the I / O of the main board 41
From the interface 54 to the sub CP of the symbol display board 44
From the U unit 99 to the peripheral device I / O controller 11
0 through the main CPU unit 9 of the symbol display board 44
8 is a signal waveform representing data for specifying an address and data for specifying a command to be executed, which are sent to FIG. Also,
Address / data signal 201 transmitted from main board 41
And address / data signal 301 sent from peripheral CPU I / O controller 110 to sub CPU unit 99
Are basically the same, but differ in that a dummy command described later is not included. Specific command data includes, for example, variation pattern designation command data from “designation of variation pattern 1” to “designation of variation pattern 25”,
From "1st stop symbol 1 designation" to "1st stop symbol 12 designation"
First stop symbol designation command data, second stop symbol designation command data from "second stop symbol 1 designation" to "second stop symbol 12 designation", and "third stop symbol designation" from "third stop symbol 1 designation" The third stop symbol designation command data of "designation of symbol 12", the first stop symbol designation command data at power on of "designation of first stop symbol 12 at power on" from "designation of first stop symbol 1 at power on", Power-on second stop symbol designation command data from "power-on second stop symbol 1 designation" to "power-on second stop symbol 12 designation" and "power-on third stop symbol 1 designation" to "power supply There is a power-on third stop symbol designation command data and the like of "Power-on third stop symbol 12 designation".

Here, the address / data signals 201, 30
The contents of each command data transmitted by the server 1 and 401 will be described in detail. Each command data is composed of preceding command data and succeeding command data. In the preceding command data, one command is composed of one byte. Specifically, one byte of information is divided into four bits, and each of the four bits is represented by a hexadecimal number.
It consists of a combination of two-digit numbers or alphabets in hexadecimal notation, and "H" is added to the end to indicate hexadecimal data. Therefore, from "00H" to "FF
H "can be configured. Also,
The succeeding command data has the same configuration as the preceding command data. Therefore, one set of signals is composed of two bytes. Of course, each command data may be configured such that one command is composed of one byte including the preceding command data from "0H" to "FH" and the succeeding command data from "0H" to "FH". . If each command data is configured so that one command is composed of one byte, there is an advantage that the transmission and reception time of the command data can be reduced.

Here, the address / data signals 201, 30
As an example of 1,401, variation pattern designation command data will be described. The variation pattern designation command data is from “designation of variation pattern 1” to “variation pattern 25”.
This variation pattern designation command data is stored in the main board ROM 53 of the main board 41 and, when transmitted to the symbol display board 44, is temporarily stored in the sub RAM 104 of the symbol display board 44. Is stored.
Here, when the variation pattern 1 is designated, the preceding command data is “80H”, and the following command data is “01H”.
H, when the variation pattern 2 is specified, the preceding command data is “80H”, the subsequent command data is “02H”, and when the variation pattern 15 is specified, the preceding command data is “80H”, When the command data is “0FH” and the variation pattern 25 is similarly specified, the preceding command data is “80H” and the succeeding command data is “19H”.

The address / data signals 201, 30
In the case of the first stop symbol designating command data of another example of 1,401, the first stop symbol designating command data is
From "1st stop symbol 1 designation" to "1st stop symbol 12 designation"
The first stop symbol designation command data received from the main board CPU 51 is stored in the sub RAM 104 of the symbol display board 44. Here, when the first stop symbol 1 is designated, the preceding command data is “81H” and the succeeding command data is “01H”.
When the first stop symbol 2 is designated, the preceding command data is “81H” and the following command data is “02H”.
H, and when the first stop symbol 12 is designated, the preceding command data is “81H” and the following command data is “0CH”. That is, the preceding command data specifies the type of data such as the variation pattern specifying command data and the first stop symbol specifying command data, and the succeeding command data specifies the type of the data.

Therefore, if the data is in the format of “00H to FFH”, the address / data signal 201 by the sub CPU 103, the address / data signal 301 by the peripheral device I / O controller 110, and the address / data signal 301 by the main CPU 100. It is recognized as command data transmitted by the data signal 401 and is treated as such.

Next, the dummy command will be described.
The dummy command is “FF” as the preceding command data.
H ", a set of command data similarly expressed in the form of" FFH "as subsequent command data. In other words, the dummy command is the same as the command data “00H”
~ "FFH", the sub CPU 10
3. I / O controller 110 for peripheral devices and main CP
In U100, address / data signals 201, 3
01 and 401 are recognized as command data. However, even if the format is “00H” to “FFH”, the content does not include any effective instruction. Therefore, the sub CPU unit 99 and the peripheral device I / O controller 1
10, and the main CPU 100, like the command data by the normal address / data signals 301 and 401,
When receiving the dummy command, the peripheral device I / O controller 110 and the main CPU 100
Unit 99 or I / O controller 110 for peripheral devices
ACK signals 304 and 404 are transmitted. However,
Since it is a meaningless command as a command, it does not perform any operation, so that a malfunction does not easily occur. In addition,
Unlike the command data by the normal address / data signal 301, when the dummy command transmitted from the sub CPU 103 is received, the peripheral device I / O controller 110 ACK signal 3 to be transmitted to CPU 103
04 starts transmission once, the start signal 406 from the main CPU 100 is transmitted to the peripheral device I / O controller 11.
The ACK signal 304 is continuously transmitted until 0 is received.

As shown in FIG. 7, the address / data switching signal 302 is transmitted from the sub CPU unit 99 of the symbol display board 44 to the peripheral device I / O controller 110. The address / data switching signal 402 is transmitted from the peripheral device I / O controller 110 to the symbol display board 44.
To the main CPU unit 98. These address / data switching signals 302, 402
The address / data signals 301 and 401 are transmitted together with the data signals 301 and 401, and indicate that the current command is transmitting the preceding command data which is the address data of the address data and the command data. Signal. As shown in FIG. 14, while the address / data switching signals 302 and 402 are HIGH, the address data signal of the address / data signals 301 and 401 described above, specifically, the preceding command data is transmitted. . When the preceding command data is transmitted, the address / data switching signals 302 and 402 become LOW, and the transmission of the preceding command data stops.

As shown in FIG. 7, the enable signal 303 is transmitted to the sub CPU unit 99 of the symbol display board 44.
Is transmitted from the I / O controller 110 to the peripheral device I / O controller 110. The enable signal 403 is a signal transmitted from the peripheral device I / O controller 110 to the main CPU unit 98 of the symbol display board 44. The enable signals 303 and 403 are transmitted together with the address / data signals 301 and 401, and the address / data signals 301 and 401 carry the following command which is the command data of the address data and the command data at present. This signal indicates that data is being transmitted. These enable signals 303 and 40
3 is HIGH while the address / data signal 30
The signal of the data among the data items 401 and 401, specifically, the subsequent command data is transmitted. The peripheral device I / O controller 110 and the main CPU unit 98 of the symbol display board 44 start receiving the subsequent command data from the sub CPU unit 99. When the transmission of the subsequent command data is completed, the enable signals 303 and 403 become LOW.
, And the transmission of the subsequent command data stops.

As shown in FIG. 7, the ACK (acknowledge) signal 304 is transmitted from the sub CPU unit 99 of the symbol display board 44 to the peripheral device I / O controller 110 in the same symbol display board 44 by preceding command data and subsequent command data. This is a signal indicating the reception of a command for the address / data signal 301 sent from the peripheral device I / O controller 110 to the sub CPU unit 99 when a command based on a pair of address / data signals 301 including data is transmitted. Also, the ACK signal 404 is transmitted to the main CPU unit 98 in the symbol display board 44 by the peripheral device I / O controller 110 by a pair of address / data signals 40 composed of preceding command data and succeeding command data.
1 is a signal indicating reception of a command corresponding to an address / data signal 401 sent from the main CPU unit 98 to the peripheral device I / O controller 110 when the command 1 is transmitted. The ACK signals 304 and 404 are transmitted at the time when the reading of the subsequent command data is completed by the peripheral device I / O controller 110 or the main CPU 100. When the command data is received, the ACK signals 304 and 404 are set to HIGH. Then, the ACK signals 304, 40
4 keeps the HIGH state for a predetermined time and
3 to continue oscillating. The peripheral device I / O controller 1 that has received the dummy command
In the case of 10, the ACK signal 304 remains at H level until the start signal 406 from the main CPU 100 is received as described above.
Maintain the state of IGH.

CLK (clock) signals 305, 405
Provides a reference time for controlling the operations of the main CPU 100, the peripheral device I / O controller 110, and the sub CPU 103, and is oscillated by a clock generator, which is a crystal oscillator built in or separately provided in the main CPU 100, and C for I / O controller 110
The LK signal 405 is transmitted from the peripheral device I / O controller 110 to the sub CPU 103.
5 is transmitted. Therefore, the main CPU 100, the peripheral device I / O controller 110, and the sub CPU 103
(See FIG. 6) operates by sharing the signal period of the clock signals 305 and 405.

Next, control when the power of the pachinko machine 1 configured as described above is turned on will be described with reference to FIGS. Here, FIG. 10 is a flowchart showing the flow of processing when the power is turned on, and FIG.
9 is a flowchart showing the details of an initialization process s3. FIG. 12 is a time chart showing the state of each part when the power of the ordinary pachinko machine 1 is turned on. FIG.
FIG. 4 is a timing chart of each signal when the power is turned on.

Hereinafter, description will be made with reference to the flowchart shown in FIG. First, the power is turned on to the symbol display board 44 (FIG. 10: when the power is turned on), and when the activation of the sub CPU 103 is completed, first, the sub RAM 104 of the symbol display board 44 is
(Step 1 (hereinafter, step is abbreviated as s1)), and this R
If AM pattern check is OK (s1: Ye
s) The processing shifts to normal processing (to normal processing).

On the other hand, if the RAM pattern check is not OK (s1: No), the RA
M clear is performed (s3), and initialization processing is performed (s5). In the initialization process (s5), first, as shown in FIG.
By causing the graphic engine 116 to interrupt the data for displaying “Please wait” stored in the sub ROM 105 via the O controller 110 and the I / O controller 114, the liquid crystal 12 of the special symbol display device 8
"Please wait" is displayed on the screen 1 (see FIGS. 6 and 9). During this time, even if data to be displayed is sent from the main CPU 100, this data is masked so as not to be displayed. This control prevents an undesired display due to a malfunction that occurs during the activation of the main CPU 100.

When "Please wait" is displayed on the screen of the liquid crystal 121 (s51), the sub RAM 104 is displayed.
Of the preceding dummy command “F”
FH ”is stored (s53), and the subsequent dummy command“ FF ”is similarly stored in the command communication buffer 2 of the sub RAM 104.
H ”is stored (s55). Further, a command reception prohibition flag (not shown) of the sub RAM 104 is set to “1” indicating that command reception is prohibited (s57).
Command reception prohibition flag is ON
While (1) is set, the sub CPU unit 99 prevents the command by the address / data signal 201 transmitted from the main board 41 via the I / O interface 54 from being received. In other words, even if the address / data signal 201 is transmitted from the main board 41 to the sub CPU 103, the sub CPU 103
Reads the command reception prohibition flag of No. 4 and turns on the flag
In the case of ("1"), the reception of the command by the address / data signal 201 is prevented. In addition, sub R
AM104 command reception prohibition flag is OFF
("0"), the sub CPU unit 99 turns off the command reception prohibition flag in the sub RAM 104.
("0"),
A command based on the address / data signal 201 transmitted from the main board 41 via the I / O interface 54 is received. Turn on command reception inhibition flag
Is completed (s57), the initialization process (s5) ends, and the process returns to the main routine shown in FIG. 10 (initialization ends).

Next, the preceding command processing is performed (s7). In the preceding command processing (s7), a preceding dummy command is transmitted from the sub CPU 103 to the peripheral device I / O controller 110 by the address / data signal 301 (FIG. 7). In this case, the address / data switching signal 302 is simultaneously transmitted to identify that the address / data signal 301 is the preceding command data. Subsequently, subsequent command processing is performed (s8). In the subsequent command processing (s8), the sub CPU 103 transmits a subsequent dummy command to the peripheral device I / O controller 110 by the address / data signal 301 (FIG. 7). In this case, the enable signal 303 is transmitted simultaneously and the address / data signal 301 is transmitted.
Is the following command data.

Next, the sub CPU 103 sets the peripheral device I
ACK signal 304 from I / O controller 110 is LOW
The level is read out (s11). When the address / data signal 301 is received by the peripheral device I / O controller 110, the peripheral device I / O controller 11
The ACK signal 304 (see FIG. 7) transmitted from 0 to the sub CPU unit 99 becomes HIGH level, and the ACK signal maintained at the HIGH level for the sub CPU unit 99 by the flip-flop circuit of the peripheral device I / O controller 110. Continue sending signal 304. And AC
When the activation signal 406 (see FIG. 7) is transmitted from the main CPU unit 98 to the peripheral device I / O controller 110 in a state where the K signal 304 is maintained at the HIGH level, the peripheral device I / O controller 110 receiving the start signal 406 (see FIG. The O controller 110 transmits the AC signal transmitted to the sub CPU unit 99.
The level of the K signal 304 is lowered to LOW. Therefore, when the main CPU unit 98 transmits the activation signal 406,
That is, when the activation of the main CPU 100 is completed, ACK
The level of the signal 304 becomes LOW. That is, the sub CP
U103 is the A of the peripheral device I / O controller 110.
If the CK signal 304 is periodically received at regular intervals, the rise of the main CPU 100 can be detected, so that the sub CPU 103 does not need to constantly monitor the peripheral device I / O controller 110 or the main CPU 100. Therefore, the control burden of the sub CPU 103 can be significantly reduced.

When the ACK signal 304 is HIGH (s11: No), the sub CPU 103 can perform other processing at a certain interval until the next ACK signal 304 is read (s13). And
The sub CPU 103 performs ACK of the peripheral device I / O controller 110 while performing other processing at this interval.
The signal 304 is repeatedly monitored (s11: No, s1
3, s11). By providing the peripheral device I / O controller 110 with a circuit for constantly monitoring the rising of the main CPU 100, the sub CPU 103
The burden of constantly monitoring the signal 304 or the activation signal 406 is relieved, and other processing can be performed in parallel while monitoring the rise of the main CPU 100, so that the processing can be performed promptly as a whole.

In this case, the sub CPU 103 sets the peripheral device I
ACK signal 304 from I / O controller 110 is LO
If it is detected that the level is W (s11: Yes),
Since the main CPU 100 has completed the startup,
The sub CPU 103 sends a predetermined signal to the power supply board 42 (see FIG. 5), and the power supply board 42 turns on the power of the main board 41 (s15). Next, since the main CPU 100 has already completed the activation, the sub CPU 103 clears the command reception prohibition flag of the sub RAM 104 to 0, and sets the address / data signal 201 from the main board 41.
(S17). Then, the special symbol display 8 "Please wait."
Is erased (see FIG. 9) (s19), and the screen based on the command by the address / data signal 201 from the main board 41 can be displayed. When the main board CPU 51 of the main board 41 has risen, since both the sub CPU 103 and the main CPU 100 of the symbol display board 44 have already risen, the address / data signal 201 from the main board 41 is used as the symbol display board 44. Ready to accept. Therefore, the address / data signal 201 from the main board 41 does not cause a malfunction.
The symbol is displayed by the liquid crystal 121 of the special symbol display device 8 on the basis of, and normal processing is performed (FIG. 10: normal processing). At this time, symbols other than the special symbols are also displayed on the liquid crystal 121 based on the address / data signal 201 from the main board 41.

Next, the timing of the operation of the pachinko machine 1 based on the control of the order as shown in the above-mentioned flowchart is shown in FIG.
This will be described in more detail with reference to FIG. 7 along the time chart of FIG. 2 and the time chart of FIG.

First, when the power of the pachinko machine 1 is turned on,
The sub CPU 103 at the timing of t0 in FIGS.
Rises, and the address / data signal 30 shown in FIG.
1, the dummy command Ad is transmitted from the sub CPU 103 to the peripheral device I / O controller (abbreviated as I / O in FIG. 14) 110 together with the address / data switching signal 302a. The subsequent dummy command Dd is transmitted to the peripheral device I / O controller 11 together with the enable signal 303d.
0 is sent. Also, as shown in FIG. 12, almost simultaneously with this, the command reception prohibition flag of the sub RAM 104 is set to 1 and the flag is turned on. Therefore, when the address / data signal 201 is received from the main board 41 thereafter, the command reception prohibition flag of the sub RAM 104 is turned ON.
Therefore, even if command data is sent, it is ignored without receiving it. Then, the peripheral device I / O controller 110 that has received the preceding dummy command Ad and the succeeding dummy command Dd sets the ACK signal 304 to a HIGH state.

In this state, the peripheral device I / O controller 110 constantly monitors the activation signal 406 of the main CPU 100. Then, the sub CPU 103 reads out an ACK signal 304 that is a notification that the preceding dummy command Ad and the succeeding dummy command Dd have been received from the peripheral device I / O controller 110 at a certain interval. During this interval, the sub CPU 103 is released from the work of monitoring the rising of the main CPU 100, and can perform other processing. Next, FIG. 12, FIG.
When the activation of the main CPU 100 is completed at the timing of t1 in FIG.
A start signal 406a is sent to the / O controller 110 by the start signal 406, and the ACK sent by the peripheral device I / O controller 110 to the sub CPU unit 99.
The signal 304 is changed from HIGH to LOW level. The sub CP monitoring the ACK signal 304 of the peripheral device I / O controller 110 at regular intervals.
When U103 detects that the ACK signal 304 is at the LOW level, it sends a signal to the power supply board 42 (see FIG. 5) to turn on the power of the main board 41. At this time, 0 is set to the command reception prohibition flag of the sub RAM 104, and the flag is turned off. Therefore, when the address / data signal 201 is transmitted from the main board 41 thereafter,
The sub CPU 103 sets the command reception prohibition flag to OFF.
Since it is (“0”), it receives this as a command and performs processing such as transmitting the address / data signal 301 to the peripheral device I / O controller 110. When a predetermined time has elapsed and the main board CPU 51 of the main board 41 completes the start-up at the timing of t2 in FIGS.

The normal processing will be briefly described below. In normal processing, the strobe signal 2
00, a pair of strobe signal 200a and strobe signal 200b are transmitted to sub CPU 103, and the timing of starting transmission of address / data signal 201 is determined by sub CP
U103 is notified. Subsequently, an address signal A1 is transmitted from the main board 41 by the address / data signal 201. The sub CPU 103 sends this address signal A1 to the peripheral device I / O controller 110 together with the address / data switching signal 302a on condition that the command reception prohibition flag of the sub RAM 104 is OFF. The device I / O controller 110 transmits these signals to the main CPU unit 9.
8 When the transmission of the address signal A1 is completed,
Next, data signal D1 is sent from main board 41. This data signal D1 is also transmitted to the sub CPU 10 on the condition that the command reception prohibition flag of the sub RAM 104 is OFF.
3 is an enable signal 30 from the sub CPU unit 99.
The peripheral device I / O controller 110 sends these signals to the main CPU unit 98 together with the peripheral device I / O controller 110. When receiving the data signal D1, the main CPU 100, when correctly receiving the pair of address signal A1 and data signal D1, transmits an ACK signal 404a to the peripheral device I / O controller 110, and transmits the ACK signal 404a to the peripheral device I / O controller 110. Sends the ACK signal 304b to the sub CPU unit 9
9

Upon receiving the ACK signal 304b, the sub CPU 103 recognizes that the first pair of address / data signals A1 and D1 have been correctly received by the main CPU 100, and sends the next address signal A2 to the address / data switching signal. Then, the next data signal D2 is transmitted together with the enable signal 303b. Then, when the main CPU 100 receives these signals A2 and D2, it sends an ACK signal 404b to the peripheral device I / O controller 110, and the peripheral device I / O controller 110 sends an ACK signal 304b to the sub CPU 103. Similarly, the address signal A3 is transmitted together with the address / data switching signal 302c, and the data signal D3
Is transmitted together with the enable signal 303c, and ACK signals 404c and 304c are returned. In this manner, data from the main board 41 is transferred to the main CPU by the shake hand transfer method.
100, and based on this data, the main CPU 100 stores the data at the designated address in the main R
Graphic engine 116 read from OM 102
The graphic engine 116 expands this and sends a control signal to the liquid crystal controller 120, and the liquid crystal controller 120 as a driver sends a drive signal to the liquid crystal 121 to display a predetermined image.

Here, each of the fluctuation patterns is simply represented by the liquid crystal 12.
1 will be briefly described. For example, when the variation pattern 1 is designated, all the symbols of the first stop symbol L1, the second stop symbol L2, and the third stop symbol L3 start to vary, and after 5100 ms, the symbols are designated by the respective stop symbol designation command data described later. It is adjusted to stop at the given stop symbol, and the daytime background is displayed without the appearance of the character. Also, if you specify other variation patterns,
The data for performing each predetermined display is stored in the main ROM 102.
Are stored as table data in the table, and respective displays are performed according to the data.

Next, the operation of the gaming machine which causes each of the above signals to occur will be briefly described. First, a game ball wins in the special symbol starting electric combination 15, and the winning opening switch 76 provided in the special symbol starting electric combination 15 detects the winning of the game ball. Then, based on the control program stored in the main board ROM 53, the main board CPU 51
After making a jackpot or reach determination, the main board CPU
51 is an I / O interface 54 and a bus line 9
5, the sub CPU 103 is instructed to start changing the screen of the liquid crystal 121 of the special symbol display device 8.

The operation when the power of the pachinko machine 1 is turned on has been described above. Next, when the power of the symbol display board 44 is turned off for some reason while the power of the main board 41 is turned on. Or, a case where the main substrate 41 is activated before the symbol display substrate 44 will be described. Even in such a case, control similar to normal control is basically performed. FIG. 13 shows that the main board CPU 51
It is a time chart at the time of starting up before U103. In FIG. 13, the main substrate 4 has already been
When 1 rises, the main board 41 cannot transmit the signal to the symbol display board 44 in only one direction, and therefore cannot recognize the state of the symbol display board 44. Therefore, the strobe signal 200 and the address / data signal 201 are sent from the main board CPU 51 of the main board 41 to the sub CPU 103 irrespective of the state of the symbol display board 44. At this stage,
Since the sub CPU 103 has not been activated, these signals sent from the main board 41 are ignored. Next, in an unstable state during the activation of the sub CPU 103, the main CPU 100 has not yet been activated at all,
Upon receiving a command from the main board 41, the sub CPU 103
Does not reach the special symbol display device 8 at all even if it malfunctions, and there is little risk of malfunction. And sub C
Immediately after the PU 103 has started up, the liquid crystal 12 of the special symbol display device 8 is initialized (see FIG. 11).
On the screen 1, the screen “Please wait” (see FIG. 9) is displayed (S 51), the command reception prohibition flag is turned on (s 57), and control is performed so as not to accept commands from the main board 41. You. Therefore, in an unstable state in which the main CPU 100 is likely to have a malfunction at the start stage of the main CPU 100, the main CPU 100 does not receive any command at all, and displays an undesired image on the screen of the liquid crystal 121 of the special symbol display device 8 due to the malfunction. Never do.

Then, at the timing of t5, the main CPU
100 is completed (FIG. 10: s11: Ye)
s), the command reception prohibition flag of the sub RAM 104 is set to O
The display is set to FF (FIG. 10: s17), the display of “Please wait”, which masks the liquid crystal 121 of the special symbol display device 8, is erased (FIG. 10: s19), and the command is received from the main board 41. Becomes possible. At this stage, not only the sub CPU 103 but also the main CPU 100 have already been started and are in a stable state, so that a malfunction does not occur. Therefore, an undesired image is displayed on the liquid crystal 121 of the special symbol display device 8. Not even.

As described above, in the pachinko machine 1 of the present embodiment, the main board 41 controlling the main control of the pachinko machine 1 is used.
And a symbol display board 44 for controlling the special symbol display device 8 are provided with independent control means, respectively, to transmit a signal for the special symbol display device 8 provided on the symbol display substrate 44.
When the main CPU 100, which is the control means, is activated, the symbol display board 44 which receives a signal from the main board 41
Of the main board 41
In order not to transmit the command from the main CPU 100 to the main CPU 100, there is an effect that the main CPU 100 does not malfunction and display an undesired screen on the display screen of the liquid crystal 121 of the special symbol display device 8.

Further, the sub CPU 103 and the main CPU
A peripheral device I / O controller 110, which is a third control means capable of transmitting and receiving signals in both directions, is provided between the peripheral device I / O controller 110 and the main device.
A circuit which is a monitoring means for constantly monitoring U100 is provided to monitor the rise of the main CPU 100,
100 when the start signal 406 from the sub-CP 100 is detected.
Since the notification is made by changing the level of the ACK signal 304 transmitted to the U103, the burden on the sub CPU 103 can be reduced.

In the pachinko machine 1 of the present embodiment,
An address transmitted from the sub CPU 103 to the peripheral device I / O controller 110 to indicate the rising of the sub CPU 103 is transmitted from the sub CPU 103 to the peripheral device I / O controller 110 for the special symbol display device 8. Since the dummy command signal has the same format as the / data signal, the sub CPU 103 can transmit the dummy command under the same control as the normal control and can notify the rise. Furthermore, even when the activation of the main CPU 100 is completed, the dummy command is an instruction that does not involve any execution, so that there is an effect that a malfunction does not occur.

Further, in the pachinko machine 1 of the present embodiment, a standby display such as "Please wait" is displayed on the special symbol display device 8 by the sub CPU 103 until the main CPU 100 of the symbol display board 44 is activated. There is an effect that can be performed. Therefore, there is an effect that an undesired screen is not displayed to the player.

In the pachinko machine 1 of the present embodiment, the activation of the main substrate 41 is performed after the entire activation of the symbol display substrate 44 is completed, so that the signal from the main substrate 41 is surely displayed on the symbol display. There is an effect that the signal is not received by the substrate 44 and a malfunction does not occur.

In the pachinko machine 1 according to the present embodiment,
When the activation of the sub CPU 103 is completed, the sub RAM 10
4 is turned on, the reception of the signal from the main board 41 is prohibited based on the reception prohibition flag, and
When the main CPU 100 is set to the LOW level due to the completion of the activation, the reception inhibition flag is turned off, and the address / data signal 201 and the strobe signal 200 from the main board 41 are turned off.
Is received, a signal from the main board 41 can be received by the sub CPU 103 at a timing at which no malfunction occurs.

The gaming machine according to the present invention has been described with reference to the pachinko machine 1 according to one embodiment.
The present invention is not limited to the above-described embodiment, and can be modified and modified by a person skilled in the art as appropriate. In addition, it goes without saying that the present invention is not limited to various pachinko machines, but can be widely applied to various game machines such as pachi-con machines and pachi-slot machines.

For example, the peripheral device I / O controller 1
The timing at which the monitoring of the activation of the main CPU 100 is started by the dummy command is taken by the dummy command. However, a signal different from the address / data signal 301 may be used separately, or the peripheral device I / O controller 110
It may be sent to. The start signal that the main CPU 100 notifies the peripheral device I / O controller 110 when the main CPU 100 completes the start is an independent circuit and signal.
The notification may be made by using the ACK signal 404 circuit and signal. Further, the ACK signal 304 for notifying the sub CPU 103 of the completion of the activation of the main CPU 100 from the peripheral device I / O controller 110 uses the same signal as the ACK signal for notifying the reception of a normal command. A signal from another circuit may be used.
The address / data signals 201 and 301 are composed of a pair of data of preceding command data and succeeding command data, but may be transmitted as a series of data. As described above, the signal configuration of the pachinko machine 1 of the present embodiment is an example, and any configuration may be used as long as signals can be exchanged between the respective control means.

The special symbol display device 8 corresponds to the symbol display device of the present invention.
For example, any configuration may be used as long as an image can be displayed, and a configuration with an action using a light bulb or an LED may be used.

Further, in the pachinko machine 1 according to the present embodiment, as shown in FIG.
100, a peripheral device I / O controller 110 is provided.
Upon receiving a dummy command from U103, the peripheral device I
Although the I / O controller 110 monitors the rising of the main CPU 100 and reports the result to the sub CPU 103 as a change in the level of the ACK signal 304, the I / O controller 1 for the peripheral device is not necessarily required.
The sub CPU 103 does not need to include the peripheral device I / O controller 110 and the sub CPU 103 directly
The activation signal 406 of the PU 100 causes the main CPU 100
The invention according to claim 1 can be implemented even in a configuration that monitors the rising edge of the signal. In this case, unlike the flowchart shown in FIG. 10, it is preferable to perform control such that the process returns to s11 directly from s11: No and is constantly monitored without performing other processes in s13. That is, sub C
If the processing capacity of the PU 103 is sufficient, the peripheral device I / O
Control is possible without the intervention of the O controller 110. With this configuration, even when the number of components is reduced or the peripheral device I / O controller 110 is provided, control of the peripheral device I / O controller can be simplified.

FIG. 8 is a block diagram showing an electric circuit configuration of a power supply monitoring circuit 78 and a reset delay circuit 79 according to a modification of the present embodiment. In the pachinko machine 1 of the present embodiment, the sound board 4
3, symbol display board 44, payout control board 45, illumination board 4
6. After the power supply current is simultaneously applied to each of the relay boards 47, a signal is sent to the power supply board 46 by the sub CPU 103 after the activation of the main CPU 100 of the symbol display board 44 is completed, and the power of the main board 41 is turned on. However, in order to prevent malfunction of each board in advance, the sound board 43, the symbol display board 44, the payout control board 45, the illumination board 46, the relay board 4
The power supply to the main substrate 41 may be turned on after a certain period of time after the power supply to the other substrates 7 is turned on.
Hereinafter, a modified example of the present embodiment including the power supply monitoring circuit 78 and the reset delay circuit 79 will be briefly described with reference to FIG. On the main board 41, a power supply monitoring circuit 78 and a reset delay circuit 79 are provided. The power supply monitoring circuit 78 includes a main board 41, a sound board 43, a payout control board 45,
A 12V power supply monitoring circuit 78 for monitoring a DC 12V voltage value supplied to the illumination board 46 and the relay board 47 (see FIG. 5).
a, and a 5V power supply monitoring circuit 78b for monitoring a voltage value of 5V DC supplied to the symbol display board 44. The 12V power supply monitoring circuit 78a includes a main board 41, a sound board 43, a payout control board 45, an illumination board 46, and a relay board 47.
And outputs an ON or OFF signal. The 5V power supply monitoring circuit 78
“b” measures the voltage value of DC 5 V supplied to the symbol display board 44 and outputs an ON / OFF signal.

The reset delay circuit 79 includes a frequency dividing counter 81 and an AND circuit 82. The frequency division counter 81 is provided with a power supply monitoring signal input unit 81a, a clock input unit 81b, and a signal output unit 81c. It is composed of circuits. In this modification, setting the clock input from the clock input 81b to the peripheral 2 ²⁵ minutes. Further, as shown in FIG. 5, an OSC circuit 80 composed of a crystal oscillator is connected to the main board CPU 51.
8.192MHz of basic clock from 0 to main board CPU
The clock is supplied to the clock input unit 50a of the unit 50. Then, a 2.048 MHz clock obtained by dividing the base clock 8.192 MHz by 4 is output from the clock output unit 50 b of the main board CPU unit 50 and input to the clock input unit 81 b of the frequency division counter 81. .

The 5V power supply monitoring circuit 78b is connected to the power supply monitoring signal input section 81a of the frequency division counter 81. In the frequency dividing counter 81, a power monitoring signal input unit 81
a from the 5V power supply monitoring circuit 78b
In the case of N, after a one period with a frequency ^{2 25} divides the clock signal of 2.048MHz supplied from the main board CPU unit 50 16.4 seconds have elapsed, the signal is turned ON from the signal output unit 81c is Output to the AND circuit 82. At this time, if the ON signal is also output from the 12V power supply monitoring circuit 78a, the AND circuit 82 outputs the ON signal.
Is input to the reset permission signal input unit 50c of the main board CPU unit 50. Reset permission signal input unit 5
When an ON signal is input to 0c, the main board CPU unit 50 outputs a signal from the interrupt reset circuit 57 shown in FIG.
The pachinko machine 1 is controlled by executing a control program (not shown) stored in the main board ROM 53 in accordance with the reset signal in units of m seconds.

Next, the operation of the power supply circuit according to this modification will be described. First, when a switch (not shown) of the power supply board 42 is turned ON (power is turned on), the power supply board 42
Is supplied from the power supply board 42 to the control unit 40 and the main board 4
1, 12 V DC is supplied to the sound board 43, the payout control board 45, the illumination board 46, and the relay board 47. In addition, DC 5V
Is supplied to the symbol display substrate 44. Here, the 12V power supply monitoring circuit 78a constituting the power supply monitoring circuit 78 includes a 12V DC power supply supplied to the The voltage value is constantly measured, and an ON signal is supplied to the AND circuit 82 if the voltage is 12 V or more, and OFF if the voltage is less than 12 V.
Is supplied to the AND circuit 82. The 5V power monitoring circuit 78b constantly measures the 5V DC voltage value supplied to the symbol display board 44, and if it is 5V or more, sends an ON signal to the power monitoring signal input section 81a of the frequency dividing counter 81. If the voltage is less than 5 V, an OFF signal is supplied to the power monitoring signal input unit 81a of the frequency dividing counter 81.

Here, 5V is applied to the power supply monitoring signal input section 81a.
When an ON signal is input from the power supply monitoring circuit 78b, a 2.048 MHz clock is output from the clock output unit 50b of the main board CPU unit 50 and input to the clock input unit 81b of the frequency division counter 81. that when, in the dividing counter 81, and a 2.048MHz input to the clock input 81b to ^{2 25} by dividing, 0.
061 Hz is obtained. Then, after a delay time of 16.4 seconds, which is one cycle of 0.061 Hz, an ON signal is output to the AND circuit 82. Here, the AND circuit 82
If an ON signal is input from the 12V power supply monitoring circuit 78a to the input terminal, an ON signal is input from the AND circuit 82 to the reset permission signal input unit 50c of the main board CPU unit 50, and the main board CPU unit 50 Control is started according to a control program stored in main board ROM 53 in accordance with a reset signal of 2 ms unit from interrupt reset circuit 57.

As soon as the switch of the power supply board 42 is turned on, the DC 12
Is supplied to the symbol display board 44, and the main board CPU unit 50 of the main board 41 is supplied.
The ON signal is input to the reset permission signal input section 50c of the main board CPU unit 50 after the elapse of the delay time of 16.4 seconds by the operation of the reset delay circuit 79. Thereafter, in the main board CPU unit 50, control of the pachinko machine 1 is started in accordance with a control program stored in the main board ROM 53 in accordance with a reset signal in units of 2 ms from the interrupt reset circuit 57.

The main board CPU unit 50 is activated by turning on the switch of the power supply board 42 and then 16.4.
Since the second delay time has elapsed, the activation of the sound board 43, the payout control board 45, the illumination board 46, and the symbol display board 44 is completed during the delay time of 16.4 seconds. This one
The delay time of 6.4 seconds is set in advance so as to be longer than the rising time of the slowest rising substrate among the substrates. This setting is performed by the frequency dividing counter 81
Is set in advance in the flip-flop circuit constituting the frequency division ratio so as to be longer than the rise time of the slowest rising substrate among the substrates. This modification has set the clock input from the clock input 81b to the peripheral 2 ²⁵ minutes. Therefore, when the activation of the main board CPU unit 50 is completed and the main board 41 has completely risen, all the other boards are in the up state, and a command signal is sent from the main board 41 to another board. Even if it is sent, it is reliably accepted, and no error occurs because the command signal from the host is not accepted because the destination board is not up.

In this modification, the 12V power supply monitoring circuit 78a
And a 5V power supply monitoring circuit 78b, so that only when a normal voltage is applied to each board, the reset enable signal from the reset delay circuit 79 is turned ON after a predetermined delay time, and the main board CPU unit 50 is input to the reset permission signal input unit 50c, a predetermined delay time is set when the DC of the correct voltage is not supplied to the other boards except the main board 41 and the other boards cannot be started up properly. , The main substrate 41 can be prevented from rising up first. In particular, since the symbol display board 44 is a slowly rising board that takes about 12 seconds to rise, by setting a delay time of 16.4 seconds in the reset delay circuit 79, the main board CPU unit 50 is set.
When the main board 41 has completely started up after the start-up, the symbol display board 44 is normally
Does not cause an error because the command signal is not accepted.

However, the main CPU 100 of the symbol display board 44 of this embodiment is a 32-bit CPU, and it is necessary to read the OS from the main ROM 102 at the time of startup, and sometimes it takes time to reset the registry. Yes, it does not always start up in exactly 12 seconds. Also, for some reason, the symbol display board 44
Power supply may be turned off. In such a case,
Even in the case of the power supply board 42 configured as in the modified example, it is assumed that the main CPU 100 of the symbol display board 44 starts up after the main board 41 starts up. In such a case, the main CPU 1
00 is a result of a signal being sent from the main board 41 to the activated symbol display board 44, which may cause a malfunction. However, according to the configuration of the present embodiment, such a case is not considered. The liquid crystal 121 of the special symbol display device 8
Undesirable images are not displayed on the screen.

As described above, it is needless to say that the gaming machine of the present invention is not limited to the present embodiment and its modifications, but can be variously modified and improved without departing from the scope of the claims.

[0092]

In the gaming machine according to the first aspect of the present invention, the main board for controlling the main control of the gaming machine and the symbol display board for controlling the symbol display device are provided with independent control means, respectively. When the second control means for transmitting a signal to the provided symbol display device is being activated, the first control means of the symbol display device for receiving a signal from the main board transmits a command from the main board to the second control means. This has the effect of preventing transmission to the control means. Therefore, there is an effect that the second control means does not malfunction and display an undesired screen on the display screen of the symbol display device.

In the gaming machine according to the second aspect of the present invention, the main board for controlling the main control of the gaming machine and the symbol display board for controlling the symbol display device are provided with independent control means, respectively. Second to send a signal for the symbol display device
When the control means is activated, there is an effect that the first control means of the symbol display board which receives the signal from the main board does not transmit the command from the main board to the second control means. Therefore, there is an effect that the second control unit does not malfunction and an undesired screen is not displayed on the display screen of the symbol display device. Further, third control means capable of transmitting and receiving signals in both directions is provided between the first control means and the second control means, and the third control means is provided with a monitoring means, and the second control means is provided. The start of monitoring of the rising edge is started, and when this is detected, it is notified to the first control means, so that the load on the first control means can be reduced.

According to a third aspect of the present invention, in addition to the effects of the second aspect of the invention, the first control means provides:
The effect is that the start signal transmitted to the third control means can be a signal in the same format as the command transmitted from the first control means to the third control means for the symbol display device. is there. Therefore, the first control means can transmit the start signal under the same control as the normal control, and does not cause a malfunction even when the activation of the second control means is completed. Play.

According to a fourth aspect of the present invention, in addition to the effects of the gaming machine according to any one of the first to third aspects, the game machine further comprises:
There is an effect that the first control means can perform a display on the symbol display device to notify that it is on standby.
Therefore, there is an effect that an undesired screen is not displayed to the player.

In the gaming machine according to the fifth aspect of the invention, in addition to the effects of the gaming machine according to any one of the first to fourth aspects, the activation of the main substrate is performed after the activation of the entire symbol display substrate is completed. There is an effect that it is performed from. Therefore, there is an effect that the signal from the main board is reliably received by the symbol display board and no malfunction occurs.

According to a sixth aspect of the present invention, in addition to the effects of the gaming machine according to any one of the first to fifth aspects, when the activation of the first control means is completed, it is provided here. The reception prohibition flag is turned on, and based on the reception prohibition flag, reception of a signal from the main board is prohibited, and the second
The reception inhibition flag is turned off in association with the completion of the activation of the control means, and the reception of the signal from the main board can be permitted. Therefore, there is an effect that the signal from the main board can be received by the first control means at a timing at which the signal does not malfunction.

[Brief description of the drawings]

FIG. 1 is a front view of a pachinko machine 1. FIG.

FIG. 2 is a front view of the game board 2 of the pachinko machine 1.

FIG. 3 is a front view of the special symbol display device 8;

FIG. 4 is a rear view of the pachinko machine 1. FIG.

FIG. 5 is a block diagram showing an electric circuit configuration of the pachinko machine 1;

FIG. 6 shows the structure of the symbol display substrate 44 and the symbol display substrate 44.
FIG. 3 is a block diagram showing a connection relationship between the main board 41 and a special symbol display device 8.

FIG. 7 is a diagram schematically showing the exchange of signals among the main board 41, the sub CPU unit 99, the peripheral device I / O controller 110, and the main CPU 100.

FIG. 8 is a block diagram showing an electric circuit configuration of a power supply monitoring circuit 78 and a reset delay circuit 79 according to a modification of the present embodiment.

FIG. 9 is a timing chart of each signal when the screen of the special symbol display device 8 stops changing.

FIG. 10 is a flowchart showing the flow of a process when power is turned on.

FIG. 11 is a flowchart showing details of an initialization process s3 in FIG. 10;

FIG. 12 is a time chart showing the state of each part when the power of the ordinary pachinko machine 1 is turned on.

13 is a time chart when the main board CPU 51 starts up before the sub CPU 103. FIG.

FIG. 14 is a timing chart of each signal when the power is turned on.

[Explanation of symbols]

 1 Pachinko machine 8 Special symbol display device 41 Main board 42 Power supply board 44 Symbol display board 50 Main board CPU unit 54 I / O interface 98 Main CPU unit 99 Sub CPU unit 100 Main CPU 103 Sub CPU 110 I / O controller for peripheral device 121 LCD

Claims (6)

[Claims] 1. A game machine comprising a main board for controlling the main control of a gaming machine and a symbol display board for controlling a symbol display device, each of which is provided independently of each other. A first control unit that receives a signal; and a second control unit that receives a signal from the first control unit and transmits a signal to the symbol display device. The first control unit includes: Monitoring means for monitoring the rise of the second control means, so that a signal from the main board is not transmitted to the second control means until the rise of the second control means is detected. A gaming machine characterized by being done. 2. A game machine in which a main board for controlling the main control of the gaming machine and a symbol display board for controlling the symbol display device are provided independently of each other, wherein the symbol display board includes First control means for receiving a signal, second control means for transmitting a signal for the symbol display device, and a bidirectional signal between the first control means and the second control means. And a third control means capable of transmitting and receiving data. The third control means receives a start signal transmitted from the first control means after the first control means rises, thereby notifying of a predetermined level. A signal is transmitted to the first control means, a monitoring means is provided, and the monitoring means starts monitoring the rising of the second control means, and the monitoring means starts the second control means. When it detects that Changing the level of the notification signal transmitted to the first control means, wherein the first control means, when the notification signal transmitted from the third control means is at a predetermined level, transmits the notification signal from the main board. A gaming machine characterized in that a signal is not transmitted to the second control means. 3. A start signal transmitted from the first control means to the third control means is transmitted from the first control means to the third control means for the symbol display device. 3. The dummy command according to claim 2, wherein the signal is a signal having a format common to that of the command to be executed and does not affect the control of the symbol display device even when received by the second control means. Gaming machine. 4. A display for notifying that the symbol display device is on standby by the first control means until the second control means is activated. Item 7. A gaming machine according to any one of Items 3. 5. The gaming machine according to claim 1, wherein the main board is started on condition that the start of the second control means is completed. 6. The first control means, when the activation of the first control means is completed, turns on a reception inhibition flag provided in the first control means, and based on the reception inhibition flag, Receiving a signal from the main board by prohibiting reception of a signal from the main board, and turning off the reception prohibition flag in association with completion of activation of the second control means. A gaming machine according to any one of claims 1 to 5.