JP2001230515A - Mounting member of electronic component, method of manufacturing mounting member of electronic component, and secondary mounting structure of mounting member - Google Patents

Mounting member of electronic component, method of manufacturing mounting member of electronic component, and secondary mounting structure of mounting member

Info

Publication number
JP2001230515A
JP2001230515A JP2000036393A JP2000036393A JP2001230515A JP 2001230515 A JP2001230515 A JP 2001230515A JP 2000036393 A JP2000036393 A JP 2000036393A JP 2000036393 A JP2000036393 A JP 2000036393A JP 2001230515 A JP2001230515 A JP 2001230515A
Authority
JP
Japan
Prior art keywords
electronic component
substrate
external connection
housing
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000036393A
Other languages
Japanese (ja)
Inventor
Hideki Higashiya
秀樹 東谷
Daizo Ando
大蔵 安藤
Sadashi Nakamura
禎志 中村
Toshio Sugawa
俊夫 須川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2000036393A priority Critical patent/JP2001230515A/en
Publication of JP2001230515A publication Critical patent/JP2001230515A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PROBLEM TO BE SOLVED: To reduce the size of a product by reducing mounting area. SOLUTION: External connection terminals 203, 210, connected electrically with an electronic component 201, are disposed on both surfaces of a package board 202 where the electronic component 201 is mounted and arranged in the inside and both surfaces are closed, and a mounting member 200 is constituted, so that external connection terminals 210 are arranged also on the upper surface part of the package board 202 positioned upward of the electronic component 201.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体素子を収容
するための半導体素子収納用パッケージや混成集積回路
モジュール等として用いられる電子部品の実装体や、こ
の実装体の製造方法や、この実装体の二次実装構造に関
するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package for electronic components used as a package for housing a semiconductor element for housing a semiconductor element, a hybrid integrated circuit module, and the like, a method for manufacturing the package, and a method for manufacturing the package. In the secondary mounting structure.

【０００２】[0002]

【従来の技術】図１２に従来の電子部品の実装体の一例
を示す。図に示したのはフリップチップ接続によって、
半導体素子が実装基板に実装されたＢＧＡ（Ball Grid
Array）基板構造の例である。図１２において、１００
は半導体素子であり、この例の場合ではフェイスダウン
状態で半田ボール１０１によって実装基板１０２の一面
に半田実装されており、さらには、実装基板１０１と実
装基板１０２との間は封止樹脂１０４によって封止され
ている。2. Description of the Related Art FIG. 12 shows an example of a conventional electronic component package. What is shown in the figure is by flip chip connection,
BGA (Ball Grid) with semiconductor elements mounted on a mounting board
Array) is an example of a substrate structure. In FIG. 12, 100
Is a semiconductor element, which is solder-mounted on one surface of the mounting substrate 102 by solder balls 101 in a face-down state in this case, and furthermore, a sealing resin 104 is provided between the mounting substrate 101 and the mounting substrate 102. It is sealed.

【０００３】半導体素子１００の実装方法は半田実装だ
けでなく、ワイヤーボンディング実装によるものや、Ｔ
ＡＢ実装によるもの、スタッドバンプに接続用の導電性
ペーストを塗布し、フリップチップ実装したものなど、
様々な実装方法が存在する。[0003] The semiconductor element 100 can be mounted not only by soldering but also by wire bonding.
AB mounting, Flip chip mounting with conductive paste applied to stud bumps for connection, etc.
There are various implementation methods.

【０００４】また、実装基板１０２として、図１２では
全層ＩＶＨ構造（Any Layer InnerVia Hole Constructi
on）をもつＡＬＩＶＨ基板（Any Layer Inner Via Hole
Structure Multilayer Printed Wiring Board）を用い
たものを示しているが、その他にセラミック基板、ガラ
スエポキシ基板、ビルドアップ基板等様々な基板を用い
たものがある。[0004] As a mounting substrate 102, in FIG. 12, an all layer IVH structure (Any Layer Inner Via Hole Constructi
on) ALIVH substrate (Any Layer Inner Via Hole)
Structure Multilayer Printed Wiring Board), but there are also others using various substrates such as a ceramic substrate, a glass epoxy substrate, and a build-up substrate.

【０００５】実装基板１０２の他面には外部接続端子１
０３が設けられている。外部接続端子１０３としては、
はんだボールを用いることが一般的である。この外部接
続端子１０３の配置構造は格子状に全面に設けられてい
る場合や、外周に沿って数列設けられる場合や、中央付
近に数列設けられている場合等さまざまである。外部接
続端子１０３は、半導体素子１００が設けられていない
実装基板１０３の他面にだけ設けられている。[0005] On the other surface of the mounting board 102, the external connection terminal 1 is provided.
03 is provided. As the external connection terminal 103,
It is common to use solder balls. There are various arrangement structures of the external connection terminals 103 such as a case where the external connection terminals 103 are provided on the entire surface in a lattice shape, a case where several lines are provided along the outer periphery, and a case where several lines are provided near the center. The external connection terminal 103 is provided only on the other surface of the mounting board 103 on which the semiconductor element 100 is not provided.

【０００６】以上の構造を有する実装体では、通常、外
部接続端子1０３を介して図示しない二次実装用基板
（以下、マザー基板と称す）に二次実装されるようにな
っている。[0006] The mounting body having the above-described structure is usually mounted on an unillustrated secondary mounting board (hereinafter, referred to as a mother board) via an external connection terminal 103.

【０００７】[0007]

【発明が解決しようとする課題】このような従来の実装
体では、上述したように、実装基板１０２の一面にしか
外部接続端子１０３が設けられていない。そのため、構
造的に、実装体を積層配置して互いに接続することがで
きず、複数の実装体をマザー基板に二次実装する場合に
は、マザー基板に対して面方向に並べて実装せざるを得
なかった。したがって、マザー基板には広い実装面積が
必要となり、結果的にマザー基板が大きくなり、製品サ
イズを小型化するにあたっての障壁となっていた。In such a conventional mounting body, the external connection terminals 103 are provided only on one surface of the mounting board 102 as described above. Therefore, structurally, the mounting bodies cannot be stacked and arranged to be connected to each other.When a plurality of mounting bodies are secondarily mounted on the mother board, they must be mounted side by side with respect to the mother board in the surface direction. I didn't get it. Therefore, a large mounting area is required for the mother board, and as a result, the mother board becomes large, which has been a barrier in reducing the product size.

【０００８】これに対しては、特にセラミック基板を用
いた実装体において、図１３に示すように、実装基板１
１０の両端に複数の側壁基板１１１を積層して側壁部１
１２を形成し、その側壁部１１２の上面に外部接続端子
１０３'を設けたものもある（例えば、特開平５−８２
７１０号公報）。On the other hand, especially in a package using a ceramic substrate, as shown in FIG.
A plurality of side wall substrates 111 are stacked on both ends of
12 is formed, and an external connection terminal 103 'is provided on the upper surface of the side wall portion 112 (see, for example, JP-A-5-82).
No. 710).

【０００９】しかしながら、この構造では、側壁部１１
２の上面上には、外部接続端子１０３'を配置する面積
が少なく、端子数の少ない電子部品１００にしか対応す
ることができなかった。However, in this structure, the side wall 11
On the upper surface of No. 2, the area for arranging the external connection terminals 103 'was small, and only the electronic component 100 having a small number of terminals could be accommodated.

【００１０】本発明の主たる目的は、端子数の多い半導
体の実装体について、従来の技術では困難であった実装
体としてのハンドリング性・信頼性を保証し、容易に積
み重ねて実装できる半導体の実装体を提供することにあ
る。[0010] A main object of the present invention is to provide a semiconductor package having a large number of terminals, which assures the handling and reliability of the package, which has been difficult with the conventional technology, and which can be easily stacked and mounted. Is to provide the body.

【００１１】[0011]

【課題を解決するための手段】本発明は上記目的を達成
するために、内部に電子部品が実装配置され、かつその
両面が閉塞された収納筺体と、前記収納筺体の両面それ
ぞれに複数設けられ、かつ、少なくともその一部が前記
電子部品に電気的に接続された外部接続端子とを有して
電子部品の実装体を構成している。SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a storage housing in which electronic components are mounted and arranged and both sides of which are closed, and a plurality of storage housings provided on both sides of the storage housing. And, at least a part thereof has an external connection terminal electrically connected to the electronic component to constitute a mounted body of the electronic component.

【００１２】これによれば、外部接続端子が収納筺体の
上面にも多数形成されることになるために、多数の外部
接続端子を有する半導体素子等の電子部品を実装した実
装体であっても、その実装体どうしを積層配置して実装
することが可能となり、実装面積の低減に大きな効果が
ある。According to this, since a large number of external connection terminals are also formed on the upper surface of the housing, even a mounted body on which electronic components such as semiconductor elements having a large number of external connection terminals are mounted. This makes it possible to mount the mounting bodies in a stacked arrangement, which is very effective in reducing the mounting area.

【００１３】また、収納筺体の上下面に設けた外部接続
端子は直接接続することが可能であるために、これらの
外部接続端子は電子部品に対して必ずしも接続する必要
はなく、自由度の大きい積層実装が可能となる。Further, since the external connection terminals provided on the upper and lower surfaces of the housing can be directly connected, these external connection terminals do not necessarily need to be connected to electronic components, and have a high degree of freedom. Lamination mounting becomes possible.

【００１４】[0014]

【発明の実施の形態】本発明の請求項１に記載の発明
は、内部に電子部品が実装配置され、かつその両面が閉
塞された収納筺体と、前記収納筺体の両面それぞれに複
数設けられ、かつ、少なくともその一部が前記電子部品
に電気的に接続された外部接続端子とを有して電子部品
の実装体を構成しており、これにより次のような作用を
有する。すなわち、収納筺体をその両面が閉塞された形
態に構成しているので、電子部品の上方に位置する収納
筺体の上面部分にも外部接続端子を設けることができ、
その分、外部接続端子の端子数を十分多く確保すること
が可能となる。DESCRIPTION OF THE PREFERRED EMBODIMENTS According to a first aspect of the present invention, there is provided a storage housing in which electronic components are mounted and arranged and both sides of which are closed, and a plurality of storage housings provided on both sides of the storage housing, Further, at least a part thereof has an external connection terminal electrically connected to the electronic component to constitute a mounted body of the electronic component, and thereby has the following operation. That is, since the housing is configured in a form in which both sides are closed, external connection terminals can be provided also on the upper surface of the housing located above the electronic component,
Accordingly, it is possible to secure a sufficiently large number of external connection terminals.

【００１５】本発明の請求項２に記載の発明は、請求項
１に係る電子部品の実装体であって、前記外部接続端子
は、前記収納筺体両面の全面にわたって設けられている
ことに特徴を有しており、これにより、次のような作用
を有する。すなわち、外部接続端子を両面の全面に設け
ることで、その数を最大限に確保することが可能とな
る。According to a second aspect of the present invention, there is provided the electronic component package according to the first aspect, wherein the external connection terminals are provided on both surfaces of the housing. Accordingly, it has the following operation. That is, by providing the external connection terminals on the entire surface on both sides, it is possible to ensure the maximum number of the external connection terminals.

【００１６】本発明の請求項３に記載の発明は、請求項
１に係る電子部品の実装体であって、当該実装体を二次
実装する際において二次実装対象部材側に位置する実装
体の面に設けられた前記外部接続端子は、前記収納筺体
を挟んで前記電子部品に対向しない当該面の領域に配置
されていることに特徴を有しており、これにより次のよ
うな作用を有する。すなわち、二次実装対象部材と実装
体との間の熱膨張係数の差や外部ストレス等により、こ
の実装体と二次実装対象部材との間に応力が集中したと
しても、前記外部接続端子は、前記収納筺体を挟んで前
記電子部品に対向する当該面の領域には配置されていな
いので、電子部品や電子部品と実装体との間の接続個所
に前記した応力集中による影響が及びにくくなる。According to a third aspect of the present invention, there is provided a mounted body of the electronic component according to the first aspect, wherein the mounted body is located on the side of the secondary mounting target member when the mounted body is secondarily mounted. The external connection terminals provided on the surface are characterized in that they are arranged in a region of the surface that does not face the electronic component with the storage housing interposed therebetween. Have. In other words, even if stress is concentrated between the mounted body and the secondary mounting target member due to a difference in thermal expansion coefficient between the secondary mounting target member and the mounted body or external stress, the external connection terminal is Since it is not disposed in the area of the surface facing the electronic component with the storage housing interposed therebetween, the influence of the stress concentration on the electronic component and the connection point between the electronic component and the mounting body is less likely to occur. .

【００１７】本発明の請求項４に記載の発明は、請求項
１ないし３のいずれかに係る電子部品の実装体であっ
て、前記収納筺体両面にある外部接続端子の一部は、両
面にあるものどうし互いに前記電子部品を介することな
く直接接続されていることに特徴を有しており、これに
より次のような作用を有する。すなわち、この実装体に
実装された電子部品を介することなく、その上下に二次
実装された二次実装対象部材どうしを直接電気的に接続
することができるようになる。According to a fourth aspect of the present invention, there is provided the electronic component package according to any one of the first to third aspects, wherein a part of the external connection terminals on both sides of the housing is provided on both sides. It is characterized in that some of them are directly connected to each other without passing through the electronic component, and thus have the following effects. That is, it is possible to directly electrically connect the secondary mounting target members which are secondarily mounted on the upper and lower sides of the mounting member without the electronic components mounted on the mounting body.

【００１８】本発明の請求項５に係る発明は、請求項１
ないし４のいずれかに係る電子部品の実装体であって、
前記収納筺体両面にある外部接続端子の一部は、両面に
あるものどうし互いに前記電子部品を介して直列接続さ
れていることに特徴を有しており、これにより次のよう
な作用を有する。すなわち、この実装体に実装された電
子部品と、二次実装対象部材とを互いに直列に接続する
ことができるようになる。According to a fifth aspect of the present invention, a first aspect is provided.
A mounted body of the electronic component according to any one of (4) to (4),
A part of the external connection terminals on both sides of the storage housing is characterized in that those on both sides are connected in series to each other via the electronic component, thereby having the following operation. That is, the electronic component mounted on the mounting body and the secondary mounting target member can be connected in series with each other.

【００１９】本発明の請求項６に記載の発明は、請求項
１ないし５のいずれかに係る電子部品の実装体であっ
て、前記収納筺体両面にある外部接続端子の一部は、前
記電子部品に対して並列接続されていることに特徴を有
しており、これにより次のような作用を有する。すなわ
ち、この実装体に実装された電子部品に対して二次実装
対象部材を並列に接続することができるようになる。According to a sixth aspect of the present invention, there is provided the electronic component package according to any one of the first to fifth aspects, wherein a part of the external connection terminals on both sides of the housing is provided with the electronic component. It is characterized in that it is connected in parallel to the components, and has the following effects. That is, the secondary mounting target member can be connected in parallel to the electronic component mounted on the mounting body.

【００２０】本発明の請求項７に記載の発明は、請求項
１ないし６のいずれかに係る電子部品の実装体であっ
て、前記収納筺体は、多層基板から構成されていること
に特徴を有しており、これにより次のような作用を有す
る。すなわち、多層基板の構造を採用することで、収納
筺体両面に多数設けられる外部接続端子どうしやこれら
外部接続端子と電子部品との間の接続を容易に実現する
ことができるようになる。According to a seventh aspect of the present invention, there is provided the electronic component package according to any one of the first to sixth aspects, wherein the housing is formed of a multilayer board. This has the following effects. That is, by adopting the structure of the multilayer board, it is possible to easily realize a large number of external connection terminals provided on both surfaces of the housing and connections between the external connection terminals and the electronic components.

【００２１】本発明の請求項８に記載の発明は、請求項
７に係る電子部品の実装体であって、前記収納筺体は、
全層ＩＶＨ構造を有する樹脂多層基板から構成されてい
ることに特徴を有しており、これにより次のような作用
を有する。すなわち、全層ＩＶＨ構造を有する樹脂多層
基板の構造を採用することで、収納筺体両面に多数設け
られる外部接続端子どうしや、これら外部接続端子と電
子部品との間の接続をさらに容易に実現することができ
るようになる。According to an eighth aspect of the present invention, there is provided the electronic component package according to the seventh aspect, wherein the housing is provided with:
It is characterized by being constituted by a resin multilayer substrate having an all-layer IVH structure, and thereby has the following operation. That is, by employing the structure of the resin multilayer substrate having the all-layer IVH structure, it is possible to more easily realize the connection between the external connection terminals provided on the both sides of the housing and the connection between the external connection terminals and the electronic components. Will be able to do it.

【００２２】本発明の請求項９に記載の発明は、請求項
７に係る電子部品の実装体であって、前記収納筺体は、
当該実装体を二次実装する際において二次実装対象部材
側に位置する実装体の面側に位置する部分が、可撓性を
有するフィルム基板から構成されていることに特徴を有
しており、これにより次のような作用を有する。すなわ
ち、外部ストレス等により、この実装体と二次実装対象
部材との間に応力が集中したとしても、そのストレス
は、可撓性を有するフィルム基板からなる部分の変形に
より吸収されるので、電子部品や電子部品と実装体との
間の接続個所に前記した応力集中による影響が及びにく
くなる。According to a ninth aspect of the present invention, there is provided the electronic component package according to the seventh aspect, wherein the housing is provided with:
It is characterized in that, when the mounting body is secondarily mounted, a portion located on the surface side of the mounting body located on the side of the secondary mounting target member is formed of a flexible film substrate. This has the following effect. That is, even if stress is concentrated between the mounting body and the secondary mounting target member due to external stress or the like, the stress is absorbed by deformation of the portion made of the flexible film substrate. The influence of the above-mentioned stress concentration on the connection point between the component or the electronic component and the mounting body is less likely to occur.

【００２３】本発明の請求項１０に記載の発明は、請求
項１ないし９のいずれかに係る電子部品の実装体であっ
て、前記電子部品と前記筺体との間に隙間を形成するこ
とに特徴を有しており、これにより次のような作用を有
する。すなわち、実装体に対して外部から伝わる物理的
ストレスにより、収納筺体が変形したとしても、その変
形は隙間により吸収されて、電子部品や電子部品と収納
筺体との接続箇所に及びにくくなる。According to a tenth aspect of the present invention, there is provided the electronic component package according to any one of the first to ninth aspects, wherein a gap is formed between the electronic component and the housing. It has the following features. That is, even if the housing is deformed by the physical stress transmitted from the outside to the mounted body, the deformation is absorbed by the gap, and it is difficult to reach the electronic component and the connection portion between the electronic component and the housing.

【００２４】この隙間は、請求項１１に記載したよう
に、当該実装体を二次実装する際において二次実装対象
部材側に位置する実装体の面と前記電子部品との間に設
けるのが好ましく、そうすれば、上記物理的ストレスを
より効率良く吸収することができるようになる。This gap is preferably provided between the electronic component and the surface of the package located on the side of the secondary mounting target member when the package is secondarily mounted. Preferably, then, the physical stress can be more efficiently absorbed.

【００２５】以上説明した実装体は、前記電子部品とし
て、外部ストレスによる影響で破損しやすい半導体素子
を実装するものであるのが好ましい。The above-described mounting body preferably mounts, as the electronic component, a semiconductor element which is easily damaged by the influence of external stress.

【００２６】また、請求項１３に記載したように、これ
ら実装体どうしを収納筺体両面のうちの一方を互いに向
かい合わせて積層配置し、両実装体の外部接続端子を電
気的に接続すれば、さらに面積効率良く実装体を実装す
ることができるようになる。According to a thirteenth aspect of the present invention, when these mounting bodies are stacked and arranged with one of both sides of the housing facing each other and the external connection terminals of both mounting bodies are electrically connected, Further, the mounting body can be mounted with a good area efficiency.

【００２７】また、この実装体は、請求項１４に記載し
たように、ＩＶＨ構造を有する多層基板からなりその裏
面には第１の外部接続端子を有する基部基板の上面に電
子部品を実装し、前記第１の外部接続端子の少なくとも
一部と前記電子部品とを、前記ＩＶＨ構造を介して電気
的に接続する工程と、ＩＶＨ構造を有する多層基板から
なる側壁基板を前記電子部品の周囲を囲んで前記基部基
板上に積層一体化するとともに、ＩＶＨ構造を有しかつ
その上面には第2の外部接続端子を有する天井基板を、
前記電子部品を覆って前記側壁基板上に積層一体化し、
前記第2の外部接続端子を、前記電子部品および前記第
１の外部接続端子それぞれの必要箇所に、各基板内のＩ
ＶＨ構造を介して電気的に接続する工程とを含んでだ製
造方法により製造することができる。Further, the mounting body is formed of a multilayer substrate having an IVH structure, and electronic components are mounted on the upper surface of a base substrate having first external connection terminals on the back surface thereof. Electrically connecting at least a part of the first external connection terminal to the electronic component via the IVH structure; and surrounding a side wall substrate made of a multilayer substrate having the IVH structure around the electronic component. A ceiling substrate having an IVH structure and having a second external connection terminal on its upper surface while being laminated and integrated on the base substrate,
Laminating and integrating the electronic component on the side wall substrate,
The second external connection terminal is connected to a necessary portion of each of the electronic component and the first external connection terminal by an I
And a step of electrically connecting via a VH structure.

【００２８】次に、本発明の実施形態を図面を参照して
詳細に説明する。図１は本発明の一実施形態である半導
体素子の実装体２００を示している。なお、以下の説明
では、便宜上、図の上下方向をこの実装体２００におけ
る上下方向としているが、この実装体２００は特に図の
上下方向の通りに配置されるものではなく、図中、上下
を逆に配置してもよいのはいうまでもなし、さらには、
図中の上下方向を左右方向として配置してもよいのもい
うまでもない。Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a semiconductor device package 200 according to an embodiment of the present invention. In the following description, for the sake of convenience, the vertical direction of the drawing is the vertical direction of the mounting body 200. However, the mounting body 200 is not particularly arranged in the vertical direction of the drawing. Needless to say, they may be arranged in reverse, and
It goes without saying that the vertical direction in the figure may be arranged as the horizontal direction.

【００２９】この実装体２００は電子部品である半導体
素子２０１と、収納筺体を構成するパッケージ基板２０
２とを備えている。パッケージ基板２０２は、全層ＩＶ
Ｈ構造（All Layer Interstitial Via Hole Structur
e）を有する樹脂多層基板から構成されており、基部基
板２０２ａと、側壁基板２０２ｂと、天井基板２０２ｃ
とを備えている。基部基板２０２ａは単層もしくは多層
の基板（この例では三層の多層基板）からなっている。
基部基板２０２ａの底面には第１の外部接続端子２０３
が設けられている。第１の外部接続端子２０３は端子電
極パターン上に半田ボールを形成することで構成されて
いる。第１の外部接続端子２０３は、基部基板２０２a
の底面を覆う全面にアレイ状に複数設けられている。基
部基板２０２ａの上面中央部には、内部接続電極２０４
が設けられている。内部接続電極２０４は端子電極パタ
ーンから構成されている。基部基板２０２ａの内部には
第１のＩＶＨ（Interstitial Via Hole）構造２０５が
その厚み方向に沿って設けられており、第１の外部接続
端子２０３の一部と内部接続電極２０４とは、第１のＩ
ＶＨ構造２０５を介して層間接続されている。The package 200 includes a semiconductor element 201 as an electronic component and a package substrate 20 forming a housing.
2 is provided. The package substrate 202 is made of all layers IV
H structure (All Layer Interstitial Via Hole Structur
e), the base substrate 202a, the side wall substrate 202b, and the ceiling substrate 202c
And The base substrate 202a is a single-layer or multilayer substrate (three-layer substrate in this example).
A first external connection terminal 203 is provided on the bottom surface of the base substrate 202a.
Is provided. The first external connection terminal 203 is formed by forming a solder ball on the terminal electrode pattern. The first external connection terminal 203 is connected to the base substrate 202a.
Are provided in the form of an array over the entire surface covering the bottom surface of. An internal connection electrode 204 is provided at the center of the upper surface of the base substrate 202a.
Is provided. The internal connection electrode 204 is formed from a terminal electrode pattern. Inside the base substrate 202a, a first IVH (Interstitial Via Hole) structure 205 is provided along the thickness direction, and a part of the first external connection terminal 203 and the internal connection electrode 204 I
The layers are connected via a VH structure 205.

【００３０】側壁基板２０２ｂは、内部接続電極２０４
の外側に沿って基部基板２０２ａの端縁に設けられてい
る。側壁基板２０２ｂは基部基板２０２ａを取り囲んで
その全周に設けても良いし、基部基板２０２ａの両端に
設けてもよい。半導体素子２０１を外部環境に晒ないよ
うにするには、基部基板２０２ａを取り囲んでその周囲
全周に側壁基板２０２ｂを設ける方が好ましい。本実施
の形態では、側壁基板２０２ｂを基部基板２０２ａの周
囲全周に設けている。側壁基板２０２ｂは、半導体素子
２０１の収納高さを確保するために、多層基板構造とな
っている。このように側壁基板２０２ｂを設けることに
より、基部基板２０２ａの上面中央には半導体素子収納
用の収納凹部２０６が形成されている。側壁基板２０２
ｂの内部には第２のＩＶＨ構造２０７がその厚み方向に
沿って設けられている。The side wall substrate 202b has an internal connection electrode 204
Along the outer edge of the base substrate 202a. The side wall substrate 202b may be provided on the entire periphery of the base substrate 202a, or may be provided at both ends of the base substrate 202a. In order to prevent the semiconductor element 201 from being exposed to the external environment, it is preferable to surround the base substrate 202a and provide a side wall substrate 202b all around the base substrate 202a. In the present embodiment, the side wall substrate 202b is provided all around the base substrate 202a. The side wall substrate 202b has a multilayer substrate structure in order to secure a storage height of the semiconductor element 201. By providing the side wall substrate 202b in this manner, a housing recess 206 for housing a semiconductor element is formed at the center of the upper surface of the base substrate 202a. Side wall substrate 202
A second IVH structure 207 is provided inside b along the thickness direction.

【００３１】内部接続電極２０４には、半導体素子２０
１の接続端子２０１ａが導電性接着剤や半田等により電
気的に接続されている。これにより、半導体素子２０１
は収納凹部２０６に収納されて基部基板２０２ａの上面
に実装されている。半導体素子２０１と基部基板２０２
ａとの間の隙間は封止樹脂２０８により埋められてい
る。The semiconductor element 20 is connected to the internal connection electrode 204.
One connection terminal 201a is electrically connected by a conductive adhesive, solder, or the like. Thereby, the semiconductor element 201
Are housed in the housing recess 206 and mounted on the upper surface of the base substrate 202a. Semiconductor element 201 and base substrate 202
The gap between a and a is filled with the sealing resin 208.

【００３２】天井基板２０２ｃは、基部基板２０２ａと
同等の大きさを備えており、収納凹部２０６の上部を覆
う形で、側壁基板２０２ｂの上端に接続固定されてい
る。天井基板２０２ｃは、複雑で接続点の多い内部接続
構造に対応できるように多層基板構造をしており、その
内部には、その厚み方向に沿って第３のＩＶＨ構造２０
９が設けられている。第３のＩＶＨ構造２０９は第２の
ＩＶＨ構造２０７に接続されている。天井基板２０２ｃ
の上面には、第２の外部接続端子２１０が設けられてい
る。第２の外部接続端子２１０は端子電極パターン上に
半田ボールを形成することで構成されている。第２の外
部接続端子２１０は天井基板２０２ｃの上面をほぼ覆う
全面にアレイ状に複数設けられている。第２の外部接続
端子２１０は第３のＩＶＨ構造２０９に接続されてい
る。The ceiling substrate 202c has the same size as the base substrate 202a, and is connected and fixed to the upper end of the side wall substrate 202b so as to cover the upper part of the storage recess 206. The ceiling board 202c has a multilayer board structure so as to be compatible with an internal connection structure having a complicated and many connection points, and has a third IVH structure 20 along its thickness direction.
9 are provided. The third IVH structure 209 is connected to the second IVH structure 207. Ceiling board 202c
A second external connection terminal 210 is provided on the upper surface of the first external connection terminal. The second external connection terminal 210 is formed by forming a solder ball on the terminal electrode pattern. The plurality of second external connection terminals 210 are provided in an array on the entire surface almost covering the upper surface of the ceiling substrate 202c. The second external connection terminal 210 is connected to the third IVH structure 209.

【００３３】次に、第１〜第３のＩＶＨ構造２０５、２
０７、２０９と、半導体素子２０１と、第１、第２の外
部接続端子２０３、２１０との間の接続関係を説明す
る。第１のＩＶＨ構造２０５は次の第１〜第３の導通路
Ａ〜Ｃを形成している。第１の導通路Ａは、第１の外部
接続端子２０３のいずれかと内部接続端子２０４とを直
列に接続している。第２の導通路Ｂは、第１の外部接続
端子２０３のいずれかに対して、内部接続端子２０４
と、基部基板２０２ａ上の側壁基板接続箇所とを並列に
接続している。第３の導通路Ｃは、第１の外部接続端子
２０３のいずれかと基部基板２０２ａ上の側壁基板接続
箇所とを、内部接続端子２０４から切り離した状態で接
続している。Next, the first to third IVH structures 205, 2
The connection relationship between the first and second external connection terminals 203 and 210, the semiconductor element 201, and the first and second external connection terminals 203 and 210 will be described. The first IVH structure 205 forms the following first to third conduction paths A to C. The first conduction path A connects any one of the first external connection terminals 203 and the internal connection terminal 204 in series. The second conduction path B is connected to one of the first external connection terminals 203 with the internal connection terminal 204.
And the side wall substrate connection portion on the base substrate 202a are connected in parallel. The third conduction path C connects any one of the first external connection terminals 203 to a connection point of the side wall substrate on the base substrate 202 a while being separated from the internal connection terminal 204.

【００３４】第２のＩＶＨ構造２０７は、次の第４〜第
６の導通路Ｄ〜Ｆを形成している。第４の導通路Ｄは、
上述した第２の導通路Ｂの上端と側壁基板２０２ｂ上の
天井基板接続箇所とを接続している。第５の導通路Ｅ
は、上述した第３の導通路Ｃの上端と側壁基板２０２ｂ
上の天井基板接続箇所とを接続している。第６の導通路
Ｆは、内部接続端子２０４のいずれかと側壁基板２０２
ｂ上の天井基板接続箇所とを接続している。第６の導通
路Ｆは第１のＩＶＨ構造２０５の一部を導通路として含
んでいる。The second IVH structure 207 forms the following fourth to sixth conduction paths DF. The fourth conduction path D is
The upper end of the second conductive path B described above is connected to the ceiling board connection point on the side wall board 202b. Fifth conduction path E
Are the upper end of the third conductive path C and the side wall substrate 202b.
It is connected to the upper ceiling board connection point. The sixth conduction path F is connected to one of the internal connection terminals 204 and the side wall substrate 202.
b. It is connected to the ceiling board connection point. The sixth conduction path F includes a part of the first IVH structure 205 as a conduction path.

【００３５】第３のＩＶＨ構造２０９は、次の第７〜第
９の導通路Ｇ〜Ｉを形成している。第７の導通路Ｇは、
上述した第４の導通路Ｄの上端と第2の外部接続端子２
１０のいずれかとを接続している。第８の導通路Ｈは、
上述した第５の導通路Ｅの上端と第２の外部接続端子２
１０のいずれかとを接続している。第９の導通路Ｉは、
上述した第６の導通路Ｆと第２の外部接続端子２１０の
いずれかとを接続している。The third IVH structure 209 forms the following seventh to ninth conduction paths GI. The seventh conduction path G is
The upper end of the fourth conduction path D and the second external connection terminal 2
10 is connected. The eighth conduction path H is
The upper end of the fifth conduction path E and the second external connection terminal 2
10 is connected. The ninth conduction path I is
The above-described sixth conduction path F is connected to one of the second external connection terminals 210.

【００３６】以上の導通路Ａ〜Ｉにより、第１、第２の
外部接続端子２０３、２１０と半導体素子２０１とは次
のように接続されている。すなわち、第１の外部接続端
子２０３のいずれかと半導体素子２０１とは直列に接続
されている。この接続は、第１の導通路Ａを介して形成
されている。また、半導体素子２０１と第2の外部接続
端子２１０のいずれかとは、第１の外部接続端子２０３
のいずれかに対して並列に接続されている。この接続
は、第2の導通路Ｂ、第４の導通路Ｄ、および第７の導
通路Ｇを介して形成されている。第１の外部接続端子２
０３のいずれかと半導体素子２０１と第2の外部接続端
子２１０のいずれかとは、互いに直列に接続されてい
る。この接続は、第１の導通路Ａ、第６の導通路Ｆ、お
よび第９の導通路Iを介して形成されている。第１の外
部接続端子２０１のいずれかと第２の外部接続端子２１
０のいずれかとは、半導体素子に０１を介することなく
互いに直列に接続されている。この接続は、第３の導通
路Ｃ、第５の導通路Ｅ、および第８の導通路Ｈを介して
形成されている。The first and second external connection terminals 203 and 210 and the semiconductor element 201 are connected as follows by the above conduction paths A to I. That is, one of the first external connection terminals 203 and the semiconductor element 201 are connected in series. This connection is formed via the first conduction path A. Further, the semiconductor element 201 and one of the second external connection terminals 210 are connected to the first external connection terminal 203.
Are connected in parallel to either of them. This connection is formed via a second conduction path B, a fourth conduction path D, and a seventh conduction path G. First external connection terminal 2
03, and any one of the semiconductor element 201 and the second external connection terminal 210 is connected in series with each other. This connection is formed via the first conductive path A, the sixth conductive path F, and the ninth conductive path I. Any one of the first external connection terminals 201 and the second external connection terminal 21
Any one of 0 is connected to the semiconductor element in series without passing through 01. This connection is formed via a third conduction path C, a fifth conduction path E, and an eighth conduction path H.

【００３７】以上のようにして半導体素子２０１を内蔵
した実装体２００は構成されている。The mounting body 200 having the semiconductor element 201 built therein is constructed as described above.

【００３８】図1では半導体素子２０１とパッケージ基
板２０２の内部接続が半田によるフリップチップ接続の
例を示したが、内部接続の形態はこれに限らない。例え
ば図２に示すようにＡｕワイヤー３０１を用いたワイヤ
ーボンディング接続でも良いし、図３に示すようにスタ
ッドバンプ４０１と導電性樹脂４０２とを用いたフリッ
プチップ接続でも良い。ワイヤーボンディング接続に比
べフリップチップ接続の方が端子数、高周波特性などの
点で有利である。FIG. 1 shows an example in which the internal connection between the semiconductor element 201 and the package substrate 202 is made by flip-chip connection using solder, but the form of the internal connection is not limited to this. For example, a wire bonding connection using an Au wire 301 as shown in FIG. 2 may be used, or a flip chip connection using a stud bump 401 and a conductive resin 402 as shown in FIG. Flip chip connection is more advantageous than wire bonding connection in terms of number of terminals, high frequency characteristics, and the like.

【００３９】この実装体２００では、パッケージ基板２
０２の上下面に第1、第2の外部接続端子２０３、２1０
を備えている。さらには、半導体素子２０１を配置した
箇所を覆ってその上方位置にも天井基板２０２ｃは設け
られている。そのため、半導体素子２０１の上側を覆っ
てその上方位置にも、第2の外部接続端子２１０を設け
ることができる。したがって、パッケージ基板２０２の
上下面でほぼ同数の外部接続コンタクトを実現すること
が可能となっている。さらには、この実装体２００で
は、パッケージ基板２０２として、全層ＩＶＨ構造の樹
脂多層基板を用いているので、第１、第2の外部接続端
子２０３、２１０の数を十分確保したうえで小型化する
ことが可能となっている。In this mounting body 200, the package substrate 2
02, the first and second external connection terminals 203, 210
It has. Further, a ceiling substrate 202c is provided at a position above and covering the place where the semiconductor element 201 is arranged. Therefore, the second external connection terminal 210 can be provided at a position above and above the semiconductor element 201. Therefore, it is possible to realize substantially the same number of external connection contacts on the upper and lower surfaces of the package substrate 202. Furthermore, in this mounting body 200, since a resin multilayer substrate having an all-layer IVH structure is used as the package substrate 202, the number of first and second external connection terminals 203 and 210 is sufficiently ensured, and the size is reduced. It is possible to do.

【００４０】また、図１に示す実装体２００では、第１
の外部接続端子２０３を、基部基板２０２aの裏面全面
にアレイ状に配置していたが、図４に示すように、基部
基板２０２ａの底面の中央部であって半導体素子２０１
と対向する部分４０１には、第１の外部接続端子２０３
を設けないようにしてもよい。このような実装体２０
０'によれば、実装体２００'を他の二次実装対象部材に
二次実装した場合において次のような利点がある。すな
わち、二次実装したのち、上記二次実装対象部材に対し
て曲げ等の外力が付加されても、その応力が実装体２０
０'との接続部分に集中せず、２次実装後の実装体２０
０'の信頼性を向上させることができる。なお、この場
合、半導体素子２０１が実装されているパッケージ基板
２０２を、フィルム基材等（例えば、ポリイミドフィル
ム）のように、薄くて剛性の小さい材料を選ぶことで、
実装体２００'との接続部分に対する応力集中を、さら
に緩和させることが可能となる。このような応力集中を
緩和させるために、先述した実装体２００では封止樹脂
２０８を設ける必要があった。これに対して、実装体２
００'では応力集中を緩和することができるので、封止
樹脂２０８を省略することも可能となる。Also, in the mounting body 200 shown in FIG.
Are arranged in an array on the entire back surface of the base substrate 202a. However, as shown in FIG. 4, the semiconductor device 201 is located at the center of the bottom surface of the base substrate 202a.
The first external connection terminal 203
May not be provided. Such a mounting body 20
According to 0 ′, the following advantages are obtained when the mounting body 200 ′ is secondarily mounted on another secondary mounting target member. That is, even if external force such as bending is applied to the secondary mounting target member after the secondary mounting, the stress is not
The package 20 after the secondary mounting without being concentrated on the connection portion with 0 '
The reliability of 0 ′ can be improved. In this case, the package substrate 202 on which the semiconductor element 201 is mounted is made of a thin and low-rigid material such as a film base material (eg, a polyimide film).
It is possible to further reduce the stress concentration on the connection portion with the mounting body 200 '. In order to alleviate such stress concentration, it is necessary to provide the sealing resin 208 in the above-described mounting body 200. On the other hand, the mounting body 2
In the case of 00 ′, the stress concentration can be reduced, so that the sealing resin 208 can be omitted.

【００４１】以上説明した実装体２００を用いれば、図
５に示すような実装構造が実現できる。この実装構造
は、図１の構成を有する第１、第2の実装体２００Ａ、
２００Ｂをマザー基板５０１上に積層した状態で実装す
る構造である。まず、マザー基板５０１上に第１の実装
体２００Ａを実装する。第１の実装体２００Ａは、その
第１の外部接続端子２０３を介してマザー基板５０１に
接続固定する。さらに、第１の実装体２００Ａに第2の
実装体２００Ｂを実装する。第２の実装体２００Ｂは、
その第１の外部接続端子２０３を、第１の実装体２００
Ａの第2の外部接続端子２１０に接続することで実装す
る。Using the mounting body 200 described above, a mounting structure as shown in FIG. 5 can be realized. This mounting structure includes first and second mounting bodies 200A having the configuration shown in FIG.
This is a structure in which 200B is mounted in a state of being stacked on a motherboard 501. First, the first mounting body 200A is mounted on the mother board 501. The first mounting body 200A is connected and fixed to the motherboard 501 via the first external connection terminals 203. Further, the second package 200B is mounted on the first package 200A. The second mounting body 200B is
The first external connection terminal 203 is connected to the first package 200
A is mounted by connecting to the second external connection terminal 210 of A.

【００４２】以上のようにして第１、第2の実装体２０
０Ａ、２００Ｂを積層した状態でマザー基板５０１に実
装すると、第１、第2の実装体２００Ａ、２００Ｂに設
けた各導通路により次のような接続形態を実現できる。
なお、以下の説明では、第１の実装体２００Ａに実装し
た半導体素子２０１を第１の半導体素子２０１Ａと称
し、第2の実装体２００Ｂに実装した半導体素子２０１
を第2の半導体素子２０１Ｂと称す。As described above, the first and second mounting bodies 20
When the motherboard 501 is mounted with the layers 0A and 200B stacked, the following connection forms can be realized by the respective conductive paths provided in the first and second mounting bodies 200A and 200B.
In the following description, the semiconductor element 201 mounted on the first mounting body 200A is referred to as a first semiconductor element 201A, and the semiconductor element 201 mounted on the second mounting body 200B.
Is referred to as a second semiconductor element 201B.

【００４３】すなわち、第１の半導体素子２０１Ａの入
出力端子のいずれかを、直接マザー基板５０１の配線に
接続できる。第１の半導体素子２０１Ａの入出力端子の
いずれかと、第2の半導体素子２０１Ｂの入出力端子の
いずれかとを、互いに直列接続状態でマザー基板５０１
の配線に接続できる。第１の半導体素子２０１Ａの入出
力端子のいずれかと、第2の半導体素子２０１Ｂの入出
力端子のいずれかとを、互いに並列接続状態でマザー基
板５０１の配線に接続できる。第２の半導体素子２０１
Ｂの入出力端子のいずれかを、第１の半導体素子２０１
Ａを介することなくマザー基板５０１の配線に直接接続
できる。なお、第１、第2の半導体素子２０１Ａ、２０
１Ｂを互いに並列状態でマザー基板５０１に接続する構
造は、これら半導体素子２０１Ａ、２０１Ｂがメモリー
素子である場合に特に都合がよい。That is, any one of the input / output terminals of the first semiconductor element 201 A can be directly connected to the wiring of the motherboard 501. One of the input / output terminals of the first semiconductor element 201A and one of the input / output terminals of the second semiconductor element 201B are connected to each other in series with the motherboard 501.
Can be connected. Any of the input / output terminals of the first semiconductor element 201A and any of the input / output terminals of the second semiconductor element 201B can be connected to the wiring of the mother board 501 in a state of being connected to each other in parallel. Second semiconductor element 201
B of the first semiconductor element 201
A connection can be made directly to the wiring of the mother board 501 without passing through A. Note that the first and second semiconductor elements 201A, 20A
The structure in which the semiconductor devices 201A and 201B are connected to the mother substrate 501 in a parallel state is particularly convenient when the semiconductor devices 201A and 201B are memory devices.

【００４４】以上の説明では、実装体２００を二層に積
層した状態でマザー基板５０１に実装したが、これはそ
の一例に過ぎず、三層以上に積層した状態で、実装体２
００をマザー基板５０１に実装することができるのはい
うまでもない。In the above description, the mounting body 200 is mounted on the mother board 501 in a state of being stacked in two layers. However, this is only an example, and the mounting body 200 is stacked in three or more layers.
Needless to say, 00 can be mounted on the motherboard 501.

【００４５】このように、実装体２００の上下に設けた
第１、第2の外部接続端子２０３、２１０によって、実
装体２００の複合化が容易に実現できる。さらには、第
１、第2の外部接続端子２０３、２１０を、パッケージ
基板２０２の表裏面上に互いに同数かつほぼ同位置に配
置することができる。したがって、実装体２００を積層
実装する際に、第１、第2の外部接続端子２０３、２１
０の位置合わを行うだけで積層実装ができるようにな
る。そのため、特にパッケージ基板２０２のサイズ規制
を受けることなく、同一サイズの実装体であっても積層
実装することが可能となる。As described above, the composite body 200 can be easily realized by the first and second external connection terminals 203 and 210 provided above and below the package body 200. Further, the first and second external connection terminals 203 and 210 can be arranged on the front and back surfaces of the package substrate 202 in the same number and substantially at the same position. Therefore, when the mounting body 200 is stacked and mounted, the first and second external connection terminals 203, 21
The stack mounting can be performed only by performing the alignment of 0. For this reason, it is possible to stack and mount even the same-sized mounting bodies without being particularly restricted by the size of the package substrate 202.

【００４６】また、図５に示す実装体２００Ａ、２００
Ｂの実装構造の場合、マザー基板５０１とこれら実装体
２００Ａ、２００Ｂとの間に生じる応力は、下側の実装
体（第１の実装体２００Ａ）で緩和されるために、上側
の実装体（第2の実装体２００Ｂ）に及びにくい。しか
しながら、その分、下側の実装体（第１の実装体２００
Ａ）とマザー基板５０１との間の接続部分に応力が集中
することになる。Further, the mounting bodies 200A, 200 shown in FIG.
In the case of the mounting structure B, the stress generated between the mother board 501 and the mounting bodies 200A and 200B is relieved by the lower mounting body (first mounting body 200A), so that the upper mounting body ( It is difficult to reach the second mounting body 200B). However, the lower package (the first package 200)
Stress concentrates on the connection between A) and the mother substrate 501.

【００４７】実装後の応力としては、マザー基板５０１
と第１、第2の実装体２００Ａ、２００Ｂとの間の熱膨
張係数の差により生じる内部応力や、実装後のマザー基
板５０１にかかる曲げ等の外部ストレスによる応力が考
えられる。As the stress after mounting, the mother board 501
Internal stress caused by a difference in thermal expansion coefficient between the first and second mounting bodies 200A and 200B, and stress due to external stress such as bending applied to the mother board 501 after mounting are considered.

【００４８】これらの応力を緩和するために、図６に示
す実装構造を取ることが効果的である。すなわち、図５
の実装構造では、第１の実装体２００Ａが有する第１の
半導体素子２０１Ａと、マザー基板５０１とが、パッケ
ージ基板２０２の基部基板２０２aを介して一体的とな
って接続固定されるために、第１の半導体素子２０１Ａ
の熱膨張とマザー基板５０１の熱膨張差を緩和させるこ
とは困難であった。これに対して、図６に示す実装構造
では、第１の実装体２００Ａを、その第2の外部接続端
子２１０を介してマザー基板５０１に接続固定してい
る。これにより、第１の実装体２００Ａを、図５の構造
とは天地逆にして実装し、第１の半導体素子２０１Ａを
第１の実装体２００Ａの内部でその上端側に配置した。In order to alleviate these stresses, it is effective to adopt a mounting structure shown in FIG. That is, FIG.
In the mounting structure of (1), the first semiconductor element 201A of the first mounting body 200A and the mother substrate 501 are integrally connected and fixed via the base substrate 202a of the package substrate 202. 1 semiconductor element 201A
It was difficult to reduce the difference between the thermal expansion of the mother substrate 501 and the thermal expansion of the mother substrate 501. On the other hand, in the mounting structure shown in FIG. 6, the first mounting body 200A is connected and fixed to the motherboard 501 via the second external connection terminal 210. As a result, the first mounting body 200A was mounted upside down from the structure of FIG. 5, and the first semiconductor element 201A was disposed inside the first mounting body 200A on the upper end side.

【００４９】これにより、マザー基板５０１と第１の半
導体素子２０１Ａとの間に、天井基板２０２ｃ、側壁基
板２０２ｂ、基部基板２０２ａという複数の部材が配置
され、しかも、第１の半導体素子２０１Ａとマザー基板
５０１との間には、収納凹部２０６の内部空間という非
常に熱伝導しにくく、しかもパッケージ基板２０２の変
形を吸収できる部材が介在することになる。Thus, a plurality of members such as a ceiling substrate 202c, a side wall substrate 202b, and a base substrate 202a are arranged between the mother substrate 501 and the first semiconductor element 201A. Between the substrate 501, a member that is very difficult to conduct heat, that is, the internal space of the storage recess 206, and that can absorb the deformation of the package substrate 202 is interposed.

【００５０】したがって、第１の半導体素子２０１Ａと
マザー基板５０１との間に多少の熱膨張係数の違いがあ
ったとしても、その内部応力は、両者（第１の半導体素
子２０１Ａとマザー基板５０１）の間で緩和される結
果、第１の半導体素子２０１Ａ（その接続箇所を含む）
が内部応力で破損することはない。Therefore, even if there is a slight difference in the coefficient of thermal expansion between the first semiconductor element 201A and the mother substrate 501, the internal stress is the same (the first semiconductor element 201A and the mother substrate 501). As a result, the first semiconductor element 201A (including its connection part)
Is not damaged by internal stress.

【００５１】さらには、収納凹部２０６において、第１
の半導体素子２０１Ａと天井基板２０２ｃとを互いに一
体に固定することなく、さらに好ましくは、両者の間に
隙間を設けておけば、実装後のマザー基板５０１にかか
る曲げ等の外部ストレスによる応力は、天井基板２０２
ｃの変形により緩和される結果、第１の半導体素子２０
１Ａ（その接続箇所を含む）が外部ストレスによる応力
で破損するはない。Further, in the storage recess 206, the first
Without fixing the semiconductor element 201A and the ceiling substrate 202c integrally to each other, more preferably, if a gap is provided between the two, the stress due to external stress such as bending applied to the mother substrate 501 after mounting is reduced. Ceiling board 202
c, the first semiconductor element 20
1A (including the connection portion) is not damaged by stress due to external stress.

【００５２】以上のようにして応力集中に起因する破損
を防止することで実装信頼性を向上させることができ
る。As described above, mounting reliability can be improved by preventing breakage due to stress concentration.

【００５３】図２では、パッケージ基板２０２の第１、
第2の外部接続端子２０３、２１０として、半田ボール
２０８を含むものを用いてるが、これは外部接続端子の
一例に過ぎず、他の構造であってもよい。例えば、半田
ボールの代わりに、導電性ペーストであっても良い。ま
た、上記した各図では基部基板２０２ａの底面や天井基
板２０２ｃの上面には第１、第2の外部接続端子２０
３、２１０だけを設けているために、これらの面にソル
ダーレジスト層を形成する必要はないが、ソルダーレジ
ストを設けても構わない。また、第１、第2の外部接続
端子２０3、２１０を構成する半田ボールにクラックが
発生することを抑制するには、その表面に補強樹脂層を
設けても良い。In FIG. 2, the first of the package substrates 202,
As the second external connection terminals 203 and 210, those including the solder balls 208 are used, but this is merely an example of the external connection terminals, and other structures may be used. For example, a conductive paste may be used instead of the solder ball. In each of the drawings described above, the first and second external connection terminals 20 are provided on the bottom surface of the base substrate 202a and the top surface of the ceiling substrate 202c.
Since only 3 and 210 are provided, it is not necessary to form a solder resist layer on these surfaces, but a solder resist may be provided. Further, in order to suppress the occurrence of cracks in the solder balls constituting the first and second external connection terminals 203 and 210, a reinforcing resin layer may be provided on the surface thereof.

【００５４】なお、図１において、符号２１１は配線で
あり、２１２は絶縁性基材であり、２１３はインナービ
アである。さらには、図１では九層の配線層を有する多
層基板の例を示したが、層数に関しては、配線引き出し
の密度や、パッケージ基板の厚み等の兼ね合いで自由に
選択することができる。この構造はセラミック基板でも
実現可能であるが、樹脂基板の方が製造中にかかる温度
が低く、パッケージ基板２０２内に半導体素子２０１を
収納する収納凹部２０６を形成しやすい点で有利であ
る。また、図１に示したパッケージ基板２０２は全層が
同じビア接続構造をもち、製造プロセスが容易であり、
パッケージ基板製造プロセス中に半導体素子２０１の実
装工程を容易に組み込める利点がある。パッケージ基板
２０１内のビアでは導電性ペーストによる電気的接続が
なされている。ビアの電気的接続はめっきや金属剛体で
も実現可能であるが、導電性ペーストによるビア接続に
よって、簡便で安価な接続工程が実現される。ビアの大
きさについては、全層同じにする必要がない。むしろ、
高密度なビア接続が必要な部分では、ビア径を小さくす
ることが望ましい。ビア径としては、２００μmから３
０μm程度までが実現されている。この構造では、ビア
オンビア構造を実現可能であるため高密度配線を実現し
易く、パッケージ基板２０２上面の第１、第2の外部接
続端子２０３、２１０への配線の引き出しが容易とな
る。特に、半導体素子２０１周囲の基板部分では、実装
体２００におけるサイズの小型化の点からも高密度な層
間接続が求められる。絶縁性基材２１２については、ガ
ラスエポキシ基材、アラミド不織布基材、フィルム基
材、樹脂とフィラからなるコンポジット基材等が使用さ
れ、全層で同じ基材にする必要はない。熱膨張係数、剛
性、配線密度、ビア密度等の点から最適な基材を選択す
ることができる。同一基材でも厚みは必要に応じて選択
できる。基材厚みとしては、１００μm以上から１０μm
程度までが実現されており、特に、フィルム基材の場合
では、薄い基材まで使用可能でる。In FIG. 1, reference numeral 211 denotes a wiring, 212 denotes an insulating base material, and 213 denotes an inner via. Further, FIG. 1 shows an example of a multilayer substrate having nine wiring layers. However, the number of layers can be freely selected depending on the density of wiring leads and the thickness of the package substrate. Although this structure can be realized with a ceramic substrate, the resin substrate is advantageous in that the temperature required during manufacturing is lower and the storage recess 206 for storing the semiconductor element 201 can be easily formed in the package substrate 202. Also, the package substrate 202 shown in FIG. 1 has the same via connection structure in all layers, and the manufacturing process is easy,
There is an advantage that the mounting process of the semiconductor element 201 can be easily incorporated into the package substrate manufacturing process. The vias in the package substrate 201 are electrically connected by a conductive paste. Although the electrical connection of the via can be realized by plating or a rigid metal body, a simple and inexpensive connection process is realized by the via connection using the conductive paste. The size of the via does not need to be the same for all layers. Rather,
In portions where high-density via connection is required, it is desirable to reduce the via diameter. The via diameter is from 200 μm to 3
Up to about 0 μm has been realized. In this structure, a via-on-via structure can be realized, so that high-density wiring can be easily realized, and wiring can be easily led out to the first and second external connection terminals 203 and 210 on the upper surface of the package substrate 202. In particular, in the substrate portion around the semiconductor element 201, high-density interlayer connection is required from the viewpoint of miniaturization of the size of the mounting body 200. As the insulating substrate 212, a glass epoxy substrate, an aramid nonwoven fabric substrate, a film substrate, a composite substrate composed of a resin and a filler, and the like are used, and it is not necessary to use the same substrate for all layers. An optimum base material can be selected from the viewpoints of thermal expansion coefficient, rigidity, wiring density, via density, and the like. The thickness of the same base material can be selected as needed. As the thickness of the substrate, from 100 μm or more to 10 μm
In particular, in the case of a film substrate, even a thin substrate can be used.

【００５５】以上の例では半導体素子２０１を実装する
実装体２００を例にして説明したが、実装する電気回路
素子は半導体素子２０１だけには限らない。抵抗・コン
デンサ・コイルなどの受動素子や水晶発振子などの能動
素子をパッケージ基板２０２に実装することも可能であ
る。この場合にもマザー基板５０１の小型化に対して大
きな効果がある。In the above example, the mounting body 200 on which the semiconductor element 201 is mounted has been described as an example, but the electric circuit element to be mounted is not limited to the semiconductor element 201. It is also possible to mount passive elements such as resistors, capacitors, and coils, and active elements such as crystal oscillators on the package substrate 202. Also in this case, there is a great effect on miniaturization of the mother substrate 501.

【００５６】次に、本発明の実装体２００の製造方法に
ついて、図を用いて詳しく説明する。ここでは、図２に
示した九層の配線層を有する全層ＩＶＨ構造のパッケー
ジ基板２０２を有する実装体について説明する。パッケ
ージ基板２０２にいては、全層同一のプロセスで形成さ
れるのであるが、説明しやすいように基部基板２０２a
と、側壁基板２０２ｂおよび天井基板２０２ｃとに分け
て説明する。Next, a method for manufacturing the mounting body 200 of the present invention will be described in detail with reference to the drawings. Here, a package having a package substrate 202 having an all-layer IVH structure having nine wiring layers shown in FIG. 2 will be described. Although the package substrate 202 is formed by the same process for all layers, the base substrate 202a is formed for ease of explanation.
And a side wall substrate 202b and a ceiling substrate 202c.

【００５７】図７には、基部基板２０２ａの製造方法が
示されている。まず、図７（ａ）に示されるように、絶
縁性基材２１２にビア７０２を形成したのち、そのビア
７０２に導電体７０３を充填する。絶縁性基材２１２と
しては、未硬化のガラスエポキシプリプレグ、未硬化の
アラミド不織布プリプレグ、未硬化のフィルム基材、両
面接着剤つきのフィルム基材等が用いられる。FIG. 7 shows a method of manufacturing the base substrate 202a. First, as shown in FIG. 7A, a via 702 is formed in an insulating base material 212, and then the via 702 is filled with a conductor 703. As the insulating substrate 212, an uncured glass epoxy prepreg, an uncured aramid nonwoven prepreg, an uncured film substrate, a film substrate with a double-sided adhesive, or the like is used.

【００５８】また、加工での基材保護マスクと、導電体
７０３充填時の保護マスクとして機能するカバーフィル
ムを絶縁性基材２１２の両面に張り付け、工程の後に剥
離する工程を設けてもよい。ビア７０２は、パンチ、ド
リル、レーザー等で加工できるが、炭酸ガスレーザーや
ＹＡＧレーザーを用いると、加工時間が短く、量産性に
優れる。導電体７０３は導電性ペーストを用いるとビア
７０２に対する導電体７０３の充填を簡便に行える。Further, a step of attaching a cover film which functions as a protective mask for the base material during processing and a cover film which functions as a protective mask when filling the conductor 703 on both sides of the insulating base material 212 and peeling off after the step may be provided. The via 702 can be processed by a punch, a drill, a laser, or the like. However, when a carbon dioxide gas laser or a YAG laser is used, the processing time is short and the mass productivity is excellent. When a conductive paste is used for the conductor 703, the via 702 can be easily filled with the conductor 703.

【００５９】次に図７（ｂ）〜（ｃ）に示すように、ビ
ア７０２に導電体７０３を充填した絶縁性基材２１２の
両面に配線材料膜７０４を接着する。配線材料膜７０４
としては、銅箔を用いるのが一般的である。なお、図８
（ａ）〜（ｃ）に示すように、配線保持基材８０１に配
線２１１が形成されている転写基材８０３を用いても良
い。配線保持基材８０１上に形成された配線２１１は、
パターンエッチングやパターンめっきによって形成でき
る。以上のようにした場合、転写基材８０１を接着した
後に配線保持基材８０１を除去すると、絶縁性基材２１
２上には配線２１１が残存することとなる。配線保持基
材８０１は金属箔、フィルム基材が用いられる。金属箔
を用いる場合には、配線保持基材８０１を容易に除去す
ることができる。Next, as shown in FIGS. 7B to 7C, a wiring material film 704 is bonded to both surfaces of the insulating base material 212 in which the conductor 703 is filled in the via 702. Wiring material film 704
It is common to use a copper foil. FIG.
As shown in (a) to (c), a transfer base 803 in which the wiring 211 is formed on the wiring holding base 801 may be used. The wiring 211 formed on the wiring holding base material 801 is
It can be formed by pattern etching or pattern plating. In the case described above, when the wiring holding base 801 is removed after the transfer base 801 is bonded, the insulating base 21 is removed.
2, the wiring 211 remains. As the wiring holding base material 801, a metal foil or a film base material is used. When a metal foil is used, the wiring holding substrate 801 can be easily removed.

【００６０】図７の工程の説明に戻り、配置された配線
材料膜７０４の積層接着は熱圧着により行う。熱圧着は
真空中で行われ、ボイドの発生を抑制することが望まし
い。接着した配線材料膜７０４は、図７（ｄ）に示すよ
うに、パターンエッチングによりパターニングして配線
２１１を形成する。パターン幅を細くする場合には、薄
い銅箔を用いるのが効果的である。銅箔としては、絶縁
性基材２１２上で断線を起こさない９μm程度のものま
でが配線２１１として実現されている。次に図７（ｅ）
に示すように、絶縁性基材２１２の両側に、もう一つの
絶縁性基材２１２（導電体７０３は充填済）を配置し、
さらにこれら絶縁性基材２１２の外側にもう一つの配線
材料膜７０４を配置し、積層接着する（図７（ｆ）参
照）。Returning to the description of the process shown in FIG. 7, the laminated wiring material film 704 is bonded by thermocompression bonding. The thermocompression bonding is performed in a vacuum, and it is desirable to suppress generation of voids. The bonded wiring material film 704 is patterned by pattern etching to form the wiring 211 as shown in FIG. 7D. When narrowing the pattern width, it is effective to use a thin copper foil. As the copper foil, a copper foil having a thickness of about 9 μm that does not cause disconnection on the insulating base material 212 is realized. Next, FIG.
As shown in the figure, another insulating substrate 212 (the conductor 703 is already filled) is arranged on both sides of the insulating substrate 212,
Further, another wiring material film 704 is disposed outside the insulating base material 212 and laminated and adhered (see FIG. 7F).

【００６１】さらに、図７（ｇ）に示すように、接着し
たもう一つの配線材料膜７０４をパターンエッチングし
て配線２１１を形成することで、基部基板２０２aがで
きあがる。Further, as shown in FIG. 7 (g), another wiring material film 704 adhered is pattern-etched to form the wiring 211, whereby the base substrate 202a is completed.

【００６２】このように形成される基部基板２０２aに
おいては、半導体素子２０１の接続用ランドとなる配線
２1１の部分や第１の外部接続端子２０３となる配線２
１１の部分には、その表面にＡｕメッキ処理を行うこと
が、接続信頼性の点から望ましい。Ａｕメッキ処理はＡ
ｕ０．０５μm、Ｎｉ２μm程度するのが好ましい。ま
た、その後のプロセスでＮｉがＡｕに拡散することが問
題となる場合には、第１の外部接続端子２０３となる部
分へのＡｕメッキ処理を、実装体２００の製造プロセス
の最後に行えば良い。In the base substrate 202a formed in this manner, a portion of the wiring 211 serving as a connection land of the semiconductor element 201 and a portion of the wiring 2 serving as the first external connection terminal 203 are formed.
It is desirable to perform Au plating on the surface of the portion 11 from the viewpoint of connection reliability. Au plating is A
Preferably, the thickness is about 0.05 μm and the Ni is about 2 μm. In the case where diffusion of Ni into Au in a subsequent process poses a problem, Au plating on a portion serving as the first external connection terminal 203 may be performed at the end of the manufacturing process of the mounting body 200. .

【００６３】次に、側壁基板２０２ｂおよび天井基板２
０２ｃの製造方法を、図９〜図１１を参照して説明す
る。Next, the side wall substrate 202b and the ceiling substrate 2
02c will be described with reference to FIGS.

【００６４】基本的には基部基板２０２ａの製造方法と
同じなので、重複するところは、省略して説明する。前
述した製造プロセス（図７（ａ）〜図７（ｄ））と同様
の工程である図９（ａ）〜（ｄ）の工程により、天井基
板２０２ｃの底面に位置する第１の絶縁性基材２１２Ａ
を作成する。第１の絶縁性基材２１２Ａには、そのビア
７０２に導電体７０３を充填し、さらには、配線２１１
を形成しておく。しかしながら、配線２１１は絶縁性基
材２１２の一方側の面だけに形成しておく。Since the method is basically the same as the method of manufacturing the base substrate 202a, the description of the overlapping parts will be omitted. 9 (a) to 9 (d), which are the same steps as the above-described manufacturing process (FIGS. 7 (a) to 7 (d)), the first insulating substrate located on the bottom surface of the ceiling substrate 202c. Material 212A
Create In the first insulating base material 212A, the conductor 703 is filled in the via 702, and further, the wiring 211
Is formed. However, the wiring 211 is formed only on one surface of the insulating base 212.

【００６５】次に、配線保持基材８０１に配線２１１が
形成された転写基材８０３を用意する。また、ビア７０
２が導電体７０３で充填され、かつその中央部に収納凹
部２０６が形成された第2の絶縁性基材２１２Ｂを用意
する。そして、図９（ｆ）に示すように、第2の絶縁性
基材２１２Ｂを間にして、その両面に第１の絶縁性基材
２１２Ａと、転写基材８０３とを積層配置する。その
際、第１の絶縁性基材２１２Ａは、配線形成面を第2の
絶縁基材側にして配置する。この状態で図９（ｇ）に示
すように、第１の絶縁性基材２１２Ａの配線材料膜７０
４をパターニングして配線２１１を形成する。このと
き、第１の絶縁性基材２１２Ａの裏面（収納凹部２０６
側）に位置する配線２１１が不用意にエッチングされて
ダメージを受けることを転写基材８０３で防止できる。
これにより、第１の絶縁性基材２１２Ａに対して簡便な
方法でその片側のみにパターニングを実施できる。な
お、収納凹部２０６側に位置する第１の絶縁性基材２１
２Ａに配線２１１を配置しない場合は、上記した転写基
材８０３を用いた転写工程を実施する必要はない。この
場合には、第2の絶縁性基材２１２Ｂの下側に配置する
第３の絶縁性基材２１２Ｃを、エッチング保護材（上述
した説明では転写基材８０３がその機能を果たしてい
る）として用いることができる。Next, a transfer substrate 803 having the wiring 211 formed on the wiring holding substrate 801 is prepared. Also, via 70
2 is filled with a conductor 703, and a second insulating substrate 212B having a storage recess 206 formed in the center thereof is prepared. Then, as shown in FIG. 9F, the first insulating base material 212A and the transfer base material 803 are stacked and arranged on both surfaces of the second insulating base material 212B. At this time, the first insulating base material 212A is arranged with the wiring forming surface facing the second insulating base material. In this state, as shown in FIG. 9G, the wiring material film 70 of the first insulating base material 212A is formed.
4 is patterned to form a wiring 211. At this time, the back surface of the first insulating base material 212A (housing recess 206
The transfer substrate 803 can prevent the wiring 211 located on the (side) side from being carelessly etched and damaged.
Thereby, patterning can be performed on only one side of the first insulating base material 212A by a simple method. Note that the first insulating base material 21 located on the storage recess 206 side is used.
When the wiring 211 is not disposed on 2A, it is not necessary to perform the transfer step using the transfer base material 803 described above. In this case, the third insulating base material 212C disposed below the second insulating base material 212B is used as an etching protection material (in the above description, the transfer base material 803 fulfills its function). be able to.

【００６６】次に図９（ｈ）に示すように、転写基材８
０３の配線保持基材８０１を除去する。さらに、図１０
（ａ）、（ｂ）に示すように、第３、第４の絶縁性基材
２１２Ｃ、２１２Ｄを、第１、第2の絶縁性基材２１２
Ａ、２１２Ｂの積層体の両面それぞれに配置する。これ
ら第３、第４の絶縁性基材２１２Ｃ、２1２Ｄは、導電
体７０３により充填されたビア７０２を有している。第
１の絶縁性機材２１２Ａ側に配置する第３の絶縁性基材
２１２Ｃの外側には、さらに、配線材料膜７０４を配置
する。第2の絶縁性基材２１２Ｂ側に配置する第４の絶
縁性基材２１２Ｄには、第２の絶縁性基材２１２Ｂと同
様、その中央部に収納凹部２０６を有している。さらに
は、第４の絶縁性基材２１２Ｄの外側には転写基材８０
３を配置する。この転写基材８０３は、上述した転写基
材８０３と同様、配線保持基材８０１に配線２１１を形
成して構成されている。ここで、転写基材８０３を用い
るのは先程と同様、第１の絶縁基材２１に形成された配
線２１１をエッチングから保護するためである。Next, as shown in FIG.
The wiring holding substrate 801 of 03 is removed. Further, FIG.
As shown in (a) and (b), the third and fourth insulating bases 212C and 212D are replaced with the first and second insulating bases 212.
A and 212B are arranged on both sides of the laminate. These third and fourth insulating bases 212C and 212D have vias 702 filled with a conductor 703. A wiring material film 704 is further disposed outside the third insulating base material 212C disposed on the first insulating device 212A side. The fourth insulating base 212D disposed on the side of the second insulating base 212B has a storage recess 206 at the center thereof, similarly to the second insulating base 212B. Further, a transfer substrate 80 is provided outside the fourth insulating substrate 212D.
Place 3. The transfer base material 803 is configured by forming the wiring 211 on the wiring holding base material 801 similarly to the transfer base material 803 described above. Here, the reason why the transfer base material 803 is used is to protect the wiring 211 formed on the first insulating base material 21 from etching as in the case described above.

【００６７】その後、図１０（ｃ）に示すように、第３
の絶縁性基材２１２Ｃの配線材料膜７０４をパターニン
グし、転写基材８０３の配線保護基材８０１を除去すれ
ば図１０（ｄ）に示す側壁基板２０２ｂと天井基板２０
２ｃとができあがる。ここでは、配線２１１の層を５層
とした例を示したが、必要な層数に応じて前述の工程を
繰り返せ良い。Thereafter, as shown in FIG.
By patterning the wiring material film 704 of the insulating base material 212C and removing the wiring protection base material 801 of the transfer base material 803, the side wall substrate 202b and the ceiling substrate 20 shown in FIG.
2c is completed. Here, an example is shown in which the number of layers of the wiring 211 is five, but the above-described steps may be repeated according to the required number of layers.

【００６８】次に、上述した図７の工程を経て作成され
た基部基板２０２ａ（図１１（ａ）参照）に、図１１
（ｂ）に示すように、半導体素子２０１を実装する。こ
こでは、半田によるフリップチップ接続の例を示してい
るが、ワイヤーボンディング接続でも良いし、スタッド
バンプと導電性樹脂を用いたフリップチップ接続でも良
い。次に、図１１（ｃ）、（ｄ）に示すように、側壁基
板２０２ｂと天井基板２０２ｃとを積層した積層体と基
部基板２０２aとを第５の絶縁性基材２１２Ｅを間にし
て、積層一体化する。第５の絶縁性基材２１２Ｅには、
予め収納凹部２０６を形成し、かつ、そのビア７０２を
導電体７０３で充填しておく。Next, the base substrate 202a (see FIG. 11A) formed through the above-described process of FIG.
As shown in (b), the semiconductor element 201 is mounted. Here, an example of flip chip connection using solder is shown, but wire bonding connection may be used, or flip chip connection using stud bumps and conductive resin may be used. Next, as shown in FIGS. 11C and 11D, a laminate in which the side wall substrate 202b and the ceiling substrate 202c are laminated and the base substrate 202a are laminated with the fifth insulating base material 212E interposed therebetween. Integrate. The fifth insulating base material 212E includes:
The storage recess 206 is formed in advance, and the via 702 is filled with the conductor 703.

【００６９】なお、絶縁性基材２１２Ａ〜２１２Ｅに未
硬化のガラスエポキシプリプレグ、未硬化のアラミド不
織布プリプレグ、未硬化のフィルム基材、両面接着剤つ
きのフィルム基材等を用いた場合、接着剤としては熱硬
化性樹脂を用いれば、低温での接着が実現され、半導体
素子２０１への熱的影響が無視できる。When an uncured glass epoxy prepreg, an uncured aramid nonwoven prepreg, an uncured film substrate, a film substrate with a double-sided adhesive, or the like is used for the insulating substrates 212A to 212E, the adhesive is used as an adhesive. If a thermosetting resin is used, bonding at a low temperature is realized, and the thermal effect on the semiconductor element 201 can be ignored.

【００７０】以上、説明した製造方法では、第１、第2
の外部接続端子２０３、２1０となる配線２１１を前も
って形成しておいた絶縁性基材２１２Ａ〜２１２Ｅを積
層接着しているが、積層接着後に、第１、第2の外部接
続端子２０３、２１０となる配線２１１をパターニング
してもかまわない。In the manufacturing method described above, the first and second
Insulating bases 212A to 212E, in which wirings 211 to be external connection terminals 203 and 210 are formed in advance, are laminated and bonded. After lamination and bonding, the first and second external connection terminals 203 and 210 are connected. May be patterned.

【００７１】第１、第2の外部接続端子２０３、２１０
となる配線２１１には、この後、図１１（ｅ）に示すよ
うに、Ａｕめっき処理が施され、その上に半田ボール１
１０１が形成されて実装体２００が完成する。なお、半
田ボール１１０１の代わりに、導電性ペーストであって
も良い。また、図１１（ｄ）ではパッケージ基板２０２
の最外層に第１、第2の外部接続端子２０３、２１０を
構成する配線（ランド）のみを配置しているため、半田
ボール１１０１を形成する際に、ソルダーレジストを必
要としないが、半田ボール１１０１のクラック発生を抑
制するためには、パッケージ基板２０２の表面に補強樹
脂層を設けても良い。First and second external connection terminals 203 and 210
Then, as shown in FIG. 11E, an Au plating process is performed on the wiring 211 to be
101 is formed, and the mounting body 200 is completed. Note that a conductive paste may be used instead of the solder ball 1101. Also, in FIG. 11D, the package substrate 202
Since only the wirings (lands) constituting the first and second external connection terminals 203 and 210 are arranged on the outermost layer of the solder ball 1101, no solder resist is required when the solder ball 1101 is formed. In order to suppress the generation of the crack 1101, a reinforcing resin layer may be provided on the surface of the package substrate 202.

【００７２】以上の製造方法は、配線２１１の転写プロ
セスと配線材料膜７０４のパターニングの組み合わせで
成り立っているが、この組み合わせは多数考えられ、必
要に応じて最適なプロセスを選択すればよい。配線転写
プロセスを用いる場合は配線２１１の形成を行った後に
転写するので、配線２１１のパターン検査後良品のみを
使用でき、歩留まりに対して利点がある。The above-described manufacturing method is based on a combination of the transfer process of the wiring 211 and the patterning of the wiring material film 704. Many combinations are conceivable, and an optimum process may be selected as needed. When the wiring transfer process is used, since the transfer is performed after the formation of the wiring 211, only the non-defective product after the pattern inspection of the wiring 211 can be used, which is advantageous in the yield.

【００７３】また、以上の製造方法では、凹状のパッケ
ージ基板の上面への外部接続端子引き出し部分を用いた
が、パッケージ基板２０２の基部基板２０２aの上面に
凹部を形成しても同様の構造が実現できる。製造プロセ
スも同様のプロセスで実現できる。In the above manufacturing method, the external connection terminal lead-out portion is used on the upper surface of the concave package substrate. However, the same structure can be realized even if a concave portion is formed on the upper surface of the base substrate 202a of the package substrate 202. it can. The manufacturing process can be realized by a similar process.

【００７４】また、以上の製造方法では、パッケージ基
板２０２の側壁基板２０２ｂ、天井基板２０２ｃの積層
体と、基部基板２０２aとを別々に分けて説明したが、
製造プロセスを上述のよう分割して実施する必要はな
い。実際には同様の製造プロセスを使用しており、同一
プロセスで実施できる。In the above manufacturing method, the stacked body of the side wall substrate 202b and the ceiling substrate 202c of the package substrate 202 and the base substrate 202a are described separately.
It is not necessary to divide the manufacturing process as described above. Actually, a similar manufacturing process is used and can be performed by the same process.

【００７５】上記製造プロセスで、容易に抵コストで、
上下両面に外部接続端子が形成された半導体素子の実装
体が実現できる。In the above manufacturing process, the cost can be easily reduced.
A semiconductor element mounted body having external connection terminals formed on both upper and lower surfaces can be realized.

【００７６】なお、以上説明した実装体２００は、それ
自体で実装信頼性を維持しているので、この実装体２０
０を積層する場合も特別な配慮は必要ない。また、半導
体素子２０１の厚みも近年、薄板化できる技術が進歩し
てきているが、この実装体２００では、半導体素子２０
１の厚みにあわせて、実装体２００の厚みも薄くするこ
とができ、半導体素子２０１の高密度実装に対して大き
な効果がある。Since the mounting body 200 described above maintains the mounting reliability by itself, this mounting body 20
No special consideration is required when laminating 0s. In recent years, the technology for reducing the thickness of the semiconductor element 201 has been advanced.
1, the thickness of the mounting body 200 can be reduced, which has a great effect on high-density mounting of the semiconductor element 201.

【００７７】[0077]

【発明の効果】以上説明したように、本発明の実装体に
よると、実装体の両面全面に外部接続端子が形成されて
いるために、多数の外部接続端子を有する電子部品（半
導体素子等）を実装したとしても、その実装体を複数積
層実装させることが可能となり、実装面積の低減を実現
することができた。また、実装体の製造プロセスも特別
なプロセスを必要とせず、パッケージ基板製造プロセス
中に、半導体素子等の電子部品を実装するだけの簡便な
ものであり、量産性、コスト面で有利であり、安価な実
装体を提供することができた。As described above, according to the mounting body of the present invention, since the external connection terminals are formed on both surfaces of the mounting body, an electronic component (such as a semiconductor element) having a large number of external connection terminals is provided. However, even if is mounted, it is possible to stack and mount a plurality of the mounting bodies, and it is possible to reduce the mounting area. In addition, the manufacturing process of the mounting body does not require a special process, and is simple in that electronic components such as semiconductor elements are simply mounted during the package substrate manufacturing process, which is advantageous in mass productivity and cost. An inexpensive mounting body could be provided.

【図面の簡単な説明】[Brief description of the drawings]

【図１】 本発明一実施の形態の実装体の断面図であ
る。FIG. 1 is a sectional view of a package according to an embodiment of the present invention.

【図２】 本発明の変形例の断面図である。FIG. 2 is a sectional view of a modification of the present invention.

【図３】 本発明のさらに他の変形例の断面図である。FIG. 3 is a sectional view of still another modification of the present invention.

【図４】 本発明のさらに他の変形例の断面図である。FIG. 4 is a cross-sectional view of still another modified example of the present invention.

【図５】 マザー基板上に本発明の実装体を積層実装し
た時の断面図である。FIG. 5 is a cross-sectional view when the mounting body of the present invention is stacked and mounted on a mother board.

【図６】 マザー基板上に本発明の実装体を積層実装し
た時の他の例の断面図である。FIG. 6 is a cross-sectional view of another example when the mounting body of the present invention is stacked and mounted on a mother board.

【図７】 本発明の実施の形態における実装体の製造
方法の第１番目の工程をそれぞれ示す断面図である。FIG. 7 is a cross-sectional view showing a first step of the method of manufacturing the package according to the embodiment of the present invention;

【図８】 本発明の実施の形態における実装体の製造方
法の第２番目の工程をそれぞれ示す断面図である。FIG. 8 is a cross-sectional view showing a second step of the method of manufacturing the mounted body according to the embodiment of the present invention.

【図９】 本発明の実施の形態における実装体の製造方
法の第３番目の工程をそれぞれ示す断面図である。FIG. 9 is a cross-sectional view showing a third step of the method for manufacturing the package according to the embodiment of the present invention;

【図１０】 本発明の実施の形態における実装体の製造
方法の第４番目の工程をそれぞれ示す断面図である。FIG. 10 is a cross-sectional view showing a fourth step in the method for manufacturing the package in the embodiment of the present invention.

【図１１】 本発明の実施の形態における実装体の製造
方法の第５番目の工程をそれぞれ示す断面図である。FIG. 11 is a cross-sectional view showing a fifth step in the method for manufacturing the package according to the embodiment of the present invention;

【図１２】 従来の実装体の断面図である。FIG. 12 is a cross-sectional view of a conventional mounting body.

【図１３】 従来のもう一つの実装体の断面図である。FIG. 13 is a sectional view of another conventional mounting body.

【符号の説明】[Explanation of symbols]

２００ 実装体 ２０１ 半導体素
子 ２０２ パッケージ基板 ２０２ａ 基部基板 ２０２ｂ 側壁基板 ２０２ｃ 天井基板 ２０３ 第１の外部接続端子 ２０４ 内部接続
端子 ２０５ 第１のＩＶＨ構造 ２０６ 収納凹部 ２０７ 第２のＩＶＨ構造 ２０８ 封止樹脂 ２０９ 第３のＩＶＨ構造 ２１０ 第２の外
部接続端子 ２１１ 配線 ２１２ 絶縁性基
材 ２１３ インナービア Ａ〜Ｉ 第１〜第
９の導通路 ５０１ マザー基板Reference Signs List 200 mounted body 201 semiconductor element 202 package substrate 202a base substrate 202b side wall substrate 202c ceiling substrate 203 first external connection terminal 204 internal connection terminal 205 first IVH structure 206 receiving recess 207 second IVH structure 208 sealing resin 209 No. 3 IVH structure 210 Second external connection terminal 211 Wiring 212 Insulating base material 213 Inner vias A to I First to ninth conduction paths 501 Mother board

フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 25/11 Ｈ０１Ｌ 25/14 Ｚ 25/18 Ｈ０５Ｋ 3/46 (72)発明者 中村 禎志 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 須川 俊夫 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 Ｆターム(参考） 5E336 AA04 AA08 BB03 BB12 BB15 BC26 BC34 CC34 CC55 CC58 EE01 GG14 GG30 5E346 AA43 BB16 CC04 CC09 CC32 DD12 DD22 DD32 EE09 FF18 FF45 GG15 HH31 Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat II (Reference) H01L 25/11 H01L 25/14 Z 25/18 H05K 3/46 (72) Inventor Satoshi Nakamura 1006 Kadoma, Kazuma, Kadoma, Osaka Address: Matsushita Electric Industrial Co., Ltd. CC04 CC09 CC32 DD12 DD22 DD32 EE09 FF18 FF45 GG15 HH31

Claims (14)

【特許請求の範囲】[Claims] 【請求項１】 内部に電子部品が実装配置され、かつそ
の両面が閉塞された収納筺体と、 前記収納筺体の両面それぞれに複数設けられ、かつ、少
なくともその一部が前記電子部品に電気的に接続された
外部接続端子と、 を有することを特徴とする電子部品の実装体。An electronic component is mounted and arranged inside the housing, and both sides of the housing are closed. A plurality of housings are provided on both sides of the housing, and at least a part of the housing is electrically connected to the electronic component. An electronic component package comprising: an external connection terminal connected to the electronic component. 【請求項２】 請求項１記載の電子部品の実装体であっ
て、 前記外部接続端子は、前記収納筺体両面の全面にわたっ
て設けられていることを特徴とする電子部品の実装体。2. The electronic component package according to claim 1, wherein the external connection terminals are provided over the entire surface of both sides of the housing. 【請求項３】 請求項１記載の電子部品の実装体であっ
て、 当該実装体を二次実装する際において二次実装対象部材
側に位置する実装体の面に設けられた前記外部接続端子
は、前記収納筺体を挟んで前記電子部品に対向しない当
該面の領域に配置されていることを特徴とする電子部品
の実装体。3. The electronic component mounted body according to claim 1, wherein the external connection terminal is provided on a surface of the mounted body located on the side of the secondary mounting target member when the mounted body is secondarily mounted. Is mounted on a region of the surface not facing the electronic component with the storage housing interposed therebetween. 【請求項４】 請求項１ないし３のいずれか記載の電子
部品の実装体であって、 前記収納筺体両面にある外部接続端子の一部は、両面に
あるものどうし互いに前記電子部品を介することなく直
接接続されていることを特徴とする電子部品の実装体。4. The electronic component package according to claim 1, wherein a part of the external connection terminals on both sides of the housing is interposed between the electronic connection parts on both sides. Electronic component mounting body, characterized in that it is directly connected without any additional components. 【請求項５】 請求項１ないし４のいずれか記載の電子
部品の実装体であって、 前記収納筺体両面にある外部接続端子の一部は、両面に
あるものどうし互いに前記電子部品を介して直列接続さ
れていることを特徴とする電子部品の実装体。5. The electronic component package according to claim 1, wherein a part of external connection terminals on both sides of the housing is mutually connected to each other via the electronic component. An electronic component mounted body that is connected in series. 【請求項６】 請求項１ないし５のいずれか記載の電子
部品の実装体であって、 前記収納筺体両面にある外部接続端子の一部は、前記電
子部品に対して並列接続されていることを特徴とする電
子部品の実装体。6. The electronic component package according to claim 1, wherein a part of external connection terminals on both sides of the housing is connected in parallel to the electronic component. An electronic component mounted body characterized in that: 【請求項７】 請求項１ないし６のいずれか記載の電子
部品の実装体であって、 前記収納筺体は、多層基板から構成されていることを特
徴とする電子部品の実装体。7. The electronic component package according to claim 1, wherein the housing is formed of a multilayer board. 【請求項８】 請求項７記載の電子部品の実装体であっ
て、 前記収納筺体は、全層ＩＶＨ構造を有する樹脂多層基板
から構成されていることを特徴とする電子部品の実装
体。8. The electronic component mounted body according to claim 7, wherein the housing is formed of a resin multilayer substrate having an all-layer IVH structure. 【請求項９】 請求項７記載の電子部品の実装体であっ
て、 前記収納筺体は、当該実装体を二次実装する際において
二次実装対象部材側に位置する実装体の面側に位置する
部分が、可撓性を有するフィルム基板から構成されてい
ることを特徴とする電子部品の実装体。9. The electronic component package according to claim 7, wherein the housing is located on a surface side of the package located on the side of the secondary mounting target member when the package is secondary mounted. Wherein the portion to be formed is formed of a flexible film substrate. 【請求項１０】 請求項１ないし９のいずれか記載の電
子部品の実装体であって、 前記電子部品と前記筺体との間に隙間を形成することを
特徴とする電子部品の実装体。10. The electronic component package according to claim 1, wherein a gap is formed between the electronic component and the housing. 【請求項１１】 請求項１０記載の電子部品の実装体で
あって、 当該実装体を二次実装する際において二次実装対象部材
側に位置する実装体の面と前記電子部品との間に、前記
隙間を設けることを特徴とする電子部品の実装体。11. The electronic component mounted body according to claim 10, wherein, when the mounted body is secondarily mounted, a space between the surface of the mounted body located on the side of the secondary mounting target member and the electronic component. And a mounting body for an electronic component, wherein the gap is provided. 【請求項１２】 請求項１ないし１１のいずれか記載の
電子部品の実装体であって、 前記電子部品は半導体素子であることを特徴とする電子
部品の実装体。12. The electronic component package according to claim 1, wherein the electronic component is a semiconductor device. 12. The electronic component package according to claim 1, wherein the electronic component is a semiconductor element. 【請求項１３】 請求項１ないし１２のいずれかに記載
の実装体どうしを、これら実装体の両面のうちの一方を
互いに向かい合わせて積層配置し、両実装体の外部接続
端子を電気的に接続することを特徴とする実装体の二次
実装構造。13. The mounting bodies according to claim 1, wherein one of both surfaces of the mounting bodies is stacked and arranged, and external connection terminals of both mounting bodies are electrically connected. A secondary mounting structure of the mounting body, characterized by being connected. 【請求項１４】 ＩＶＨ構造を有する多層基板からなり
その裏面には第１の外部接続端子を有する基部基板の上
面に電子部品を実装し、前記第１の外部接続端子の少な
くとも一部と前記電子部品とを、前記ＩＶＨ構造を介し
て電気的に接続する工程と、 ＩＶＨ構造を有する多層基板からなる側壁基板を、前記
電子部品の周囲を囲んで前記基部基板上に積層一体化す
るとともに、ＩＶＨ構造を有しかつその上面には第2の
外部接続端子を有する天井基板を、前記電子部品を覆っ
て前記側壁基板上に積層一体化し、前記第2の外部接続
端子を、前記電子部品および前記第１の外部接続端子そ
れぞれの必要箇所に、各基板内のＩＶＨ構造を介して電
気的に接続する工程と、 を含むことを特徴とする電子部品の実装体の製造方法。14. An electronic component is mounted on an upper surface of a base substrate having a multi-layer substrate having an IVH structure and having a first external connection terminal on a back surface thereof, wherein at least a part of the first external connection terminal and the electronic component are mounted. Electrically connecting components to each other via the IVH structure; and laminating and integrating a side wall substrate composed of a multilayer substrate having the IVH structure on the base substrate around the electronic component. A ceiling substrate having a structure and having a second external connection terminal on its upper surface is laminated and integrated on the side wall substrate so as to cover the electronic component, and the second external connection terminal is provided with the electronic component and the electronic component. Electrically connecting the first external connection terminal to a required portion of the first external connection terminal via an IVH structure in each substrate.
JP2000036393A 2000-02-15 2000-02-15 Mounting member of electronic component, method of manufacturing mounting member of electronic component, and secondary mounting structure of mounting member Pending JP2001230515A (en)

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