JP2001229687A - Voltage regulator circuit and semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a voltage regulator circuit which can generate voltage clamped accurately at a required level and can prevent DC current consumption, and to provide a semiconductor memory using it for a word line voltage generating circuit. SOLUTION: A voltage regulator circuit is constituted of regulators of two stages being connected in series for adjusting high voltage and generating regulated output voltage. The regulator of the preceding stage adjusts the high voltage to a sufficiently constant voltage, the regulator of the post stage is provided with a depletion type transistor, and adjusts the high voltage to a voltage of a required level by utilizing the voltage adjusted by the regulator of the preceding stage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage regulator circuit, and more particularly to a semiconductor memory device using the circuit in a word line voltage generation circuit, and more particularly to a nonvolatile memory device which can be electrically erased and programmed. It is.

[0002]

2. Description of the Related Art As is well known, a flash memory device as a non-volatile memory device includes an array of memory cells, each of which is called a floating gate and a gate electrode located on a channel region. With
It is composed of MOS transistors. The floating gate electrode has a high DC impedance with respect to a circuit to which all other electrodes of the same cell and the memory cell are connected.
e). On this, the memory cell includes a second electrode called a control gate electrode, the second electrode being activated by a specific control voltage. The other electrodes of the memory cell transistor are known as source, drain and bulk terminals.

[0003] By applying a specific voltage value to the cell terminal, the amount of charge existing on the floating gate is reduced by the Fowler-Nordheid.
m's Tunneling or Channel Hot Electron Injection
It changes by such a phenomenon. As a result, the memory cell transistor has two logic states, a first logic state (referred to as an "off state") with a "high" threshold voltage (threshold voltage of 6-7V) and a "low" threshold. It has any one of a second logic state (called “ON state”) of a voltage (threshold voltage of 1 V to 3 V).

[0004] Because the floating gate has a high impedance to the other terminals of the memory cell, the stored charge remains in the floating gate even when the power is turned off. Therefore, the memory cell has characteristics of a nonvolatile memory.

Whether a memory cell has one of an off state and an on state is determined by a read operation. The read operation of each cell is performed by applying a specific voltage (for example, 4.5 V) to the control gate, a voltage of an appropriate level (for example, 1 V) to the drain connected to the bit line, and a ground voltage to the source. if,
When the memory cell is off, no current flows from the drain to the source. This increases the voltage on the bit line, so that the memory cell is turned off by a sense amplifier (not shown) as is well known to those skilled in the art. If the memory cell is on, a current flows from the drain to the source. This reduces the voltage on the bit line, so that the memory cells are turned on by the sense amplifier.

FIG. 1 is a configuration diagram showing a schematic configuration of a NOR flash memory device having a general voltage regulator. The memory device of FIG.
WWLi) and an array 10 of memory cells arranged in a matrix of columns (bit lines BL0〜BLj). The voltage VPPi supplied from the word line voltage generation circuit 30 is supplied to the word line WLi through the decoder 20 as a word line voltage (or read voltage). The word line voltage generation circuit 30 includes a high voltage generator 32 (for example, a boost circuit as is well known to those skilled in the art) that generates a high voltage VPP higher than the power supply voltage in response to a boost enable signal EN as a control signal. The voltage regulator 34 adjusts VPP to a required level of voltage VPi.
The high voltage VPP is maintained at the power supply voltage when the boost enable signal EN is in an inactive state. FIG. 2 is a circuit diagram showing the voltage regulator 34 of FIG.

As shown in FIG. 2, a general voltage regulator 34 includes a comparator COMP, a PMOS transistor MP1 used as a driver, and resistors R1 and R2 used as dividers. It is connected to. Comparator COMP is the divider output voltage
It is determined whether Vdiv is lower than the reference voltage Vref, and the PMOS transistor MP1 operates according to the determination result of the comparator COMP. For example, the voltage VPPi adjusted by the voltage regulator 34 is lower than a required level (Vref> Vdiv).
And PM so that the voltage VPPi is higher than the required level.
Current is supplied through the OS transistor MP1. On the other hand, the voltage VPPi is higher than the required level (Vref
<Vdiv), the current supply by the PMOS transistor MP1 is cut off such that the voltage VPPi becomes lower than the required level.

[0008]

As described above, the output voltage VPP of the high voltage generator 32 is maintained at the power supply voltage Vcc when the boost enable signal EN is in an inactive state.
On the other hand, when the boost enable signal EN is in an activated state (t1, see FIG. 3), the high voltage generator 32 operates in a short time (for example, nanoseconds) to quickly raise the high voltage VPP from the power supply voltage Vcc. Generate. Such a high voltage VPP generated by the level of the voltage VPPi required through voltage regulator 34, i.e., it is adjusted to the word line voltage V _WL. However, as shown in FIG. 2, a general voltage regulator 34 having a feedback scheme has the following problems.

Since the voltage VPPi adjusted by the voltage regulator 34 is always sensed, a DC current path is created between the high voltage VPP and the ground voltage, and the DC current is consumed.
Generally, the DC current generated between the high voltage VPP and the ground voltage can be reduced by designing the resistors R1 and R2 constituting the divider to have a large value. But,
By setting the resistance to a large value, the response speed of the voltage regulator 34 decreases. The main cause of the decrease in response speed is RC delay due to the capacitance component of the PMOS transistor having a large operation capability and the resistance component of the divider. As a result, as shown in FIG. 3, the voltage VPPi adjusted by the voltage regulator 34 is not accurately clamped at the required level. That is, as shown in FIG. 3, the voltage VPPi overshoots to a required level or more between times t2 and t3 (the voltage level overshoot is
Is determined by the RC delay time), overshoot voltage VPPi is applied to the word line WL through the decoder as a word line voltage V _WL. As a result, the word line voltage V _WL becomes higher than the required level,
Reading failure (especially, reading failure for the memory cell in the off state) occurs. This is because the word line voltage _VWL exists in the off-state threshold voltage distribution, or the sensing margin for the off-state memory cell is reduced. Therefore, it is desirable to accurately clamp the voltage VPPi at a required level without overshoot (the portion indicated by the dotted line A in FIG. 3).

[0010] The present invention has been made in view of the above points,
It is an object of the present invention to provide a voltage regulator circuit capable of generating a voltage that is accurately clamped at a required level and preventing DC current consumption.

Still another object of the present invention is to provide a semiconductor memory device using the above-mentioned voltage regulator circuit in a word line voltage generation circuit.

[0012]

According to a feature of the present invention,
Non-volatile semiconductor memory devices, particularly flash memory devices, include a circuit for generating a word line voltage higher than a power supply voltage. The word line voltage generation circuit includes a voltage regulator circuit coupled to a high voltage generator for generating a high voltage higher than a power supply voltage and having an output terminal for outputting a regulated output voltage. The voltage regulator circuit adjusts the high voltage and outputs a constant voltage lower than the adjusted output voltage, and the second regulator adjusts the high voltage according to the constant voltage and outputs the adjusted output voltage. Consists of a regulator. The second regulator is a depletion type having a drain connected to a high voltage, a source connected to an output terminal, and a gate connected to receive a constant voltage.
It is composed of NMOS transistors.

[0013]

Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

According to the semiconductor memory device of the present invention, there is provided a voltage regulator circuit used in a word line voltage generation circuit. The voltage regulator circuit is composed of a series-connected two-stage regulator that regulates a high voltage to generate a regulated output voltage. The previous regulator regulates the high voltage to a sufficiently constant voltage, which is lower than the required level of the regulated output voltage.
The subsequent-stage regulator adjusts the high voltage to a required level of voltage by using the voltage adjusted by the preceding-stage regulator. Further, the latter-stage regulator is constituted by a depletion-type transistor having a negative threshold voltage. According to such a structure, the output voltage of the voltage regulator circuit of the present invention can be adjusted to the absolute value of the threshold voltage of the depletion-type transistor and the voltage value adjusted by the regulator in the preceding stage without overshoot to a required level or more. Is clamped exactly at the voltage level plus

FIG. 4 is a configuration diagram showing a schematic configuration of a flash memory device as a nonvolatile memory device provided with the voltage regulator circuit of the present invention. The memory device of FIG. 4 has rows (word lines WL0-WLi) and columns (bit lines BL).
0 to BLj), including an array 100 of memory cells arranged in a matrix. The voltage VPPi supplied from the word line voltage generation circuit 130 is supplied to the word line WLi through the decoder 120 as a word line voltage (or read voltage).
Supplied to The word line voltage generation circuit 130 includes a high voltage generator 132 (for example, a boost circuit) for generating a high voltage VPP higher than the power supply voltage in response to the boost enable signal EN, and a voltage VPPI of a level required for the high voltage VPP.
And a voltage regulator circuit 134 for adjusting the voltage.
The high voltage VPP is maintained at the power supply voltage when the boost enable signal EN is in an inactive state.

The voltage regulator circuit 134 has a two-stage regulator structure connected in series. That is, the voltage regulator circuit 134 of the present invention includes the first regulator 136 and the second regulator 138 connected in series.
The first regulator 136 regulates the output voltage VPP of the high voltage generator 132 to a constant voltage V1 lower than the required level of the word line voltage _VWL , and the second regulator 138 utilizes the constant voltage V1 to regulate the high voltage VPP. Adjust to the required level of voltage VPPi. Voltage regulator circuit 13 of FIG.
Four embodiments are shown in FIG.

Referring to FIG. 5, a voltage regulator circuit 134 includes a depletion type NM constituting a first regulator 136.
OS transistor DMN1, load L1 and NMOS transistor
MN1 and a depletion type NMOS constituting the second regulator 138
And a transistor DMN2. The depletion type NMOS transistor DMN1 having a gate connected to the reference voltage Vref has a drain (or a first current electrode) connected to the output voltage of the high voltage generator 132, that is, the high voltage VPP. Depletion type
The source (referred to as a second current electrode) of the NMOS transistor DMN1 is grounded through the load L1 and the NMOS transistor MN1. The gate electrode (or control gate electrode) of the depletion type NMOS transistor DMN2 is connected to the source of the depletion type NMOS transistor DMN1 (or one terminal of the load L1 located on the opposite side of the ground voltage). The drain of the depletion type NMOS transistor DMN2 is connected to the high voltage VPP, and the source of the depletion type NMOS transistor DMN2 is the voltage VPP.
It is connected to the output terminal 139 of PPi. The NMOS transistor MN1 of the first regulator 136 is turned on / off according to the boost enable signal EN. That is, the NMOS transistor MN1 is turned on when the high voltage generator 132 operates, and turned off when the high voltage generator 132 does not operate. Therefore, when the high voltage generator 132 does not operate, the DC current path between the high voltage VPP and the ground voltage is cut off by the NMOS transistor MN1.

As shown in FIG. 5, the load L1 of the first regulator 136 may include a plurality of NMOS transistors connected in series between the transistors DMN1 and MN1. However, it goes without saying that the load L1 can be configured using another integrated circuit element that operates as a resistor.

As is well known to those skilled in the art, each of the depletion type NMOS transistors DMN1 and DMN2 has a negative threshold voltage −V
thd (−Vthd indicates a threshold voltage of a depletion type NMOS transistor), and the drain-source voltage Vds is Vg − (− Vt
hd), or when it is larger than this (Vds ≧ Vg − (− Vthd)), it operates in the saturation region. That is, the depletion type NMOS transistors DMN1 and DMN2 are shut off under such a condition (Vds ≧ Vg − (− Vthd)). According to such transistor characteristics, the voltage VPPi adjusted by the voltage regulator circuit 134 is V1-(-Vt
hd2) (-Vthd2 indicates the threshold voltage of the depletion type NMOS transistor DMN2 forming the second regulator 138)
The operation in this regard is described in detail below with reference to FIG.

As shown in FIG. 6, the high voltage generator 13
2 does not operate (when the boost enable signal EN is maintained at a logic low level in an inactive state),
During the interval t0 to t1, the output voltage VPP of the high voltage generator 132
Are maintained at the power supply voltage Vcc. Boost enable signal E
At time t1, when N goes to an active logic high level, the output voltage VPP of the high voltage generator 132 gradually and quickly rises from the power supply voltage Vcc within a short time (eg, within nanoseconds). Then, as the high voltage VPP increases, the gate voltage of the depletion type NMOS transistor DMN2 (or the source voltage of the transistor DMN1) also increases.

Thereafter, the drain-source voltage Vds of the depletion type NMOS transistor DMN1 is Vref-(-Vthd1) (-Vthd1 indicates the threshold voltage of the depletion type NMOS transistor DMN1).
, The depletion type NMOS transistor DMN1 is shut off. Therefore, depletion type NMOS transistor DMN
2, the gate voltage V1 becomes Vref + Vthd1. That is, depletion type N
The MOS transistor DMN1 adjusts (or clamps) the high voltage VPP to Vref + Vthd1. Here, the voltage Vref + Vthd1
Is higher than the power supply voltage Vcc and lower than the required level of the word line voltage _VWL .

The load L1 of the first regulator 136 and
The NMOS transistor MN1 is a depletion type NMOS transistor DMN
It is used to prevent one source from floating. If load L1 and NMOS transistor MN
If 1 is not provided, the gate voltage of the depletion type NMOS transistor DMN2 is boosted when the source voltage of the depletion type NMOS transistor DMN1 becomes Vref + Vthd1 (or when the depletion type NMOS transistor DMN1 is shut off). This causes voltage VPPi to be set higher than required.

Next, the output voltage of the high voltage generator 132
T2 when VPP reaches the word line voltage V _WL of the required level, the depletion-type NMOS transistor DMN2 is shut off, as a result, the voltage VPPi is accurately clamped at the required level of the word line voltage V _WL . This will be described in more detail below. When the high voltage VPP becomes higher than the voltage V1, the depletion type NMOS transistor DMN2
Is also high. At this time, the depletion type NMOS transistor DMN1 is shut off, and the source voltage V1 of the depletion type NMOS transistor DMN1 is fixed at Vref + Vthd1. Thereafter, when the drain-source voltage Vds of the depletion-type NMOS transistor DMN2 reaches V1-(-Vthd2) (-Vthd2 indicates the threshold voltage of the depletion-type NMOS transistor DMN2), at t2, the depletion-type NMOS transistor DMN2 shuts down. Turned off. Therefore, the voltage VPPi adjusted by the voltage regulator circuit 134 is equal to the depletion type NMOS transistor DM
It is adjusted (clamped) to the voltage Vref + Vthd2 by N2. The voltage VPPi is equal to the reference voltage Vref and the threshold voltage −
It is well known to those skilled in the art that it can be changed by adjusting Vthd1 and -Vthd2.

As described above, according to the voltage regulator circuit 134 of the present invention including the two-stage regulator,
When VPP reaches the word line voltage V _WL of the required level, the depletion-type NMOS transistor DMN2 the second regulator 138 is shut off. Accordingly, the voltage VPPi adjusted by the voltage regulator circuit 134 is
It is clamped accurately without overshoot above the level required at time t2. Therefore, problems caused by overshoot of the voltage VPPi (reduction in sensing margin and read failure due to an increase in word line voltage) can be prevented.
Further, according to the voltage regulator circuit 134 of the present invention, the DC current path between the high voltage VPP and the ground voltage generated in the voltage regulator circuit shown in FIG.
Current consumption can be prevented.

Another embodiment of the first regulator 136 shown in FIG. 4 is shown in FIGS. 7A and 7B. Referring to FIG. 7A, the first regulator 136
A first PMOS transistor MP2 having a first current electrode connected to the high voltage VPP, a commonly connected second current electrode and a control electrode, a first current electrode connected to the high voltage VPP, and the first PMOS transistor MP2; A second PMOS transistor MP3 having a control electrode connected to the control electrode of the transistor MP2 and a second current electrode;
A first current electrode connected to a second current electrode of the first NMOS transistor
A second NMOS transistor MN2 having a second current electrode grounded through a transistor MN3 and a control electrode connected to receive a reference voltage Vref;
One end is connected to a second current electrode of the transistor MP3,
And a resistor R3 having the other end connected to the ground voltage through the first NMOS transistor MN3. The first NMOS transistor MN3 controls a control signal (boost enable signal E).
N) and a sufficiently constant voltage V1 is output from the second current electrode of the second PMOS transistor MP3.

When the boost enable signal EN is at a logic high level, the first regulator 136 clamps the high voltage VPP to the voltage V1. The voltage V1 is higher than the power supply voltage Vcc and lower than the required level of the word line voltage _VWL . As in FIG. 5, the second regulator 138 is a depletion type.
Since the NMOS transistor DMN2 is used, the voltage VPPi is accurately clamped to the voltage V1 + Vthd2 without overshoot. The operation related to this is the same as that in FIG.

The first regulator 136 of FIG. 7B includes a first current electrode in which the resistor R3 of FIG. 7A is commonly connected to a diode-connected NMOS transistor MN4, that is, a second current electrode of a second PMOS transistor MP3. A control electrode;
Except that the third NMOS transistor MN4 having the second current electrode grounded through the first NMOS transistor MN3 is replaced with the third NMOS transistor MN4, the description is omitted because it is the same as FIG.

Although the structure and operation of the circuit according to the present invention have been described with reference to the drawings and the drawings, these are only examples.
Various changes and modifications may be made to the present invention without departing from the technical spirit and scope of the present invention.

[0029]

As described above, according to the present invention, when the output voltage of the high voltage generator reaches the required level of the word line voltage, the depletion type NMOS transistor of the second regulator is shut off. . Accordingly, the voltage VPPi adjusted by the voltage regulator circuit is accurately clamped at the required level without overshoot. Therefore, not only the voltage VPPi, that is, a problem due to the overshoot of the word line voltage (reduction of the sensing margin and read failure due to the rise of the word line voltage) can be prevented, but also the output voltage of the high voltage generator and the ground voltage can be prevented. The DC current path can be cut off, and DC current consumption can be prevented.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating a schematic configuration of a flash memory device including a general voltage regulator.

FIG. 2 is a circuit diagram showing the voltage regulator shown in FIG.

FIG. 3 is a characteristic diagram showing a change in output voltage of the voltage regulator of FIG. 2;

FIG. 4 is a configuration diagram showing a flash memory device including the voltage regulator circuit of the present invention.

FIG. 5 is a circuit diagram showing an embodiment of the voltage regulator circuit shown in FIG.

FIG. 6 is a characteristic diagram showing a change in output voltage of the voltage regulator circuit of FIG. 5;

FIG. 7 is a circuit diagram showing another embodiment of the voltage regulator circuit shown in FIG. 4;

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 memory cell array 120 row decoder 130 word line voltage generating circuit 132 high voltage generator 134 voltage regulator circuit 136 first regulator 138 second regulator DMN1, DMN2 depletion type NMOS transistor L1 load MN1-MN4 NMOS transistor MP2, MP3 PMOS transistor R3 resistor

Claims (10)

[Claims] 1. A voltage regulator circuit coupled to a high voltage generator for generating a high voltage VPP and having an output terminal for outputting a regulated output voltage VPPi, wherein the voltage regulator circuit receives the high voltage VPP and has a sufficiently constant voltage. V1 includes first means for generating V1, and second means having a driver connected between the high voltage VPP and the output terminal, wherein the second means clamps the high voltage VPP, and A regulated output voltage VPPi, and the adjusted output voltage VPPi is a voltage V1 + Vth obtained by adding the sufficiently constant voltage V1 and a threshold voltage Vth of the driver. 2. The driver includes a first depletion-type MOS transistor, wherein the transistor has a first current electrode connected to the high voltage VPP, a second current electrode connected to the output terminal, and the sufficiently constant MOS transistor. A control electrode coupled to receive the voltage V1, wherein the first depletion-type MOS transistor is adapted to output the regulated output voltage VPPi to the voltage V1 + Vt
The voltage regulator circuit according to claim 1, wherein the voltage regulator circuit is shut off when the voltage reaches h. 3. The first means includes a first current electrode connected to receive the high voltage VPP, a second current electrode connected to a control electrode of the first depletion type MOS transistor, and a reference voltage Vref. A second depletion-type MOS transistor having a control electrode coupled to receive the second depletion-type MOS transistor; and a switch coupled between the second depletion-type MOS transistor and a ground voltage and switched according to a control signal. The voltage regulator circuit according to claim 2. 4. The voltage regulator circuit according to claim 3, wherein said first means additionally includes a load connected between said second depletion type MOS transistor and a switch. 5. The first means includes: a first PMOS transistor having a first current electrode connected to the high voltage VPP, a commonly connected second current electrode and a control electrode; and a first PMOS transistor connected to the high voltage VPP. A first current electrode,
A second PMOS transistor having a control electrode and a second current electrode connected to a control electrode of the first PMOS transistor; a first current electrode connected to a second current electrode of the first PMOS transistor; and a ground through a first NMOS transistor. A second NMOS transistor having a second current electrode and a control electrode connected to receive the reference voltage Vref; a first current electrode and a control electrode commonly connected to a second current electrode of the second PMOS transistor; A third with a second current electrode grounded through one NMOS transistor
An NMOS transistor, wherein the first NMOS transistor is switched in accordance with a control signal, and wherein said first constant voltage
2. The voltage regulator circuit according to claim 1, wherein 1 is output from a second current electrode of the second PMOS transistor. 6. The first means includes a first PMOS transistor having a first current electrode connected to the high voltage VPP, a second current electrode connected to the high voltage VPP, and a control electrode.
A second PMOS transistor having a first current electrode connected to VPP, a control electrode connected to the control electrode of the first PMOS transistor, and a second current electrode; and a second current electrode connected to a second current electrode of the first PMOS transistor. 1 current electrode, 1st
A second NMOS transistor having a second current electrode grounded through an NMOS transistor and a control electrode connected to receive a reference voltage Vref; one end connected to a second current electrode of the second PMOS transistor;
A resistor connected at the other end to a ground voltage through a transistor, the first NMOS transistor is switched according to a control signal, and the sufficiently constant voltage V1 is applied to the second
The voltage regulator circuit according to claim 1, wherein the voltage is output from a second current electrode of a PMOS transistor. 7. An array of memory cells arranged in a matrix of rows and columns, a row decoder for selecting one of the rows, and a word line for generating a word line voltage supplied to the selected row. A voltage generating circuit, wherein the word line voltage generating circuit receives the high voltage from a high voltage generator that generates a high voltage and generates a constant voltage lower than the word line voltage, and the word line voltage generating circuit includes: A semiconductor memory device comprising a depletion type MOS transistor which clamps a high voltage and outputs the word line voltage. 8. When the high voltage reaches a voltage value obtained by adding a threshold voltage of the depletion type MOS transistor and the constant voltage, the depletion type MOS transistor is shut off, and as a result, the word line is turned off. The semiconductor memory device according to claim 7, wherein the high voltage is clamped so that a voltage has a voltage value obtained by adding the threshold voltage and the constant voltage. 9. A voltage regulator circuit coupled to a high voltage generator for generating a high voltage higher than a power supply voltage and having an output terminal for outputting a regulated output voltage, the voltage regulator circuit comprising: A first regulator that outputs a constant voltage lower than the adjusted output voltage; and a second regulator that adjusts the high voltage according to the constant voltage and outputs the adjusted output voltage. Voltage regulator circuit. 10. The second regulator includes a depletion type NMOS transistor, the depletion type NMOS transistor being connected to the drain connected to the high voltage, the source connected to the output terminal, and receiving the constant voltage. The voltage regulator circuit according to claim 9, further comprising a gate.