JP2001229143A - Multiprocessor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the wait time which a processor needs to access a common memory as to a multiprocessor system having processors and the common memory. SOLUTION: Serial-parallel conversion parts 5-1 to 5-3 are connected to respective processors 1-1 to 1-3; and a serial-parallel conversion part 7 of a memory control part 3 connected to the common memory 2 and the serial- parallel conversion parts 5-1 to 5-3 are connected by buses 4-1 to 4-3 which transfer serial data; and a data buffer selector 6 is connected between the common memory 2 and serial-parallel conversion part 7 and a priority decision circuit 8 is provided which performs priority control between data buffers of the data buffer selector 6 which correspond to the processors and the common memory 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control system in which a plurality of processors and a shared memory are connected via a bus corresponding to a processor for performing serial data transfer, and a shared memory is accessed by a memory control unit. And a multiprocessor system for performing the following.

[0002]

2. Description of the Related Art In a system having a large amount of processing, a multiprocessor system having a plurality of processors to perform a function distribution process and a load distribution process is employed. This multiprocessor system is known as a system in which an individual memory is provided for a processor, a system in which a shared memory is commonly accessed by processors, or a system in which both an individual memory and a shared memory are provided. I have.

In general, a common memory and a plurality of processors are connected by a common bus for performing parallel data transfer. The common bus includes the number of processing bits of the processor, the number of address bits, and various control signals. It is composed of signal lines corresponding to the numbers. The number of bits of data transferred between processors and between the processor and the shared memory is known to be, for example, about 8 to 128 bits. Therefore, in the case of a common bus for transferring 128 bits of data in parallel, Further, the number of transfer bits including control signals, address bits, and the like increases, and the number of signal lines corresponding to the number of transfer bits is required. Therefore, since a bus is also connected between the boards on which the processors are mounted, a space for a common bus for connecting the boards is large, and a configuration in which the boards are connected via a connector is generally used. Therefore, it is difficult to secure a space for mounting on the substrate.

Therefore, a configuration is known in which data is serially transferred in order to reduce the bus width and facilitate connection between boards. FIG. 25 shows a conventional multiprocessor system for performing such serial transfer.
101-3 are processors (CPU1 to CPU3), 10
2 is a shared memory, 103 is a memory control unit, 104 is a common bus composed of signal lines for transmission data SD, reception data RD, and a clock signal CLK, 105-1 to 105
-3, 107 are serial / parallel conversion units (P / S / S / P), 10
Reference numerals 6-1 to 106 denote signal lines for the request signal REQ and the response signal ACK, and reference numeral 108 denotes a bus priority determination circuit.

For example, processors 101-1 to 101-
Reference numeral 3 denotes a serial / parallel conversion unit 105-1 to 105- having a total of 35 bits of 32-bit parallel data (write data, read data or memory address), a read / write command to the shared memory 102, and a clock signal. 3
And processors 101-1 to 101-
Three signal lines for transferring the transmission data SD, the reception data RD, and the clock signal CLK between the serial-to-parallel conversion units 105-1 to 105-3 corresponding to the three and the serial-to-parallel conversion unit 107 of the shared memory 102 Are connected by a common bus 104 consisting of
A bus acquisition request signal REQ is transmitted between the serial / parallel conversion units 105-1 to 105-3 and the bus priority determination circuit 108, respectively.
And the signal lines 106-1 to 106-3 including the bus acquisition response signal ACK.

Accordingly, the serial-parallel conversion units 105-1 to 105-1
-3 is 32 from the processors 101-1 to 101-3.
Bit data (write data, address, command, etc.) is serially converted to transmission data SD, and serial reception data RD is converted to 32-bit data and transferred to processors 101-1 to 101-3. Processor 1
The access request signal REQ to the shared memory 102 from 01-1 to 101-3 is transmitted from the control signal lines 106-1 to 103-1.
6-3, is sent to the bus priority determination circuit 108, and the bus priority determination circuit 108
Send CK. As a result, the number of signal lines for connecting the boards on which the processors are mounted is reduced, so that the size of the connector and the space for the common bus can be reduced.

FIG. 26 is a diagram for explaining the operation of the conventional example.
Q1 to REQ3 indicate bus acquisition request signals from the processors 101-1 to 101-3, ACK1 to ACK3 indicate bus acquisition response signals from the bus priority determination circuit 108, and a bus acquisition CPU (processor), a clock signal CLK, ,
Transmission data SD (write data, memory address),
It shows received data RD (read data) and shared memory access.

The memory access operation is represented by
The bus acquisition operation will be described with reference to symbols (a) to (l). The processors will be described as CPU1 to CPU3. CPU
1 sends a bus acquisition request signal REQ1 and the bus priority determination circuit 108 sends a bus acquisition response signal ACK to the CPU1.
1 and the CPU 1 sends the transmission data SD,
The memory control unit 103 performs write and read access operations to the shared memory 102. Next, the received data RD is transmitted from the memory control unit 108, the completion of bus acquisition is notified from the CPU 1, and the bus priority determination circuit 108
The bus acquisition response signal ACK1 to PU1 is terminated.

The bus acquisition operation is as follows: (a) The CPU 1 issues a bus acquisition request. (b) CPU from the bus priority determination circuit 108
A bus acquisition response is returned to 1. (c) A bus acquisition request from the CPU 2 and (d) a bus acquisition request from the CPU 3, that is, a case where a conflict occurs between the bus acquisition requests. In this case, the bus priority determination circuit 108 determines the CPU that has transmitted the bus acquisition request first.
Select 1 and return the bus acquisition response of (b). And
(e) Notifying the end of the bus acquisition by the end of the processing of the CPU 1,
(f) The bus priority determination circuit 108 releases the bus from the CPU 1, (g) the bus priority determination circuit 108 transmits a bus acquisition response to the CPU 2 which has transmitted the bus acquisition request, and (h) the CPU 2
(I) The bus priority determination circuit 108 releases the bus from the CPU 2, and (j) the bus priority determination circuit 108 sends a bus acquisition response to the CPU 3.
(k) The end of bus acquisition is notified by the end of processing by the CPU 3.

Therefore, as shown as a bus acquisition CPU, control by the bus priority determination circuit 102 is performed so that the shared memory 102 can be accessed in the order of the CPU1, CPU2, and CPU3. , Shared bus 104 shared with shared memory 102
Write data (SD) and read data (RD) via
Will be sent and received.

[0011]

In the conventional multiprocessor system, the common bus 104 is shared, so that the bus priority determination circuit 108 responds to a conflicting bus acquisition request with one processor. Returns a bus acquisition response only to the
, And access to the shared memory 102 is enabled.

However, when a contention for an access request (bus acquisition request) to the shared memory 102 occurs, a low-priority processor continues to wait until the processing of the high-priority processor ends. That is, FIG.
As shown by the CPU 3 access waiting time between (d) and (j) in the above, there is a problem that the bus acquisition is delayed until the processing of the CPU 2 having a higher priority is completed, and high-speed processing cannot be performed. SUMMARY OF THE INVENTION It is an object of the present invention to eliminate a processing delay due to a bus acquisition wait and to shorten a bus occupation time.

[0013]

According to the present invention, there is provided a multiprocessor system comprising: (1) a plurality of processors 1-1 to 1-1;
3 (CPU1 to CPU3) and a shared memory 2, a plurality of processors 1
The serial-parallel converters 5-1 to 5-1 connected to -1 to 1-3, respectively.
A bus 4 for transferring serial data between 5-3 and the serial-parallel converter 7 of the memory controller 3 connected to the shared memory 2.
1 to 4-3, and a data buffer selector 6 is connected between the shared memory 2 and the serial / parallel conversion unit 7 of the memory control unit 3. The data buffer selector 6 has a transmission / reception function corresponding to a plurality of processors. A configuration is provided in which a data buffer is provided and a priority determination circuit 8 for performing priority selection control between the transmission / reception data buffer and the shared memory 2 is provided.

(2) The memory control unit 3 determines whether or not the communication is between processors, and for the communication between processors, performs a data transfer control via a transmission / reception data buffer.
An inter-PU communication determination / control unit can be provided.

(3) The memory control unit 3 includes a serial / parallel conversion unit 7, a data buffer selector 6, and a priority determination circuit 8.
The data buffer selector 6 temporarily accumulates data from the processor, and upon completion of the accumulation of the data, a reception data buffer for transmitting a bus acquisition request signal REQ to the priority determination circuit 8 and a data for transmission to the processor. And a transmission data buffer for sending to the processor in response to a bus acquisition response signal ACK from the priority determination circuit 8. The priority determination circuit 8
A configuration is provided for performing priority selection control of Q and transmitting a bus acquisition response signal ACK.

(4) The priority judging circuit 8 can include a priority judging unit for transmitting a bus acquisition response signal ACK in accordance with a preset priority when a bus acquisition request signal conflicts.

(5) The priority judging circuit 8 judges the number of transmissions of the bus acquisition response signal ACK corresponding to the processor, and the bus acquisition request signal REQ according to the number of transmissions stored in the judgment number storage. And a priority order determination unit that changes the priority order.

(6) The priority judging circuit 8 can include a data analyzing section for analyzing the data stored in the received data buffer and changing the priority in the priority judging section.

(7) The memory control unit 3 has a configuration in which the processor to which the occupation is permitted is occupied in the shared memory by transmitting and receiving the exclusive control message, and the shared memory is accessed via the data buffer selector. be able to.

(8) The memory control unit 3 gives the processor which has given the occupation permission in accordance with the mark state and the space state of the data transmitted / received via the bus corresponding to the processor.
A configuration may be provided in which the shared memory is occupied and the shared memory is accessed via the data buffer selector.

(9) A plurality of processors 1-1 to 1-3
And the serial-parallel converters 5-1 to 5-3 connected to the shared memory 2 and the serial-parallel converters 7 of the memory controller 3 connected to the shared memory 2, respectively.
A multi-processor system connected by serial buses 4-1 to 4-3 for transferring commands and responses transmitted and received between a processor and a shared memory and between the processors. In addition, a configuration may be provided in which an abnormal point is determined in accordance with error detection and monitoring time lapse.

[0022]

FIG. 1 is an explanatory diagram of a first embodiment of the present invention, wherein 1-1 to 1-3 are processors (CPUs).
1 to CPU 3), 2 is a shared memory, 3 is a memory control unit,
Reference numerals 4-1 to 4-3 denote buses corresponding to a processor including signal lines of transmission data SD, reception data RD, and a clock signal CLK; 5-1 to 5-3, 6 data buffer selectors; The unit (P / S · SP), 8 indicates a priority determination circuit.

The serial-parallel converters 5-1 to 5-3 exchange, for example, 32-bit parallel data, 2-bit read / write commands with the processors 1-1 to 1-3.
The clock signal CLK is transferred, and serial / parallel conversion is performed between the serial transmission / reception data RD and the clock signal CLK between the serial / parallel conversion unit 7 of the memory control unit 3. is there. The transmission data SD includes write data, a memory address, and a write command, and the reception data RD includes read data.
Therefore, the buses 4-1 to 4-3 between the processors 1-1 to 1-3 and the shared memory 2 can be constituted by three signal lines. Also, the serial-parallel conversion unit 5-1
5-3 and the processors 1-1 to 1-1 are connected by, for example, 35 signal lines, and between the serial-parallel conversion unit 7 and the data buffer selector 6, for example, per processor, , 35 signal lines.

The memory control unit 3 includes the serial / parallel conversion unit 7, the data buffer selector 6, and the priority determination circuit 8
The priority determination circuit 8 includes a function similar to that of the conventional bus priority determination circuit. The priority determination circuit 8 responds to the bus acquisition request signal REQ from the data buffer selector 6 to determine the priority when a conflict occurs. The corresponding bus acquisition response signal ACK is returned to the data buffer selector 6. The data buffer selector 6 has a function of controlling read / write access to the shared memory 2 and a function of the processors 1-1 to 1-1.
Transmission of the bus acquisition request signal REQ between the buffer function corresponding to J.-3 and the priority determination circuit 8 and the bus acquisition response signal AC
It includes a K reception function and a buffer function selection control function using a bus acquisition response signal ACK.

FIG. 2 is a diagram for explaining the operation of the first embodiment of the present invention, wherein CLK is a clock signal, SD1 to SD3 are transmission data (write data, memory address, Commands, etc.), RD1 to RD3
Is reception data (read data, response, etc.) corresponding to the processors 1-1 to 1-3, and REQ1 to REQ3 are
-1 to 1-3 corresponding bus acquisition request signals, ACK1 to AC
K3 indicates a bus acquisition response signal corresponding to the processors 1-1 to 1-3. Shared memory access and bus acquisition CPU
(Processor). Processors 1-1 to 1-3
Are shown as CPU1 to CPU3.

An operation for accessing the shared memory 2 is as follows.
This will be described with reference to FIG. Transmission data SD from CPU1
1 is transmitted to the bus 4-1 via the serial / parallel converter 5-1. In this case, the buses 4-1 to 4-3 are connected to the processor 1-1.
Since it corresponds to an individual bus corresponding to .about.1-3, if it can be received by the memory control unit 3, it can be transmitted at an arbitrary timing. That is, there is no need for bus contention control.

The transmission data SD from the CPU 1
When the data buffer 1 has been stored in the data buffer selector 6 via the serial / parallel conversion unit 7, the bus acquisition request signal REQ1 is sent from the data buffer selector 6 to the priority determination circuit 8. On the other hand, if there is no contention of the bus acquisition request signal, the priority determination circuit 8 immediately sends the bus acquisition response signal AC
K1 is returned. The data buffer selector 6 accesses the shared memory in response to the bus acquisition response signal ACK1, and controls reading / writing of data corresponding to the processor CPU1.

The read data from the shared memory 2 is
The data is transmitted from the data buffer selector 6 to the bus 4-1 as the reception data RD of the processor CPU1. And
The data buffer selector 6 notifies the priority determination circuit 8 of the end of the bus acquisition. The priority determination circuit 8 includes the CPU 1
, And processing for the next bus acquisition request is performed. Then, the transmission of the data RD from the data buffer selector 6 via the serial / parallel converter 7 is completed.

The bus acquisition operation in the priority determination circuit 8 is
This will be described with reference to (a) to (l). First, (a) when the transmission data SD1 is completely stored in the data buffer selector 6 from the CPU 1, the bus acquisition request signal REQ1 is transmitted from the data buffer selector 6. If another bus acquisition request signal is not input to the priority determination circuit 8 at this time,
(b) The priority determination circuit 8 sends a bus acquisition response signal ACK1 to the data buffer selector 6. CPU2, CP
When the transmission data SD2 and SD3 from U3 are also stored in the data buffer selector 6, respectively, the bus acquisition request signals REQ2 and REQ3 are sent to the priority determination circuit 8 in (c) and (d).

The priority determination circuit 8 has a bus acquisition response signal AC
A priority determination process is performed on the bus acquisition request signals REQ2 and REQ3 during transmission of K1. For example, when it is determined that the bus acquisition request signal REQ2 is given priority, (e) the write access to the shared memory 2 for the transmission data SD1 is terminated. , Terminates the bus acquisition request signal REQ1, thereby terminating the (f) bus acquisition response signal ACK1 and transmitting the waiting (g) bus acquisition response signal ACK2.

The data buffer selector 6 transmits the transmission data SD of the CPU 2 according to the bus acquisition response signal ACK2.
When the write access to the shared memory 2 is performed and the access is completed, (h) the bus acquisition request signal ACK2
Is terminated, and (i) the bus acquisition response signal ACK2 is terminated, and the priority determination circuit 8 sends the bus acquisition response signal ACK3 for the waiting (j) bus acquisition request signal REQ3.

The data buffer selector 6 transmits the transmission data SD3 of the CPU 3 according to the bus acquisition response signal ACK3.
Is performed, the bus access request signal REQ3 is terminated, and accordingly, the (k) bus acquisition response signal ACK3 is terminated. Therefore, (l) the shared memory access ends. That is, the bus acquisition CPUs are CPU1, CPU2,
The order of the CPU 3 is established, and the access to the shared memory 2 becomes possible.

FIG. 3 is an explanatory diagram of a memory control unit according to the first embodiment of the present invention, wherein 2 is a shared memory, 3 is a memory control unit, 6 is a data buffer selector, 7 is a serial-parallel conversion unit, 8 is a priority determination circuit, 10 is an inter-processor communication unit, 1
1 is an S / P converter, 12 is a P / S converter, 13 is a reception data buffer, 14 is a transmission data buffer, 15 is a memory access controller, 16 is a transmission WT pulse generator, 17
Indicates a gate circuit, 18 indicates an OR circuit, and 19 indicates a priority determination unit.

The inter-processor communication unit 10 in the memory access control unit 15 enables inter-processor communication without passing through the shared memory 2, as will be described later. Although it includes a forward switching unit and the like, an inter-processor communication unit 10 will be described below for simplicity.
A description will be given of a case where the configuration is omitted. The S / P converter 11 converts the transmission data SD into parallel data according to the clock signal and transfers the parallel data to the reception data buffer 13. The reception data buffer 13 sends the bus acquisition request signals REQ1 to REQ3 to the priority determination circuit 8 when the data accumulation is completed. The priority determination processing unit 19 of the priority determination circuit 8 includes a bus acquisition request signal RE corresponding to the processors CPU1 to CPU3.
The bus acquisition response signals ACK1 to ACK3 resulting from the priority determination processing of Q1 to REQ3 are
And to the gate circuit 17. The reception data buffer 13 that has received the bus acquisition response signal transfers parallel data such as write data, addresses, and read / write commands to the shared memory 2 via the gate circuit 18.

The transmission WT pulse generator 16 transmits the transmission WT pulse.
A (write) pulse is generated and applied to the transmission data buffer 14 via the gate circuit 17. The pulse corresponds to the output timing of the parallel data from the shared memory 2 and is transmitted to the transmission data buffer 14 corresponding to the bus acquisition response signal. , Transmit WT pulse to store the parallel data, and upon completion of the storage, transfer the parallel data of the transmission unit from the transmission data buffer 14 to the P / S converter 12 and convert it into serial data to convert the received data RD into the serial data. I do. This transmission data RD is sent to the processor via an individual bus.

FIG. 4 is an explanatory diagram of a priority judging circuit according to the first embodiment of the present invention, wherein 19 is a priority order judging unit, 20 is a judgment count storage unit, 21 and 22 are flip-flops, 23
Indicates an update clock generator, 24 to 29 indicate AND circuits (&), 31 to 33 indicate AND circuits (&), 34 to 36 indicate flip-flops, and 37 to 39 indicate AND circuits (&). The priority order determination unit 19 includes the flip-flops 21 and
2, an AND circuit 24 to 29, an inverter indicated by a triangle, and an update clock generator 23.
Bus acquisition request signals REQ1-RE corresponding to U1-CPU3
In response to Q3, bus acquisition response signals ACK1 to ACK3 according to the priority determination are output.

The number-of-determinations storage unit 20 includes flip-flops 34 to 36 and AND circuits 31 to 33, and stores the processors that have transmitted the bus acquisition response signals ACK1 to ACK3. The bus acquisition response signals ACK1 to AC
The number of times K3 is stored and the second bus acquisition request signal REQ
1 to REQ3 are masked by the AND circuits 37 to 39 with respect to the priority order determination unit 19. Then, it returns to the initial state after transmitting a bus acquisition response signal in response to all the bus acquisition request signals.

The update clock generator 23 outputs a clock signal for determining the interval of the priority order determination, inputs the clock signal to the clock terminals CLK of the flip-flops 21 and 22, and inputs the data terminals D1 to D3 at that time. Latch the signal. As described above, the bus acquisition request signals REQ1 to REQ3 are output when the data storage in the reception data buffer 13 (see FIG. 3) is completed, and the flip-flops 34 to 36 of the determination count storage unit 20 are inverted. Output terminal *
When Q is “1”, it is input to the data terminals D1 to D3 of the flip-flop 21 via the AND circuits 37 to 39. The transmission completion pulse is input to the priority determination circuit 8 when data is transmitted from the transmission data buffer 14 (see FIG. 3) via the P / S converter 12.

For example, when the bus acquisition request signals REQ1 to REQ3 due to the completion of data storage in the reception data buffers 13 corresponding to the CPU1 to CPU3 are input almost simultaneously, the inverted output terminals * Q of the flip-flops 34 to 36 become "1".
, "1" is input to the data terminals D1 to D3 of the flip-flop 21 via the AND circuits 37 to 39,
The output terminals Q1 to Q3 of the flip-flop 21 become “1” by the clock signal from the update clock generator 23.

Output terminals Q1 to Q of flip-flop 21
The inverters 3 are connected to respective inverters, and the output signals of the AND circuits 24 and 25 become "0". Therefore, the output signal of the AND circuit 27 is “1”, and the AND circuits 26 and 2
The output signals of 8, 29 become "0". As a result, only the output terminal Q1 of the flip-flop 22 becomes "1", and the bus acquisition response signal ACK1 ("1") for the processor CPU1 having the highest priority is output.

This bus acquisition response signal ACK1 ("1")
And a transmission completion pulse ("1") corresponding to the processor CPU1 which has completed data transmission / reception in accordance therewith, is input to the AND circuit 31, and its output signal becomes "1". Therefore, the inverted output terminal * Q of the flip-flop 34 becomes “0”, and is masked by the AND circuit 37 even if the next bus acquisition request signal REQ1 is input. Then, the output terminal Q1 of the flip-flop 21 becomes “0” by the next clock signal from the update clock generation unit 23, and the output terminals Q2 and Q3 are “1”. 1 ", and only the output terminal Q2 of the flip-flop 22 becomes" 1 ". That is, a bus acquisition response signal ACK2 corresponding to the processor CPU2 is output.

By the transmission completion pulse ("1") corresponding to the processor CPU2 according to the bus acquisition response signal ACK2, the inverted output terminal * Q of the flip-flop 35 becomes "0".
Becomes As a result, the output signal of the AND circuit 38 becomes “0”, so that the next clock signal from the update clock generator 23 causes the output terminals Q1 and Q2 of the flip-flop 21 to become “0” and only the output terminal Q3 to “0”. 1 ". Therefore, only the output signal of the AND circuit 29 is "1".
And only the output terminal Q3 of the flip-flop 22 becomes "1". That is, a bus acquisition response signal ACK3 corresponding to the processor CPU3 is output.

When the transmission completion pulse corresponding to the processor CPU3 according to the bus acquisition response signal ACK3 is input, the inverted output terminal * Q of the flip-flop 36 becomes "0".
Becomes Then, the next clock signal from the update clock generator 23 causes the output terminal Q
1 to Q3 are "0". Thereby, the AND circuit 26
Becomes "1", and this is used as an empty signal (no bus acquisition request signal) as flip-flops 34-3.
6 to the clear terminal CL. As a result, the inverted output terminals * Q of the flip-flops 34 to 36 become "1" and return to the initial state.

As described above, when the bus acquisition request signals compete with each other, the priority determination section 19 sends a bus acquisition response signal corresponding to the processor having the higher priority. A bus acquisition response signal corresponding to the processor of the priority can be transmitted. In this case, even for lower priority processors,
The bus acquisition response signal can always be output.

FIG. 5 is an explanatory diagram of a priority judging circuit according to a second embodiment of the present invention. Reference numerals 41 and 42 denote flip-flops, 43 denotes an update clock generator, and 44, 45, 47 to 4
Reference numeral 9 denotes an AND circuit (&). The priority determination circuit of this embodiment corresponds to a case where it is constituted by the main part of the priority determination unit 19 in FIG. 4, and enables high-speed determination of the priority for the bus acquisition request signal.

For example, if the bus acquisition request signals REQ1 and REQ3 corresponding to the processors CPU1 and CPU3 are inputted, the output terminals Q1 and Q3 of the flip-flop 41 become "1" by the clock signal from the update clock generator 43. The output signal of the AND circuit 47 becomes "1", the output signals of the AND circuits 48 and 49 become "0", and only the output terminal Q1 of the flip-flop 42 becomes "1". That is, a bus acquisition response signal ACK corresponding to the processor CPU1.
1 is output.

When the processing corresponding to the flip-flop CPU 1 is completed in accordance with the bus acquisition response signal ACK 1, the bus acquisition request signal ACK 1 becomes “0”, and the output terminal of the flip-flop 41 is output by the next clock signal from the update clock generator 43. Only Q3 becomes "1". Therefore,
Only the output signal of the AND circuit 49 becomes "1", and only the output terminal Q3 of the flip-flop 42 becomes "1". That is, a bus acquisition response signal ACK corresponding to the processor CPU3.
3 is output.

In this embodiment, a priority can be determined for the bus acquisition request signal for each cycle of the clock signal of the update clock generator 43, and a bus acquisition response signal can be output. , Processor CPU
2. If the CPU 3 is used for normal system control and the processor CPU 1 is used for system failure control, a bus acquisition response signal ACK1 is sent to the processor CPU 1 at a high speed when a system failure occurs, and an access right to the shared memory is given. In FIG. 3, the reception data buffer 1
3 can write data to the shared memory 2 and transfer data read from the shared memory 2 to the processor CPU1 via the transmission data buffer 14.

FIG. 6 is an explanatory diagram of a priority judging circuit according to a third embodiment of the present invention. The same reference numerals as those in FIG. 4 denote the same parts, 51 to 53 denote a data analysis unit, and 54 denotes a mask control unit.
55 to 57 indicate AND circuits (&). In this embodiment, the data analysis units 51 to 53 analyze received data corresponding to the processors CPU1 to CPU3 to determine whether the data is urgent and notify the mask control unit 54 of the data.

The mask control unit 54 includes AND circuits 55 to 5
7, bus acquisition request signals REQ1 to REQ3
Is masked in accordance with the analysis result of the reception data. For example, when the mask control unit 54 determines that the analysis result of the reception data from the processors CPU1 to CPU3 and the priority of the reception data from the processor CPU2 are the highest. , A bus acquisition request signal REQ2 via an AND circuit 56
To the AND circuit 38. At this time, if the output signals of the number-of-determinations storage unit 20 are all “1”, the AND circuit 38
, The bus acquisition request signal REQ2 is input to the priority determination circuit 19, and the bus acquisition response signal ACK2 corresponding to the processor CPU2 is output as described above. Can be accessed.

Priority determination section 19 and determination count storage section 20
Means that the configuration shown in FIG. 4 can be applied.
EMPTY of the priority determination unit 19 corresponds to the output signal of the AND circuit 26 in FIG. 4 and is a signal for clearing the number of times stored in the number-of-times-of-determination storage unit 20. It should be noted that the number-of-times-of-determination storage unit 20 is omitted, and the
The configuration shown in FIG. Further, when the processing processor at the time of occurrence of a failure is, for example, CPU1, the mask control unit 54 processes the processor CPU1 preferentially and performs processing in accordance with the data analysis results of the data analysis units 51 to 53. can do.

FIG. 7 is an explanatory diagram of a priority judging circuit according to a fourth embodiment of the present invention.
39 is an AND circuit (&), 60 is a judgment count storage unit, 61
63 is an AND circuit (&), 64 is a shift register, 6
Reference numerals 5 and 66 indicate flip-flops.

The shift register 64 includes a processor CPU
When the bus acquisition response signal ACK1 corresponding to 1 is output four times, the inverted output terminal * Q becomes "0", and the flip-flops 65 and 66 output the bus acquisition response signals ACK2 and ACK3 corresponding to the processors CPU2 and CPU3 of 1 respectively. The inverted output terminal * Q becomes "0" when the signal is output once. Then, when all the inverted output terminals * Q become “0”, the empty signal EMPTY (“1”) of the priority order judging unit 19 determines that there is no bus acquisition request and the shift register 64 and the flip-flops 65 and 66 The signal is input to the clear terminal CL and returns to the initial state.

In this case, the processor CPU1 processes image data and audio data in real time,
When the PU 2 and the CPU 3 are systems for processing normal data, the processing of the processor CPU 1 can be prioritized, and a desired communication band can be secured for image data and audio data for processing. Therefore, the number of stages of the shift register 64 can be further increased according to the relationship with the other processors CPU2 and CPU3. Further, the flip-flops 65 and 66 corresponding to the other processors CPU2 and CPU3 may be configured by a plurality of stages of shift registers to store the output of the bus acquisition response signal a plurality of times.

FIG. 8 is an explanatory diagram of a priority judging circuit according to a fifth embodiment of the present invention. The same reference numerals as those in FIGS. 6 and 7 denote the same parts, 70 is a judgment count storage unit, and 71 to 73 are AND circuit (&), 74 to 76 are shift registers, 77 to 7
Reference numeral 9 denotes a selector.

The data analyzers 51 to 53 are provided with the processor C
It is analyzed whether the received data corresponding to PU1 to CPU3 is urgent or not. If the received data is urgent, a signal is input to the selection terminals SEL of the selectors 77 to 79 and the input terminals A and B are input. Is selected, and otherwise, A is selected. That is, in the case of data to be processed in real time, such as audio data, the fourth-stage inverted output terminal * Q4 of the shift registers 74 to 76 corresponding to the input terminal B
By using this output signal, a bus acquisition response signal can be output four consecutive times.

The inverted output terminal * Q1 of the first stage of the shift registers 74 to 76 becomes "0" by outputting the bus acquisition response signal once. A similar operation is performed. That is, the shift registers 74 are selected by the selectors 77 to 79.
The number of stages from -76 is switched.

Therefore, when the data analyzers 51 to 53 determine that the received data is, for example, image data or audio data, the terminal B of the selectors 77 to 79 is selected, whereby the bus acquisition response signal is obtained. By increasing the number of ACK transmissions, the communication band can be expanded, and image data and audio data can be processed without interruption. Although a case is shown in which shift registers 74 to 76 having the same configuration are provided for the processors CPU1 to CPU3, shift registers having different numbers of stages may be provided according to the degree of importance or the like. Also, the shift registers 74 to 76 of the number-of-times-of-determination storage unit 70 return to the initial state according to the empty signal EMPTY of the priority order determination unit 19.

FIG. 9 is an explanatory diagram of a priority judging circuit according to a sixth embodiment of the present invention.
39 is an AND circuit (&), 80 is a judgment count storage unit, 81
And 83 are AND circuits (&), 84 to 86 are counters, 8
Reference numerals 7 to 89 indicate selectors. In this embodiment, the number of outputs of the bus acquisition response signals ACK1 to ACK3 is
Counting is performed by 4 to 86, and this count value (the number of stages) is selected by selectors 87 to 89. The selectors 87 to 89 are set in advance or each time by the frequency setting information.

Therefore, during the operation of the system, the bandwidth required for processing the image data, audio data, and the like by the processors CPU1 to CPU3 is changed by the selectors 87 to 89 via control signal lines and the like (not shown). By setting the number of steps of the counters 84 to 86 based on the number of times setting information, the number can be secured. Bus acquisition response signal A
A counter 84 that stores the number of outputs of CK1 to ACK3
The content of 86 is the empty signal E of the priority determination unit 19.
It can be cleared by MPTY and returned to the initial state.

FIG. 10 is an explanatory diagram of access control of the shared memory. The bus acquisition request signal REQ of the processor CPU1 is shown in FIG.
1, the bus acquisition response signal signal ACK1 and the processor CP
U2 bus acquisition request signal REQ2 and bus acquisition response signal A
CK2, the processor CPU occupied by the access, the transmission data SD, the reception data RD, and the access to the shared memory. The transmission data from the processor CPU1 is written as the shared data in the shared memory, and the processor CPU2 reads the shared data. The bus acquisition response signal A
CK1 and ACK2 enable exclusive access control to the shared memory.

FIG. 11 is an explanatory diagram of the shared memory. When the processor CPU1 writes the shared data A (n) to the shared memory and the processor CPU2 reads the shared data at a constant period, the processor CPU1 n)
During the writing of the shared data A
If the writing of (n) is stopped halfway, the shared memory will
Data A (n) up to the middle of this time and previous data A
(N-1) is stored. When the processor CPU2 reads the shared data from the shared memory in such a state, a part of the latest data A (n) and a part of the previous data A (n-1) are read. That is, exclusive control is required during writing of the common data to the shared memory.

Multiprocessors connected by a common bus
In the system, the contention control can be performed for the occupation request of the common bus, and the exclusive control can be performed. However, as shown in FIG. When connected via 4-1 to 4-3, exclusive control is not sufficient only with the function of the priority determination circuit 8 of the memory control unit 3. Therefore, according to the present invention, a communication message enabling exclusive control is defined as described below.

FIG. 12 is an explanatory diagram of a shared memory access according to the seventh embodiment of the present invention.
This shows a case where a dedicated message is used in a multiprocessor system having CPUn, and the following message is defined. (1). Occupancy request: The CPU requests the shared memory for exclusive control of memory access. (2). Occupation permission; the common memory notifies the CPU of the completion of exclusive control of memory access. (3). Release of occupancy: The CPU requests the common memory to release exclusive control of memory access. (4). Release Completed: The common memory notifies the CPU of the completion of release of exclusive control of memory access. (5). Access prohibited; indicates that a certain CPU occupies the memory from the common memory to another CPU. (6). Access permission; indicates that a certain CPU has released the occupation of the memory from the shared memory to another CPU.

The operating rules of the common memory and the processor (CPU) are as follows. (1). A processor that performs exclusive control on the shared memory; If an “access prohibited” message was previously received from the shared memory, the “access allowed” message is awaited. . If the “access permission” message is received from the shared memory or the “access permission” message is received before,
Sends an "occupation request" message to the shared memory and waits for a response. (a). If the response message is "permission allowed", execute memory access. After the completion of this memory access, a "release of exclusive use" message is sent, and a response is waited for.・ If the response message is “Release completed”, from the shared memory,
It is determined that the “access permitted” message has been received, and the access ends. -If the response message is "access prohibited", the shared memory
It recognizes that it is in the exclusive control state and ends access. (b) If the response message is "access prohibited", it recognizes that the other CPU is occupying the shared memory by exclusive control, waits for a response until it receives a "permission allowed" message, and
When a message is received, the above-mentioned operation (a) is performed.

(2). The operating rules of the common memory are as follows. . When receiving an “occupancy request” message from a certain CPU,
A "permission occupation" message is transmitted to the CPU, an "access prohibition" message is transmitted to another CPU at the same time, and exclusive control is performed for only the CPU that has transmitted the "occupation request" so that memory access is possible. . . When a “release of exclusive use” message is received from the CPU that transmitted the “occupancy request” of the shared memory, the exclusive control of the memory access is released, and the “release complete” message is sent to the CPU that sent the “exclusive release” message. Sending, and at the same time, another CP
U sends 4 access permission message. . When receiving an "occupation request" message from a plurality of CPUs, a priority determination is performed, a CPU to which "occupation permission" is given is selected, and an "occupation permission" message is sent to the selected CPU, and simultaneously sent to another CPU. Send an "access prohibited" message. . When receiving an “occupation request” message from a plurality of CPUs, the CPU performs a priority determination and occupies the shared memory.
Is selected, and a "permission exclusive" message is transmitted to the selected CPU, and at the same time, the CPU which previously transmitted the "release exclusive" message.
And sends an "access prohibited" message to the other CPUs.

The operation of FIG. 12 is described by defining a message as described above. Only the processor CPU1 transmits the transmission signal S.
Sends an "occupation request" message as D1 and sends the message to processor CP.
To U1, an "occupation permission" message is transmitted as the reception signal RD1, and an "access prohibited" message is transmitted as the reception signals RD2 to RDn to the other processors CPU2 to CPUn, and the processor CPU1 occupies the shared memory. When a memory access is performed, a response from the shared memory is received, and a “release of exclusive use” message is transmitted upon completion of access to the shared memory, a “release complete” message is received from the shared memory. An “access permitted” message is sent to the other processors CPU2 to CPUn.

FIG. 12 shows a case where the occupation requests do not conflict, and FIG. 13 shows a case where the occupation requests conflict. That is, when the "occupation request" message is transmitted from the processors CPU1 and CPU2, for example, the processor C
PU1 is selected and an "occupation permission" message is sent to this processor CPU1.
An Unaccessible message is sent to Un.

The processor CPU1 occupies and accesses the shared memory, and when the access is completed, sends a "release exclusive" message. The shared memory sends an “occupation permission” message to the processor CPU2, and the other processors CPU1 and CPU2.
An "access prohibited" message is sent to CPU3 to CPUn. In this way, it is possible to easily perform exclusive control for accessing the shared memory while occupying the shared memory and prohibiting access by other processors.

FIGS. 14 and 15 are diagrams for explaining shared memory access according to the eighth embodiment of the present invention. FIG. 14 shows the mark states and the transmission signals SD1 to SDn and the reception signals RD1 to RDn of the processors CPU1 to CPUn. Define the space state. The “mark” state is a continuous high-impedance (high-level) state when the non-communication state and the exclusive control of the shared memory are not performed, and the “space” state is a continuous low-level state other than the “mark” state. Show.

Therefore, the processors CPU1 to CPUn
When the reception signals RD1 to RDn are in the “space” state, the device recognizes that the shared memory is in the exclusive control state and stops accessing the shared memory. The processor requesting the shared memory to perform exclusive control changes the transmission signal to the “space” state. The shared memory is stored in each processor C
Monitor transmission signals SD1 to SDn of PU1 to CPUn,
If the transmission signal SD is in the “space” state during the fixed time T1, it is considered that the processor CPU has requested exclusive control.

When one processor requests the exclusive control, the reception signal RD of another processor is set to the "space" state (access prohibited). If a plurality of processors request exclusive control at the same time, a priority determination is made, a processor to which occupancy is granted is selected, and the reception signal RD other than the processor is set to a "space" state (access prohibited). The processor that requests the shared memory to perform the exclusive control changes the transmission signal SD to the “space” state, and after a lapse of a predetermined time T2 (> T1), if the reception signal RD is in the “mark” state, The memory access is performed assuming that the occupation permission has been given to the shared memory.

After the memory access is completed, the transmission signal SD is sent for a certain time T1,
Set to "space" state. In order to distinguish between the normal memory access power supply and response message and the "space" state for a fixed time T2 used for exclusive control, the memory access message and the response message must be marked with "mark" within a certain time T1 from the start of the message. Is added such that a state appears.

FIG. 14 shows a case where the occupation requests do not conflict with each other.
1. If the reception signal RD1 is not in the "space" state after the elapse of the predetermined time T2, it is determined that the occupancy is permitted, and the memory access is started. The reception signals RD2 to RDn of the other processors CPU2 to CPUn
Is "space" state and access is prohibited. The shared memory is accessed by occupying the shared memory by the processor CPU1, and upon completion of the access, the transmission signal SD1 is transmitted for a certain time T1,
As the "space" state, notification of release of occupancy is notified, and the "space" state is continued until a certain time T2 has elapsed, so that the reception signals R of the other processors CPU2 to CPUn are output.
The access prohibition is released by setting D1 to RDn to the “mark” state.

FIG. 15 shows a case where the occupation requests compete with each other.
When SD3 is sequentially set to the "space" state and an occupancy request is made, if the processor CPU1 is preferentially selected, the reception signal RD1 of the processor CPU1 maintains the "mark" state and the reception signals RD of the other processors CPU2 to CPUn.
2 to RDn are set to the “space” state and access is prohibited. As a result, the processor CPU1 occupies and accesses the shared memory, and upon completion of the access, the transmission signal SD1 is released for a certain period of time T1 in the "space" state, thereby canceling the occupation.
The receiving signal RD2 of PU2 is set to the “mark” state to give occupation permission, and the processor CPU2 occupies and accesses the shared memory.

FIG. 16 is an explanatory view of the tenth embodiment of the present invention, wherein the same reference numerals as those in FIG. 1 denote the same parts, and 10 denotes an inter-CPU communication section setting / control section. That is, as shown in FIG. 3, the data buffer selector 6 has a configuration including the reception data buffer 13, the transmission data buffer 14, and the inter-processor communication unit 10, and performs a write / read operation to the shared memory 2. Without processor CPU1
~ Communication between the CPU 3.

FIG. 17 is an explanatory diagram of the operation of the tenth embodiment of the present invention.
The transmission data SD1 to SD3 and the reception data RD1 to RD3 corresponding to PU1 to CPU3, and the bus acquisition request signal REQ1
To REQ3 and bus acquisition response signals ACK1 to ACK3
, A shared memory access, and a bus acquisition CPU.
The timing when communication is performed from the processor CPU1 to the processor CPU2 is indicated by.

From the processor CPU1 to the processor CP
The transmission data SD1 to U2 is transmitted, and the data buffer
When the data is stored in the reception data buffer of the selector 6, a bus acquisition request signal REQ 1 is sent to the priority determination circuit 8. On the other hand, when there is no conflict, the priority determination circuit 8 sends out the bus acquisition response signal ACK1. Further, the inter-processor communication unit 10 determines the inter-processor communication command, identifies the communication destination processor, stores the processor of the communication source and the communication destination, and sends it out as the reception data RD2 of the processor CPU2.

The processor CPU2 receives the received data RD
2, the response to the CPU 1 is transmitted to the transmission data SD.
Send out as 2. When the data is stored in the reception data buffer corresponding to the processor CPU 2 of the data buffer selector 6, the bus acquisition request signal REQ is sent to the priority determination circuit 8.
Send out 2. On the other hand, when there is no conflict, the priority determination circuit 8 sends out the bus acquisition response signal ACK2.
Further, since the inter-processor communication unit 10 stores the communication destination and the communication source, the inter-processor communication unit 10 sends out a response from the processor CPU2 as reception data SD1 of the processor CPU1.

Thus, the processors CPU1, CPU1
Communication between the two can be performed via the data buffer selector 6 under the control of the communication determination / control unit 10 between the CPUs. In this case, the transfer between the reception data buffer and the transmission data buffer of the data buffer selector 6 is completed without accessing the shared memory 2.

FIG. 18 is an explanatory diagram of an inter-processor communication unit according to the tenth embodiment of the present invention. Reference numeral 91 denotes a command determination unit, 92 denotes a transfer destination analysis unit, 93 denotes a transfer destination switching unit, and 94 denotes a transmission WT. A pulse selector 95, an OR circuit (OR), 9
Reference numeral 6 denotes a selector (SEL).
2 shows a configuration corresponding to the CPU 2 and another processor CPU
3 is similar, but is not shown. (CPU1) and (CPU2) are processor CPUs.
1 shows a configuration corresponding to CPU2.

The command from the reception data buffer 13 (see FIG. 3) is taken into the command judgment section 91 at the timing of ACK1 from the priority judgment circuit 8, and in the case of a memory write / read command to the shared memory 2, And in the case of an inter-processor communication command,
It notifies the transfer destination analysis unit 92 and the transmission WT pulse selector 94. The transfer destination analyzing unit 92 analyzes the received data to identify a transfer destination processor, and sends a transfer destination selector signal to the transfer destination switching unit 93.

The transfer destination switching unit 93 controls the transfer destination selector 96 in accordance with the transfer destination selector signal, and transfers the data from the reception data buffer 13 to the transmission data buffer 14 as shown as communication data between CPUs. 95. After a certain time, the transmission WT pulse generator 16
Is transmitted from the transfer destination corresponding selector 96 to the transfer destination corresponding transmit WT pulse selector 94,
The transmission WT pulse selector 94 sends a transmission WT pulse to the transmission data buffer 14 corresponding to the transfer destination in accordance with the determination result of the inter-processor communication command from the command determination unit 91.

As a result, the reception data buffer 1 can be read without performing write / read operations on the shared memory 2.
3 and the transmission data buffer 14 to enable communication between processors. If the communication is not the inter-processor communication, the data from the shared memory 2 is transferred to the transmission data buffer 14 via the OR circuit 95, and the transmission WT pulse from the transmission WT pulse generator 16 is transmitted via the transmission WT pulse selector 94. Transfer to the transmission data buffer 14.

FIG. 19 is an explanatory diagram of abnormality detection, and shows a case where an abnormal part is specified based on a command and a response between the processor CPUn and the shared memory. (A) shows a case where the cable is disconnected, (b) shows a case where the power of the shared memory is turned off, (c) shows a command error, (d) shows a response error, and (e) shows a case where a medium error occurs in the shared memory.

FIG. 20 is a flowchart of the abnormality detecting operation. The timer is started by issuing a command (A1) from the processor (A2), and it is determined whether or not a response is received within a predetermined time (A3). If a response cannot be received even after a lapse of time, it is determined that an overtime has occurred (A4), and it is determined whether or not a clock loss has occurred (A5). judge. If the clock is not cut off, the command CRC (C
jclic Redundancy Check) Error (A
7).

If a response can be received within a certain period of time after the command is issued, the timer is cleared (A8), and it is determined whether or not a CRC error has occurred (A9). (A10). Also CR
If no C error has occurred, it is determined whether a memory parity error has occurred (A11), and if an error has occurred, a memory parity error is determined (A13). If no error occurs, the process ends normally (A12).

FIG. 21 is a diagram for explaining the abnormality type determination, in which the above-described abnormality types are summarized in a table.
There are an RC error and a memory parity error, and individual hardware abnormality causes include a cable disconnection / memory power cutoff, a command CRC error, a response CRC error, and a memory parity error.

Accordingly, when the processor CPU detects the bus overtime, it is determined that the cable disconnection / memory power-off or the command CRC error has occurred. Can be. By specifying the location where the abnormality has occurred, the recovery work can be performed quickly, and the reliability of the system can be improved.

FIG. 22 is a diagram for explaining an inter-processor communication abnormality. In FIGS. 22 (a) to (g), the master processor (C)
PU) and the slave processor (CPU) communicate with each other via the shared memory, (a) and (b) show the disconnection of the cable between the master processor and the shared memory and the power cut off of the shared memory, and (c) (D) Cable break between shared memory and slave processor, (e) Command CRC error for slave processor detection, (f) Response CRC error for shared memory detection, (g) ) Shows the case of a response CRC error detected by the master processor.

FIG. 23 is a flowchart of the abnormality detecting operation. The master processor issues a command (B1),
A timer is started (B2). It is determined whether the response has been received within the timer set time (B3). If no response has been received within the timer set time, an overtime occurs (B4), and the clock from the shared memory to the master processor is generated. It is determined whether or not a disconnection has occurred (B5). If a clock has occurred, it is determined that the cable between the master processor and the shared memory has been disconnected or the power of the shared memory has been disconnected (B5).
6).

In step (B3), if the response reception is completed within the set time of the timer, the timer is cleared (B7) and it is determined whether a CRC error has occurred (B7).
8) If no CRC error has occurred, terminate normally (B10). If a CRC error has occurred, it is determined that a CRC error has occurred in the master processor response (B9).

In step (B5), if no clock interruption has occurred, it is determined whether or not a clock interruption from the slave processor to the shared memory has occurred (B11). It is determined that the cable is disconnected from the memory (B12). If the clock is not cut off, it is determined whether or not a CRC error has occurred from the slave processor to the shared memory (B13).
If a C error has occurred, it is determined that a shared memory detection response CRC error has occurred (B14).

If no CRC error has occurred in step (B13), it is determined whether or not a CRC error has occurred on the slave processor side (B15). If a CRC error has occurred, it is determined that a slave processor detection command CRC error has occurred (B15). B17) If no CRC error occurs,
Judge as a shared memory detection command CRC error (B
16).

FIG. 24 is an explanatory diagram of the determination of the type of abnormality.
RC error and master C
PU-shared memory cable disconnection / shared memory power disconnection, shared memory detection command CRC error, shared memory-slave CPU cable disconnection, slave CPU detection command CRC error, shared memory detection response command, master CPU detection The response to the response CRC error is shown.

As described above, the location where an abnormality has occurred when communicating between the master processor and the slave processor via the shared memory can be specified based on the flowchart of FIG. Therefore, the recovery process can be speeded up by specifying the abnormal point, and the reliability of the system can be improved.

The present invention is not limited to only the above-described embodiments, and combinations of the embodiments are also possible. Although a multiprocessor system having three processors is shown, the present invention can be applied to a system including a larger number of processors. For read access and write access to the shared memory 2, various known means can be applied.

[0098]

As described above, according to the present invention, the buses 4-1 to 4 for performing serial data transfer between the plurality of processors CPU1 to CPU3 and the memory control unit 3 having the data buffer selector 6 are provided. The connection by -3 does not require a waiting time for bus occupation as compared with the case where the connection is made via a common bus, so that the processing delay can be reduced and the processing speed of the system can be improved. .
Further, since the buses 4-1 to 4-3 for transferring serial data can be configured with a small number of signal lines, connection between boards on which processors are mounted is also easy.

In addition, the control between the data buffer selector 6 and the shared memory 2 is performed in accordance with the priority order by the priority determination circuit 8. In response to the bus acquisition request signal REQ sent out upon completion of storing data in the reception data buffer. It is also possible to transmit the bus acquisition response signal ACK at high speed, and it is also possible to store the number of times the bus acquisition response signal ACK is transmitted and control the priority to be the lowest when the bus acquisition response signal ACK is transmitted a predetermined number of times. It is possible to provide the minimum number of occupation of the shared memory to all the processors without making the shared memory occupied only by the processor having the higher priority.

Further, by providing the inter-CPU communication determination / control unit 10 in the memory control unit 3, the inter-processor communication can be performed via the data buffer selector 6 without performing the operation of writing / reading data to / from the shared memory 2. There is an advantage that control becomes possible. Also, the presence or absence of a response to a command within a certain period of time and the presence or absence of a CRC error detection make it easy to identify an abnormal location, and therefore, it is possible to quickly repair the abnormal location, thereby improving the reliability of the system. can do.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a first embodiment of the present invention.

FIG. 2 is an operation explanatory diagram of the first embodiment of the present invention.

FIG. 3 is an explanatory diagram of a memory control unit according to the first embodiment of this invention.

FIG. 4 is an explanatory diagram of a priority determination circuit according to the first embodiment of this invention.

FIG. 5 is an explanatory diagram of a priority determination circuit according to a second embodiment of the present invention.

FIG. 6 is an explanatory diagram of a priority determination circuit according to a third embodiment of the present invention.

FIG. 7 is an explanatory diagram of a priority determination circuit according to a fourth embodiment of the present invention.

FIG. 8 is an explanatory diagram of a priority determination circuit according to a fifth embodiment of the present invention.

FIG. 9 is an explanatory diagram of a priority determination circuit according to a sixth embodiment of the present invention.

FIG. 10 is an explanatory diagram of access control of a shared memory.

FIG. 11 is an explanatory diagram of a shared memory.

FIG. 12 is an explanatory diagram of a shared memory access according to the seventh embodiment of this invention.

FIG. 13 is an explanatory diagram of a shared memory access according to the seventh embodiment of this invention.

FIG. 14 is an explanatory diagram of a shared memory access according to the eighth embodiment of this invention.

FIG. 15 is an explanatory diagram of a shared memory access according to the ninth embodiment of the present invention.

FIG. 16 is an explanatory diagram of a tenth embodiment of the present invention.

FIG. 17 is an operation explanatory diagram of the tenth embodiment of the present invention.

FIG. 18 is an explanatory diagram of an inter-processor communication unit according to a tenth embodiment of the present invention.

FIG. 19 is an explanatory diagram of abnormality detection.

FIG. 20 is a flowchart of an abnormality detection operation.

FIG. 21 is an explanatory diagram of abnormality type determination.

FIG. 22 is an explanatory diagram of a communication error between processors.

FIG. 23 is a flowchart of an abnormality detection operation.

FIG. 24 is an explanatory diagram of abnormality type determination.

FIG. 25 is an explanatory diagram of a conventional example.

FIG. 26 is an operation explanatory diagram of the conventional example.

[Explanation of symbols]

 1-1 to 1-3 processors (CPU1 to CPU3) 2 shared memory 3 memory control unit 4-1 to 4-3 bus 5-1 to 5-3 serial / parallel conversion unit (P / S / S / P) 6 data Buffer selector 7 Serial / parallel converter (P / S / S / P) 8 Priority determination circuit

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Hitoshi Maehara 1-17-3 Sakado, Takatsu-ku, Kawasaki-shi, Kanagawa F-term (reference) 5B045 BB12 BB28 BB29 BB34 DD01 EE03 EE12 EE16 5B061 BA01 BB01 BB16 BC10 DD09 GG16 QQ03 RR02 RR03 SS01 5B077 AA23 BA02 DD02 HH03 MM01 MM02 5B098 AA03 AA07 AA10 GB10 GD03 GD15

Claims (9)

[Claims] 1. In a multiprocessor system including a plurality of processors and a shared memory, a serial / parallel converter connected to each of the plurality of processors and a serial / parallel converter of a memory controller connected to the shared memory. Are connected by a bus for transferring serial data, a data buffer selector is connected between the shared memory and the serial / parallel conversion unit of the memory control unit, and the plurality of data buffer selectors are connected to the data buffer selector. A transmission / reception data buffer corresponding to the processor and a priority determination circuit for performing priority selection control between the transmission / reception data buffer and the shared memory. 2. A memory control unit for determining whether or not communication between processors is performed, and for communication between processors, a CP which controls data transfer via the transmission / reception data buffer.
2. The multiprocessor system according to claim 1, further comprising an inter-U communication determination / control unit. 3. The memory control unit includes: a serial-parallel conversion unit;
Including a data buffer selector and a priority determination circuit,
The data buffer selector temporarily stores data from the processor, and temporarily stores data to be transmitted to the processor, and a reception data buffer for transmitting a bus acquisition request signal to the priority determination circuit upon completion of the data storage. A transmission data buffer for transmitting to the processor in response to a bus acquisition response signal from the priority determination circuit, wherein the priority determination circuit performs priority selection control of the bus acquisition request signal and transmits the bus acquisition response signal. 3. The multiprocessor system according to claim 1, further comprising a configuration. 4. The priority determination circuit according to claim 1, wherein said priority determination circuit includes a priority determination unit for transmitting a bus acquisition response signal in accordance with a preset priority when said bus acquisition request signal conflicts. A multiprocessor system according to any one of the preceding claims. 5. The priority determination circuit includes: a determination count storage unit that stores a transmission count of the bus acquisition response signal corresponding to a processor; and a priority determination unit that determines a priority of the bus acquisition request signal according to the transmission count stored in the determination count storage unit. 4. The multiprocessor system according to claim 1, further comprising: a priority determining unit that changes the order. 6. The data processing apparatus according to claim 1, wherein the priority determination circuit includes a data analysis unit that analyzes data stored in the reception data buffer and changes a priority in the priority determination unit. A multiprocessor system according to any one of claims 1 to 5. 7. The memory control unit has a configuration in which a processor to which occupancy has been granted occupies the shared memory by transmitting / receiving an exclusive control message and accesses the shared memory via the data buffer selector. 3. The multiprocessor system according to claim 1, wherein: 8. The processor according to claim 1, wherein said memory controller occupies said shared memory by a processor to which occupancy has been granted according to a mark state and a space state of data transmitted and received via said bus corresponding to said processor.
3. The multiprocessor system according to claim 1, further comprising a configuration for accessing said shared memory via a selector. 9. A multiprocessor system in which a serial-parallel converter connected to a plurality of processors and a serial-parallel converter of a memory controller connected to a shared memory are connected by a bus for transferring serial data. A multi-function device comprising: a multi-function device configured to judge an abnormal portion in accordance with an error detection and monitoring time elapse with respect to a command and a response transmitted and received between the processor and the shared memory and between the processors. Processor system.