JP2001222467A - Cache device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the quantity of data transfer between a main memory and a cache memory and to reduce overhead due to the use of an external bus when registers are continuously retreated/restored to/from a stack area in a microprocessor loaded with a cache mechanism. SOLUTION: When the registers are continuously retreated to the stack, a memory control device writes data from a processor core to the cache memory without executing refilling processing from the main memory to the cache memory. When the registers are continuously restored from the stack, the memory control device forcibly clears a dirty bit on a hit cache entry simultaneously with the reading of data from the cache memory by the processor core. Consequently, the retreating/restoring processing of registers to/from the stack area can be accelerated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a microprocessor having a cache mechanism, and more particularly to a cache device for implementing a memory control method suitable for accessing a memory in a stack area.

[0002]

2. Description of the Related Art Usually, instructions to be executed by a processor are stored in a main memory, and when a program is run or executed on the processor, the instructions are called from the main memory, sent to the processor, and executed there. . This process consumes valuable time.

It is known that providing a processor with cache memory for use in the processor is one way to efficiently increase the instruction execution speed of the processor. Such a cache memory is a relatively small memory as compared with the size of the main memory. However, by using a memory whose access time is much faster than that of the main memory as the cache memory, relatively quick access to the most frequently used instructions and data can be realized. In a typical microprocessor, the main memory is inexpensive but relatively slow DRAM
Thus, the cache memory is formed of an expensive but high-speed SRAM.

[0004] The main principle of operation of the cache is that when the microprocessor calls instructions and data from main memory for execution, they are also stored in the cache memory. This allows the microprocessor to quickly retrieve the information from the fast cache memory instead of retrieving the information from the slower main memory for subsequent accesses if the microprocessor needs relatively recently referenced instructions and data. Can be.

[0005] In the cache memory, there is a tag address area as information for storing which data in the main memory is cached data stored therein. A tag address exists for each cache entry. The microprocessor requests an instruction or data in the form of an address, and the cache circuit determines a cache hit or a cache miss by comparing the address value requested by the microprocessor with all tag address values in the cache memory. .

If a cache hit occurs, the microprocessor can retrieve information directly from the cache memory. On the other hand, if a cache miss occurs,
The cache circuit must generate a memory cycle to the main memory to obtain the necessary data information. During this memory cycle to the main memory, the microprocessor is in a wait state, consuming valuable time. Further, if a cache miss occurs, the data currently stored in the cache memory must be written back to the main memory and the area must be vacated for the next information to be cached. This process also consumes valuable time between memory cycles to the main memory.

[0007]

Consider a case in which a plurality of registers are successively pushed to a stack area in a microprocessor equipped with the above-described cache mechanism. Assume that the register length of the microprocessor is 32 bits (for 4 bytes), the line size of the cache is 16 bytes, and the registers to be pushed onto the stack are R0 to R3.
(16 bytes). Consider the case where all four registers are pushed onto the stack under this condition.

First, the microprocessor generates a request to write the value of the first register R0 to the stack area of the memory. If a cache miss occurs here, the tag entry to be refilled is specified, and the cache information already there is written back to the main memory according to the state of the dirty bit. Next, of the stack area on the main memory, an amount corresponding to the cache line size of 16 bytes is transferred to the cache memory (refill).
After that, the value of the R0 register is written in the cache memory.

Next, the microprocessor follows R1 to R3.
Generate a request to sequentially write registers to memory. Here, since the cache always hits by the refill operation described above, R1 to R1 can be accessed without accessing the main memory.
The value of the R3 register is sequentially written on the cache.

By the above processing, the values of the registers R0 to R3 are all written in the cache memory, and the writing operation for 16 bytes has been performed. However, the acquired 16-byte information of the main memory has been completely overwritten by the refill operation that has occurred when the first R0 register is written. Therefore, useless memory access time is consumed at the time of refile.

The same applies to the case where values are successively popped from the stack area to a plurality of registers. Here, if the cache hits, the microprocessor can easily pop the register values of R0 to R3. However, since the write operation is performed at the time of the push, the dirty bit of the tag that has hit the cache may be set. If the dirty bit remains set, a write-back operation to the main memory will be performed when the cache information is purged in the future. However, the information on the already popped stack is already unused data, so there is no need to write back. By writing back this data information, wasteful time is consumed.

Accordingly, one object of the present invention is to propose a cache device having a memory control means for performing a continuous high-speed push operation of a plurality of registers to a stack area in a microprocessor having a cache mechanism. It is. Another object of the present invention is to provide a cache device having a memory control means for performing a continuous pop operation of a plurality of registers from a stack area at a high speed.

[0013]

The invention of claim 1 of the present application is directed to a microprocessor, a cache memory coupled to the microprocessor, a memory control device coupled to the microprocessor, and an external controller coupled to the microprocessor. Memory, the memory control device performs a refill operation from the external memory to the cache memory even when a write request from the microprocessor to the external memory occurs and a cache mismatch occurs at that time. A control means for realizing a write operation from the microprocessor to the cache memory without performing the operation is provided.

[0014] The invention of claim 2 of the present application includes a microprocessor, a cache memory coupled to the microprocessor, a memory control device coupled to the microprocessor, and an external memory coupled to the microprocessor. When the microprocessor issues a read request from the external memory and the cache is adapted at that time, the memory controller performs a read operation from the cache memory to the microprocessor, and simultaneously executes a read operation on the adapted cache entry. And a control means for forcibly resetting the dirty bit in the above.

According to a third aspect of the present invention, in the cache device of the first aspect, the microprocessor refills the memory control device when a plurality of registers are continuously pushed to a stack area. By outputting a control signal for preventing operation, push processing of a plurality of registers is performed at high speed.

According to a fourth aspect of the present invention, in the cache device according to the third aspect, when the microprocessor continuously pushes a plurality of registers to a stack area, the current value of the stack pointer is set to the value of the current stack pointer. When the value does not match the line size boundary of the cache memory, by raising the stack pointer by an appropriate amount, the value of the stack pointer is automatically adjusted to the line size boundary.

According to a fifth aspect of the present invention, in the cache device according to the fourth aspect, when the microprocessor continuously pushes a plurality of registers to the stack area, the microprocessor is arranged at a line size boundary of the cache memory. The value of the stack pointer before matching is pushed to the stack area together with other registers.

According to a sixth aspect of the present invention, in the cache device according to the second aspect, when the microprocessor successively pops a plurality of registers from a stack area, the microprocessor reads data from the cache memory, By outputting a control signal for forcibly resetting a dirty bit of an appropriate cache entry to the memory control device, writing from the cache memory to the external memory which may occur in the future may be performed. The back operation is not performed.

According to a seventh aspect of the present invention, in the cache device of the sixth aspect, when the plurality of registers are successively popped from a stack area, the microprocessor has a stack having a value stored when the register is pushed. By popping the pointer value together with another register, the stack pointer value before being aligned with the line size boundary of the cache memory is restored.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a configuration of a cache device according to an embodiment of the present invention. The cache device includes a processor core 101 of a microprocessor, a cache circuit 102, a bus control unit 103, and a main memory 104. The processor core 101 is connected to a cache circuit 102 and a bus control unit 103 via an address bus and a data bus. Further, the processor core 101 outputs two control signals, NORFL and CLRDT, which are input to the cache circuit 102. The former NORFL signal is a control signal for preventing refilling from the main memory 104 to the cache memory even if a cache miss occurs. The latter CLR
The DT signal is transmitted from the processor core 101 to the cache circuit 1.
02 is a control signal for resetting a dirty bit (refer to FIG. 3) on a corresponding cache entry when data is acquired from 02. The bus control unit 103 accesses the main memory 104 according to a request from the processor core 101 or the cache circuit 102, and
Is provided to the processor core 101 or the cache circuit 102. The processor core 101 has a built-in register array 105, and the register array 10
Reference numeral 5 includes general-purpose registers R0, R1, R2, and R3, a processor status word PSW, a stack pointer SP, a program counter PC, and a temporary register tmp.

The cache circuit 102 comprises a cache memory and a memory control device, and FIG. 2 shows the internal configuration thereof. The role of the address value on the address bus is determined in bit units as shown by the address field 201. The lower bit is connected to the cache memory array 202 as a word select signal, and the middle bit is connected as an index select signal. The upper bits are input to the tag address comparator 203 and compared with the address tag value in the cache memory output from the cache memory array 202 to determine whether the cache has hit or missed. If the cache hits here, at least one of the tag address comparators 203 asserts, and its signal is output to the data selector 205.
, And at the same time, the cache data input from the cache memory array 202 is selected, and the information of the hit cache is placed on the data bus. On the other hand, if the cache misses, all the outputs of the tag address comparator 203 become inactive, and this output is accepted by the cache control unit 204. When the cache control unit 204 receives the cache miss, the cache control unit 204
, And registers the obtained data in the cache memory array 202. Next, the registered data is put on the data bus via the data selector 205.

FIG. 3 shows the internal configuration of the cache memory array 202. The figure shows a 4-way set associative cache configuration having a capacity of 4 Kbytes. The tag memory 301 has 64 entries, each entry being a tag address field ADDR-TAG storing 31 to 10 bits (22 bits) of a data address, a valid bit (V) indicating whether or not the entry is valid,
It consists of a dirty bit (D) indicating that the entry has been written. The data memory holds data in units of 16 bytes, and the data memory per way is 1 Kbyte, that is, 4 Kbytes in total. The line size of the data memory is 16 bytes, and the number of entries is 64.
Data transfer from the main memory 104 to the cache memory array 202 is performed in units of 16 bytes (128 bits).
Is transferred in 32-bit units. The write-back buffer includes a tag write-back buffer 303 and a data write-back buffer 304, and is used to temporarily hold the data in the cache memory array 202 when the data is written back to the main memory 104. .

Next, the operation of the microprocessor according to the embodiment will be described with reference to FIG. First, the stack memory image is in the state shown at 401, and the stack pointer SP points to 0x2818. In this state, the microprocessor executes an instruction to continuously save all registers. The following is an assembler instruction for sequentially storing the registers R0, R1, R2, R3, and PSW in the area indicated by the SP. push [r0, r1, r2, r3, psw] At this time, the microprocessor according to the present embodiment 1) Stores the value of the SP register in the tmp register. 2) Raise the SP value to the boundary of the cache circuit line size (16 bytes). 3) Activate the NORFL control signal. 4) Store the value of the tmp register in the area pointed to by the SP,
Execute P ← SP-4. 5) Subsequently, the data is stored in the area indicated by the SP in the order of R0, R1, R2, R3, and PSW registers. At this time, SP ← SP-4 is executed every time one register is stored. 6) The push command is executed in a sequence of returning the NORFL control signal activated in 3) to an inactive state.

1) only transfers data from the SP register to the tmp register inside the processor core.
The reason 2) is to write the data from the end of the cache entry (the position of W3 in the diagram shown in the data memory 302) by elevating the SP value to the line size of the cache circuit. Specifically, S
The level is raised from the state of P = 0x2818 to SP = 0x2810.
3) asserts the NORFL control signal so as not to perform the refill process from the main memory 104 to the cache memory 202 during execution of the push instruction. In 4), the value of tmp = 0x2818 is saved on the stack. At this time, the cache is determined inside the cache circuit 102.

Here, if a cache miss occurs, L
The entry number of the cache to be purged is determined by the RU logic, and the address tag information and data information of the entry are written in the write-back buffers 303 and 304.
Is stored temporarily. Next, since the NORFL signal has already been asserted, the refill processing is not performed, and the value 0x2818 of the tmp register is overwritten in the data memory of the entry purged earlier. At this time, the address tag area is newly overwritten.

On the other hand, if the cache hits in 4), the register value tmp = 0x2818 is directly overwritten on the data memory of the cache entry hit.
In 5), following 4), the values of the remaining registers are sequentially stored. Even if a cache miss described in 4) occurs during this process, the refill processing is not performed in the same manner as in 4). Finally, in 6), NOR activated in 3)
The FL control signal is returned to the inactive state. 4)
Since the external bus is open while the register value is overwritten on the cache memory in (5) and (5), the cache control unit 204 transfers the data in the data write back buffer 304 to the tag write back buffer 30.
A request is made to the bus control unit 103 to perform a write-back process to the address position on the main memory indicated by No.3. In this way, the process of refilling the cache memory 202 from the main memory 104 can be omitted, the execution cycle of the push instruction is reduced, and the register can be saved at high speed. A memory image 402 of the stack frame after the registers are finally saved is shown in 402.

Next, a case where a plurality of registers are successively popped from the stack will be described. First, the memory image of the stack frame is in the state shown at 402. At this time, the stack pointer SP points to 0x27F8. In this state, the microprocessor executes an instruction to continuously restore all registers. Below are the registers PSW, R3, R
2, an assembler instruction for sequentially extracting R1, R0, and SP from the area indicated by the current SP. pop [r0, r1, r2, r3, psw] At this time, the microprocessor of the present embodiment: 1) Activates the CLRDT control signal. 2) reading the value of the PSW register from the area indicated by SP,
Execute SP ← SP + 4. 3) Then, read from the area indicated by SP in the order of R3, R2, R1, R0, and SP register. At this time, SP ← SP + 4 is executed each time one register is read. 4) Return the CLRDT control signal activated in 1) to the inactive state. The above-mentioned pop instruction is executed in the sequence. 1) The tag memory 301 of the cache after executing this pop instruction
This is for resetting the dirty bit D of the corresponding entry above. 2) reads out the value of the PSW stacked on the stack and reads out the PSW register 105 in the processor core
To be stored. At this time, the cache is determined inside the cache circuit 102. Here, when a cache miss occurs, the cache entry number to be purged is determined by the LRU logic, and the address tag information and data information of the entry are stored in the write-back buffer 3.
03 and 304 are temporarily stored. Next, NORFL
Since the signal is not particularly asserted, necessary information is fetched from the main memory 104 to the cache memory 202 (refill processing).

On the other hand, when the cache hits or after the previous refill processing is completed, the cache memory 20
2 is loaded on the data bus via the data selector 205 and transmitted to the processor core 101 by the PSW.
The contents of the SW are passed. In 3), following 2), the values of the remaining registers R3, R2, R1, R0, and SP are sequentially fetched from the cache memory 202. In the case where a cache miss occurs during this process, the main memory 104 is used in the same manner as in 2).
From the cache memory 202 is performed. When data is extracted from the cache memory 202 to the processor core 101 in 2) and 3), the extracted data information is stored in the data memory 302 of the cache.
In the case of the word data corresponding to W3, the register information on the cache entry has already been taken into the register array 105 in the processor core 101. At this time, since the CLRDT signal is asserted, the dirty bit D on the address tag field of the corresponding cache entry is cleared. This prevents write-back from occurring when the cache entry is purged in the future. Speaking of this pop instruction, when the R3 and SP registers are read from the cache memory 202, the dirty bit D is cleared. Finally, in 4), CLRDT activated in 1)
Return control signal to inactive state.

By performing the above-described pop processing, the processing of writing back from the cache memory 202 to the main memory 104 can be reduced as much as possible, the execution cycle of the pop instruction can be reduced, and high-speed register return can be performed. It becomes possible. The memory image of the stack frame after the register is finally restored is as shown at 401.

While only certain preferred features of the invention have been illustrated, many modifications and changes may be made.
It is therefore intended that the appended claims cover all such modifications and changes as fall within the true spirit of the invention.

For example, although the detailed operation sequence of the push instruction has been described above, the addition and subtraction processing of the stack pointer SP is not performed every time the register is saved, but after the stack frame necessary for saving the register is secured in advance, the S
Processing for saving the register relative to P may be performed. Also in the case of the pop instruction, all necessary register restoration may be performed in advance similarly to the push instruction, and then the stack frame may be deleted at the end. Furthermore, CL
Regarding the RDT control signal, in the above example of the pop instruction,
During the execution of the pop instruction, the CLRDT signal is always asserted, and whether or not the dirty bit of the cache entry is actually cleared is determined by the cache circuit 102.
Is judged inside. However, this determination is made inside the processor core 101, and the CLRDT signal is asserted only when the dirty bit needs to be cleared. The cache circuit 102 is configured to always clear the dirty bit if the CLRDT signal is active. This also means that the cache device falls under the claims of the present invention.

[0032]

The invention of claims 1, 3, 4 and 5 of the present application is
In a microprocessor system equipped with a cache mechanism, when continuously saving the values of a plurality of registers in the stack area, the data transfer between the cache memory and the main memory is reduced, and the registers are stored at a higher speed. The effect is obtained that the cache device can be provided with a memory control device that realizes the save processing.

According to the second, sixth, and seventh aspects of the present invention, in a microprocessor system equipped with a cache mechanism, when the values of a plurality of registers are successively returned from a stack area, the cache memory and the main memory are used. In this case, it is possible to obtain a cache device having a memory control device that can reduce the data transfer during the period and realize the register restoration process at a higher speed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a cache device according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating an internal configuration of a cache circuit according to the embodiment;

FIG. 3 is a block diagram showing an internal configuration of a cache memory array according to the embodiment.

FIG. 4 is a memory image diagram of a stack area in the embodiment.

[Explanation of symbols]

 101 processor core 102 cache circuit 103 bus control unit 104 main memory 105 register array 201 address field 202 cache memory array 203 tag address comparator 204 cache control unit 205 data selector 301 tag memory 302 data memory 303 tag write back buffer 304 data write back Buffer 401 Stack area memory image before saving registers 402 Stack area memory image after saving registers R0 to R3 General purpose registers PSW Processor status word PC Program counter SP Stack pointer tmp Temporary register NORFL Refill processing suppression control signal CLRDT Dirty bit clear control signal TAG address tag field NDEX address index field WS word select field D dirty bit V valid bit

Claims (7)

[Claims] A microprocessor; a cache memory coupled to the microprocessor; a memory controller coupled to the microprocessor; and an external memory coupled to the microprocessor. Even if a write request from the processor to the external memory occurs and a cache mismatch occurs at that time, the microprocessor does not perform a refill operation from the external memory to the cache memory. A cache device including control means for realizing a write operation. 2. A microprocessor, comprising: a microprocessor; a cache memory coupled to the microprocessor; a memory controller coupled to the microprocessor; and an external memory coupled to the microprocessor. If the processor issues a read request from the external memory and the cache is matched at that time, the processor performs a read operation from the cache memory to the microprocessor and simultaneously forcibly removes the dirty bit on the matched cache entry. And a control unit for resetting the cache. 3. The microprocessor outputs a control signal for preventing a refill operation from being performed to the memory control device when a plurality of registers are continuously pushed to a stack area. 2. The cache device according to claim 1, wherein a plurality of registers are pushed at a high speed. 4. The microprocessor according to claim 1, wherein the plurality of registers are successively pushed to a stack area, and when a current value of the stack pointer does not match a line size boundary of the cache memory, the stack pointer is updated. 4. The cache device according to claim 3, wherein the value of the stack pointer is automatically adjusted to the line size boundary by raising the level by an appropriate amount. 5. The microprocessor according to claim 1, wherein, when a plurality of registers are continuously pushed to a stack area, a value of a stack pointer before being aligned with a line size boundary of the cache memory is stored in the stack area together with other registers. 5. The cache device according to claim 4, wherein said data is pushed to said cache device. 6. The microprocessor reads data from the cache memory and pops a dirty bit of a cache entry suitable for the memory controller when populating a plurality of registers from a stack area continuously. A control signal for forcibly resetting the cache memory to prevent a write-back operation from the cache memory to the external memory which may occur in the future. 2. The cache device according to 2. 7. The cache memory according to claim 1, wherein, when successively popping a plurality of registers from a stack area, the microprocessor pops a stack pointer value having a value stored at the time of pushing together with other registers, to thereby execute the cache memory. 7. The cache device according to claim 6, wherein the stack pointer value before the line size boundary is restored is restored.