JP2001211110A - Digital satellite broadcast receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital satellite broadcast receiver which can quickly perform resynchronization when a site is switched. SOLUTION: A superframe which is a previously set number of superframes after the indication of site diversity execution is detected and dummy data in a frame having the dummy data in its final slot in the detected superframe are detected, and data of an 8PSK modulated signal are received for carrier regeneration in a frame-synchronous pattern section in the frame right after the detected dummy data, the phase is made absolute in the frame-synchronous pattern section, and after carrier regeneration is performed while a digital filter 9 is set to a gain for fast acquisition, the digital filter 9 is set to the gain normal reception.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a digital satellite broadcast receiver, and more particularly, to a digital satellite broadcast receiver for receiving a broadcast based on site diversity.

[0002]

2. Description of the Related Art In digital satellite broadcasting, when it is expected that it is impossible to secure a line around one of the operating uplink broadcasting stations due to rain or the like, site diversity is switched to operation by another uplink broadcasting station. Is adopted. In this site diversity, it is desirable to minimize the influence of switching between uplink broadcasting stations, such as interruption of video and audio, as much as possible.

[0003] In this specification, switching from one operating uplink broadcasting station to operating by another uplink broadcasting station is referred to as site switching.

In view of the above, the site diversity method proposed in digital satellite broadcasting uses a freeze and a digital satellite broadcast receiver which are generated at the time of site switching so as to minimize interruption of video and audio due to switching. In order to make the mute as inconspicuous as possible, it has been proposed to switch the site within a superframe.

Specifically, using the extended area (1 to 4 bits) shown in FIG. 5A in the transmission / reception control information in the TMCC information, a bit of a site diversity execution superframe instruction is set in bit 4 thereof. (Bit 4 =
1) After the bit is set, N is set as shown in FIG.
(N = 16) Site diversity is performed in the superframe after the superframe, and after the site diversity is performed, bit 4 is set in the M (M = 0) superframe.
(Bit 4 = 0).

In order to cope with the site diversity described above, the demodulation section of the digital satellite broadcast receiver, as shown in FIG. 6, carries out a carrier reproduction phase corresponding to the modulation scheme based on the modulation scheme identification signals (A1, A0). According to the carrier reproduction phase error table selected from the error table 8,
A phase error voltage based on a reception phase error with respect to the detected baseband signal is obtained, the phase error voltage is supplied to a carrier filter 9A composed of a digital filter, and an output from the carrier filter 9A is supplied to an AFC circuit 10 for cumulative addition. The oscillation frequency of the numerically controlled oscillator 11 is controlled by the cumulative addition value, the output from the numerically controlled oscillator 11 is supplied to the arithmetic circuit 1 as a reproduction carrier, and the quasi-synchronous detected signal input to the reproduction carrier and the arithmetic circuit 1 Is multiplied by the baseband signals I and Q to demodulate the quasi-synchronous detection output.

The detection output output from the arithmetic circuit 1 is band-limited by the roll-off filter 2, and the frame synchronization pattern W1 is detected in the frame synchronization circuit 31 from the band-limited detection output to extract TMCC information. T
The MCC information is supplied to the TMCC decoder 32 for decoding, the extracted TMCC information is supplied to the site diversity control circuit 33, and the site diversity control circuit 33 issues a site diversity execution instruction based on bit 4 in the extension area. Detect whether or not it has been done.

When it is detected that a site diversity execution instruction has been issued, the site diversity control circuit 33
In step (2), every time a superframe is detected, the N value is counted down. When the N value reaches 0, that is, when the superframe reaches N = 0, an execution instruction signal is supplied to the frame synchronization circuit 31. The received frame synchronization circuit 31 performs detection until the frame synchronization pattern W1 is detected in accordance with the execution instruction signal, and when detected, performs resynchronization using the frame synchronization pattern W1.

[0009]

However, according to the above-described proposed site diversity method, site switching is performed somewhere in the superframe, and site switching is performed anywhere in the superframe. There is a problem that it is unclear whether the process is performed.

[0010] Further, at the time when the site is switched, a shift in the carrier frequency and a shift in the clock phase between the main station and the sub-station are assumed, and a shift in the frame period, for example, a shift of about 5 msec before and after the switching. This shift causes a problem that the video is disturbed and the sound is interrupted.

According to this method, the switching of the site is switched somewhere in the superframe. At the moment of the switching, the carrier frequency, clock phase,
When the frame cycle is shifted, the system lock is once released in the digital satellite broadcast receiver, and resynchronization must be performed. Since the location in the superframe at which switching is performed is undefined within one superframe, resynchronization is performed at least in the next superframe by performing a system lock, which is the shortest period.

Therefore, the data in the superframe at the moment when the site is switched cannot be reproduced, and for example, an error occurs in the video data in the digital satellite broadcast receiver, the video is disturbed, and the sound is interrupted. A point occurs.

[0013] It is an object of the present invention to provide a digital satellite broadcast receiver capable of resynchronizing quickly when switching sites.

[0014]

A digital satellite broadcast receiver according to claim 1 of the present invention detects a predetermined number of superframes after a site diversity execution instruction, and detects the last slot in the detected superframe. Is a dummy data in a frame in which the dummy data is detected, and an 8PSK modulated signal is received for carrier reproduction in a frame synchronization pattern section in a frame immediately after the detected dummy data, and absolute phase conversion is performed in the frame synchronization pattern section. And performing the carrier regeneration by setting the loop gain of the carrier regeneration loop to the gain for high-speed acquisition, and then setting the loop gain of the carrier regeneration loop to the gain for normal reception.

According to the digital satellite broadcast receiver of the first aspect of the present invention, the 8PSK modulation method is received for carrier reproduction in the frame synchronization pattern section following the dummy data in which the site is switched, and the carrier reproduction loop is performed. Since the loop gain is set to the gain for high-speed acquisition, carrier regeneration is performed quickly, synchronization is achieved by the frame synchronization pattern following the dummy data where site switching is performed, and resynchronization is performed at the shortest time. As a result, no error occurs in the video data, the video is not disturbed, and no sound is cut off.

A digital satellite broadcast receiver according to a second aspect of the present invention is the digital satellite broadcast receiver according to the first aspect, in which the gain of the carrier reproduction loop is set to the TMCC information from the time when the gain for the normal reception is set. It is characterized in that a modulated signal based on a receiving method is received for each receiving method.

According to the digital satellite broadcasting receiver of the second aspect of the present invention, the reception of the modulated signal based on the TMCC information according to the receiving system from when the gain of the carrier reproduction loop is set to the gain at the time of normal reception, That is, the state is returned to the normal reception state.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A digital satellite broadcast receiver according to the present invention will be described below with reference to embodiments.

FIG. 1 is a block diagram showing a configuration of a demodulation unit of a digital satellite broadcast receiver according to one embodiment of the present invention.

Prior to the description of a digital satellite broadcast receiver according to an embodiment of the present invention, switching of sites proposed by the applicant will be described.

FIG. 3A is a schematic diagram showing the configuration of one superframe in digital satellite broadcasting.

In the hierarchical broadcasting system, one super frame is composed of eight frames as shown in FIG. 3A, and each frame has a frame synchronization pattern W1 and a TMCC (transmission multiplex) as shown in FIG. 3B. Configuration control) information, a frame identification synchronization pattern W2 or W3 for identifying whether the frame is the first frame in a superframe, a main signal,
It is composed of a reference burst signal, a main signal, a burst signal,..., A main signal, and a burst signal. The first frame in the superframe has a synchronization pattern W for frame identification.
2 and 2 to 8 frames use the frame identification synchronization pattern W3. FIG. 3B shows the second frame.

The main signal is a modulation method trellis code 8PS.
K, QPSK or BPSK, the frame synchronization pattern W1, the frame identification synchronization patterns W2, W3, T
The MCC information and the reference burst signal are BPSK,
The frame synchronization pattern W1, the frame identification synchronization patterns W2 and W3 each have 32 symbols (including 20 fixed-bit symbols), the TMCC information has 128 symbols, the main signal has 203 symbols, and the burst has 4 symbols. One frame is composed of 39936 symbols.

In one embodiment of the present invention, when it is desired to switch the uplink broadcast station, a bit is set in bit 4 of the extension area shown in FIG. Site switching is performed during the superframe when the superframe is counted 16 times from when the bit is set, that is, when the site switching execution instruction signal is received.

The switching of the site in the superframe is performed by detecting a frame whose last slot is dummy data from the superframe in which the site switching is performed, and detecting the last slot of the frame in which the last slot is detected as dummy data. In the transmission / reception control information in the TMCC information, bit 3 of the extension area indicated by (xxx) in FIG.
, The frame in which the site has been switched is included in the TMCC information by using the three bits of bit 1 to indicate the frame in which the site has been switched.

In this case, the information of the frame in which the site has been switched is replaced by bits 1 to 3 of the extension area shown in FIG. 3 in the transmission / reception control information in the TMCC information. May be included in the TMCC information by using 3 bits in the extension area of.

On the other hand, the transmission method (coding rate) and the number of effective slots / the number of transmission slots in the hierarchical transmission are shown in FIG.
As shown in FIG. Here, the transmission slot is the minimum number of slots for transmission, and the effective slot indicates the number of slots that can transmit information among the transmission slots.

As apparent from FIG. 4A, for example,
TC8PS from slot number 1 to slot number 46
For transmission of a K-modulated signal, slot number 4
7 is for the transmission of a QPSK (1/2) modulated signal, as shown in FIG. 4B, where slot numbers 1 to 44 are for the transmission of a TC8PSK modulated signal, When the slot number 45 to the slot number 48 are for the transmission of the BPSK (1/2) modulated signal, as shown in FIG. 4C, the slot number 1 to the slot number 44 are for the transmission of the TC8PSK modulated signal. When the slot numbers 45 to 46 and the slot numbers 47 to 48 are for transmission of a QPSK (1/2) modulated signal, the situation is as shown in FIG.

When the slot numbers 1 to 48 are TC8PSK modulated signals, the last slot is the slot number 48, and FIG. 4 (b), FIG. 4 (c), and FIG.
4D, the last slot is the slot number 47 in FIG. 4B, the slot number 45 in FIG. 4C, and the slot number 47 in FIG. 4D. . When the last slot is dummy data, that is, when all are TC8PSK modulated signals, a frame including the slot number 48 which is dummy data is detected, and the site is switched in the last slot of the frame, and FIG. 4), a frame including the slot number 47 is detected, and the site is switched in the last slot of the frame. In FIG. 4C, a frame including the slot number 45 is detected, and In the last slot, the site is switched, and FIG.
In the case of (d), the frame including the slot number 47 is detected, and the site is switched in the last slot of the frame.

Returning to the demodulation section of the digital satellite broadcast receiver shown in FIG. 1, the description will be continued.

In the demodulation unit of the digital satellite broadcast receiver shown in FIG. 1, the orthogonal reproduction carriers output from the numerically controlled oscillator 11 are converted into the baseband signals I and Q by the arithmetic circuit 1.
, And the baseband signals I and Q are demodulated. The demodulated baseband signals I and Q are supplied to a roll-off filter 2 and band-limited.

The baseband signals I and Q band-limited by the roll-off filter 2 are supplied to an absolute phase calculation circuit 6 and a remapper circuit 7. The absolute phase calculation circuit 6 obtains a phase difference signal based on the difference between the signal point arrangement of the baseband signals I and Q based on the reception phase of the frame synchronization pattern W1 and that on the transmission side, and the remapper circuit 7 uses the absolute phase calculation circuit 6 The signal point arrangement of the baseband signals I and Q is rotated by the remapper circuit 7 in response to the phase difference signal obtained by Is made identical to that of The baseband signals I and Q via the remapper circuit 7 are supplied to a carrier reproduction phase error table 8.

On the other hand, the baseband signals I and Q band-limited by the roll-off filter 2 are supplied to a frame synchronization detection circuit 3, and the frame synchronization detection circuit 3 detects a frame synchronization pattern W1. When it is determined that the synchronization with the pattern W1 has been achieved, the signals A1 and A0 shown in FIGS. 3C and 3D generated from the TMCC information are output from the absolute phase calculation circuit 6 and the carrier reproduction phase. It is sent to the error table 8.

When the signals A1 and A0 are both at a low potential, the modulation method of the main signal is the 8PSK modulation method. When the signal A1 is at a low potential and the signal A0 is at a high potential, the modulation method of the main signal is used. Is a QPSK modulation system, and when the signal A1 is at a high potential and the signal A0 is at a low potential, the modulation method of the main signal is a BPSK modulation system, and when both the signals A1 and A0 are at a high potential, it is a burst signal. And is supplied to the absolute phase calculation circuit 6 and the carrier reproduction phase error table 8 as a modulation method identification signal of the main signal.

In the absolute phase calculation circuit 6 receiving the signals A1 and A0, a phase difference signal is obtained based on the reception phase of the frame synchronization pattern W1 and output to the remapper circuit 7,
In the remapper circuit 7, the baseband signals I and Q are rotated by an angle based on the phase difference signal so as to have the same phase as the transmitting side.

The baseband signals I and Q matched with the phase on the transmission side in the remapper circuit 7 are supplied to the carrier recovery phase error table 8. In the carrier reproduction phase error table 8, a phase error table corresponding to the modulation method identified based on the signals A1 and A0 is referred to,
A phase error voltage based on the phase error of the baseband signals I and Q is output from the carrier error phase error table 8 from the phase error table referred to based on the modulation method of the main signal.

The phase error voltage read from the carrier recovery phase error table 8 is supplied to an AFC circuit 10 via a digital filter 9 which forms a carrier recovery loop filter composed of a low-pass filter. The phase error voltages are taken out and passed through the digital filter 9 in the AFC circuit 10 to be sequentially cumulatively added.

The cumulative addition output at each addition point from the AFC circuit 10 is supplied to the numerically controlled oscillator 11, and the positive and negative sine wave data and the positive and negative cosine wave data of the frequency based on the cumulative addition value are output. Here, the oscillation frequency of the numerically controlled oscillator 11 is changed according to the output at the time of the cumulative addition, and carrier regeneration is performed. Here, it is similar to AFC in the sense that the oscillation frequency of the numerically controlled oscillator 11 is changed, and is described as an AFC circuit 10.

In the arithmetic circuit 1, the numerically controlled oscillator 11
Is output from the baseband signal I
, And the negative cosine wave data is multiplied by the baseband signal Q. The result of the multiplication is added and output as the baseband signal Q. Similarly, the positive cosine wave data is multiplied by the baseband signal I, and the negative sine wave data is multiplied by the baseband signal Q. The result of the multiplication is added and output as the baseband signal I. Thus, the signal is demodulated in the arithmetic circuit 1.

On the other hand, in the frame synchronization detecting circuit 3 which has received the baseband signals I and Q band-limited by the roll-off filter 2, the frame synchronization pattern W1 and the frame identification synchronization are obtained from the supplied baseband signals I and Q. Pattern W2 (W3) and TMCC information are detected. The detected TMCC information is sent to the TMCC decoder 4, where it is decoded and held.

When the TMCC decoder 4 detects that the site diversity execution instruction is given by the bit 4 in the extension area in the TMCC information, the site diversity control circuit 5 counts down the N value every time a super frame is detected, and sets the N value to N. When the super frame reaches = 0, an execution instruction signal is sent from the site diversity control circuit 5 to the frame synchronization detection circuit 3 and the digital filter 9.

In the frame synchronization detecting circuit 3 which has received the execution instruction signal from the site diversity control circuit 5, N =
During the period of the frame synchronization pattern W1 of the frame following the last dummy data of the predetermined frame of the superframe that has become 0, the modulation identification signal in the 8PSK modulation system is calculated by the absolute phase calculation circuit 6 and the carrier reproduction phase error table 8 To send to. In the digital filter 9 which has received the execution instruction signal from the site diversity control circuit 5, the digital filter 9 detects whether the frame synchronization pattern W1 of the frame following the last dummy data of the predetermined frame of the superframe in which N = 0 is detected. The setting is changed from a setting for maintaining synchronization to a parameter for high-speed acquisition such as increasing the loop gain.

Next, the operation of the digital satellite broadcast receiver according to the embodiment of the present invention will be described with reference to the flowchart of FIG.

In the normal reception state, it is detected for each superframe whether or not bit 4 is set in the extension area of the transmission / reception control information in the TMCC information, and it is checked whether or not a site switching instruction has been detected. (Step S1). When it is determined that a site switching instruction has been issued, the TMCC information is held if the TMCC information is normally received. At the time of normal reception, it is in a state of receiving normally, and the TMCC information is held.

If it is determined in step S1 that a site switching instruction has been issued, the position of a frame in which site diversity is performed is detected (step S1).
2) Count down for each detected frame,
It repeats from step S2 until the N value reaches N = 0, and waits until it reaches N = 0 (step S3).

The frame position where the site diversity is performed in step S3 is determined by the TMCC as described above.
Bit 3 to bit 1 in the transmission / reception control information in the information
Or the 3-bit information in the extension area in the extension information in the TMCC information, and is counted down to N = 0 each time this frame position in the super frame is detected.

If it is determined in step S3 that N = 0, in the last slot of the frame when N = 0, only the carrier reproduction is set to the 8PSK modulation signal receiving system, and the frame synchronization state is reset. Is performed (step S4).

Here, the reason for setting the receiving method of the 8PSK modulated signal is as follows. When performing site diversity, what is assumed for a modulated wave is a frequency shift and a phase shift. The frequency shift is determined by the performance of the transmission equipment, and is known to be within about 1 kHz. In contrast, the phase shift is undefined. However,
As for the demodulation operation of the demodulation section, considering the reproduction of the carrier within several tens of symbols, it is desirable to suppress the phase shift to a minimum and to quickly eliminate the frequency shift. For this reason, the phase shift can be minimized to a minimum by using the 8SK modulation signal having a large convergence point rather than receiving the BPSK modulation section as the BPSK modulation signal reception method. Therefore, in step S4, 8P
The SK modulation signal receiving method is set.

The reset of the frame synchronization state is performed in the frame synchronization detection circuit 3. In the frame synchronization detection circuit 3, a periodic frame synchronization pattern is confirmed during frame synchronization, but after the frame synchronization is reset, the synchronization pattern is detected.

In step S4, following the reset of the frame synchronization state, the loop parameters for carrier regeneration in the digital filter 9 are set for high-speed acquisition.
Normally, by increasing the gain of the digital filter 9, high-speed capturing, that is, high-speed locking is achieved. Next, it waits until the frame synchronization pattern W1 of the frame following the last dummy data of the frame detected in step S3 is detected (step S5).

In step S5, when the frame synchronization pattern W1 is detected, the section of the frame synchronization pattern W1 is subjected to absolute phasing (step S6). .
That is, the remaining TMCC section is set to the data reception method of the BPSK modulation method, the loop gain setting in the digital filter 9 is set from the setting for high-speed acquisition to the normal reception, and the carrier reproduction is performed according to the modulation method of the main signal. Changed to receiving.

The carrier reproduction is changed to the reception of the main signal according to the modulation scheme, and the normal reception state is set after the TMCC information is normally received. That is, the reception for each modulation scheme based on the TMCC information is performed from the time when the gain of the carrier reproduction loop is set to the gain for normal reception. It should be noted that whether or not the TMCC information has been normally received depends on the TMC
It is determined that the error correction by the Reed-Solomon error correction code as the outer code added to the C information has been normally completed.

As described above, according to the digital satellite broadcast receiver according to one embodiment of the present invention, information of a superframe in which a site is switched in TMSC information from TMCC information, and transmission / reception control in TMCC information From the frame information in the extended area in the information or the frame information in the extended area in the extended information, the number (0 to 7) of the frame to which the site is switched is obtained.

Since the frame synchronization pattern W1 always exists next to the 48th slot, which is the last slot of the frame, in response to the frame information at which the site switching is performed, resynchronization can be performed in the frame synchronization pattern W1. it can. Therefore, only the last slot of the frame in which the site is switched cannot be normally received, and the disturbance of the image and the interruption of the sound are minimized.

The dummy data is used for adjusting the rate variation caused by digitizing and compressing the video signal in a rate-fixed system such as digital satellite broadcasting. Even if it is not decoded correctly, it does not affect the decoding of the broadcast contents.

[0056]

As described above, according to the digital satellite broadcast receiver of the present invention, synchronization is established by the frame synchronization pattern following the last dummy data in the predetermined frame in the superframe in which the site is switched. As a result, resynchronization can be performed in the shortest time, and there is obtained an effect that the image is not disturbed and the sound is not interrupted.

Further, according to the digital satellite broadcast receiver of the present invention, carrier reproduction is started as the 8PSK modulated signal receiving method in the frame synchronization pattern section immediately after the switching of the site, and the frame synchronization pattern The absolute phase is determined in the section, and in the TMCC section immediately after that, carrier reproduction is performed as a normal BPSK modulation signal receiving method, so that the section having only 192 symbols of the frame synchronization pattern, the TMCC information and the frame identification synchronization pattern is used. Carrier reproduction (convergence operation to the receiving point) can be performed at high speed and stably.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a demodulation unit of a digital satellite broadcast receiver according to one embodiment of the present invention.

FIG. 2 is a flowchart illustrating an operation of a demodulation unit of the digital satellite broadcast receiver according to the embodiment of the present invention.

FIG. 3 is an explanatory diagram of super frames and frames in digital satellite broadcasting.

FIG. 4 is an explanatory diagram showing allocation of transmission systems and slots in digital satellite broadcasting.

FIG. 5 is an explanatory diagram of operation of a TMCC information section for site switching in digital satellite broadcasting.

FIG. 6 is a block diagram showing a configuration of a conventional digital satellite broadcast receiver.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 arithmetic circuit 2 roll-off filter 3 frame synchronization detection circuit 4 TMCC decoder 5 site diversity control circuit 6 absolute phase calculation circuit 7 remapper circuit 8 carrier recovery phase error table 9 digital filter 10 AFC circuit 11 numerically controlled oscillator

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Akihiro Horii 1-14-6 Dogenzaka, Shibuya-ku, Tokyo F-term in Kenwood Corporation (reference) 5C025 AA11 BA08 BA18 BA25 DA01 5C064 DA02 DA10 5K004 AA01 AA05 BA02 FA06 FA09 FJ00 5K059 CC01 CC04 DD01 EE01 EE02

Claims (2)

[Claims] 1. A superframe after a predetermined number of times after a site diversity execution instruction is detected, dummy data in a frame whose last slot is dummy data in the detected superframe is detected, and immediately after the detected dummy data. In the frame synchronization pattern section of the frame, the receiving system of the 8PSK modulation signal is used for carrier reproduction, the absolute phase is performed in the frame synchronization pattern section, and the loop gain of the carrier recovery loop is set to the gain for high-speed acquisition. A digital satellite broadcast receiver characterized in that after performing carrier reproduction, the loop gain of the carrier reproduction loop is set to the gain for normal reception. 2. The digital satellite broadcast receiver according to claim 1, wherein the reception of the modulated signal based on the TMCC information according to the receiving system is started when the gain of the carrier reproduction loop is set to the gain at the time of normal reception. Digital satellite broadcast receiver.