JP2001210685A - Test system and method of manufacturing semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten extremely long test time of a test in wafer stage using a prober, where individual semiconductor chips are tested sequentially in conventional IC inspection, in which inspection is made both in a wafer stage and in a packaged stage. SOLUTION: A test without using a tester can be made, by constructing test circuits on a probe card or on a wafer in which semiconductor chips to be tested are formed and by electrically connecting the test circuits respectively to the semiconductor chips to be tested for performing the test. In addition, by conducting test in wafer stage in an aging apparatus, it is possible to simplify or omit the test, after being packaged.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology effective when applied to a test of a semiconductor integrated circuit device and a manufacture of the semiconductor integrated circuit device, and more particularly to a technology effective when applied to a test at a wafer stage. is there.

[0002]

2. Description of the Related Art As a test method for a semiconductor device such as a logic integrated circuit (hereinafter, referred to as a logic IC), test pattern data is generated by a device called a tester, input to the logic IC, and output from the logic IC. A method of comparing the data signal with an expected value to make a determination has been common. There is also a BIST (Built in self test) type test technique in which a pattern generation circuit for generating a random test pattern such as a pseudo random number generation circuit is built in a semiconductor device.

In a test method in which test pattern data is externally input to a logic IC by a tester, a scan path designed in advance to operate as a shift register by connecting flip-flops provided in a semiconductor integrated circuit device is used. A shift scan method is provided in which test data is directly input to the back of the IC from the scan path or a test result is output to reduce the amount of test patterns.

In the BIST system, a tester function including a test pattern generation circuit, a test output compression circuit, a test result determination circuit, and the like is incorporated in a chip of a semiconductor integrated circuit device, and the test is performed by the semiconductor integrated circuit device itself. And a self-test that outputs the result.

[0005] The above-described logic IC test includes a probe test performed by bringing a probe into contact with a pad of a semiconductor chip at a wafer stage, and a test on a test board at a stage when the semiconductor chip is sealed in a package. The test has been performed in two stages of a burn-in test in which an IC is inserted into a provided socket. In the burn-in test, a plurality of ICs can be mounted on a test board and the test can be performed simultaneously.

As a well-known example which describes in detail a test method for a semiconductor integrated circuit device of this kind, there is known a method disclosed by Ohm Co., Ltd. on November 30, 1984.
There is a technology disclosed in the Institute of Electronics and Communication Engineers (ed.), "LSI Handbook" P165, P166,
This document describes the configuration of various scan path systems and the like.

[0007]

However, it has been found by the present inventors that the following problems arise in the test method of the semiconductor integrated circuit device as described above.

That is, the shift scan method and the BIST
In the method, it is necessary to form a circuit (scan path) and a test circuit constituting a test function inside the semiconductor integrated circuit device to be tested, so that the chip size becomes large and it is difficult to miniaturize the semiconductor integrated circuit device. Will be.

In addition, IC inspection is performed at the wafer stage and at the package stage, respectively. In a test using a prober at the wafer stage, it is difficult to simultaneously apply probes to the electrode pads of all chips on the wafer. Therefore, a method of sequentially measuring individual semiconductor chips is employed, but this significantly increases the test time. In addition, when semiconductor chips are tested one by one, there is a problem that the cost performance does not increase because the use efficiency of an expensive tester deteriorates, and the TAT (turn around time) is not shortened. In addition, the speed of operation and the increase in the number of pins associated with the miniaturization of semiconductor integrated circuit devices are rapidly progressing, and the usefulness of expensive testers is rapidly reduced. But it has increased further.

An object of the present invention is to provide a test technique capable of testing a semiconductor chip in a short time without using an expensive tester.

An object of the present invention is to provide a method of manufacturing a semiconductor integrated circuit device which can test a semiconductor integrated circuit device without using an expensive tester, thereby reducing the total cost required for the test. Is to do.

Another object of the present invention is to perform a high-precision test in a test at the wafer stage, thereby shortening the time required from the start of design to the completion of the semiconductor integrated circuit device. It is to provide a manufacturing method of.

Another object of the present invention is to provide a method of manufacturing a semiconductor integrated circuit device capable of performing a test efficiently while suppressing an increase in overhead of a test circuit in a semiconductor chip.

Still another object of the present invention is to provide a semiconductor integrated circuit device capable of performing a test of a semiconductor chip without using an expensive tester, and which does not affect the manufactured semiconductor integrated circuit device at all. It is to provide a manufacturing method of.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0016]

The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows.

That is, a test system according to the present invention includes a probe card having conductive needles formed in accordance with the arrangement of electrode pads of a semiconductor chip formed on a wafer, and a test card mounted on the probe card. The test circuit includes a test circuit that tests a semiconductor chip based on a program, and a control device that rewrites a test program in the test circuit and stores a test result output from the test circuit.

Further, according to the method of manufacturing a semiconductor integrated circuit device of the present invention, a plurality of semiconductor chips having desired functions are formed on a semiconductor wafer, and the semiconductor chips having a size corresponding to the wafer are formed. On a probe substrate formed with conductive needles in accordance with the arrangement of the electrode pads, a test circuit connected to the needles and operated according to a program to test the semiconductor chip is mounted. The semiconductor chip is superimposed on the wafer so as to be in contact with the corresponding electrode pad of the semiconductor chip, the semiconductor chip is tested by the test circuit, and a semiconductor chip determined as a non-defective product is selected as a product.

According to the above-described means, the test of the semiconductor chip on the wafer can be performed by the test circuit mounted on the probe substrate, so that the test can be performed without using an expensive tester. The required total cost can be reduced. In addition, since a highly accurate test can be performed in the test at the wafer stage, it is not necessary to perform the test again after packaging, or the test after packaging can be simplified. Thus, the time required from the start of the design to the completion of the semiconductor integrated circuit device can be reduced.

Preferably, a programmable logic IC (F) capable of configuring an arbitrary logic on the probe substrate is provided.
PGA) is provided corresponding to the semiconductor chip, the test circuit is configured in the programmable logic IC based on design data described in a hardware description language, and the semiconductor chip is tested by the test circuit. I do. As a result, the test circuit can be configured efficiently, and the test circuit suitable for another semiconductor chip can be reconfigured by rewriting the programmable logic IC, so that the probe substrate can be reused, and the total cost can be further reduced. Can be lowered.

Preferably, the test circuit further comprises:
A test signal generation circuit (ALPG) configured to generate a test signal supplied to a semiconductor chip to be tested according to a predetermined algorithm. by this,
A test circuit optimal for the semiconductor chip to be tested can be configured, and the test can be performed efficiently while suppressing an increase in overhead of the test circuit.

According to a second method of manufacturing a semiconductor integrated circuit device according to the present invention, a test circuit module which operates according to a program and tests the semiconductor chip is formed together with the semiconductor chip on a wafer on which the designed semiconductor chip is formed. Then, a power supply voltage is supplied from an external source to at least the test circuit module, the semiconductor chips on the same wafer are tested by the test circuit module, and a semiconductor chip determined to be non-defective is selected as a product. .

According to the above-described means, the test of the semiconductor chip can be performed at the wafer stage by the test circuit module formed on the wafer, so that the test can be performed without using an expensive tester, and at the wafer stage. In this test, a highly accurate test can be performed, so that the time required from the start of the design to the completion of the semiconductor integrated circuit device can be reduced.

Preferably, the connection between the test circuit module and the semiconductor chip to be tested is performed by a wiring formed in a scribe area of a wafer or a wiring layer dedicated to the test. Further, the test wiring for connecting the test circuit module to the semiconductor chip to be tested is formed so as to meander in the scribe area of the wafer. This makes it possible to simplify the configuration of the probe board,
The test wiring can be reliably cut during dicing, and the remaining wiring after cutting is minimized, thereby avoiding the adverse effect of the remaining wiring.

[0025]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is an explanatory diagram showing a first embodiment of a test system to which the present invention is applied, and FIG. 2 is an explanatory diagram showing an example of a mounting structure of a test IC in the test system of the first embodiment. It is.

In this embodiment, the test system 1
1 includes a probe card 2 having a size corresponding to the semiconductor wafer W and a control device 3 for controlling the probe card 2, as shown in FIG. In the probe card 2, a test IC 5 is provided on the insulating substrate 4 corresponding to each semiconductor chip CH on the semiconductor wafer W, and the test IC and each semiconductor chip CH are mounted on the lower surface of the insulating substrate 4. A needle 6 for electrical connection is provided, and the test IC 5 is configured to test each semiconductor chip CH. The control device 3
It controls writing of data to the test IC 5 and control of the test operation.

The insulating substrate 4 has the same size and shape as the semiconductor wafer W, and is provided on the surface opposite to the surface on which the test IC is provided, of each of the semiconductor chips CH formed on the semiconductor wafer W. Conductive needles 6 are arranged in accordance with the arrangement of the electrode pads. The needle 6 is formed on the entire surface of the insulating substrate 4 by a technique such as a microprobe. In addition, wiring and through holes are formed on the surface of the insulating substrate 4 and inside the substrate for connecting the terminals of the test IC 5 to the corresponding needles, which are formed by a printed wiring technique.

On the surface of the insulating substrate 4, test ICs 5 are mounted corresponding to the individual semiconductor chips CH on the wafer W. The test IC 5 is an FPGA (Field Progr
ammable Gate Array). FPG
A is currently available on the market with a size of 130K gates, but if it is not enough to construct a test circuit, a plurality of (three in FIG. 2) F
It is preferable to use a structure in which the PGAs 7 to 9 are stacked and mounted.

In this embodiment, the test IC 5
Generates a predetermined test pattern according to a predetermined algorithm including a microprogram written by the control device 3 based on tester construction data described in HDL (Hardware Description Language),
It is configured to make a test determination of the semiconductor chip CH. This test IC 5 is not a FPGA but a tester H
It may be a semiconductor device such as a microcomputer that can understand DL. In this case, the microcomputer mounted on the probe card 2 operates so as to supply a predetermined test pattern to the corresponding semiconductor chip CH by generating an output signal according to a microprogram given from the control device 3.

When the test IC 5 is composed of a plurality of FPGAs, any one of the FPGAs 7 to 9 may be an analog FPGA. This allows
Analysis tests such as DC measurement and analog waveform characteristic analysis can also be performed. For example, even if the semiconductor integrated circuit device to be tested is a mixed digital / analog type semiconductor integrated circuit device, the test can be performed efficiently. .

Next, the relationship between the test circuit constructed on the test IC 5 and the HDL description for constructing the test circuit will be described.

FIG. 3 is a conceptual diagram of a general tester. As shown in FIG. 3, the tester T includes a power supply unit 12 that supplies a power supply voltage to the semiconductor integrated circuit device TIC to be tested, a driver 14 that inputs a test signal to an input pin of the semiconductor integrated circuit device TIC, A comparator 15 for comparing a signal output from an output pin of the integrated circuit device TIC with an expected value signal, and a signal generator (a so-called test pattern) input to the semiconductor integrated circuit device TIC and a pattern generator 10 for generating an expected value signal
A timing generator 11 for generating an application timing of a signal input to the semiconductor integrated circuit device TIC; and a CPU 16 as a controller for controlling these circuits.
It is composed of

The CPU 16 reads a test program from an external storage device, interprets the test program using an OS (operating system), determines the generation of a test signal (a so-called test pattern), and performs a predetermined test. It is configured as follows. Further, the tester T includes a DC test circuit 13 for performing a DC test such as detection of a voltage level of an output pin of the semiconductor integrated circuit device TIC and an analog signal generating an analog waveform applied to an analog input terminal of the semiconductor integrated circuit device TIC. There may be provided a waveform generation unit, a waveform observation unit for observing the output waveform of the analog output terminal of the semiconductor integrated circuit device TIC, and the like. In FIG. 3, the illustration of the analog waveform generation unit and the waveform observation unit is omitted.

Conventionally, the functions of the blocks 10 to 16 of the tester T as shown in FIG. 3 and the function of the semiconductor integrated circuit device TIC to be tested are described in HDL, and the HDL description is hard-coded. A tool called a virtual tester that performs simulation and verification by a wear emulator is known.

HD input to hardware emulator
The L description can be generated by, for example, a function entry tool. The function entry tool is a support tool that supports creation of an HDL description sentence. The function entry tool includes a function of each block of the tester T expressed by a logical transition diagram, a flowchart, and the like on a screen of a computer display device, and a half to be tested. The function of the integrated circuit device TIC and H
Convert to DL description. As such a function entry tool, for example, EDA (Engineering Design Co., Ltd.) such as ATE Service Co., Ltd.
Automation) Vis provided by vendor
ual Test ”.

The virtual tester logically synthesizes the tester and the semiconductor integrated circuit device from the HDL description sentence generated by the function entry tool and mounts the tester on a hardware emulator to verify the simulation. By doing so, it is used as a tool that enables debugging of test programs in a short time. The present inventors have taken a step forward from such a virtual tester technique, and have conceived that a tester can be constructed in an FPGA from the description of HDL and a test of a semiconductor integrated circuit device can be performed in a wafer state using this tester. With this, the present invention has been developed.

In this embodiment, the HDL description sentence
When constructing a tester in A, an ALPG (Algo) that generates a test pattern in accordance with a known algorithm
rithmic Memory Pattern Generator). According to the verification by the present inventors, it has been found that the ALPG can be constructed with about several hundred K gates in terms of the number of logic gates, so that the ALPG can be constructed from several FPGAs as shown in FIG. It is quite possible to build in a semiconductor device.

Here, a specific procedure for constructing the ALPG in the FPGA will be briefly described. AL in FPGA
To construct a PG, it is necessary to first create data for constructing an ALPG.

In the creation of the ALPG construction data, first, the logical configuration of the semiconductor integrated circuit device to be tested and the test program used by the virtual tester are analyzed to generate a test pattern to be input to the semiconductor integrated circuit device to be tested. The most suitable algorithm is extracted to determine the type of ALPG to be constructed, that is, the schematic configuration (architecture). For example, depending on the semiconductor integrated circuit device to be tested, such as an ALPG that generates an address and data when the semiconductor device to be tested is a memory, and an ALPG that generates input data and expected value data when the semiconductor device is a logic LSI. The algorithm and the form of the ALPG that embodies it will be determined.

In general, existing testers can execute various required test items as much as possible so that a variety of newly developed semiconductor devices can be tested by one tester. The semiconductor device is designed to be compatible with a wide range of operating frequencies and the expected maximum number of pins in terms of the performance and the number of pins of the semiconductor device, and is provided as a highly versatile device. have. However, as in the present embodiment, the ALPG (test circuit) for only the semiconductor integrated circuit device to be tested requires a small-scale configuration, and can be built in several FPGAs.

Next, A having the determined architecture
The LPG is described in HDL. The description of the ALPG in HDL may be manually performed by a testing engineer.
This can be performed efficiently by using a function entry tool called “Test”.

Thereafter, an ALPG is constructed in the FPGA using the data described in the HDL. Note that FPGAs that can configure arbitrary logic are, for example, 130
K-gate scale one-chip LSI (model number EPF10K13
0E) is provided, and by using it, A
LPG can be constructed. As a support tool for configuring logic in an FPGA from an HDL description, for example, “MAX + p” provided by Altera
rusII ", which can be used automatically by a computer.

Next, a wafer test technique using the probe card 2 in the test system 1 of FIG. 1 will be described.

In this embodiment, the wafer test is performed at the time of wafer burn-in. First, the needle 6 of the probe card 2 is brought into contact with the electrode pad formed on each semiconductor chip CH on the semiconductor wafer W mounted on the wafer stage WS having the temperature control function,
The probe card 2 is pressed against the wafer W by applying pressure from above, and each test IC 5 and each semiconductor chip CH
Electrical connection with the

When the semiconductor chip CH and the test IC 5 are electrically connected to each other, the control device 3 starts supplying the power supply voltage. Test IC supplied with power supply voltage
5 operates in accordance with a microprogram written by the control device 3 based on the tester construction data described in HDL, and generates and applies a test pattern to the corresponding semiconductor wafer W in a predetermined order. At this time,
All the semiconductor chips CH are tested simultaneously by the plurality of test ICs 5 provided in the probe card 2, and the results are sent to the control device 3 and stored in the memory in the control device.

The control device 3 creates a pass / fail map of the semiconductor wafer based on the input test results, and provides data for removing defective products and classifying in a subsequent process (wafer dicing process).

As described above, in the test system according to the present embodiment, all the semiconductor chips CH formed on the semiconductor wafer W at the time of wafer burn-in are connected to the plurality of test ICs 5 provided on the probe card 2. Since tests can be performed in a batch, the test time can be greatly reduced, and the product development period can be shortened. This is true even when the test IC 5 is replaced with a microcomputer device.

Further, since the FPGA is programmable, a necessary tester function can be rewritten at any time by using the FPGA as the test IC 5, so that the test method can be easily changed or added. Similarly, when the test IC 5 is replaced with a microcomputer device, the internal RAM or EEPROM
This becomes possible by rewriting the control program stored in the OM or the like.

Further, even when the test of the entire semiconductor chip CH is complicated, the semiconductor chip CH is divided into a plurality of blocks, and an optimal ALPG is rebuilt for each block in the FPGA, and the test is performed sequentially. It is also possible. As a result, the test can be performed even if the logic scale of the FPGA used is small, and the feasibility of the test IC 5 corresponding to each semiconductor chip CH on the wafer increases.

Further, by performing the test using the virtual tester together, before the trial production of the sample of the semiconductor integrated circuit device to be tested, the evaluation of the test program and the verification of the logical function by the simulation using a hardware emulator or the like. This allows concurrent testing, and allows the data used in the virtual tester to be used when constructing a test circuit (ALPG) in an FPGA, thereby efficiently configuring the test system of FIG. It becomes possible.

Further, as a test IC 5, a patent application (Japanese Patent Application No. 11-122229) separately proposed by the present inventors has been proposed.
), A self-verifying FPGA having a self-checking function, a self-healing function, and the like may be used. As a result, the test IC 5 has a structure capable of self-test and self-repair, and can have a structure resistant to defective exposure.

FIG. 4 is an explanatory view showing a second embodiment of a test system to which the present invention is applied. FIG. 5 is a diagram showing a needle, a test IC, and a needle formed on a probe card in the test system of the second embodiment. Explanatory diagram showing the relationship of FIG.
FIG. 8 is a diagram illustrating an example of forming a wafer piece constituting a probe card in the test system according to the second embodiment.

As shown in FIG. 4, the test system 1 of the second embodiment comprises a probe card 2a and a control device 3, as in the first embodiment. The probe card 2a includes a fixed frame 18 and a plurality of wafer pieces 17 on which a test (test circuit) IC is formed.

Also in this embodiment, as shown in FIG. 5, a test IC 5a composed of an FPGA or a microcomputer device is formed directly on the wafer piece 17 corresponding to each semiconductor chip CH to be tested. Have been. On the surface of the wafer piece 17 in the vicinity of the test IC 5a, a needle 6a that is in contact with the electrode pad of the semiconductor chip CH is provided, and the needle 6a is also mounted on the wafer 1 using the processing technology of the semiconductor manufacturing process.
7 directly.

The needle 6a is formed by, for example, a technique called silicon contact. The silicon contact is a structure formed by using a silicon process by using a nanotechnology processing technology. The needle 6a formed by the silicon contact has a fine structure, and the contact property with the electrode pad of the semiconductor chip CH to be tested is improved, so that the contact load can be significantly reduced, and the wafer test can be performed more easily and It can be done reliably.

As shown in FIG. 6, the wafer piece 17 is formed by cutting the semiconductor wafer W1 on which the test IC 5a (including the needle 6a) is formed into a rectangular shape having a predetermined size, and cutting the plurality of cut wafer pieces. As shown in FIG. 4, the fixing member 17 is abutted and fixed to a fixing frame 18 made of aluminum or the like.

The probe card 2a has its needle 6
The semiconductor chip CH and the test IC 5a are electrically connected by superimposing the semiconductor chip CH on the semiconductor wafer CH mounted on the wafer stage WS such that the semiconductor chip CH is in contact with the electrode pad of each semiconductor chip CH on the semiconductor wafer W mounted on the wafer stage WS. Then, a wafer test is performed.

Further, by mounting a rewritable function on the test IC 5a, flexible addition and deletion of test items becomes possible. As for the test pattern, a test circuit is formed so as to form a test pattern for each pin, and by using pattern compression, a control program to be written to the test IC 5a is shortened and rewriting is facilitated. By doing so, when testing using the probe card 2a of FIG.
It becomes possible to deal with a plurality of semiconductor chips by rewriting a part of the control program without creating C or a control program, and the application range is expanded.

Further, according to the second embodiment, the probe card 2a is constituted by the plurality of wafer pieces 17, so that the wafer piece 17 of a high-performance portion is cut out from the plurality of semiconductor wafers W1, and the probe card 2a is cut out. , The reliability can be greatly improved. Further, even when testing a large-diameter wafer, the wafer piece 17
The number of wafers 1 can be flexibly adjusted by increasing the number of wafers 1 and the wafer pieces 1 constituting a test IC.
7 can be formed on a wafer having a smaller diameter than the wafer W on which the semiconductor integrated circuit device to be tested is formed.

Further, in the above description, the probe card 2a is constructed by combining a plurality of wafer pieces 17, but for example, as shown in FIGS. 7, 8 (a) and 8 (b), On a semiconductor wafer W1 separate from the wafer W, a plurality of test ICs 5a corresponding to individual semiconductor chips CH of the semiconductor wafer W to be tested are formed, and the semiconductor wafer W1 itself is used as a probe card 2
You may make it use as a.

In this case, the individual semiconductor chips C to be tested on the semiconductor wafer W1 on which the test IC 5a is formed
The needle 6b is formed at a position corresponding to the H electrode pad. The needle 6b can be constituted by, for example, a bump B as shown in FIG. Then, at the time of the wafer test, as shown in FIG.
By overlapping the main surface of the semiconductor wafer W with the main surface of the semiconductor wafer W1 as the probe card 4b, the needle 6b formed of the bump B and the electrode pad of the semiconductor chip CH are brought into contact. Thereby, use durability can be improved.

Also in the second embodiment, if a self-verifying FPGA having a self-test function, a self-repair function, and the like is used as the test IC 5a, it is possible to make the structure resistant to defective exposure.

If there is an unrepairable test IC 5a in the probe card 2a, the fact that it cannot be repaired is recorded in the test IC 5a and the test IC 5a closest to the test IC 5a is recorded. By automatically allocating the substitute test function, it is possible to realize a test system capable of performing an inspection without being affected by a yield or a failure of the test IC 5a.

FIG. 9A is a view showing an example of the arrangement of test ICs formed on a semiconductor wafer by applying the third embodiment of the present invention, and FIG. 9B is a view showing the third embodiment. And FIG. 10 is an explanatory diagram of a test measurement range in a tester according to the third embodiment.

In this embodiment, the test system 1
Comprises a test IC 5b formed on a semiconductor wafer, a probing module 19, and a power supply device 3a. As shown in FIG. 9A, the test IC 5b has a chip on which the test IC (test circuit) 5b is formed on the same semiconductor wafer W as the semiconductor wafer on which the semiconductor chip CH serving as a product is formed. They are arranged at appropriate positions at predetermined intervals.

The test IC 5b formed on the same wafer as described above allows the test IC 5b
The test of the peripheral semiconductor chip CH is performed. For example, as shown in FIG.
, Or 24 semiconductor chips CH including the eight semiconductor chips and the sixteen semiconductor chips surrounding them are tested at a time.

In the present embodiment, the connection between the semiconductor chip CH to be tested and the test IC 5b is established as shown in FIG.
This is performed by the probing module 19 shown in FIG. Wiring is provided on the probing module 19, and a needle is provided on the surface. Then, the needles are brought into contact with the electrode pads of the semiconductor chips CH formed on the semiconductor wafer and the electrode pads of the test ICs 5b, and the individual semiconductor chips CH and the test ICs 5b are connected via the wiring of the probing module 19.

The test IC 5b on the wafer W is supplied from the power supply 3a via the probing module 19.
The wafer test is started by supplying the power supply voltage to the semiconductor chip under test and its surroundings. When a power supply voltage is applied from the power supply device 3a, the test I
A test signal is output to each semiconductor chip CH measured from C5b, and the number of semiconductor chips CH to be tested, a voltage drop due to the arrangement of analog circuits measured through a Kelvin circuit, and the like are determined for each semiconductor chip CH. It is stored as information. Based on this, the test items are automatically and sequentially executed.

As a result of the execution of this test, the signal output from each semiconductor chip CH is supplied to the test IC 5b and compared with the data stored in the memory inside the test IC 5b or the expected value data generated by the test IC 5 It is determined whether the product is good or defective. In the case of a defective product, processing is performed on the test IC 5b so that the semiconductor chip CH of the defective product can be identified from the appearance.

As a process for determining the appearance, for example, cutting is performed by passing an overcurrent through a part of the aluminum wiring or polysilicon wiring in the defective semiconductor chip CH, or a current is applied to the zener zap. For example, a method of utilizing the high heat generated by flowing water to change the color of a heat-denatured color former applied to the periphery thereof is effective. In this way, the test is completed only by applying the power supply voltage to the chips on the wafer by the probing module, and as a result, the semiconductor chip CH determined to be defective is a mark that can be seen to be defective in appearance. Can be easily distinguished.

As described above, in the third embodiment, by forming the test IC 5b on the semiconductor wafer W, the configuration on the probe card side can be simplified, and the cost and space of the test apparatus can be greatly reduced. be able to. Moreover, since the test IC 5b is manufactured by the same process as that of the semiconductor chip CH as a product, the circuit scale, that is, the area can be reduced, and the overhead of the semiconductor wafer W can be greatly reduced. In other words, the conventional tester is configured using a semiconductor integrated circuit device manufactured by a process technology of one or two generations lower in integration degree than the semiconductor integrated circuit device to be tested. However, when this embodiment is applied, a test IC using the latest process technology is required.
Since 5b can be formed, the circuit scale of the test apparatus can be significantly reduced.

Further, in the conventional test apparatus, a long signal wiring (cable) for connecting the probe card and the tester main body was required. In the present embodiment, such a signal wiring is not required, and the test signal is not required. Since the distance between the IC 5b and the semiconductor chip to be tested is short, the stray capacitance of the wiring is minimized, and a high-speed clock actual operation test can be stably performed. Superiority can be exhibited even more.

Further, when the present embodiment is applied, each chip can be tested while performing aging (also called burn-in) in the state of the semiconductor wafer W, so that the period from the start of development of the semiconductor integrated circuit device to shipment thereof Can be greatly reduced.

Hereinafter, the usefulness of the present embodiment will be described in terms of the process from the start of development of the semiconductor integrated circuit device to shipment when the test method of the present embodiment is applied, and the semiconductor integrated circuit device when the conventional tester is used. The process is described in comparison with the process from development start to shipment. FIG.
4 shows a process from the start of development of a semiconductor integrated circuit device to shipment when a conventional tester is used. FIG.
9 illustrates a process from the start of development of the semiconductor integrated circuit device to the shipment thereof when the test method of the present embodiment is applied.

As shown in FIG. 18, in developing a conventional semiconductor integrated circuit device, first, a logic function of a semiconductor integrated circuit to be developed is designed (step S11). This logic function design is generally performed using HDL. Note that, since the EDA vendor provides a support tool (program) for automatically creating an HDL description from a state transition diagram and a flowchart, the HDL description can be efficiently performed. The design data described in the HDL is subjected to a virtual test for verifying whether the operation is appropriate by a verification program for generating a test pattern called a test vector. If a defect is found by the virtual test, the HDL description is corrected.

Next, a circuit is designed at the logic gate level based on the data designed in step S11 (step S12). Specifically, cells such as logic gates and flip-flops that constitute a circuit having a desired function are designed. Then, based on the design data, logic synthesis is performed to create design data in which connection information between each logic gate and cell is described in the form of a netlist (step S13). When a desired logic function is configured on an LSI for which a logic gate circuit has already been designed, such as a gate array, the circuit design in step S12 can be omitted. Also in this case, since a program called a logic synthesis tool for converting design data described in HDL into design data at a logic gate level and synthesizing the design data is provided by the EDA vendor, it can be performed using the program. . The generated logic gate level design data is verified again by a test vector (virtual tester). If a defect is found by the virtual tester, the design data at the logic gate level is corrected.

Next, based on the logic gate level design data described in the netlist format, element level layout data is generated by a program called an automatic layout tool (step S14). Such automatic layout tools are also provided by multiple EDA vendors. Then, the layout of the chips on the wafer is determined (step S15). Then, mask pattern data is generated by the artwork based on the determined layout data, and a mask is created based on the data (step S16).

After that, a semiconductor integrated circuit is formed by performing processing such as diffusion processing and wiring pattern formation on the semiconductor wafer in the previous process (step S17). then,
The probe at the tip of the cable extended from the tester is brought into contact with the electrode pad of each chip on the wafer, and a probe test for inputting a test pattern and observing an output is performed (step S18). When the probe test is completed, dicing is performed to divide the wafer into chips (step S19).

The divided chips are sealed in a package with a sealing material such as a resin (step S20). At this time, the chips determined to be defective in the probe test in step S18 are removed in advance. Then, the semiconductor integrated circuit device in a package state is subjected to a high temperature by an aging (or pan-in) device, and then a test is performed again by a tester in the package state (steps S21 and S22). The test content at this time is almost the same as the content of the probe test performed in step S18. Then, a mark determined to be defective in this test is marked on the package surface (step S2).
3), only non-defective products are packed and shipped in the sorting process (step S24).

FIG. 19 shows a process from the start of development of a semiconductor integrated circuit device to shipment when the test method of the above embodiment is applied, that is, a procedure of a method of manufacturing a semiconductor integrated circuit device according to the present invention. As is apparent from comparison with FIG. 18, steps S11 to S14 are the same as those in the related art.

However, in the process of the present invention, the function design of the semiconductor integrated circuit device to be developed (step S1)
1) In parallel with circuit design (step S12), logic synthesis (step S13) and automatic layout (step S14), data (tester IP) used in the virtual test performed in steps S11 and S12 is used. Then, the function necessary for testing the semiconductor integrated circuit device under development is determined, that is, the tester function is optimized (step S31).

Then, as described in the above embodiment,
This tester function is described in HDL (step S3
2). Then, similarly to the semiconductor integrated circuit device to be developed, the logic synthesis tool performs logic synthesis of the test circuit (ALPG) from the HDL description and converts it into design data at the logic gate level (step S33). Then, based on the generated logic gate level design data, element level layout data is generated by an automatic layout tool (step S34).

When the layout data of the test circuit is generated in this way, the present invention uses the semiconductor chip developed on the wafer and the test circuit module in order to form the test circuit as a module on the wafer. The chip layout arranged in a predetermined arrangement is determined (step S15 '). At this time, as described later, the test circuit module is not one-to-one with the semiconductor chip to be tested.
They are arranged at a ratio such as 1: 8 or 1:24.

Then, based on the determined layout data, mask pattern data is generated by the artwork including the test circuit module, and a mask is created based on the data (step S16 ').

Thereafter, the semiconductor integrated circuit and the test circuit module are formed by performing processes such as diffusion process and wiring pattern formation on the semiconductor wafer in the previous process (step S17). Then, in the process of the present invention, a probe card or a probing module for supplying power and connecting the test circuit module and the semiconductor chip is brought into contact with the test circuit module on the wafer and the electrode pads of the semiconductor chip, and the power is supplied on the wafer. Then, the test of the semiconductor chip by the test circuit module is automatically performed (step S18 '). Moreover, in this embodiment, the wafer test is performed in an aging device.

When the test is completed, dicing for dividing the wafer into chips is performed (step S1).
9). Thereafter, the divided chips are sealed in a package with a sealing material such as a resin (Step S20). At this time, the chips determined to be defective in the probe test in step S18 are removed. Then, the test of the packaged semiconductor integrated circuit device is performed by the tester (step S22 '). The test at this time is only a simple test such as the DC test not performed in step S18 '. Those that are determined to be defective in this test are marked on the package surface (step S23), removed in the sorting process, and only non-defective products are packed and shipped (step S24). If the test circuit module on the wafer also has a DC test function, the test by the tester in step S22 'can be omitted.

As described above, in the process of the present invention, the tests conventionally performed in the wafer state and the package state can be completed only once, so that the development period from functional design to product shipment is shortened. be able to. In addition, when a defect is found in the package test and the design needs to be changed, the TAT becomes very long because the wafer test and the package test must be performed again in the conventional process. In the above process, even if there is a design change, only the wafer test is required, so that the TAT is greatly reduced.

Further, in the third embodiment,
Semiconductor wafer W on which semiconductor chips to be tested are formed
The test circuit module 5b is formed on the semiconductor wafer W and the test circuit module 5b is connected to the semiconductor chip CH by the probing module 19. For example, the scribe area SA between the chips CH on the semiconductor wafer W as shown in FIG. Then, a test wiring for connecting the test circuit module 5b and the semiconductor chip CH may be formed.

In the case where the test wiring is formed in the scribe area SA, when each semiconductor chip CH is cut apart by dicing along the scribe area SA, the semiconductor chip CH extends far outside the center line of the scribe area SA. The extended wiring may remain without being cut. If there is any remaining wiring that is not cut in this way, it plays the role of an antenna and picks up electromagnetic noise, and it is expected that noise will easily enter the internal circuit from the electrode pad of the chip.

FIGS. 12 and 13 show a devised structure for reducing the influence of the residual wiring in the scribe area SA. Among them, FIG.
FIG. 13 shows an example of a layout effective when applied to a test wiring H formed by a single-layer wiring, and FIG. 13 shows an example of a layout effective when applied to a test wiring H formed by a two-layer wiring.

As shown in FIGS. 12 and 13, the test wiring H is arranged so as to meander over the scribe line SL which is the center line of the scribe area SA many times. As a result, the test wiring H is always cut when dicing the semiconductor chip CH, and the length lc of the remaining wiring extending from the electrode pad PAD of the chip to the scribe area SA is equal to the distance from the center line of the scribe area SA. And the cut is made to remain in the shortest length.

FIGS. 20 and 21 show one test circuit module and eight semiconductor chips C around it.
In the case where the test of H is performed, a relatively efficient wiring connection method will be described. FIG. 20 shows a case where the test wiring H is constituted by a single-layer wiring. FIG.
0, 5b is a test circuit module, and CH
1, CH2 and CH3 indicate three of the eight surrounding semiconductor chips.

FIG. 20 is a circuit diagram of the test circuit module 5b.
Each of the sides is divided into two, and all the electrode pads provided on the periphery of the right half of the adjacent chip CH1 and all the electrodes provided on the periphery of the chip CH2 are provided on the half sides X2 and Y1 at the upper right corner. Terminals connected to the electrode pads and all the electrode pads provided on the left half around the chip CH3 are provided, and scribe areas SA1, SA2, SA
3 and SA4 to use those terminals and chips CH1 and C
This shows that a test wiring for connecting the selected electrode pads of H2 and CH3 is formed. The terminals provided on the four sides of the test circuit module 5b other than the terminals receiving the power supply voltage need not be electrode pads, and the scribe areas SA1, SA2, SA3, SA4
Is formed as a virtual terminal to which one end of the test wiring formed is connected. Accordingly, 4 of the test circuit module 5b
Terminals can be arranged closer to the side than the semiconductor chip to be tested.

Similarly, for the five chips (not shown) other than the chips CH1, CH2, and CH3, the half sides Y2, X3; X of the three corners of the test circuit module 5b.
4, Y3; Y4, X1 are provided with terminals connected to the electrode pads of the same parts of the three adjacent chips as described above, and the connection is made by the test wiring formed in the scribe area. This makes it possible to connect one test circuit module to eight semiconductor chips around it using a relatively short length of test wiring.

By the way, when the connection system as shown in FIG. 20 is adopted, the test wiring becomes densest at the diagonal line DL connecting the opposite corners of the chips CH1 and CH3. Therefore, it is calculated whether or not all the wirings that want to pass therethrough are within the width of the diagonal line DL at an allowed pitch. If not, the two-layer wiring system shown in FIG. Just choose.

In FIG. 21, reference numeral 5b denotes a test circuit module, CH1 to CH8 denote eight surrounding semiconductor chips, H1 to H4 denote test wirings for connecting the test circuit module 5b and the semiconductor chips CH1 to CH8, A ~ D
Represents an electrode pad. It is to be noted that the electrode pads having the same reference numerals are connected to the same test wiring. In FIG. 21, for convenience of illustration, the test wirings H1 to H4 are shown to extend along the periphery of each chip. However, in the actual layout, they are arranged in the scribe area SA.

In FIG. 21, scribe area SA
Is composed of four forked wiring bodies H1, H2, H3, H4 each having three tooth portions and a connecting portion which is orthogonal to them and which connects them at one end. ing. The four fork-shaped wiring bodies H1, H2, H3, and H4 have their respective tooth portions entering the scribe area SA of the chip matrix from four directions different from each other by 90 °. Are arranged to mesh with each other, and each chip CH1 to CH1
CH8 is connected to these forked wiring bodies H1, H2, H3,
The four sides are arranged so as to be surrounded by any tooth portion of H4. Then, each chip CH1 to CH8
And the electrode pads A, B, C,
D is connected to the wiring of the tooth portions of the forked wiring bodies H1, H2, H3, and H4 arranged along the side.

The four forked wiring bodies H1, H
In H2, H3, and H4, those having parallel tooth portions are formed of the same layer of wiring, and those having orthogonal portions are formed of wiring of different layers. Specifically, the forked wiring bodies H1 and H3 are formed by first-layer wirings, and H2 and H4 are formed by second-layer wirings. As a result, the portions that intersect each other are electrically insulated.

As described above, the fork-like wiring bodies H1, H2,
By connecting the test circuit module 5b to the eight semiconductor chips CH1 to CH8 around the test circuit module 5b by H3 and H4, the number of wirings can be reduced, and connection using scribe lines having a relatively narrow width is possible. Becomes However, since the connection method in FIG. 21 is a bus method, and a plurality of chips are connected to one wiring, each of the semiconductor chips CH1 to C
A chip selection signal is sent to H8 so that one of the chips is connected to the test circuit module 5b in a certain time zone, and control is performed such that tests are sequentially performed in a time division manner. There is a need.

FIG. 22 shows one test circuit module 5
b, 24 semiconductor chips CH1 to CH24 around it
In the embodiment, the test circuit module 5b and the semiconductor chips CH1 to
A wiring connection method considered to be the most efficient when connecting to the CH 24 will be described. This method is merely an increase in the scale of the method shown in FIG. 21, and the basic configuration is the same. That is, similarly to the method of FIG. 21, the connection between the test circuit module 5b and the 24 semiconductor chips CH1 to CH24 around the test circuit module 5b is performed by four forked wiring bodies H1, H2, H3, and H4. FIG.
The difference from the first method is that each of the forked wiring bodies H1, H
2, H3 and H4 are provided with five tooth portions instead of three tooth portions. Also in this embodiment, the chips CH1 to CH24 and the electrode pads A, B, C, D of the test circuit module 5b are connected to the fork-shaped wiring bodies H1, H2, H3, H4 arranged along their sides. It is connected to the wiring of the tooth part.

The layout of the test circuit module and the semiconductor chips to be tested on the wafer is not limited to the examples shown in FIGS.
As shown in FIG. 7, a plurality of test circuit modules 5c to 5e are collectively arranged at the center of the semiconductor wafer W, and a test wiring is extended to each chip CH therefrom, or the semiconductor wafer W is formed by the above-described probing module. The above test circuit modules 5c to 5e may be connected to the semiconductor chip CH for testing.

These test circuit modules 5c to 5e
May have the same functions, but may have dedicated functions, for example, an analog-only test module or a digital-only test module. In this way, by providing a plurality of test ICs 5c to 5e having dedicated test functions on a wafer, a more accurate test can be performed.
Further, since a test function dedicated to a high frequency can be taken in, a test with a large degree of freedom can be performed.

The test circuit module 5f may be divided into four parts, each of which is arranged at four peripheral parts of the semiconductor chip CH as shown in FIG. For example, in the peripheral portion of the central semiconductor chip CH1 shown in FIG. 15, a test circuit module 5f (a shaded region) for testing the semiconductor chip CH1 and another test circuit module located near the peripheral portion of the semiconductor chip CH1. Semiconductor chip C
A test circuit module 5f (open area) for testing H is arranged. In this case, it is difficult to provide the electrode pads in the scribe area having a relatively small width. Therefore, the electrode pads are formed in the empty area of the peripheral portion of the semiconductor wafer W, and the wiring or the wires formed in the scribe area from the electrode pads are formed. An insulating synthetic resin film such as a PIQ (polyimide insulating film) is formed on the surface of the final protective film above the semiconductor chip, and power is supplied to each test circuit module 5f via the wiring formed thereon. It is good to configure.

In the case of such a configuration, the test circuit modules 5f can be arranged evenly on the respective semiconductor chips CH, and the optimum position for each test function, that is, the position closest to the electrode pad to which the test signal is input. A test function unit for generating the test signal can be arranged on the side. In addition, the test circuit module 5f
Is cut by dicing after the test, so that the semiconductor chip CH has no electrical influence.

Further, as shown in FIG. 16, the test circuit module 5 is mounted on the probe card 2b formed on a semiconductor wafer W1 separate from the semiconductor wafer W to be tested.
g may be arranged at predetermined intervals, and one test circuit module 5g may test a plurality of semiconductor chips CH on the semiconductor wafer W corresponding to the test circuit module 5g. In the probe card 2b, the hatched portions are the test circuit modules, and the other portions are regions where bumps and wirings are formed. Also, in FIG.
The mark indicates the range covered by one test circuit module 5g as a test target.

FIG. 16 shows a total of 9 chips of the chip facing each other and the chips around it by one test circuit module 5g.
An example covering the test of one semiconductor chip CH is shown. In this case, the semiconductor wafer W1 has the structure shown in FIG.
As shown in (b), a needle 6b made of a bump B is provided. At the time of the wafer test, as shown in FIG. 17A, the test circuit module 5g of the semiconductor wafer W1 as the probe card 2b is formed on the main surface of the semiconductor wafer W on which the semiconductor chips are formed. By overlapping the surfaces, the needle 6 composed of the bump B is formed.
b and the electrode pads of the semiconductor chip CH. Thereby, use durability can be improved. FIG. 17B is a partially enlarged view showing a portion indicated by reference numeral A in FIG. 17A in an enlarged manner.

FIG. 23 shows an example of a mounting structure of a semiconductor chip cut out from a wafer after the test by the test circuit is completed. Among these, (a) is a general one-chip one-package type, (b) to (d) are structures having a plurality of chips sealed in one package, (e),
(F) shows a structure in which a chip mounted on a substrate such as a ceramic by a face-down method is molded with a resin RS. In FIG. 23, CH is a semiconductor chip, PG
Is a package made of resin or the like, and BP is a semiconductor chip C
The bumps and LDs provided on the H electrode pads are lead terminals electrically connected to the electrode pads of the semiconductor chip CH via the bumps BP.

Among the above structures, the structure shown in FIG. 23A can be tested by a conventional tester.
In the case of (d), since there are two or more chips in the package, when testing with a tester, if each chip does not exist as an independent chip from the viewpoint of the tester, that is, the configuration can be tested separately. Otherwise, the test pattern becomes very complicated, and the development time and test execution time of the test program become considerably long.
In particular, in the structures of (b) and (f), since the test of the upper chip CH2 must be performed via the lower chip CH1, separate tests are impossible. (E)
In this structure, the test after mounting is difficult because the electrode pads of the chip are not exposed.

Therefore, for a semiconductor chip having a mounting structure as shown in FIGS. 23 (b) to 23 (f), it is better to adopt a test method performed at the wafer stage as in the above embodiment.
The test program is much simpler and the test execution time is shorter than a test using a conventional tester.

Next, when the semiconductor chip to be tested is a logic integrated circuit (logic IC), a specific example of an ALPG as a test circuit constructed in an FPGA to generate a test pattern will be described with reference to FIGS. This will be described with reference to FIG. Among them, FIG. 24 shows a schematic configuration of an entire ALPG for generating test signals for a plurality of input terminals of a semiconductor chip under a control of a common control circuit in a shared resource manner according to a predetermined algorithm, and a specific example of a sequence control circuit. Is shown.

The ALPG shown in FIG. 24 includes a sequence control circuit 400 for sequentially controlling the entire ALPG, a test signal generated by receiving a control signal from the sequence control circuit 400, and a logic circuit (semiconductor chip) to be tested. It comprises a driver / comparator block 300 which receives an output signal and outputs a pass / fail judgment signal by comparing it with an expected value, and an interface circuit 210 which performs an interface between the ALPG and an external control device. A specific example of the driver / comparator block 300 is shown in FIG. 25, and a specific example of the interface circuit 210 is shown in FIG.

The sequence control circuit 40 among the above circuits
0, as shown in FIG. 24, an instruction memory 411 storing a microprogram composed of a plurality of microinstructions described according to a predetermined test pattern generation algorithm, and a microinstruction to be read from the instruction memory 411. , A command decoding control circuit 430 that decodes an instruction code in a microinstruction read from the instruction memory 411 to form a control signal for a circuit in the sequence control circuit 400 such as the program counter 412, A timing generator 420 for forming a timing control signal based on a clock φ0, a timing setting bit MFd in a microinstruction
Data register set 41 that outputs control data to timing generator 420 based on (TS bit)
7. Timing setting bit MFd (T
S bit) to decode the data register set 417
And a decoder 418 for reading control data from the CPU. The instruction memory 411 and the data register set 417 are a data rewritable RAM or EE.
It is composed of a PROM or the like.

Also, of the logic circuits to be tested, a circuit whose function is specified (for example, ALU: Arithmetic)
In the case of a Logic Unit, an appropriate test pattern formation method has already been established in many cases, so that efficient use of test pattern assets enables efficient test pattern generation. As for the combinational logic circuit, there is known a fault assumption method and an efficient test pattern generation method called a D algorithm based on the idea of a single fault in which one circuit has one fault. By using this method, a microprogram for generating a test pattern can be shortened, and an increase in the capacity of the instruction memory 411 can be suppressed to an achievable level.

In the ALPG of this embodiment, although not particularly limited, the timing setting bit TS decoded by the decoder 418 is composed of two bits, and the data register set 417 stores seven control data. One of these control data is data “RATE” that defines a test cycle, and the remaining six control data are:
Two types of control data “ACLK1” and “ACLK2” for giving a high-level or low-level signal output timing for each signal line of the test bus, and two types of control data “BC” for giving rise timing of a pulse signal
LK1 ”and“ BCLK2 ”, and two types of control data“ CCLK1 ”and“ CCLK2 ”that provide a comparison between the fall timing of the pulse signal and the expected value.

When each of these control data is supplied to the timing generation section 420, a signal RATE at a predetermined timing is supplied to the program counter 412 with respect to the control data RATE, and the micro instruction code from the instruction memory 411 is supplied to the program counter 412. Capture is performed. When “ACLK1” to “CCLK2” are supplied to the timing generator 420 as control data, a clock corresponding to the control code is output to the driver / comparator circuit 300 from the timing clocks ACLK1 to CCLK2. Connection and selection for use of each clock are appropriately performed as needed.

Furthermore, the ALPG sequence control circuit 4
In 00, the value of the program counter 412 is set to “+”.
Incrementer 421 for incrementing to "1"
A multiplexer 422 for selecting either the incrementer 421 or the jump address in the address field MFa and supplying it to the program counter 412; an index register 423 for holding the number of repetitions in the operand field MFc;
A decrementer 424 for making the value of 23 “−1”;
A working register 425 holding a value decremented to "-1", a flag 427 indicating whether or not an operand used in a predetermined instruction is transferred to the program counter 412, and a value of the registers 423 and 425 are selectively decremented by the decrementer. A multiplexer 428 that feeds 424
A demultiplexer 429 that distributes the value of the decrementer 424 to any plane of the working register 425
And so on.

In the ALPG of FIG. 24, an operand field MFc for storing the number of instruction repetitions is provided in the micro-instruction code and an index register 423 for holding the number of repetitions is provided, so that the same test signal is repeatedly generated. In such a case, the number of necessary micro-instructions can be reduced and the micro-program can be shortened. Further, in the ALPG of this embodiment, the index register 423, the working register 425, and the flag 427 are provided in a plurality of planes (four in the figure).
Further, sub-loop processing in the sub-loop processing can be easily executed, and the microprogram can be shortened.

FIG. 25 shows a specific example of the driver / comparator circuit 300. The circuit shown in FIG. 25 is one of the signal lines constituting the test bus 220.
Although only the driver / comparator circuit corresponding to the present invention is representatively shown, actually, the circuits shown in FIG. 25 are provided by the number of signal lines constituting the test bus 220. The test bus is formed in a scribe area on the wafer, and the ALPG is connected to a semiconductor chip as a logic circuit to be tested.

As shown in FIG. 25, the driver / comparator circuit of this embodiment includes a driver circuit (signal forming circuit) 340 for forming a signal to be output to the test bus, a signal on the test bus and an expected value signal. Comparator circuit (comparing circuit) 350 for comparing match / mismatch by comparing
And a switching circuit 360 for switching between the driver circuit 340 and the comparator circuit 350. The switching circuit 360 includes a driver circuit 340 and an input / output node Ni.
o, and a transmission gate TG2 provided between the input / output node Nio and the comparator circuit 50, and an input / output control bit I / I supplied from the sequence control circuit 400. One of them is opened according to O and the other is shut off.

The driver circuit 340 receives the input / output control bit TP by the timing clock ACLKi supplied from the timing generator 420 and holds the input / output control bit TP, and the timing clock BCLKi supplied from the timing generator 420.
OR gate 342 which takes the logical sum of the OR and CCLKi, a J / K flip-flop 343 using the output of the OR gate 342 and the output of the edge trigger flip-flop 341 as input signals, and the J / K flip-flop 34
3 and an input / output control bit CONT supplied from the sequence control circuit 400 as an input signal;
1 and an input / output control bit CONT supplied from the sequence control circuit 400 as an input signal, and a driver 346 for driving a test bus by the outputs of the AND gates 344 and 345. ing.

On the other hand, the comparator circuit 350 is provided with a timing clock C supplied from the timing generator 420.
CLKi and an input / output control bit CONT supplied from the sequence control circuit 400 as an input signal; an output (expected value) of the D-type flip-flop 341 and a test signal supplied via a transmission gate TG2. An exclusive OR gate 352 that receives a signal on the bus as an input signal; an AND gate 353 that receives the outputs of the exclusive OR gate 352 and the AND gate 351 as input signals; and a flip-flop that latches the output of the AND gate 353. 354, and a signal obtained by calculating the logical sum of the outputs of all the comparator circuits 350 is output as a total fail signal TFL. The above input / output control bits I / O, TP, C
ONT corresponds to the control signal.

As shown in FIG. 24, the microinstruction in the ALPG of this embodiment includes an address field MFa for storing a PC address indicating a jump address of an instruction used in a jump instruction, and a sequence control code. An operation code field MFb to be stored, and an operand field MFc to store the number of instruction repetitions, etc.
A timing setting field MFd for storing a timing setting bit TS for reading a control signal for the timing generator 420 from the data register set 14, and an input / output for storing an input / output control bit of the driver / comparator circuit 300 Control field MF
e.

The timing setting bits TS stored in the timing setting field MFd are two bits in this embodiment as described above, but may be three or more bits. The input / output control bits stored in the input / output control field MFe correspond to three signal lines of the driver bus TP, the I / O bit, and the control bit CONT corresponding to the n signal lines of the test bus 220. Are set as one set, and only n sets are provided. Of these bits, the I / O bit is a control bit for designating input or output, and when "1", the transmission gate TG1 is opened and T
G2 is cut off and the driver output signal is sent to the test bus 22
0 on the corresponding signal line, and when it is "0", shut off the transmission gate TG1 and open TG2 to open the test bus 2
The gate 352 for comparing the signals on the corresponding signal lines of the 20
To input. The driver bit TP and the control bit CONT are set to a high output or a low output, a positive pulse or a negative pulse output,
Specify the input invalid state or output high impedance state.

Table 1 shows that the input / output control bits TP, I
The relationship between / O, CONT and a test signal (test pattern) output from the driver / comparator circuit 300 is shown.

[0126]

[Table 1] As shown in Table 1, the input / output control bits TP, I
When / O, CONT is "111", the driver circuit 34
0 outputs a high-level signal, and when it is “011”, the driver circuit 340 outputs a low-level signal and “11”
When the value is "0", control is performed so that the driver circuit 340 outputs a positive pulse signal, and when the value is "110", control is performed so that the driver circuit 340 outputs a negative pulse signal. When the input / output control bits TP, I / O, and CONT are “101”, the comparator circuit 350 expects a high-level input signal.
Expects a low-level input signal, and when "100", control is performed to invalidate the input signal.

In the driver / comparator circuit 300 of this embodiment, the control bits TP, I / O, CONT
Is set to have no meaning at all. However, control bits TP, I / O, CO
When NT is "000", for example, the transmission gate TG1 is closed and TG2 is opened, and the exclusive OR gate 352 is a Schmitt circuit operating at the two levels between the high level and the low level. Input / output node N connected to test bus 220
State where io potential exists (high impedance state)
Driver / comparator circuit 300 so that
Can also be configured.

FIG. 26 shows the timing clock ACL supplied from the timing generator 420 in the above embodiment.
K1 to CCLK2 and driver / comparator circuit 300
2 shows an example of a signal output from the test bus 220 to the test bus 220. 26, (a) shows the reference clock φ0 supplied from the outside, (b) to (g) show the waveforms of the timing clocks ACLK1 to CCLK2, and (h) shows “1” as the output test signal in Table 9. 13 shows a waveform of an output signal of a terminal designated and ACLK1 selected as a clock. (I) shows the waveform of the output signal of the terminal in which “0” is designated as the output test signal in Table 1 and ACLK2 is selected as the clock. (J) shows the waveform of the output signal of the terminal in which "P" is designated as the output test signal in Table 1 and BCLK1 and CCLK1 are selected as the clock. Further, (k) designates “N” as the output test signal in Table 1 and BC as the clock.
LK2 and CCLK2 show the waveforms of the output signals of the selected terminals.

As can be seen from FIG. 26, the input / output control bits TP, I / O, and CONT are set to "111" and the clock ACLK1 is supplied from the terminal designated by the clock ACL.
A high-level signal as shown in FIG. 26 (h) is output in accordance with K1, and TP, I / O, CONT are set to "011" and a clock ACLK2 is designated from a terminal designated by clock ACLK2 in accordance with clock ACLK2. TP, I / O, CONT are set to "110" and the clocks ACLK1, BCLK1, CCLK1
Output a positive pulse as shown in FIG. 26 (j) with BCLK1 and CCLK1 as edges in accordance with the data set by the clock ACLK1.
/ O, CONT are set to “010” and the clock ACL
From the terminals where K2, BCLK2 and CCLK2 are designated, BCL is applied in accordance with the data set by clock ACLK2.
A negative pulse as shown in FIG. 26 (k) having K2 and CCLK2 as edges is output.

Although not shown, the input / output control bit T
At the terminal where P, I / O, and CONT are set to "101" and the clock CCLK1 is designated, the expected value is set to the high level, and the comparison is performed using the clock CCLK1 in FIG. , CONT are set to “001” and the terminal to which the clock CCLK2 is designated makes the expected value a low level, and the comparison is performed using the clock CCLK2 of FIG. 26 (g) as a strobe signal. Note that the selection of the clock is not limited to the above, and may be any combination.

The ALPG having the above-described configuration can arbitrarily change the generated test pattern and its output timing by rewriting the program stored in the instruction memory 411 and the control data stored in the data register set 417. Can be. Therefore, even when the semiconductor chips to be tested are different, it is possible to form an ALPG having the same architecture on the same wafer and perform the test. Also, even when ALPGs having the same architecture cannot be used,
If the test target is in the same category, such as a logic IC or a memory, the architecture of the ALPG that tests it is similar, so the optimum ALPG for each semiconductor chip is
Designing a PG does not place a great burden on the designer.

By the way, in order to rewrite data using the ALPG as a programmable device as described above, it is necessary to be able to connect to an external device. Therefore, the interface circuit 210 is provided in the ALPG of the embodiment of FIG. FIG. 27 shows the interface circuit 210
The following shows a specific example. When the test circuit is formed on the same wafer as the semiconductor chip to be tested as in the third embodiment, the number of electrode pads for connecting to an external device for rewriting data in the test circuit is large. Is not desirable. Therefore, in the ALPG of this embodiment,
IEEE11 as an interface circuit with external devices
TAP (Test Access Pos) specified in the 49.1 standard
rt) 210 is used. By using the TAP as an interface, only a few electrode pads are required to connect to an external device for rewriting data.

TAP is an interface and control circuit for a scan test and a BIST circuit defined by the IEEE1149.1 standard. The TAP is a bypass register 211 used to shift test data from an input port to an output port. A data register 212 used for transmitting a specific signal to the device, a device ID register 213 for setting a manufacturing identification number unique to a chip, an instruction register 214 used for controlling selection of a data register and an internal test method, TAP
It is composed of a controller 215 for controlling the entire circuit.

The data register 212 is a register treated as an option. The instructions set in the instruction register 214 include four essential instructions and three optional instructions. Controller 21
5, a test mode select signal TMS for designating a test mode, a test clock TCK, and a reset signal TRST are input from three dedicated external terminals, and based on these signals, the registers 211 to 21 are used.
4 and control signals for the selector circuits 216 to 218 are formed.

The TAP is provided with an input terminal for the test data TDI and an output terminal for the test result data TDO. The input test data TDI is supplied via the selector circuit 216 to each of the registers 211 to 214 or the internal register. It is supplied to the scan paths Iscan and Bscan. Further, the contents of the registers 211 to 214 and the scan-out data from the internal circuit are output to the outside of the chip via the selector circuits 217 and 218. Further, the TAP has a data register 212 and an instruction register 21.
4, a signal for the internal BIST circuit is formed and supplied, and a signal indicating a test result output from the BIST circuit is supplied to the selector circuits 217 and 218.
And output to the outside of the chip.

In the test system of the present invention, a test circuit (ALPG) formed on a wafer on which a logic circuit (semiconductor chip) to be tested is formed is regarded as a BIST circuit, and a signal for the BIST circuit of the TAP is provided. Using the input / output function, ALPG data register set 41
It is configured to input the setting data for 7 and the microprogram stored in the instruction memory 411 and output the test result by ALPG. AL
The clock φ0 for the PG timing generator 420 is also supplied via the TAP 210. In FIG. 27, the clock φ0 for the timing generator 420 is TAP
Although the clock is a separate clock from the clock TCK of the clock 210, the timing generator 420
May be supplied.

In FIG. 27, "Iscan" is a test for diagnosing the internal logic circuit using a shift register in which flip-flops constituting the internal logic circuit are connected in a chain as a scan path for test data. Means a path. “Bscan” uses a shift register in which flip-flops provided in a signal input / output unit are connected in a chain as a scan path to diagnose a connection state with another semiconductor integrated circuit (boundary scan test). Means a test pass to be performed. T
The functions of the AP for the scan test and the function of the boundary scan test are not used in the test system of the present embodiment, and thus description thereof is omitted.

As described above, the invention made by the inventor has been specifically described based on the embodiments of the present invention. However, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed. For example, in the embodiments shown in FIGS. 9 and 10, a test circuit is arranged on a wafer on which a semiconductor chip to be tested is formed, and the test circuit is an ALPG as shown in FIG.
However, instead of forming the ALPG of FIG. 24 directly on the wafer, an FPGA is formed on the wafer on which the semiconductor chip to be tested is formed.
It is also possible to construct and test an ALPG as shown in FIG. 24 in the GA.

In the embodiment of FIG. 24, when a test circuit is arranged on a wafer on which a semiconductor chip to be tested is formed, a TA interface is provided to an external device.
P is used, but when configuring a test circuit in the probe card or probing module described above,
It is also possible to use TAP as the interface.

[0140]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

That is, according to the present invention, the developed semiconductor chip can be tested without using an expensive tester, and the total cost required for the test can be greatly reduced. Further, according to the present invention, it is possible to perform a test at the wafer stage, and by performing this wafer test in an aging apparatus, the test after packaging can be simplified or omitted, and the test time can be greatly reduced. Can be increased. Further, the time required from the start of the design to the completion of the semiconductor integrated circuit device can be reduced.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a test system according to a first embodiment of the present invention.

FIG. 2 is a mounting explanatory diagram of a test IC mounted on the probe card according to the first embodiment of the present invention.

FIG. 3 is an explanatory diagram of a virtual tester according to the first embodiment of the present invention.

FIG. 4 is an explanatory diagram of a test system according to a second embodiment of the present invention.

FIG. 5 is an explanatory diagram of a needle and a test IC formed on a probe card according to a second embodiment of the present invention.

FIG. 6 is a view showing an example of forming a wafer piece constituting a probe card according to a second embodiment of the present invention.

FIG. 7 is an explanatory diagram of a layout of a semiconductor chip to be tested and a test circuit module according to another embodiment of the present invention.

FIG. 8A is a diagram showing an example of a contact between a semiconductor wafer to be tested and a probe card according to another embodiment of the present invention, and FIG. 8B is an explanatory diagram showing a part of the contact.

FIG. 9A is a diagram showing an example of an arrangement of test circuit modules formed on a semiconductor wafer according to a third embodiment of the present invention, and FIG. 9B is an explanatory diagram of a probing module.

FIG. 10 is an explanatory diagram of a test measurement range in a tester according to a third embodiment of the present invention.

FIG. 11 is a view showing an example of forming a test circuit module on a semiconductor wafer to be tested according to another embodiment of the present invention.

FIG. 12 is an explanatory diagram showing an example in which wiring for connecting a test circuit module and a semiconductor chip according to another embodiment of the present invention is formed on a scribe area of a semiconductor wafer.

FIG. 13 is an explanatory view showing another example in which a wiring connecting a test circuit module and a semiconductor chip according to another embodiment of the present invention is formed on a scribe area of a semiconductor wafer.

FIG. 14 illustrates an example of forming a test circuit module on a semiconductor wafer to be tested according to another embodiment of the present invention.

FIG. 15 is a view showing another example of forming a test circuit module on a semiconductor wafer to be tested according to another embodiment of the present invention.

FIG. 16 is a view showing still another example of forming a test circuit module on a semiconductor wafer to be tested according to another embodiment of the present invention.

FIG. 17A is a diagram showing another example of a contact between a semiconductor wafer to be tested and a probe card according to another embodiment of the present invention, and FIG. It is.

FIG. 18 is a flowchart showing a process from the start of development of a semiconductor integrated circuit device to shipment when a conventional tester is used.

FIG. 19 is a flowchart showing a process from the start of development to shipment of a semiconductor integrated circuit device when the test method according to the embodiment of the present invention is applied.

FIG. 20 shows one test circuit module and its surroundings
FIG. 9 is an explanatory layout diagram showing a relatively efficient wiring connection method when testing individual semiconductor chips.

FIG. 21 shows one test circuit module and its surroundings
FIG. 11 is a layout explanatory diagram showing another example of a relatively efficient wiring connection method when testing individual semiconductor chips.

FIG. 22 shows two test circuits around one test circuit module;
FIG. 11 is a layout explanatory diagram showing another example of a relatively efficient wiring connection method when testing four semiconductor chips.

FIG. 23 is an explanatory sectional view showing an example of a mounting structure of a semiconductor chip cut out from a wafer;

FIG. 24 shows AL as a test circuit used in the present invention.
It is a block diagram which shows the example of a structure of PG.

FIG. 25 is a logical configuration diagram showing a specific example of a driver / comparator circuit configuring ALPG.

26 is a waveform chart showing an example of a test signal waveform formed by the ALPG of FIG. 24.

FIG. 27 is a block diagram illustrating a configuration example of an interface circuit configuring the ALPG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Test system 2, 2a, 2b probe card 3 Control device 3a Power supply device 4, 4a, 4b Probe card board 5-5f Test IC, test circuit module (test circuit) 6, 6a, 6b Needle 7-9 FPGA DESCRIPTION OF SYMBOLS 10 Pattern generation part 11 Timing generation part 12 Power supply part 13 DC test circuit 14 Driver 15 Comparator 16 Microcomputer 17 Wafer piece 18 Fixed frame 19 Probe module 210 Interface circuit 300 Driver / comparator block 340 Driver circuit 340 350 Comparator circuit (comparison circuit) 360 switching circuit 400 sequence control circuit 411 instruction memory 412 program counter 420 timing generator 430 instruction decoding control circuit W, W1 semiconductor wafer CH Semiconductor chip TCI Semiconductor integrated circuit device B Bump SA Scribe area D1, D2 Electrode pad H Test wiring

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G01R 31/3183 G01R 31/28 F 31/30 Q UK (72) Inventor Hiroshi Fukiage Kodaira, Tokyo 5-20-1, Mizumotocho F-term within Hitachi, Ltd. Semiconductor Group (reference) 2G011 AA02 AB01 AC11 AC31 AD01 AE03 AF06 2G032 AA00 AB01 AB02 AC03 AE06 AE08 AE11 AE14 AF02 AG01 AK11 AL11 4M106 AA01 AA08 AC01 CA05 BA01 BA01 DD10 DD11 DD23

Claims (22)

[Claims] 1. A test system for performing an electrical test of a semiconductor chip formed on a semiconductor wafer, wherein a conductive needle is arranged in accordance with an arrangement of electrode pads on the semiconductor chip, and connected to a test circuit. A probe card, a test circuit mounted on the probe card and testing the semiconductor chip based on a program, a control device for rewriting a program in the test circuit, and storing a test result output from the test circuit. A test system, comprising: 2. A test system for performing an electrical test on a semiconductor chip formed on a semiconductor wafer, comprising: a test circuit for testing the semiconductor chip formed at an arbitrary position on the semiconductor wafer; A test system, comprising: a probing module formed with test wiring for connecting to the test circuit; and a power supply device for supplying power to the semiconductor chip and the test circuit via the probing module. . 3. A test system for performing an electrical test of a semiconductor chip formed on a semiconductor wafer, wherein a test circuit for testing the semiconductor chip is formed in a scribe area or a chip area of the semiconductor wafer, A test system comprising a configuration in which a test wiring for connecting the test circuit and a semiconductor chip is formed in a scribe area or a test wiring layer of a semiconductor wafer. 4. The test system according to claim 1, wherein the test circuit includes an FPGA or a microcomputer device. 5. A function of each block in a tester for performing an electrical test of a semiconductor chip formed on a semiconductor wafer and a function of the semiconductor chip to be tested are described in a hardware description language, and the hardware description and the test are performed. A method for generating a test program, comprising: inputting a program to a hardware emulator; performing a simulation with the hardware emulator; and debugging the test program. 6. A plurality of semiconductor chips having desired functions are formed on a semiconductor wafer, and conductive needles are formed having a size corresponding to the wafer and corresponding to the arrangement of the electrode pads of the semiconductor chips. On the probe substrate, a test circuit connected to the needle and operated according to a program to test the semiconductor chip is mounted, and the probe substrate is moved so that the needle is brought into contact with a corresponding electrode pad of the semiconductor chip. A method of manufacturing a semiconductor integrated circuit device, comprising superimposing the semiconductor chip on the wafer, testing the semiconductor chip by the test circuit, and selecting a semiconductor chip determined as a non-defective product as a product. 7. A programmable logic IC capable of configuring an arbitrary logic on the probe substrate is provided for each semiconductor chip on the wafer, and the logic data is written in the design data of the semiconductor chip described in a hardware description language. Configuring the test circuit in the programmable logic IC based on the
7. The method according to claim 6, wherein the test circuit tests the semiconductor chip. 8. The test circuit according to claim 6, wherein the test circuit is a test signal generation circuit configured to generate a test signal supplied to a semiconductor chip to be tested according to a predetermined algorithm. A manufacturing method of the semiconductor integrated circuit device according to the above. 9. The test signal generation circuit includes an instruction memory for holding a program, a control unit for decoding a program instruction to generate a control signal, and a signal generation unit for generating a signal to be output. The method for manufacturing a semiconductor integrated circuit device according to claim 8, wherein: 10. The method according to claim 9, wherein a program stored in the instruction memory is rewritable from the outside. 11. The test signal generating circuit further includes timing generating means for receiving a clock signal serving as a reference and control data from a storage means for holding control data relating to timing and generating a desired timing signal. The method of manufacturing a semiconductor integrated circuit device according to claim 9, wherein: 12. The storage means according to claim 1, wherein the stored control data is rewritable from outside.
2. The method for manufacturing a semiconductor integrated circuit device according to item 1. 13. A test circuit module that operates according to a program and tests the semiconductor chip is formed on a semiconductor wafer on which a plurality of semiconductor chips having desired functions are formed, and at least a power supply voltage is applied to at least the test circuit module from outside. And testing the semiconductor chip on the wafer by the test circuit module, and selecting a semiconductor chip determined as a non-defective product as a product. 14. The connection between the test circuit module and the semiconductor chip to be tested is adjusted according to the size of the wafer on which the semiconductor chip is formed and the arrangement of the test circuit module and the electrode pads of the semiconductor chip. 14. The method for manufacturing a semiconductor integrated circuit device according to claim 13, wherein the method is performed by a probe means in which a wiring connecting between the conductive needle and a predetermined needle is formed. 15. The semiconductor integrated circuit according to claim 13, wherein the connection between the test circuit module and the semiconductor chip to be tested is performed by a wiring formed in a scribe area of a wafer or a wiring layer dedicated to the test. A method for manufacturing a circuit device. 16. The semiconductor integrated circuit according to claim 15, wherein the test wiring connecting the test circuit module and the semiconductor chip to be tested is formed so as to meander in a scribe area of a wafer. Device manufacturing method. 17. The test of a semiconductor chip on the wafer by the test circuit module is performed during a burn-in or aging process.
17. A method of manufacturing a semiconductor integrated circuit device according to any one of the above items. 18. The function of the semiconductor chip to be tested is described in a hardware description language, the hardware description and a test program are input to a hardware emulator, and simulation is performed by the hardware emulator for verification. While converting the data into logic gate level design data and generating the element level layout design data of the semiconductor chip to be tested based on the design data, while extracting the test function based on the data used in the simulation. Performing the test function in a hardware description language, converting the description into logic gate-level design data, and generating element-level layout design data of the test circuit module based on the design data. The above semiconductor chip to be tested A wafer mask is manufactured using the child-level layout design data and the element-level layout design data of the test circuit module, and the semiconductor chip to be tested and the test circuit module are combined into one wafer using the mask. The method for manufacturing a semiconductor integrated circuit device according to claim 13, wherein the semiconductor integrated circuit device is formed on the upper surface. 19. The semiconductor integrated circuit device according to claim 13, wherein said test circuit module generates a test signal to be supplied to a plurality of semiconductor chips disposed therearound. Manufacturing method. 20. The test system according to claim 2, wherein the test circuit tests a plurality of semiconductor chips formed on a semiconductor wafer. 21. The test system according to claim 20, wherein said test circuit comprises an FPGA or a microcomputer device. 22. The method of manufacturing a semiconductor integrated circuit device according to claim 13, wherein the test circuit module comprises:
A method of manufacturing a semiconductor integrated circuit device, comprising testing a plurality of semiconductor chips formed on the semiconductor wafer.