JP2001209366A - Sampling clock control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To optimize a phase of a clock by automatically generating a sampling clock of a cycle matching with pixel intervals of a video signal composed of the pixels in a sampling clock control circuit used for a video display device. SOLUTION: This sampling clock control circuit is provided with a PLL circuit 2 for generating a sampling clock and also varying the phase of the sampling clock, a display pixel number arithmetic circuit 6 for calculating the number of pixels of an input video signal, and a judging part 7 for setting a frequency dividing ratio on the basis of the number of pixels in a video area of the input video signal assumed from an input synchronizing signal and a frequency dividing ratio on the basis of the calculation result of the display pixel number arithmetic circuit 6, and by assuming the number of pixels of the input video signal in the video area by measuring the input synchronizing signal, and calculating the number of pixels of the video area by varying the phase of the sampling clock, the control circuit controls the sampling clock so as to let the calculated number of pixels in the video area match with the assumed number of pixels in the video area.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sampling clock control circuit, and more particularly to a means for reproducing a sampling clock corresponding to the number of pixels of an input video signal.

[0002]

2. Description of the Related Art In a conventional circuit in which the frequency of a sampling clock signal (dot clock signal) is automatically adjusted, especially when an input signal is formed based on pixels and has discrete information, Japanese Patent Laid-Open Publication No. As shown in JP-A-6-66752, a pixel cycle is detected from a video signal, a horizontal scanning cycle is detected from a horizontal synchronization signal, and P
The dot clock is reproduced by determining the frequency division ratio of the frequency division counter of the LL circuit.

[0003] With respect to a conventional dot clock reproducing circuit,
This will be described with reference to FIG. In FIG. 1, edge detection circuits 1-1, 1-2, and 1-3 detect edge information at a change point of a signal from an input video signal, and the cycle measurement circuits 2-1 to 2-2, and 2--3. Output to 3. Period measurement circuit 2-
1, 2-2 and 2-3 measure the frequency between the signal change points from the inputted edge information and output it to the arithmetic unit 4. The period measurement circuit generally has a configuration based on a method of counting intervals between change points included in edge information using a reference pulse, for example. The cycle measuring circuit 2-4 measures the frequency of the input horizontal synchronization signal and outputs the same to the arithmetic unit 4. Then, the arithmetic unit 4 performs the period measurement circuits 2-1, 2-2, 2-3.
Calculates the ratio between the change point interval of the signal measured in the above and the frequency of the horizontal synchronizing signal measured by the period measuring circuit 2-4, that is, the multiplication number, and sets this value as the dividing ratio of the PLL circuit 5. , A dot clock signal corresponding to the number of pixels of the input video signal is automatically generated.

[0004]

However, in the above-mentioned conventional configuration, the frequency is measured using the reference pulse for the edge detected from the input video signal, and when the cycle is calculated, the output of the edge detection circuit is used. If the method of counting the intervals between transition points with the reference pulse is used, the frequency of the reference pulse must be higher than the highest frequency included in the input video signal, and if the highest frequency of the input video signal becomes higher, If the frequency of the reference pulse needs to be increased and the period of the reference pulse is half or more of the shortest edge interval of the video signal, the accuracy of the calculation is reduced and the sampling clock may not be reproduced accurately. There was a problem. Therefore, the present invention has been made to solve the above problem, and an object of the present invention is to provide a sampling clock control circuit capable of accurately adjusting the frequency of a sampling clock to the number of pixels of an input signal.

[0005]

According to a first aspect of the present invention, there is provided a sampling clock control circuit in an apparatus for displaying a video signal on a display device having a unique number of pixels. Assuming the number of pixels in the video area of the video signal from the synchronization signal, calculate the number of pixels in the video area of the video signal from the sampling position information of the video area in the video signal, the calculated video area of the video area The sampling clock is controlled so that the number of pixels matches the number of pixels of the video area assumed from the synchronization signal.

According to a second aspect of the present invention, there is provided a sampling clock control circuit in an apparatus for displaying a video signal on a display device having a unique number of pixels, comprising: a synchronization signal comprising a horizontal synchronization signal and a vertical synchronization signal; A terminal for applying a video signal, means for detecting a video area of the video signal, means for assuming the number of pixels in the video area of the video signal from the synchronization signal, means for generating a sampling clock, and Means for generating a clock, means for setting a frequency division ratio based on the number of pixels in the video area of the video signal assumed from the synchronization signal, means for changing the phase of the sampling clock, and , Horizontal position information (horizontal address) that changes based on the sampling clock
Means for generating, and position information corresponding to pixels at both ends of a video area in the video signal in one horizontal synchronization period,
A dividing unit based on the number of pixels of the calculation result is set in the holding unit, the unit for calculating the number of pixels in the video area of the video signal based on the position information, and the unit for generating the sampling clock. Means for measuring the synchronization signal, assuming the number of pixels in the video area of the video signal, calculating the number of pixels in the video area by changing the phase of the sampling clock, and calculating the calculated video. The sampling clock is controlled so that the number of pixels in the region matches the number of pixels in the video region assumed from the synchronization signal.

According to a third aspect of the present invention, in the sampling control circuit according to the second aspect, the means for detecting a video area of the video signal comprises an analog comparator.

According to a fourth aspect of the present invention, in the sampling clock control circuit of the second aspect, the means for detecting a video area of the video signal comprises an A / D converter and a digital comparator. Features.

According to a fifth aspect of the present invention, in the sampling clock control circuit of the second aspect, the means for generating the sampling clock comprises a PLL circuit, and the position information (horizontal address) in the horizontal direction is provided. The means for generating ()) comprises a frequency divider of the PLL circuit.

According to a sixth aspect of the present invention, there is provided an image display apparatus including the sampling clock control circuit according to the second aspect.

[0011]

(Embodiment 1) Hereinafter, an embodiment of the present invention will be described with reference to FIGS. FIG. 2 is a block diagram of the entire sampling clock control circuit according to the embodiment of the present invention. First, a case where a video signal and a synchronization signal as shown in FIG. 3 are input to the sampling clock control circuit shown in FIG. 2 will be described. The video signal shown in FIG. 3 is one or more systems, and this video signal is supplied to the video detection circuit 3 in a state where the signal level of a non-signal portion is maintained at a constant value, for example, through a clamp circuit. The input synchronization signal includes a horizontal synchronization signal and a vertical synchronization signal.

In FIG. 2, a horizontal synchronizing signal and a vertical synchronizing signal applied to input terminals are supplied to an input signal measuring circuit 1. The input signal measuring circuit 1 measures the frequency of the horizontal synchronizing signal and the number of horizontal synchronizing signals (the number of lines) per vertical synchronizing period, and outputs them to the judging section 7 as input signal information. Hereinafter, the input signal information will be described.

FIG. 4 is a block diagram of the input signal measurement circuit 1. Reference numeral 10 denotes a reference clock generator, 11 denotes a horizontal synchronization frequency measurement circuit, and 12 denotes a line number measurement circuit. In FIG. 4, a reference clock having a predetermined frequency A [MHz] is output from a reference clock generation unit 10 and supplied to a horizontal synchronization frequency measurement circuit 11 in the input signal measurement circuit 1. The horizontal synchronization signal is supplied to the horizontal synchronization frequency measurement circuit 11.
And the vertical synchronization signal is supplied to the line number measuring circuit 12. Horizontal synchronization frequency measurement circuit 11
Is supplied to the horizontal synchronization signal by the differentiating circuit 11-1.
Differentiated based on the reference clock, and as a horizontal reference pulse of one clock width at a rate of once during one horizontal synchronization period,
It is supplied to a counter 11-2 and a latch circuit 11-3.
The counter 11-2 operates according to the reference clock. If the horizontal reference pulse from the differentiating circuit 11-2 is valid, the counter 11-2 outputs a count value 0 at the next reference clock after the horizontal reference pulse becomes valid. On the other hand, if the horizontal reference pulse from the differentiating circuit 11-2 is invalid, the count value increases by +1 according to the reference clock. That is, the counter 11-2
Is maximized when the horizontal reference pulse becomes valid, and the value becomes one smaller than the value obtained by dividing the horizontal synchronization period by the period of the reference clock. The horizontal reference pulse is also supplied to the latch circuit 11-3. The latch circuit 11-3 outputs and holds the count value input when the horizontal reference pulse becomes valid, that is, the maximum value B output by the counter 11-2. As described above, the horizontal synchronization frequency information is output from the horizontal synchronization frequency measurement circuit 11, and the horizontal synchronization frequency fH can be expressed by the following equation (Equation 1). fH = A * 1000 / (B + 1) [kHz] (Equation 1)

The vertical synchronizing signal input to the line number measuring circuit 12 is differentiated by a differentiating circuit 12-1 based on the supplied horizontal synchronizing signal, and is differentiated once during one vertical synchronizing period. As a vertical reference pulse having a width of one horizontal synchronization period (one line), the counter 12-2 and the latch circuit 12-
3 is supplied. The counter 12-2 operates according to the horizontal synchronization signal. If the vertical reference pulse from the differentiating circuit 12-1 is valid, the counter 12-2 outputs a count value 0 in the next horizontal synchronization period when the vertical reference pulse becomes valid. On the other hand, the differentiation circuit 1
If the vertical reference pulse from 2-1 is invalid, the count value increases by +1 according to the horizontal synchronization signal. That is, the count value output from the counter 12-2 becomes maximum when the vertical reference pulse becomes valid, and the value becomes one smaller than the value obtained by dividing the vertical synchronization period by the period of the horizontal synchronization signal. The vertical reference pulse is also supplied to the latch circuit 12-3. The latch circuit 12-3 counts the count value input when the vertical reference pulse becomes valid, that is, the counter 12
-2 outputs and holds the maximum value C output. As described above, the line number information is output from the line number measurement circuit 12, the number of horizontal synchronization signals (number of lines) in one vertical synchronization period is C + 1 [lines], and the vertical synchronization frequency fv is calculated by the following equation (equation). It can be expressed in 2). fv = fH / (C + 1) [Hz] (Expression 2)

As described above, in FIG. 2, the input signal measurement circuit 1 outputs the horizontal synchronization frequency information and the number of horizontal synchronization signals (the number of lines) in one vertical synchronization period as input signal information, and supplies them to the determination unit 7. You. Since the number of horizontal synchronization signals (the number of lines) in one vertical synchronization period can be calculated from the horizontal synchronization frequency information and the vertical synchronization frequency information, the same result is obtained by using the horizontal synchronization frequency information and the vertical synchronization frequency information as the input signal information. be able to.

FIG. 5 shows a block diagram of the PLL circuit 2. The PLL circuit 2 includes a phase comparator 20, an LPF 21,
A CO 22, a frequency divider 24, a delay circuit 23, etc.
A sampling clock having a cycle based on the frequency division ratio set by the determination unit 7 is generated and supplied to the video detection circuit 3 and the like. The sampling clock is delayed by the delay circuit 23 in accordance with the phase change amount set by the determination unit 7, and is output in a state where the phase of the pixel of the horizontal synchronization signal or the video signal has changed. Note that the delay circuit 23 can be realized by being set before the input terminal of the phase comparator 20 or being built in the frequency divider 24. The frequency divider 24 supplies horizontal position information (horizontal address) that changes based on the sampling clock with reference to the horizontal synchronization signal to the leftmost endpoint detection circuit 4 and the rightmost endpoint detection circuit 5. . Note that, except for using the frequency divider 24 of the PLL circuit 2 as means for generating horizontal position information (horizontal address),
In general, a method in which the address generation circuit is constituted by a counter or the like is used.

The image detecting circuit 3 is a means for detecting an image area of an input image signal. In this embodiment, a case where the image detecting circuit 3 includes an A / D converter and a digital comparator will be described. In the video detection circuit 3, the A / D converter performs A / D conversion (sampling and quantization) of the video signal based on the sampling clock supplied from the PLL circuit 2, and outputs the data to a digital comparator. The digital comparator compares the quantized data with a preset value D, and outputs a video determination signal that becomes “H” only when the quantized data is larger than the set value D. Note that the set value D is a value that is equal to or greater than the maximum value that can be taken by the non-signal portion of the video signal in the video signal in which the signal level of the non-signal portion has become constant through a clamp circuit or the like.

The image detection circuit 3 can also be constituted by an analog comparator or the like. In this case, when a set value D is input as a reference signal of the analog comparator and a video signal is input as a signal to be compared, a video signal Can be output when the signal level is higher than the set value D.

FIG. 6 shows the relationship between the synchronization signal, the video signal, the video determination signal, and the horizontal address as the horizontal position information in FIG. The value of the horizontal address output from the frequency divider 24 (counter) of the PLL circuit 2 is
When the synchronous portion of the horizontal synchronizing signal is input to the counter, it is reset to 0 in one clock period, and thereafter, the count value is incremented by +1 based on the clock until the synchronous portion is input again and reset. The video determination signal becomes “H” at a portion having a signal level larger than the non-signal portion of the video signal as described above.

The leftmost pixel of the video area during one horizontal synchronization period (line) is the point (HAmin) where the horizontal address becomes the minimum during the period when the video determination signal is "H" (video area) in FIG. . Since the relationship between the horizontal address and the display position is constant, the leftmost pixel in one screen of the video signal is a point where the horizontal address in one vertical period is the smallest.

The leftmost point detection circuit 4 is means for detecting and holding position information HAmin corresponding to the leftmost pixel of the video area in one horizontal synchronizing period in the entire display screen of the video signal. The minimum value that can be taken in the line is detected, and the minimum value during one vertical synchronization period is detected and held, and supplied to the display pixel number calculation circuit 6 as the leftmost point position information E.

The rightmost pixel of the video area in one line has the maximum horizontal address during the period when the video determination signal in FIG. 6 is "H" (video portion) (HAma).
x) points. Since the relationship between the horizontal address and the display position is constant, the rightmost point on one screen of the video signal is 1 point.
This is the point at which the horizontal address becomes the maximum during the vertical period.

The rightmost point detecting circuit 5 is means for detecting and holding the position information HAmax corresponding to the rightmost pixel in one horizontal synchronization period in the entire display screen of the video area of the video signal. The maximum value that can be taken in the line is detected, and the maximum value during one vertical synchronization period is detected and held, and supplied to the display pixel number calculation circuit 6 as the rightmost end point position information F.

The display pixel number calculation circuit 6 calculates the leftmost point position information E supplied from the leftmost point detection circuit 4 and the rightmost point position information F supplied from the rightmost point detection circuit 5 as follows: By substituting into Expression 3), the number G of display area pixels calculated by the sampling clock based on the frequency division ratio at the time of the above calculation is supplied to the determination unit 7. G = F−E + 1 (Equation 3)

The judging section 7 holds a combination of the input signal information supplied from the input signal measuring circuit 1 and the signal information assumed from the input signal information, and a video signal assumed from the input synchronization signal. And the standard value Y of the total number of pixels per line in the video area X.
Further, in order to change the phase of the sampling clock, the amount of phase change is set in the delay circuit 23 of the PLL circuit 2 and the frequency dividing ratio is set in the frequency divider 24 of the PLL circuit 2. Further, the phase of the sampling clock is changed for one division ratio, the average value H of the number of pixels in each display area is obtained, and the true value (division ratio) W of the total number of pixels in one horizontal synchronization period is calculated. Ask. The true value (division ratio) W of the total number of pixels in one horizontal synchronization period is J: H, where J is the current division ratio.
= W: X, it can be expressed by the following calculation formula (Formula 4). W = J * X / H (Equation 4)

Next, a description will be given of how the total number of pixels per one horizontal synchronization period of a video signal is obtained from the average value H of the number of pixels in the display area measured while changing the phase of the sampling clock. FIG. 7 is a diagram schematically showing the relationship between the sampling clock and the pixel of the video signal when the phase of the sampling clock is changed. In FIG. 7, the numerical value [%] indicates the distance between the arrow and the width of one pixel. The percentage is shown.

If the total number of pixels of the input video signal during one horizontal synchronization period is equal to the frequency division ratio set in the PLL circuit 2, the pixel interval of the video signal and the sampling as shown in FIG. Since the clock intervals are equal, the positional relationship between the two is constant. For example, when the sampling clock is at the position T1 with respect to the pixel immediately after the horizontal synchronization signal, the position of the sampling clock in all pixels is always T1.

When the frequency division ratio set in the PLL circuit 2 is smaller by 1 than the total number of pixels of the input video signal during one horizontal synchronization period, the interval of the sampling clock is longer than the interval of the pixels in the video area of the video signal. Therefore, the position of the sampling clock with respect to the pixels in the video area is gradually delayed, for example, one pixel is delayed from T1 to T2 per one horizontal synchronization signal period as shown in FIG. Since the video area of the input video signal is about 80% of one horizontal synchronization period, the phase of the sampling clock is delayed by about 80% of one pixel between the leftmost point and the rightmost point of the video area. If the phase of the sampling clock at the leftmost point of the video area is within the range of 20% of one pixel from the leftmost point of the pixel, the sampling at the position of T3 at the leftmost point of the video area as shown in FIG. The clock moves to T4 at the rightmost point. Therefore, in this case, although the position of the sampling clock with respect to the pixels in the video area is gradually delayed, the phase of the sampling clock at the leftmost point of the video area is in the range from the left end of the pixel to 20% of one pixel, so that The next right sampling clock always points to the next right pixel. That is, although the period of the sampling clock is not equal to the pixel interval of the video signal, the number of sampled video regions of the video signal is determined by the determination unit 7 in the video region of the input video signal assumed from the input synchronization signal. It becomes equal to the number of pixels.

When the frequency division ratio set in the PLL circuit 2 is larger than the total number of pixels of the input video signal during one horizontal synchronization period by 1, the interval of the sampling clock becomes shorter than the interval of the pixels of the video signal. The position of the sampling clock for the pixel of the signal gradually advances, for example, from T2 to T1 per one horizontal synchronization period as shown in FIG.
When the phase of the sampling clock at the leftmost point of the video area is within the range of 20% of one pixel from the rightmost pixel, the pixel moves from T4 to T3 as shown in FIG. Become. Therefore, the number of samplings of the video area of the video signal is equal to the number of pixels of the video area of the input video signal assumed by the determination unit 7 based on the input synchronization signal.

The division ratio set in the PLL circuit 2 is smaller by 1 than the total number of pixels of the input video signal during one horizontal synchronization period, and the phase of the sampling clock at the leftmost point of the video area is one pixel from the left end of the pixel. If it is not within the range of 20%, the sampling clock interval becomes longer than the pixel interval of the video signal. Therefore, as shown in FIG. Move to T6 at the rightmost end point of the video area. If the phase of the sampling clock gradually points to the right end of the pixel during the display area period, the sampling clock interval is longer than the pixel interval. Refers to the next pixel. Therefore, the number of samples of the video area of the video signal is smaller than the number of pixels of the video area of the video signal assumed by the input synchronization signal by one.

Further, the frequency division ratio set in the PLL circuit 2 is larger than the total number of pixels of the input video signal during one horizontal synchronization period by 1, and the phase of the sampling clock at the leftmost point of the video area is shifted from the rightmost pixel. If the pixel is not within the range of 20% of one pixel, the sampling clock interval is shorter than the pixel interval. Therefore, as shown in FIG. Move to T5 at the rightmost point of. When the phase of the sampling clock gradually advances during the video display area period and points to the left end of the pixel, the sampling clock interval is shorter than the pixel interval, so the sampling clock on the right side also indicates the same pixel. Therefore, the number of samples of the video area of the video signal is increased by one from the number of pixels of the video area of the video signal assumed from the input synchronization signal.

The case where the total number of pixels of the input video signal during one horizontal synchronization period is different from the frequency division ratio of the PLL circuit by 2 or more can be considered in the same manner as described above, and the phase of the sampling clock at the leftmost point of the video area is The number of samples of the video area when it is within the range of 20% from the boundary is different from the number of samples of the video area when the phase of the sampling clock at the leftmost point is within the remaining 80%. Therefore, an error occurs when a numerical value sampled at one phase is used.

The sampling numbers of the video area and the non-video area in the input video signal can be expressed by an integer ratio. If the total number of pixels of the input video signal during one horizontal synchronization period is not equal to the division ratio set in the PLL circuit 2, the video signal is sampled with a clock having a cycle different from the cycle of the pixels in the signal. In this case, the sampling number of the video area and the non-video area is represented by an integer ratio, but to be exact, the same ratio as the integer ratio of the number of pixels of the video signal. The average value of the number of samplings of the video area measured while changing the phase of the sampling clock means that the video signal area portion having this integer ratio is obtained. The smaller the phase change amount of the sampling clock is with respect to the pixel interval, the higher the accuracy is. However, the average value of the number of sampled image areas of the video signal is obtained by changing the phase at an interval of 1/3 or less in one pixel. In this case, the precision of the sampling number of the image area increases by one or more digits, and the precision of the first decimal place in the proportional calculation by (Equation 4) increases. Therefore, the frequency division obtained by rounding the result of (Equation 4) is obtained. The ratio will be an accurate value.

Next, an operation when a video signal and a synchronization signal as shown in FIG. 8 are newly input to the sampling clock control circuit according to the embodiment of the present invention will be described. In FIG. 8, the number of lines in one vertical synchronization period is seven, and 3H of line numbers 3 to 5 is a vertical video period. One horizontal synchronization period is composed of 14 pixels. The non-signal portion is a total of one pixel in the synchronization period, one pixel in the front porch on the left side of the synchronization period, and one pixel in the back porch on the right side of the synchronization period. The image area is composed of three pixels, and a signal in which “H” and “L” are repeated for each pixel from the left end for 11 pixels is present in all lines in a vertical video period of three RGB systems.

The horizontal synchronizing signal and the vertical synchronizing signal applied to the input terminals are input to the input signal measuring circuit 1. According to (Equation 1), fH is output from the horizontal synchronization frequency measurement circuit 11 as the horizontal synchronization frequency information, 7 [lines] is output from the line number measurement circuit 12 as the line number information, and supplied to the determination unit 7 as input signal information. You.

The judging unit 7 obtains, as input signal information, the number of pixels 11 of the image area of the image signal assumed from the input synchronization signal and the standard value 13 of the total number of pixels per line. Thereafter, the determination unit 7 sets the total number of pixels 13 as the frequency division ratio in the frequency divider 24 of the PLL circuit 2.

When "0" is set as the phase change amount in the delay circuit 23, the sampling clock and the horizontal address are output from the PLL circuit 2 based on the setting. The video signal is A / D-converted by the video detection circuit 3 in accordance with the sampling clock, and the digital comparator outputs a video determination signal which becomes "H" at a signal level larger than the non-signal portion. Since there is no video signal in line numbers 0 to 2 and 6 in FIG. 8, the video determination signal in this period is always “L” during one horizontal synchronization period. FIG. 9A shows the relationship between the sampling clock, the video signal, the video determination signal, and the horizontal address in the video detection circuit 3 during the line numbers 3 to 5. First, if the line number is 3
During the third period, the leftmost point detection circuit 4 detects the minimum address 2 in which the video determination signal becomes 'H' among the three systems since the video determination signal of FIG. . Also, the minimum address 2 is similarly detected during the fourth and fifth line numbers. At the end of the vertical display period, that is, at the time of input of the next vertical synchronization signal, the minimum address 2 in one vertical synchronization period is set as the leftmost point position information.
Is output to the display pixel number calculation circuit 6. Similarly, during the third period of the line number, the rightmost point detection circuit 5
Since the video determination signal of (a) is input into three RGB systems,
The maximum address 12 at which the video determination signal becomes "H" is detected among the three systems. The maximum address 12 is similarly detected during the fourth and fifth line numbers. And
At the end of the vertical display period, that is, when the next vertical synchronization signal is input, the maximum address 12 in one vertical synchronization period is output to the display pixel number calculation circuit 6 as the rightmost point position information.
After that, the display pixel number calculation circuit 6 calculates (Equation 3) from the minimum address 2 and the maximum address 12, and outputs the display area pixel number 11 to the determination unit 7.

The determination unit 7 holds the measured value 11 of the number of pixels in the display area when the phase change amount is “0”, and sets the PLL so that the phase change amount is delayed from the set value “0” by one-fourth of one pixel. When set in the delay circuit 23 of the circuit 2, P
The sampling clock and the horizontal address are output from the LL circuit 2. The video determination signal output from the video detection circuit 3 is always “L” in the line numbers 0 to 2 and 6 in FIG. 8, and the sampling clock and the video signal in the video detection circuit 3 in the period of the line numbers 3 to 5 FIG. 9B shows the relationship among the image determination signal and the horizontal address. Similarly to the above, during the period in which the line number is the third, the leftmost point detection circuit 4 receives the video determination signal of FIG. 'Is detected. Also, the minimum address 2 is similarly detected during the fourth and fifth line numbers. Then, at the end of the vertical display period, that is, at the time of inputting the next vertical synchronization signal, the minimum address 2 in one vertical synchronization period is output to the display pixel number calculation circuit 6 as the leftmost point position information. Similarly, if the line number is 3
During the third period, the rightmost point detection circuit 5 detects the maximum address 11 where the video determination signal is 'H' among the three systems because the video determination signal of FIG. . The maximum address 11 is also detected during the fourth and fifth line numbers. Then, at the end of the vertical display period, that is, at the time of input of the next vertical synchronization signal, the maximum address 11 in one vertical synchronization period is set as the rightmost point position information.
Is output to the display pixel number calculation circuit 6. After that, the display pixel number calculation circuit 6 calculates (Equation 3) from the minimum address 2 and the maximum address 11, and outputs the display area pixel number 10 to the determination unit 7.

The determination unit 7 holds the measured value 10 of the number of pixels in the display area in the case where it is delayed from the initial value '0' by 1/4 of one pixel as the phase change amount, and sets the phase change amount to the set value '0'. Is set in the delay circuit 23 of the PLL circuit 2 so as to be delayed by two quarters of one pixel from P.
The sampling clock and the horizontal address are output from the LL circuit 2. The video determination signal output from the video detection circuit 3 is always “L” in the line numbers 0 to 2 and 6 in FIG. 8, and the sampling clock and the video signal in the video detection circuit 3 in the period of the line numbers 3 to 5 9 (c), the relationship between the leftmost point detection circuit 4 and the video determination signal and the horizontal address is as shown in FIG.
Outputs the minimum address 2 in one vertical synchronization period to the display pixel number calculation circuit 6 as the leftmost point position information at the end of the vertical display period, and the rightmost point detection circuit 5 The maximum address 11 during one vertical synchronization period is output to the display pixel number calculation circuit 6 as the rightmost point position information. Then, the display pixel number calculation circuit 6 calculates the minimum address 2
And the maximum address 11 to calculate (Equation 3), and output the display area pixel number 10 to the determination unit 7.

The judging section 7 holds the measured value 10 of the number of pixels in the display area in the case where it is delayed from the initial value '0' by 2/4 of one pixel as the phase change amount, and sets the phase change amount to the set value '0'. Is set in the delay circuit 23 of the PLL circuit 2 so as to be delayed by 3/4 of one pixel from P.
The sampling clock and the horizontal address are output from the LL circuit 2. The video determination signal output from the video detection circuit 3 is always “L” in the line numbers 0 to 2 and 6 in FIG. 8, and the sampling clock and the video signal in the video detection circuit 3 in the period of the line numbers 3 to 5 9 (d), the relationship between the leftmost point detection circuit 4 and the video determination signal and the horizontal address is as shown in FIG.
Outputs the minimum address 2 in one vertical synchronization period to the display pixel number calculation circuit 6 as the leftmost point position information at the end of the vertical display period, and the rightmost point detection circuit 5 The maximum address 11 during one vertical synchronization period is output to the display pixel number calculation circuit 6 as the rightmost point position information. Then, the display pixel number calculation circuit 6 calculates the minimum address 2
And the maximum address 11 to calculate (Equation 3), and output the display area pixel number 10 to the determination unit 7.

The judging unit 7 holds the measured value 10 of the number of pixels in the display area when the amount of phase change is delayed by three quarters of one pixel from the initial value '0', and sets the phase of the sampling clock to one quarter. Calculating the average value of the number of pixels in the display area when changing pixel by pixel gives (11 + 10 + 10 + 10) /
4 = 10.25. Therefore, the total number of pixels of the input signal is 13 * 11 / 10.25 = 13.9 from (Equation 4).
5, rounded to 14

Next, a description will be given of a case where a video signal composed of the same number of pixels as the number of pixels in the video area of the input video signal assumed from the input synchronization signal and the total number of pixels per horizontal synchronization period is input. I do. In this case, the interval of the sampling clock and the interval of the pixel of the input video signal become equal, and the pixel of the video signal and the sampling clock always keep the same phase relationship. Therefore, as shown in FIG. When the pixel is not at the pixel boundary, the number of samples of the video area matches the assumed number of pixels of the video area of the input video signal. However, when the sampling clock is near the pixel boundary of the video signal, FIG.
As shown in (b), the quantized data at the sampled point may be a threshold value for determining a signal portion and a non-signal portion. The data corresponding to the even-numbered sampling points in FIG. 10B may be determined to be a video signal and output “H”, or may be determined not to be a video signal and output “L” ( The video determination signal in the figure indicates that there is a possibility of outputting “H” and “L”.)
The number of sampled video areas may be shifted by ± 1 from the assumed number of pixels of the video area of the input video signal. In this case, the reason why the number of pixels of the video area of the input video signal assumed to be different from the number of sampled video areas is because the phase of the sampling clock is only one point near the boundary in the pixel of the video signal, The value obtained by rounding the average value of the number of sampled video regions by changing the phase of the clock at intervals of one third or less of one pixel matches the assumed number of pixels of the video region of the input video signal.

[0043]

As described above, according to the sampling clock control circuit of the present invention, the input synchronization signal is measured, the number of pixels in the video area of the input video signal is assumed, and the sampling clock (the input video signal By calculating the number of pixels in the video area by changing the phase (with respect to the pixels), sampling is performed so that the calculated number of pixels in the video area matches the number of pixels in the video area assumed from the input synchronization signal. The clock can be controlled, and the frequency of the sampling clock can be accurately adjusted to the number of pixels of the input video signal.

[Brief description of the drawings]

FIG. 1 is a block diagram of a dot clock (sampling clock) reproducing circuit according to a conventional embodiment.

FIG. 2 is an overall block configuration diagram of a sampling clock control circuit according to the embodiment of the present invention.

FIG. 3 is a diagram schematically showing a video signal and a synchronization signal input to a sampling clock control circuit according to the embodiment of the present invention.

FIG. 4 is a block diagram of an input signal measurement circuit of the sampling clock control circuit according to the embodiment of the present invention.

FIG. 5 is a block diagram of a PLL circuit of the sampling clock control circuit according to the embodiment of the present invention.

FIG. 6 is a diagram illustrating a relationship among a synchronization signal, a video signal, a video determination signal, and a horizontal address in FIG. 2 according to the embodiment of the present invention.

FIG. 7 is a diagram schematically showing a phase relationship between a pixel of an input video signal and a sampling clock in the embodiment of the present invention.

FIG. 8 is a diagram schematically showing an input signal for explaining an operation when a signal is input to the sampling clock control circuit according to the embodiment of the present invention.

FIG. 9 is a diagram schematically illustrating a relationship between a video signal, a sampling clock, and a video determination signal when the phase of the sampling clock is changed in the video detection circuit of the sampling clock control circuit according to the embodiment of the present invention.

FIG. 10 is a diagram illustrating an example of a configuration of a sampling clock control circuit according to an embodiment of the present invention. In the sampling clock control circuit, a video signal having a value equal to the number of pixels in a video area assumed from an input synchronization signal and the total number of pixels per horizontal synchronization period is input. FIG. 4 is a diagram schematically showing a relationship among a video signal, a sampling clock, and a video determination signal for explaining an operation in a case where the video signal is determined.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input signal measurement circuit 2 PLL circuit 3 Video detection circuit 4 Leftmost point detection circuit 5 Rightmost point detection circuit 6 Display pixel number calculation circuit 7 Judgment unit 10 Reference clock generation unit 11 Horizontal synchronization frequency measurement circuit 12 Line number measurement circuit 20 Phase comparator 21 LPF 22 VCO 23 Delay circuit 24 Divider 11-1, 12-1 Differential circuit 11-2, 12-2 Counter 11-3, 12-3 Latch circuit

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Koichi Yamazaki 1 Koshinmachi, Takamatsu City, Kagawa Prefecture 1 F-term (reference) in Matsushita Hisashi Denshi Kogyo Co., Ltd. 5C020 AA01 AA17 AA35 CA13 CA15 CA20 5C080 BB05 DD09 JJ02 JJ04 5C082 AA01 CA85 CB01 DA76

Claims (6)

[Claims] A sampling clock control circuit in an apparatus for displaying a video signal on a display device having a unique number of pixels, wherein the number of pixels in a video area of the video signal is assumed from an input synchronization signal, The number of pixels of the video area of the video signal is calculated from the sampling position information of the video area, and sampling is performed so that the calculated number of pixels of the video area matches the number of pixels of the video area assumed from the synchronization signal. A sampling clock control circuit for controlling a clock. 2. A sampling clock control circuit in a device for displaying a video signal on a display device having a unique number of pixels, a terminal for applying a synchronization signal comprising a horizontal synchronization signal and a vertical synchronization signal, and a video signal; Means for detecting a video area of the video signal; means for estimating the number of pixels of the video area of the video signal from the synchronization signal; means for generating a sampling clock; and means for generating the sampling clock. Means for setting a frequency division ratio based on the number of pixels in the image area of the image signal assumed from: means for changing the phase of the sampling clock; and based on the horizontal synchronization signal, based on the sampling clock. Means for generating changing horizontal position information (horizontal address); and the image for one horizontal synchronization period Means for detecting and holding position information corresponding to pixels at both ends of the video area in the signal, means for calculating the number of pixels in the video area of the video signal based on the position information, and means for generating the sampling clock. Means for setting a frequency division ratio based on the number of pixels of the calculation result, and by measuring the synchronization signal, assuming the number of pixels in a video area of the video signal, and changing the phase of the sampling clock. Calculating the number of pixels of the video area by controlling the sampling clock so that the calculated number of pixels of the video area matches the number of pixels of the video area assumed from the synchronization signal. Clock control circuit. 3. The sampling clock control circuit according to claim 2, wherein said means for detecting a video area of said video signal comprises an analog comparator. 4. The sampling clock control circuit according to claim 2, wherein the means for detecting a video area of the video signal comprises an A / D converter and a digital comparator. 5. The sampling clock control circuit according to claim 2, wherein the means for generating the sampling clock comprises a PLL circuit, and the position information (horizontal address) in the horizontal direction.
Wherein the means for generating the clock signal comprises a frequency divider of the PLL circuit. 6. An image display device comprising the sampling clock control circuit according to claim 2.