JP2001202391A - Simulation method for logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a simulation method for a logic circuit, with which a time for simulation to be performed after a change applied only to the block of one part is shortened in the simulation of a logic circuit composed of plural blocks. SOLUTION: In the simulation for inputting circuit information 101 and a test pattern 102, when only the block designated by block designation information 105 is changed, by using information 103 and 104 of signals prepared in previous simulations, a simulation time is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of simulating a logic circuit using a computer, and provides a method for shortening the simulation time of the operation of the logic circuit.

[0002]

2. Description of the Related Art Conventionally, logic verification is performed by performing a computer simulation on a logic circuit to be verified. Further, as a technique for analyzing a result during a simulation, a method for storing information during a simulation and reproducing the state during the simulation by using the information after the simulation is disclosed (Japanese Patent Laid-Open No. 4-42371). ,
JP-A-4-76775).

[0003]

In a simulation of a logic circuit, when performing logic verification of a large-scale logic circuit,
The simulation time becomes very long. For this reason, when debugging a logic circuit, information during the simulation is saved, and after the simulation is executed, the information during the simulation is used to reproduce the state during the simulation. I have.

However, in this method, if a part of the logic circuit is changed, the stored information cannot be used, and it is necessary to execute the simulation again.

[0005] Recently, by performing a reusable design using verified design data such as design data designed in the past, the ratio of a debug target circuit which may be changed to a logic circuit to be simulated is changed. Is getting smaller. In such a case, when the simulation is performed again after the debug target circuit is changed, the same operation as the previous simulation is simulated in many parts of the logic circuit to be simulated, resulting in an extra simulation.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to compare a past simulation with a simulation performed after making a change to a debug target circuit which is a part of a logic circuit to be simulated. It is an object of the present invention to provide a method of simulating a logic circuit that can omit redundant simulations and reduce the simulation time.

[0007]

A method of simulating a logic circuit according to claim 1 is a method of simulating a logic circuit comprising a plurality of blocks, excluding the internal signal information of one predetermined debug target block. During the simulation performed after saving the signal information during execution and making changes to the debug target block, the logic circuit is separated into the debug target block and the circuit excluding the debug target block, and based on the signal information saved from the simulation initial time. Performs a partial simulation of the debug target block, compares the signal information of the partial simulation with the stored signal information, terminates the partial simulation if the comparison result does not match, and ends the signal information of the partial simulation and the stored signal information. Matched It is characterized in that the simulation of all the blocks from simulation time.

According to the logic circuit simulation method of the present invention, signal information is stored during the execution of the simulation, and the logic circuit is debugged during a simulation performed after a change is made to one debug target block specified in advance. The block and the peripheral circuit excluding the debug target block are separated, and part of the simulation of the peripheral circuit is omitted using the stored signal information. Therefore, 1
During the simulation performed after making changes to one of the blocks, the information saved during the simulation is used to change the output signal of the changed block until the difference from the previously executed simulation occurs. It is possible to omit a part of the simulation for the part not added, and to shorten the entire simulation time of a large-scale logic circuit, for example.

According to a second aspect of the present invention, there is provided a method for simulating a logic circuit comprising a plurality of blocks, wherein the signal information during the execution of the simulation is stored, and the simulation is performed after the block to be debugged is changed. At the time, the logic circuit is separated into a debug target block and a circuit excluding the debug target block, a partial simulation of the debug target block is performed based on the signal information stored from the initial time of the simulation, and the signal information of the partial simulation and the stored signal information are compared. And if the comparison result is inconsistent, terminate the partial simulation, and perform simulation of all blocks from the simulation time when the signal information of the partial simulation and the stored signal information finally match. Than it is.

According to the logic circuit simulation method of the second aspect, the same effect as that of the first aspect is obtained.

According to a third aspect of the present invention, there is provided a method for simulating a logic circuit including a plurality of blocks, wherein when a plurality of debug target blocks specified in advance exist, a part or all of the blocks are changed. At the time of the simulation performed after the addition, the plurality of blocks including the changed block are reconfigured as one block, and the logic circuit is separated into the reconfigured block and the circuit excluding the blocks included in the reconfigured block, Except for the internal signal information of the reconstructed block, save the signal information during the execution of the simulation, perform a partial simulation of the debug target block based on the saved signal information from the initial time of the simulation, and obtain the signal information of the partial simulation and the saved signal information. And the comparison results do not match There the exit portion simulation, in which the signal information stored signal information of partial simulation and performing a simulation of all the blocks from the last matching simulated time.

According to the logic circuit simulation method of the third aspect, when there are a plurality of debug target blocks to which a change can be made, the change is made at the time of the simulation performed after making a change to a part or all of the blocks. A plurality of blocks including blocks are reconfigured as one block, a logic circuit is separated into a reconfigured block and a circuit excluding blocks included in the reconfigured block, and a part of the simulation is saved using the stored signal information. Omitted.
Therefore, during the period until the difference between the output signal of the reconstructed block and the previously executed simulation occurs, part of the simulation for circuits other than the reconstructed block can be omitted. The entire circuit simulation time can be reduced.

According to a fourth aspect of the present invention, there is provided a method for simulating a logic circuit including a plurality of blocks, wherein signal information is stored during execution of the simulation, and a plurality of debug target blocks designated in advance exist. In such a case, a plurality of blocks including the changed block are reconfigured as one block during a simulation performed after a change is made to a part or all of the block, and a logic circuit is reconfigured as a reconfigured block. Blocks are separated into circuits excluding the blocks included in the block, a partial simulation of the debug target block is performed based on the signal information saved from the simulation initial time, and the signal information of the partial simulation is compared with the saved signal information. If there is a mismatch, the partial simulation ends. And one in which signal information stored signal information of partial simulation and performing a simulation of all the blocks from the last matching simulated time.

According to the logic circuit simulation method of the fourth aspect, the same effect as that of the third aspect is obtained.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) A first embodiment of the present invention corresponding to claims 1 and 2 will be described with reference to FIGS.

FIG. 1 is a diagram showing a configuration of a simulation method according to claim 1. In FIG. 1, reference numeral 101 denotes circuit information of a logic circuit including a plurality of blocks to be simulated, and 102 denotes a logic circuit 1 at the time of simulation.
01 is a test pattern given as an input, 103 is circuit state information storing the state of a previously executed logic circuit in the middle of a simulation, 104 is a signal storing changes in input / output signals of a debug target block in a previously performed simulation Change information 105 is block designation information for designating a debug target block from the logic circuit;
6 is circuit information 101, test pattern 102, circuit state information 103, signal change information 104, and block designation information 1
Simulation was performed using the circuit status information 1
03 and a simulation means for updating the signal change information 104. However, the test pattern 102 and the block designation information 105 cannot be changed for each simulation, and the input / output signals of the debug target block cannot be changed.

Here, the simulation means 106
From the circuit information 101 of the logic circuit to the block designation information 105
A partial circuit simulation means 107 for selecting a debug target block specified by the above and performing a simulation using the circuit information of the selected block and the signal change information 104; a logic circuit 101 and logic circuit state information 103
Circuit state reproducing means 10 for reproducing the state of the peripheral circuit excluding the debug target block during the simulation using
8 and a whole circuit simulation means 109 for continuing the simulation using the test pattern 102 and the state of the whole circuit created by using the circuit state created by the partial circuit simulation means 107 and the circuit state reproduction means 108. I have.

FIG. 2 is a flowchart showing a simulation method performed by the partial circuit simulation means 107 of FIG. In FIG. 2, step 201 is a circuit extraction process for selecting a logic circuit of a block designated by block designation information 105 from circuit information 101 of the logic circuit, and step 202 is whether the signal change information 104 used as an input signal has reached the end. End determination processing for determining whether or not the simulation has been completed and ending the simulation when the end has been reached; step 203, a signal input processing for reading an input signal included in the signal change information 104 at the simulation time and registering a signal change as an event; It is determined whether there is an unprocessed event at the simulation time. If there is an unprocessed process, the process proceeds to step 205. If there is no unprocessed event, the process proceeds to step 206. Is an event that performs processing on unprocessed events Preparative process, step 206 is comparing process for comparing the output signal included in the output signal and the signal change information 104 of the block, step 207
Is a time update process for advancing the simulation time.

FIG. 3 is a flowchart showing the processing performed by the circuit state reproducing means 108 of FIG. In FIG. 3, step 301 is a block deletion process for deleting the debug target block specified by the block specification information 105 from the circuit information 101 of the logic circuit, and step 302 is a time before and closest to the simulation end time of the partial circuit simulation means 107. Circuit state reading processing for reading the circuit state information from the circuit state information 103,
Step 303 is a circuit state information selection process for deleting information on the debug target block designated by the block designation information 105 from the circuit state information selected in the circuit state selection process of step 302, and step 304 is selected by the block deletion process of step 301. Using the circuit state selected by the circuit state selection processing of step 303 and the output signal of the deleted block obtained from the test pattern 102 and the signal change information 104, the simulation up to the simulation end time of the partial circuit simulation means 107 is performed. This is a peripheral circuit simulation process to be performed. However, if the logic circuit state information selection processing in step 303 cannot obtain the logic circuit information that meets the conditions, the initial state of the circuit is used in the peripheral circuit simulation processing in step 304.

FIG. 4 is a flowchart showing the processing performed by the overall circuit simulation means 109 of FIG. In FIG. 4, a step 401 simulates the entire simulation target circuit by combining the mid-simulation state of the debug target circuit created by the partial circuit simulation means 107 and the mid-simulation state of the peripheral circuit created by the circuit state reproduction means 108. An overall circuit state synthesizing process for creating an intermediate state. Step 402 is an end determining process for determining whether the simulation has reached an end time and terminating the process if the end time has been reached. Step 403 is a test pattern 102.
Signal input processing for reading the input of the simulation time from
04 determines whether there is an unprocessed event at the simulation time, and if there is an unprocessed process, step 40
Proceed to the processing of step 5 and if there is no unprocessed processing, step 4
Event determination processing for proceeding to the processing of step 06, step 405 is event processing for processing an unprocessed event, step 406 is signal change information updating processing for outputting the input / output signal change of the debug target block and updating the signal change information 104, Step 407 is a circuit state information update process for periodically outputting the circuit state and updating the logic circuit state information 103, and step 408 is a time update process for advancing the simulation time.

Next, the simulation method according to the first embodiment will be specifically described using a simple example.
FIG. 5 shows an example of circuit information 101 of a logic circuit to be simulated. The entire logic circuit 501 is composed of two logic circuit blocks, a block BLK1 (502) and a block BLK2 (503). As shown in FIG. 5, the logic circuit block BLK1 includes a flip-flop 504, AND gates 505 and 506, an OR gate 507, and a NOT gate 508. The logic circuit block BLK2 includes a flip-flop 509, 510 and AND gates 511 and 512. In addition, each signal line has A
ＭM. FIG. 6 is an example of a test pattern 102 given as an input signal to the entire logic circuit 501, and a test pattern for the input signal of the circuit information 101 of the logic circuit shown in FIG. 5 is given. FIG.
Is an example of the block designation information 105, and the entire logic circuit 5
The block BLK1 (502) in 01 is designated as a debug target block (TARGET).

In the first simulation, the signal change information 104 and the logic circuit state information 103 do not exist. For this reason, the partial circuit simulation unit 107 does not proceed with the simulation for the block BLK1 selected using the block designation information (FIG. 7) from the entire logic circuit 501, and executes the entire circuit simulation of the block BLK1 in the initial state. Hand over to means 109. Also, since the partial circuit simulation means 107 has not proceeded with the simulation, the logic circuit state reproduction means 108 also passes the initial state to the whole circuit simulation means 109 without proceeding with the simulation of the peripheral circuit. Then, the whole circuit simulation means 109
The state of the entire circuit is created by matching the state of the block BLK1 with the state of the peripheral circuit, a simulation is performed using the test pattern (FIG. 6) according to the method shown in FIG. 4, and the signal change of the input / output signal of the block BLK1 shown in FIG. Information 104
And the logic circuit state information 103 shown in FIG. However, in this example, the initial value of the output value of each flip-flop is 0. In addition, the signal change information 104 is created for each constant simulation time. In FIG. 8, a value 901 of each signal line at the simulation time T1 and a value 902 of each signal line at the simulation time T2 are recorded. .

Next, after correcting the debug target block BLK1, a second simulation is performed. FIG.
Is an example of the entire logic circuit 1001 to be simulated for the second time. The block BLK1 (502) is changed to the block BLK1 (1002) for the circuit to be simulated first (FIG. 5). Block BLK2 (1003) has not been changed. Also,
Since the test pattern 102 and the block designation information 105 cannot be changed, the same one as in the previous simulation (FIGS. 6 and 7) is used, and the signal change information 104 and the logic circuit state information 103 are created in the previous simulation. (FIGS. 8 and 9) are used.

In response to these inputs, the partial circuit simulation means 107 causes the entire logic circuit 1001 (FIG. 1).
A simulation is performed on the block BLK1 (1002) selected from 0) using the block designation information (FIG. 7) according to the method of FIG. At this time, block BL
For input signals A, B, D, and E of K1 (1002), the value of the corresponding signal of the signal change information (FIG. 8) is given as a test pattern. As a result of the simulation, the output signal of the block BLK1 (1002) is shown in FIG.
However, since the difference from the signal 1101 of the signal change information (FIG. 8) occurs at time T3, the simulation by the partial circuit simulation means 107 ends at time T3.

Next, using the method shown in FIG. 3, the logic circuit state reproducing means 110 reproduces the state during the simulation of the circuit excluding the block BLK1 (1002) from the entire circuit (FIG. 10). At this time, since the simulation end time at the partial circuit simulation means 107 is T3, state information (902) at time T2 closest to T3 is selected from information before T3 from the logic circuit state information (FIG. 9). Used. Then, the simulation up to time T3 is executed using the signals C and D of the test pattern (FIG. 6) and the signal F of the signal change information (FIG. 8) as input signals. Finally, the whole circuit is simulated by the whole circuit simulation means 109 using the method shown in FIG.

In the above example, when the circuit size of the entire logic circuit 1001 is X and the circuit size of the debug target circuit block 1002 is Y, and the time required for the simulation is proportional to the circuit size, the circuit state information (FIG. 9) ), The simulation time up to time T3 of the second simulation is (X × T3 + (Y−X) × (T3-T2)) /
(Y × T3). At this time, for example, X: Y = 1: 1
0, T3: T2 = 10: 9, the time T1
It can be seen that the simulation time up to 0.19 times the simulation time is significantly reduced.

As described above, according to the first embodiment of the present invention, the simulation method according to the first and second aspects of the present invention designates a block to be debugged and creates information during the simulation. By using the obtained information, it is possible to reduce the simulation time when performing a simulation using the same test pattern after making a change to the debug target block.

In this example, a simulation without a wiring delay or a gate delay has been described as an example. However, it goes without saying that a simulation including these can also shorten the simulation time.

(Second Embodiment) In a second embodiment, the invention according to claims 3 and 4 will be described with reference to FIG.
This will be described with reference to FIG.

FIG. 12 is a diagram showing the configuration of the simulation method according to the third and fourth aspects. In FIG. 12, reference numeral 1201 denotes circuit information of a logic circuit including a plurality of blocks to be simulated; 1202, a test pattern provided as an input to the circuit information 1201 of the logic circuit at the time of simulation; 1203, a state of the previously executed logic circuit during the simulation; 1204 is signal change information that stores the change of the input / output signal of the debug target block in the simulation performed before, and 1205 is the change in the debug target block from the logic circuit after the previous simulation. The block designating information 1206 for designating the added block is obtained by performing a simulation using the circuit information 1201, the test pattern 1202, the logic circuit state information 1203, the signal change information 1204, and the block designating information 1205 as input information. Circuit status information 1203 and the signal change information 1204
Is a simulation means for updating. However, the block to which the change specified by the block specification information 1205 has been added needs to be included in the debug target block, and the debug target block cannot be changed for each simulation. Also, the test pattern 1202 and the block designation information 1205 cannot be changed for each simulation, and the input / output signals of the debug target block cannot be changed.

Here, the simulation means 1206
Is a block reconfiguration unit 12 that selects a changed block specified by the block specification information 1205 from the circuit information 1201 of the logic circuit and forms a new block.
07, a partial circuit simulation unit 1208 for simulating the block created by the block reconfiguration unit 1207 using the circuit information of the selected block and the signal change information 1204, the circuit information 1201 of the logic circuit, and the logic circuit state information A circuit state reproducing means 1209 for reproducing a state of a logic circuit other than a block to be debugged during a simulation of a logic circuit except for a block to be debugged;
An entire circuit simulation means 1210 for continuing the simulation using the state of the entire logic circuit created using the state of the logic circuit created in step 09 and the test pattern 1202 is provided.

Next, a simulation method according to the second embodiment will be specifically described using a simple example.
FIG. 13 is an example of circuit information 1201 of a logic circuit to be simulated, and includes BLK1, BLK2, and BLK.
3 and four blocks BLK4.

FIG. 14 shows an example of the block designation information 1205. BLK1, BLK2, and BLK3 are designated as debug target blocks (TARGET), and BLK1 and BLK are designated.
2 is designated as a block (MODIFIED) changed from the previous simulation.

Then, the block reconstructing means 1207 selects from the circuit information 1201 of the logic circuit the BLK1 and BLK2 circuits designated as blocks changed from the previous simulation by the block designation information 1205, and selects a new block shown in FIG. Create BLK5. At this time, the input / output signals of BLK1 and BLK2 are set to BL.
Although the input / output signal of K5 is used, a signal which is not connected to a block other than the BLK1 and BLK2 and is not an input / output signal of the entire circuit like the signal C is excluded from the input / output signal of BLK5.

Then, as in the first embodiment, the partial circuit BL is
The simulation of K5 is performed according to the processing after the end determination processing in step 202 of the flowchart shown in FIG. 2, and the circuit state reproducing means 1209 reproduces the state during the simulation of the circuit except for BLK1 and BLK2 according to the flowchart shown in FIG. The simulation after the difference between the output signal of BLK5 and the previous simulation is generated by the circuit simulation means 1210 according to the flowchart shown in FIG. 3 to update the logic circuit state information 1203 and the signal change information 1204.

As described above, according to the second embodiment of the present invention, there are a plurality of blocks to be debugged by the simulation method according to the third and fourth aspects of the present invention. In this case, by using the information created during the previous simulation, the simulation time for performing the simulation using the same test pattern can be reduced.

In this example, the changed block is directly designated, but the changed block is automatically selected by comparing the circuit information before the change and the circuit information after the change. It goes without saying that you can do this.

[0039]

According to the logic circuit simulation method of the present invention, signal information is saved during the execution of the simulation, and the logic circuit is used during the simulation performed after a change is made to one pre-designated debug target block. The debug target block and the peripheral circuit excluding the debug target block are separated, and a part of the simulation of the peripheral circuit is omitted using the stored signal information. Therefore,
During the simulation performed after making a change to one block, the information saved during the simulation is used to change the period until the difference between the output signal of the changed block and the previously executed simulation occurs. It is possible to omit a part of the simulation for the part where the symbol is not added, and to shorten the entire simulation time of a large-scale logic circuit, for example.

According to the logic circuit simulation method of the second aspect, the same effect as that of the first aspect is obtained.

According to the logic circuit simulation method of the third aspect, when there are a plurality of debug target blocks to which a change can be made, the change is made at the time of the simulation performed after making a change to a part or all of the blocks. A plurality of blocks including blocks are reconfigured as one block, a logic circuit is separated into a reconfigured block and a circuit excluding blocks included in the reconfigured block, and a part of the simulation is saved using the stored signal information. Omitted.
Therefore, during the period until the difference between the output signal of the reconstructed block and the previously executed simulation occurs, part of the simulation for circuits other than the reconstructed block can be omitted. The entire circuit simulation time can be reduced.

According to the logic circuit simulation method of the fourth aspect, the same effect as that of the third aspect is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a simulation method according to a first embodiment of the present invention.

FIG. 2 is a flowchart illustrating a method of simulating a partial circuit according to the first embodiment of the present invention.

FIG. 3 is a flowchart illustrating a method of reproducing a state of a peripheral logic circuit according to the first embodiment of the present invention.

FIG. 4 is a flowchart illustrating a simulation method of an entire circuit according to the first embodiment of the present invention.

FIG. 5 is a circuit diagram illustrating an example of a logic circuit to be simulated for the first time in the first embodiment of the present invention;

FIG. 6 is a waveform chart showing an example of an input test pattern according to the first embodiment of the present invention.

FIG. 7 is a diagram showing an example of block designation information for designating a debug target block according to the first embodiment of the present invention.

FIG. 8 is a waveform chart showing an example of signal change information of an input / output signal of a debug target block according to the first embodiment of the present invention.

FIG. 9 is an explanatory diagram showing an example of logic circuit state information in which a state of a logic circuit during a simulation is recorded in the first embodiment of the present invention;

FIG. 10 is a circuit diagram illustrating an example of a logic circuit to be subjected to a second simulation according to the first embodiment of the present invention;

FIG. 11 is a waveform chart showing an example of an output signal of a debug target block according to the first embodiment of the present invention.

FIG. 12 is a block diagram illustrating a configuration of a simulation method according to a second embodiment of the present invention.

FIG. 13 is an explanatory diagram showing an example of a logic circuit to be simulated according to the second embodiment of the present invention.

FIG. 14 is a diagram illustrating an example of block designation information for designating a debug target block and a changed block according to the second embodiment of the present invention;

FIG. 15 is an explanatory diagram of an example of a new block created by combining changed blocks in the second embodiment of the present invention.

[Explanation of symbols]

 101, 1201 Circuit information 102, 1202 Test pattern 103, 1203 Circuit state information 104, 1204 Signal change information 105, 1205 Lock designation information 106, 1206 Simulation means 107, 1208 Partial circuit simulation means 108, 1209 Circuit state reproduction means 109 , 1210 Overall circuit simulation means 1207 Block reconstruction means

Claims (4)

[Claims] 1. A method for simulating a logic circuit comprising a plurality of blocks, wherein signal information during execution of a simulation is saved except for internal signal information of one designated debug target block, and a change is made to the debug target block. At the time of the simulation performed after the addition, the logic circuit is separated into the debug target block and a circuit excluding the debug target block, and a partial simulation of the debug target block is performed based on the signal information saved from a simulation initial time. The signal information of the simulation is compared with the stored signal information, and if the comparison result is inconsistent, the partial simulation is terminated, and the signal information of the partial simulation and the saved signal information are all compared from the last simulation time. Simulation method of a logic circuit, characterized in that the simulation of the lock. 2. A method of simulating a logic circuit including a plurality of blocks, wherein the logic circuit is configured to store signal information during execution of the simulation and to execute the simulation after modifying the block to be debugged. The block and the circuit other than the debug target block are separated, a partial simulation of the debug target block is performed based on the signal information stored from a simulation initial time, and the signal information of the partial simulation is compared with the stored signal information. If the comparison results in a mismatch, the partial simulation is terminated, and simulation of all blocks is performed from the simulation time at which the signal information of the partial simulation and the stored signal information finally match each other. Configuration method. 3. A method for simulating a logic circuit comprising a plurality of blocks, wherein, when a plurality of blocks to be debugged specified in advance exist, a change is made in a simulation performed after a part or all of the blocks are changed. A plurality of blocks including the added block are reconfigured as one block, and the logic circuit is separated into the reconfigured block and a circuit excluding the blocks included in the reconfigured block. The signal information is saved during the execution of the simulation except for the signal information, a partial simulation of the debug target block is performed based on the signal information saved from the simulation initial time, and the signal information of the partial simulation is compared with the saved signal information, If the comparison result is inconsistent, partial simulation Exit ® down, a simulation method of a logic circuit in which the signal information stored and signal information of the partial simulation and performing a simulation of all the blocks from the last matching simulated time. 4. A method for simulating a logic circuit comprising a plurality of blocks, wherein signal information is stored during execution of the simulation,
When there are a plurality of blocks to be debugged specified in advance, at the time of simulation performed after making a change to a part or all of the blocks, a plurality of blocks including the changed block are reconfigured as one block, and the logic The circuit is separated into the reconstructed block and the circuit excluding the blocks included in the reconstructed block, and a partial simulation of the debug target block is performed based on the signal information saved from a simulation initial time. The stored signal information is compared with the stored signal information, and if the result of the comparison does not match, the partial simulation is terminated, and the simulation of all blocks is performed from the simulation time when the signal information of the partial simulation and the stored signal information finally match. Characterized by Simulation method for logic circuits.