JP2001196460A - Semiconductor integrated circuit and method for designing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce number of kinds of the cells contained in a library. SOLUTION: A cell containing a plurality of circuit elements each of which is arranged in a specified position and among which specified mutual connections are made is called from a library. Signal application forms to the cell are specified depending on required basic logic functions (NAND and NOR), and mutual wiring among each of a plurality of the cells is determined. For example, if open drain terminals 19 and 21 are grounded and an input signal (C) that is independent from other input signals is applied to a drain terminal 20, a three-input NAND can be formed. If open drain terminals 20 and 21 are connected to a power source and the independent signal is applied to the terminal 19, a three-input NOR can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and a method of manufacturing the same, and more particularly, to an integrated circuit such as an application specific integrated circuit (ASIC), a microprocessor, a microcontroller, a signal processor and the like, and to efficiently use them The present invention relates to a manufacturing method for manufacturing.

[0002]

2. Description of the Related Art Conventionally, when realizing a large-scale logic circuit, a method such as a gate array, a standard cell (or a cell-based integrated circuit) and the like are widely used. The feature of these integrated circuits is that a partial circuit called a cell is prepared in advance.

A cell is a small-scale logic circuit such as a NAND or a NOR in which a layout of a mask pattern is completed.
Usually, in addition to the mask layout, the positions of input / output terminals and the operation speed are determined.

A cell library (also referred to as a macro cell library, a macro library, a device library, a standard cell library, or the like) is a collection of information about the cells and an auxiliary storage device of a large-scale computer for supporting an integrated circuit design. .

[0005] If such a cell library for CAD is prepared in advance, an integrated circuit having a desired logic function can be realized simply by arranging cells on a chip and connecting the terminals of the cells by wiring. be able to. Therefore, since logic design can be performed without considering the transistor operation and layout at the transistor level, an integrated circuit having a desired function can be manufactured in a short time.

[0006] Another related technique related to the present invention is a pass transistor circuit. When a pass transistor circuit is used, logics such as AND, OR, and exclusive OR (XOR) of two inputs use the same internal circuit connection,
It is known that by changing the form of application of two external input signals and its inverted two input signals (that is, two complementary input signals), it is possible to realize a smaller area and higher speed than a normal CMOS circuit.

[0007] As a known technique relating to this pass transistor circuit, reference can be made to JHPasternak, et al., IEEE Circuits.
and Devices, July 1993, PP 23-28 and literature K. Yano
et.al., IEEE Journal of Solid-State Circuits, Vo
l. 25, No. 2, pp 388-395 (1990).

Further, in these documents, a three-input OR, AN is used by using the method of the pass transistor circuit.
In order to configure logic such as D and XOR, the internal circuit connection for configuring XOR is different from the internal circuit connection for configuring OR and AND, and a three-input signal application mode for configuring XOR Is different from a three-input signal application mode for forming OR and AND.

On the other hand, the 1992 IEICE Spring Conference
Et al., “Speed performance of pass transistor logic gate using CMOS / SIMOX process”, published on page 5-181 of C-560, includes output voltage on the source-drain path of the pass transistor. When an inverter for amplification is connected and the drain and gate of one pass transistor are driven by complementary input signals or the same input signal, the input signal of the drain is connected to the ground level _VSS or the power supply voltage level Vss. A two-input NAND / AND gate circuit with improved speed performance by using _DD is disclosed.

[0010]

SUMMARY OF THE INVENTION Conventional gate arrays,
A plurality of cells used in a large-scale logic integrated circuit such as a standard cell have different internal circuit connections if their logics are different. Therefore, a cell library for realizing a large-scale logic integrated circuit usually includes a large number of cells of 60 or more. Preparing such a large number of cells requires a great deal of effort. Because
This is because it is necessary to determine the internal circuit connection and input / output terminal positions of each cell, perform a mask layout, and evaluate the delay time. However, to reduce this effort,
If the number of cells is reduced, the required logic is often not prepared as cells. In such a case, it is necessary to implement the required logic by combining two or more cells. As a result, the area, delay time, and power consumption of the integrated circuit increase. Therefore, reducing the number of registered cells is not a practical solution in terms of performance.

More importantly, the provision of as many as 60 cells provides only a fraction of the actual logic functions used. For example, there are a total of 256 types of three-input logic, and 655 types of four-input logic.
There are 36 types. Therefore, in order to realize a simple logic of three inputs and four inputs, it is actually necessary to realize a logic function by combining many cells in a cell library. An integrated circuit realized by such a combination of cells cannot be said to be a circuit configuration most suitable for a target logical function. There is a problem that the speed, area, and power are all inferior to the optimal circuit.

In the above-mentioned document by JHPasternak, et al, two-input and three-input OR, AND, and X are obtained by a standard cell design method using a pass transistor circuit.
A method for implementing the logic of OR is shown. FIG. 5 shows in detail the standard cell that realizes the logic of OR and AND of two inputs and three inputs introduced in this paper, in accordance with the common sense of those skilled in the art regarding standard cells. Since this cell has two or three inputs, it is necessary to arrange an inverter for signal inversion inside the cell. Therefore, after the layout of the mask patterns such as the source / drain regions and the gate electrodes of the transistors in the cell internal circuit as shown in FIG.
By performing the internal connection of the cells, a logic circuit which realizes OR or AND logic using a pass transistor can be provided. This simple example is shown in the lower diagram of FIG.

However, in this cell, since the source / drain path of the pass transistor in the cell is directly connected to the output terminal of the cell, the driving capability of the cell output is limited by the on-resistance of the pass transistor. In particular, in a three-input circuit, the source / drain paths of the two pass transistors are connected in series between the input terminal and the output terminal.
There is a disadvantage that the driving capability of the cell output is extremely low.

Further, in this cell, it is necessary to arrange an inverter for inverting a signal, so that there is a disadvantage that the cell area is large.

On the other hand, K. Yano, et al.
A plurality of complementary input signals are applied to the pass transistor circuit described in the above document by ado, et al.
An inverter for inverting a signal inside the circuit is omitted, and an inverter for amplifying an output voltage is connected to the source / drain path of the pass transistor. This pass transistor circuit is used for a cell of a cell library for CAD. The concept is not suggested.

According to the present invention, an internal circuit of a cell for realizing various logics in an integrated circuit designed using a cell library for CAD is made the same, and a plurality of input signals from the outside of the cell are provided in accordance with a target logic. The purpose of the present invention is to develop a large-scale logic integrated circuit capable of realizing a target logic simply by changing an application form. It is an object of the present invention to make it possible to improve the driving performance and further improve the speed performance.

[0017]

According to one embodiment of the present invention, there is provided a semiconductor integrated circuit comprising a first circuit having substantially the same internal circuit connection and substantially the same internal circuit element arrangement. Cell (31 in FIG. 3) and the second cell
(32 in FIG. 3) at least at different positions on the chip, wherein each of the first and second cells has a substantially square shape and the first, second, third,
The fourth active element (M13, M14, M15, M1 in FIG. 1)
6), an output amplifier circuit (I5 in FIG. 1), and a first node (N
3), a second node (N4), and first, second, third, fourth, fifth, sixth and seventh input terminals (15, 16, 17,.
18, 19, 20, 21), the output terminal (22) and the first
A first operating potential supply line to which an operating potential point (V _CC ) is supplied;
A second operating potential supply line to which a second operating potential point (GND) is supplied, and inside each of the first and second cells, the output amplifier circuit (I5) First
An operating potential is supplied by being connected to the operating potential supply line and the second operating potential supply line, and the first active element
The gate electrode of (M13) is connected to the first input terminal (15), the gate electrode of the second active element (M14) is connected to the second input terminal (16), The gate electrode of the active device (M15) is connected to the third input terminal (17), and the gate electrode of the fourth active device (M16) is connected to the fourth input terminal (18). The source / drain path of one active element (M13) is the first node
(N3) and the seventh input terminal (21),
A source / drain path of the second active element (M14) is connected between the first node (N3) and the second node (N4), and a source / drain path of the third active element (M15). The path is between the second node (N4) and the sixth input terminal
(20), the fourth active element (M16)
Are connected between the second node (N4) and the fifth input terminal (19), and the input and output of the output amplifier circuit (I5) are connected to the first node (N5), respectively.
(N3) and the output terminal (22), and one of the first and second cells (32 in FIG. 3) is externally connected to the first input terminal (15). The first input signal (A) is applied to the second input terminal (16), and the second input signal (AN) having a phase opposite to that of the first input signal (A) is applied to the second input terminal (16). A third input signal (B) is applied to the input terminal (17), and the third input signal (B) is applied to the fourth input terminal (18).
A fourth input signal (AN) having a phase opposite to that of (B) is applied, and among the fifth input terminal (19), the sixth input terminal (20), and the seventh input terminal (21), At least two input terminals (19, 20) are different from the signals of the first, second, third, and fourth input signals (A, AN, B, BN). E) N, V _CC ) is applied.

A semiconductor integrated circuit according to another embodiment of the present invention comprises a first cell (31 in FIG. 3) having substantially the same internal circuit connection and substantially the same internal circuit element arrangement.
And a second cell (32 in FIG. 3) at least at different locations on the chip, wherein each of the first and second cells has a substantially square shape and
Second, third, and fourth active elements (M13, M14,
M15, M16), first and second inverters, an output amplifier circuit (I5 in FIG. 1), a first node (N3), a second node (N4), first, second, and third , Fourth and fifth input terminals (16, 18, 19, 20, 21) and an output terminal (22).
A first operating potential supply line to which a first operating potential point (V _cc ) is supplied, and a second operating potential supply line to which a second operating potential point (GND) is supplied. And inside each of the second cells, the output amplifier circuit (I5) is connected to the first operating potential supply line and the second operating potential supply line to supply an operating potential, The gate electrode of the second active element (M14) is connected to the first input terminal.
(16), the gate electrode of the fourth active element (M16) is connected to the second input terminal (18), and the input and output of the first inverter are connected to the first input terminal.
(16) and the gate electrode of the first active element (M13), respectively, and the input and output of the second inverter are connected to the second input terminal (18) and the third active element (M13).
(M15) and the first electrode.
The source / drain path of the active element (M13)
The source / drain path of the second active element (M14) is connected between the node (N3) and the fifth input terminal (21), and is connected to the first node (N3) and the second node (N4). ), And the source / drain path of the third active element (M15) is connected between the second node (N4) and the fourth input terminal (20). Active element of
The source / drain path of (M16) is connected to the second node (N
4) and the third input terminal (19), and the input and output of the output amplifier circuit (I5) are connected to the first node (N3) and the output terminal (22), respectively. A first input signal (AN) is applied to one of the first and second cells (32 in FIG. 3) to the first input terminal (16) from the outside thereof, and The second input terminal (18)
Is applied to the third input terminal (1).
9), the fourth input terminal (20), and the fifth input terminal
At least two input terminals (19, 20) of (21)
Is characterized in that signals ((CDE) N, _Vcc ) different from the first and second input signals (AN, BN) are applied.

In the semiconductor integrated circuit according to a specific embodiment of the present invention, the fifth input terminal (19), the sixth input terminal (20) and the fifth input terminal (20) of the one cell (32 in FIG. 7 among the different signals ((CDE)
N, _Vcc ) is applied to at least one input terminal (2
0) is connected to either the first operating potential supply line (V _cc ) or the second operating potential supply line (GND) (V _cc ) (see FIG. 3).

In a semiconductor integrated circuit according to a more specific embodiment of the present invention, the first operating potential supply line (V _cc ) and the second operating potential supply line (GND) are arranged substantially in parallel. The first and second cells of the one cell (32 in FIG. 3) are provided between the first operating potential supply line and the second operating potential supply line.
The second, third and fourth active elements (M13, M13
14, M15, M16) and the output amplifier circuit (I5) are arranged (see FIG. 3).

In a semiconductor integrated circuit according to a more specific embodiment of the present invention, in one of the cells (32 in FIG. 3),
The first active element (M13) and the second active element (M14) extend in a direction substantially orthogonal to the longitudinal directions of the first operating potential supply line (V _CC ) and the second operating potential supply line (GND). ),
The third active element (M15) and the fourth active element (M
16), the longitudinal direction of each of the gate electrodes of the two active elements ( _MP , _MN ) constituting the output amplifier circuit (I5) is arranged (see FIG. 1).

In a semiconductor integrated circuit according to a more specific embodiment of the present invention, the above one cell (32 in FIG. 3)
The two active elements constituting the output amplifier circuit (I5)
Each of (M _P , M _N ) is characterized by comprising a plurality of active elements whose gate electrodes are commonly connected and whose source / drain paths are connected in parallel (see FIG. 1).

In the method of manufacturing a semiconductor integrated circuit according to one embodiment of the present invention, the input / output terminal positions and the internal circuit element arrangements substantially the same as those of the first and second cells are stored in the storage means of the computer. A first step of registering in advance;
The input / output terminal position and the internal circuit element arrangement of the cell registered in the step of reading from the storage means,
A second step of designating an external signal application mode of the read cell, and a third step of transferring a layout pattern onto a semiconductor substrate according to the external signal application mode of the cell specified in the second step. (See FIG. 24).

According to the semiconductor integrated circuit according to one embodiment of the present invention as described above, the first cell (31 in FIG. 3) and the second cell (32 in FIG. 3) have substantially the same internal circuit. Even if the connection and the substantially identical internal circuit element arrangement are provided, the first input terminal (15), the second input terminal (16), and the third input terminal ( 17), application of a plurality of input signals to a fourth input terminal (18), a fifth input terminal (19), a sixth input terminal (20), and a seventh input terminal (21). By simply changing the form, various desired logics can be realized. It goes without saying that if the independence of the plurality of input signals is high, more complicated logic can be realized.

In the cell, the input and output of the output amplifier circuit (I5) are respectively connected to a first node (N3) and an output terminal.
(22), the output drive capability of the cell can be increased.

In one cell (32 in FIG. 3), a first input signal (A) is applied to the first input terminal (15) from the outside, and a second input terminal (16) is applied to the second input terminal (16). A second input signal (AN) having a phase opposite to that of the first input signal (A) is applied, a third input signal (B) is applied to a third input terminal (17), and a fourth input terminal (AN) is applied. Since the fourth input signal (AN) having a phase opposite to that of the third input signal (B) is applied to 18), the inverter for inverting the input signal is omitted inside the cell. As a result, the cell can have a small area.

According to the semiconductor integrated circuit of another embodiment of the present invention, the first signal for inverting the input signal inside the cell is provided.
And the second inverter, the cell area is slightly increased, but there is no need to apply a complementary input signal from outside the cell. As a result, the area of the wiring channel outside the cell can be reduced.

Further, according to the semiconductor integrated circuit of one embodiment of the present invention, the first circuit for supplying the operating potential to the output amplifier circuit (I5) for improving the output drive capability inside the cell.
An operating potential supply line (V _CC ) and a second operating potential supply line (GND) are arranged. One of the cells (32 in FIG. 3) has a sixth input terminal (20) and a seventh input terminal
(21) and the first, second, third, and fourth input signals (A, A
N, B, or BN) can also achieve the intended logic.
However, as in the specific embodiment of the present invention, the first operating potential supply line (V _CC ) and the second operating potential supply line (V _CC ) are connected to the sixth input terminal (20) and the seventh input terminal (21) of one cell. Operating potential supply line (G
By applying any one of the fixed potentials (ND), it is possible to realize the same target logic. As described above, when the fixed potential is applied, the driving load for applying a plurality of input signals from the preceding circuit to one of the cells becomes smaller, and the speed performance can be further improved.

A semiconductor integrated circuit according to a more specific embodiment of the present invention is arranged between a first operating potential supply line (V _cc ) and a second operating potential supply line (GND) which are arranged substantially in parallel. First, second, third, and fourth active elements (M13, M14, M15, M16) of one cell (32 in FIG. 3) and an output amplifier circuit
(I5), the first operating potential supply line
(V _cc ) and the second operating potential supply line (GND) are connected to the sixth input terminal (20) and the seventh input terminal (21) of one of the cells by a wiring substantially orthogonal to the first operating potential supply line ( V _CC ) or the fixed potential of the second operating potential supply line (GND) can be easily applied.

In a semiconductor integrated circuit according to a more specific embodiment of the present invention, the first operating potential supply line (V _cc ) and the second
The longitudinal direction of the operating potential supply line (GND) and the first active element
(M13), second active element (M14), third active element
(M15), the fourth active element (M16), and the output amplifier circuit (I
Since the arrangement of the two active elements (M _P , M _N ) constituting 5) in the longitudinal direction of each gate electrode is devised,
A small cell area can be realized (see FIG. 1).

In a semiconductor integrated circuit according to a more specific embodiment of the present invention, each of the two active elements (M _P , M _N ) constituting the output amplifier circuit (I5) includes a plurality of parallel-connected plural active elements. Because of the active elements, the output drive capability of the output amplifier circuit (I5) can be increased despite the small cell area (see FIG. 1).

A method of manufacturing a semiconductor integrated circuit according to an embodiment of the present invention (see FIG. 24) is a method of designing a computer integrated circuit (CA) including a cell having the above-mentioned advantages.
D) and the actual production by this design.

[0033] Other objects and features of the present invention will be apparent from the following examples.

[0034]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The basic structure and operation of the present invention have been described above, and embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows an example of two cells registered in a cell library having the above-described basic configuration of the present invention. The cell sizes and terminal positions of the two cells PC3 and PC4, the logical functions, The cell internal circuit and the delay time characteristics are shown at the top, and the internal circuit element arrangement (layout pattern) of the cell PC3 is shown at the bottom.

The cell PC4 has two more internal circuit elements than the cell PC3 and has one more input signal, so that it is possible to realize more complicated logic than the cell PC3.

As shown in the internal circuit element layout (layout pattern) of the cell PC3 at the bottom of FIG. 1, a first operating potential supply line (V
_CC ) and a second operating potential supply line (GND) are arranged substantially in parallel, and an n-channel first and second n-channel type are provided between the first operating potential supply line and the second operating potential supply line. 2, 3rd, 4th
MOS transistors (M13, M14, M15, M1)
6), a p-channel type output MOS transistor (M _P ) and an n-channel type output MOS transistor (M _N ) which constitute the output inverter (I5), and the output inverter (I5) has a first operating potential. The operating potential is supplied by being connected to the supply line and the second operating potential supply line,
The gate electrode of the MOS transistor (M13) is connected to the first input terminal (15), and the second MOS transistor (M13)
The gate electrode of (M14) is connected to the second input terminal (16), the gate electrode of the third MOS transistor (M15) is connected to the third input terminal (17), and the fourth MOS transistor (M16 ) Is connected to the fourth input terminal (18), and the source / drain path of the first MOS transistor (M13) is connected to the first node (N3) and the seventh input terminal.
(21), a second MOS transistor
The source / drain path of (M14) is the first node (N3)
And a source / drain path of the third MOS transistor (M15) is connected between the second node (N4) and the sixth input terminal (20),
The source / drain path of the fourth MOS transistor (M16) is connected between the second node (N4) and the fifth input terminal (19), and is a p-channel type output which is an input of the output inverter (I5). The gate electrode of the MOS transistor (M _P ) and the n-channel output MOS transistor (M _N ) and the output of the output inverter (I5) are the p-channel output MOS transistor (M _P ) and the n-channel output M.
The drain region of the OS transistor (M _N ) is connected to the first node (N3) and the output terminal (22), respectively.

In the cell PC3 of FIG. 1, the input and output of the first inverter are connected to the second input terminal (16) and the first MO.
The input and output of the second inverter are connected to the gate electrode of the S transistor (M13), respectively.
(16) and the gate electrode of the fourth MOS transistor (M16), the cell area is slightly increased, but the first input terminal (15) and the third input terminal
(18) can be omitted, and it is not necessary to supply a complementary input signal from outside the cell, and the wiring channel area outside the cell can be reduced.

In particular, in the cell, the first operating potential supply line
(V _cc ) and the n-channel first, second, third, and fourth M in a direction substantially orthogonal to the direction of the second operating potential supply line (GND).
OS transistor (M13, M14, M15, M16)
And the channel length (L ₁ ) of the n-channel output MOS transistor (M _N ) constituting the output inverter (I5). Also, a p-channel type MOS transistor for reducing the steady-state current of the output inverter (I5)
(M _P ′), the output inverter (I5)
P-channel type output MOS transistor
The channel length (L ₂ ) of (M _P ) is slightly larger than the channel length (L ₁ )
It is smaller.

In order to increase the output driving capability of the output inverter (I5), the p-channel type output MOS transistor (M _P ) and the n-channel type output MOS transistor (M _N ) have two common gate electrodes. Note that the two source / drain paths are connected in parallel.

As described above, the cell PC3 has the n-channel M
Using an internal circuit in which OS transistors (M13 and M14, or M15 and M16) are connected in a binary tree shape, a mask pattern layout corresponding to this circuit connection is performed in advance (FIG. 1, lower diagram).

The cell PC3 has four gate input terminals.
(15-18) and three open drain input terminals (19-
21), and 22 is an output terminal. These terminals are formed, for example, by using through holes between the first layer wiring and the second layer wiring (see the lower diagram in FIG. 1).

At this time, the wiring between the transistors inside the cell is mainly performed by the wiring of the first layer (refer to the “layout pattern in the cell” at the bottom of FIG. 1), and the wiring between the cells is formed through the through hole. This is performed by connecting two-layer wiring. The horizontal wiring crossing the second-layer wiring can be further performed by a third-layer wiring (see “Cell Arrangement and Wiring Outside the Cell” in FIG. 3).

In this cell, the drain terminals (19, 20, 21 in FIG. 1) of the MOSFET are open, and different logic outputs can be obtained by changing the form of application of an input from outside the cell to the open drain terminal. Obtainable. There are the following modes for applying an input to the open drain terminals (19, 20, 21) (see FIG. 2).

That is, the input application form is (1) power supply line
(V _CC ), (2) Connect to ground line (GND),
(3) Connect with the same signal as the signal given to the other input terminal (15-21), (4) Connect with the complementary signal of the signal given to the other input terminal (15-21), (5) and more Connect independent signals that do not apply.

Incidentally, the internal circuit element arrangement (layout pattern) of the cell PC4 can be configured in the same manner as the internal circuit element arrangement (layout pattern) of the cell PC3.

As shown in FIG. 2, the open drain terminal (1
Various logic outputs can be obtained by changing the application form of the signal given in 9-21). In the nine examples of FIG. 2, the signals of A, AN, B, and BN are all given equally to the gate input terminals (15, 16, 17, 18).
(The complementary signal is indicated by adding N to the end.) Open drain terminal
(19-21) are applied in different forms. In FIG. 2A, the open drain terminals 19 and 21 are connected to the ground line, and another input signal (15-19, 2
A signal (C) independent of 1) is given. At this time, (15)
= A, (16) = AN, (17) = B, (18) = BN, (1
If the conditions of 9) = 0, (20) = C, and (21) = 0 are substituted into the cell output equation (see “Logic Function” in FIG. 1) given by the following equation, (22) = (((( 19) (18) + (20) (17))
(16) + (21) (15)) N It is possible to obtain a logical output to the output terminal (22). In this case, (22) = ((AN) BC) N, and a three-input NAND function can be realized (however, A
Input is negative logic).

As shown in FIG. 2B, the open drain terminals 20 and 21 are connected to a power supply line, and a signal (C) independent of the other input terminals is applied to 19, thereby providing a three-input NOR.
Can be realized. The same applies to other logic functions.

As described above, the simple two cells PC3 ((31) and (32)) having the same internal circuit connection as each other are used.
FIG. 3 shows an example in which a complicated logical function is realized by using.

As shown in FIG. 3, the cell PC3 ((31),
(32)), the power supply line (V _cc ) and the ground line (GND) of the two cells are connected in common, and the signal input wiring outside the cell is made different, so that a three-input NA is provided.
ND and 3-input NOR can be realized. At this time, since the element arrangement in the cell and the wiring in the cell are naturally the same in the two cells, the layout pattern when the chip is viewed from above is the same for both cells (the lower part of FIG. 3). Layout pattern in cell ”).

The major feature of the cell PC3 of this embodiment is that
Not only a simple logic such as an input NAND, but also a complicated operation of XORing two inputs (BN, C) as shown in FIG. 2D and further NANDting the output with the third signal (A). Is that a single function can be realized by one cell. In this case, the open drain terminal 19 is connected to a ground line (GND), the terminal 20 is connected to an independent signal C, and the terminal 21 is connected to a complementary signal of the signal C. In order to realize the same logical function using a conventional cell library as shown in FIG. 5, it is necessary to combine at least two cells OR3 and AN3 having different internal circuit connections and internal circuit element arrangements.

On the other hand, FIG. 4 shows an example in which a considerably complicated logic function is realized by using only two cells PC3 of this embodiment having the same internal circuit connection and internal circuit element arrangement. In the example of FIG. 4, it is shown that the conventional logic requiring seven cells can be realized only by two cells PC3 having the same internal circuit connection and internal circuit element arrangement.

As described above, by using only one cell PC3, various complicated logical functions can be realized.
A logic circuit having a complicated logic function can be realized extremely compactly.

As described above, in the conventional practical cell library, it was necessary to prepare 60 or more cells, but in the present invention, a cell library can be realized with 10 or less types of cells. If the PC 4 of FIG. 1 and various inverter circuits are provided in addition to the PC 3 (see FIG. 1) described above, much more functions can be realized than the conventional 60 libraries. PC4 in FIG. 1 is obtained by connecting two more MOSFETs to the terminal 21 of PC3, and can realize a more complicated logic function than PC3. Therefore, a high-performance integrated circuit can be realized in a short time by these cells PC3 and PC4.

Further, since a complicated logic function can be realized compactly, all of the circuit speed, area and power consumption can be greatly improved.

The PC3 cell of the present embodiment shown in FIG.
It may look like a part of the three-input OR (the part connecting M9-M12) of FIG. 5 disclosed in the literature of ernak et al is simply re-registered as a cell. However, it should be pointed out that there is great difficulty for those skilled in the art to conceive of this. This is due to the circumstances described below.

The cells registered in the CAD cell library are logic circuits that have been laid out as described above, and are prepared before the logic design of the entire integrated circuit is performed. Since laying out cells is a time-consuming task, it is natural to select a cell having a logic function that is frequently used in logic design and construct a cell library. Conventionally, a frequently used logic function is a one-input INV
ERTER, 2-input or 3-input AND, OR, X
OR (or the negation of these), and it is a logical designer's skill to show how to combine them to efficiently construct a complicated logic of an integrated circuit.

On the other hand, when the logical output (22) of the PC3 cell of this embodiment shown in FIG. 1 is represented by a Boolean expression as a function of the signal of the input terminals (15 to 21), the following complex ones are obtained. (See "Logic Function" in FIG. 1).

(22) = (((19) (18) + (20) (17)) (16) + (21) (15)) N Therefore, having such a complicated logic function, Those skilled in the art have considerable resistance to dare to use circuits considered to be low as basic cells in a cell library. In other words, creating a cell library is a rather time-consuming task, so registering a circuit that is rarely used in a conventional logic design as a cell at that time can be done without very strong motivation. is not.

The above-mentioned document of Pasternak et al also mentions AND, OR, and XOR as the logical functions of the standard cell in line with this traditional concept. Also, the above-mentioned document by Yano et al follows this traditional idea. This Yano is one of the inventors of the present invention, but as of 1990, when this document was written, the AND circuit was changed only by partially changing the signal application connection of the internal circuit of the two-branch pass transistor circuit. Is O
Recognizing that it can be changed to an R circuit, this is described in this paper. However, since it was necessary to change the connection even partially, it was thought that separate cells, AND and OR, were necessary. Further, the conventional assumption that the logic design is performed on the basis of another cell such as AND, OR, or XOR has not been doubted. Thus, for a logic circuit designer, performing logic design using separate cells of AND, OR, and XOR is a premise similar to "using numbers for arithmetic". It was extremely difficult for those skilled in the art to review this traditional way of thinking.

On the other hand, the present inventors have shown that the cell PC of FIG.
It has been found that by using only one of the three types, many different logic functions can be realized only by changing the application form of the input signal from outside the cell. This departs from the conventional stereotype that the function of the cell must be easy to understand based on AND or OR, registers the two-branch connection circuit itself as a cell, and creates a logic based on this. The idea was that the ideal form of design should be reconstructed.

On the other hand, the plurality of cells PC3 having different logic functions shown in FIG. 1 have the same internal circuit connection and internal circuit element arrangement, and differ only in the form of application of an input signal from outside the cell. The fact that the function of the cell PC3 is complicated and difficult to understand was a fatal drawback a few years ago. Even if it is assumed that the cell PC3 is prepared in the cell library, the logic designer would have tried to use such an obscure cell.

However, recently, an automatic logic synthesis tool (a tool for automatically outputting a connection netlist of cells for realizing a desired logic function when a desired logic function is input) has been rapidly put into practical use. It is not the designer who decides (that is, determines the connection relationship of the cells), but the computer. Based on the above situation, whether the cell function is easy for the designer to understand is
The inventor has noticed that it is no longer potentially important. Based on this, the present invention has been completed, which overturns the basic logic design of an integrated circuit using AND, OR, XOR, and INVERT as basic cells, which has been used for many years. In fact, the inventors have also succeeded in developing software for realizing an arbitrary logic function by combining cells as shown in FIG. In addition, it has been confirmed that the use of this greatly improves the area, speed, and power consumption of an integrated circuit.

The output section of the cell PC3 in FIG. 1 is provided with an amplifier circuit (inverter, I5). This amplifier circuit I5 having a large output drive capability allows the output terminal (22) to be turned on by the on resistance of the pass transistors (M13 to M15).
Of the cell becomes substantially zero, and the output signal of the cell is applied to the open drain terminal (19, 20, 2) on the input side.
There is no reverse transmission to 1). That is, once the input signal is determined, even if the output signal changes, the input signal is not affected. Therefore, the delay time of the entire circuit including many cells can be expressed as the sum of the delay times of the respective cells. Therefore, if the cell delay time is evaluated in advance as a function of the output load capacity,
The overall delay time can be evaluated in a very short time.

If there is no amplifier circuit in the output section, the delay time of the cell of interest cannot be determined only by the input / output conditions of the cell, but is determined by the operation of the entire circuit as an analog circuit. Therefore, the delay time cannot be determined unless the analog circuit analysis of the entire circuit is performed. This requires a great deal of labor and time for timing design.

The input / output terminal 1 of the cell PC3 in the embodiment of FIG.
5 to 21 are placed on the wiring grid. This wiring grid is a grid composed of channels in which connection wiring between cells can be arranged. For example, in FIG. 3, the channels of the second-layer wiring are provided at equal intervals in the vertical direction, and the channels of the third-layer wiring are provided at equal intervals in the horizontal direction. Is provided at this intersection. With respect to the wiring limited on such a wiring grid, an area-efficient connection can be performed in a short time by an automatic wiring tool. PC3 shown in FIG.
The connection of the cell internal circuit is performed using the first layer wiring, and at this time, the wiring is set at an arbitrary place without considering the wiring grid. Thereby, the area of the cell can be reduced. The input / output terminals (15 to 19) are installed on a wiring grid as shown in FIG. Even when the open drain terminals (19 to 21) are connected to the gate terminals of the same cell, the connection is performed using the wirings of the second and third layers along this wiring grid. As a result, automatic placement and routing can be performed, and an integrated circuit can be realized in a short time.

In the above example, the input / output terminal of the cell is formed by one through hole, but the input / output terminal can be formed by one electrode. Alternatively, one terminal can be formed by two or more through holes.

Next, a high-performance ASI according to an embodiment of the present invention
C (Application Specific Integrated Circuit) will be described. The ASIC uses the cell library including the new cells shown in FIG. 1 to perform various logic functions shown in FIGS. 2, 3, and 4 by using only one type of cell PC3 as described above. This can be realized by connecting the external wiring in various forms by applying the external wiring. Thus, an integrated circuit with high speed, high integration, and low power consumption can be realized in a short time.

The process of designing and manufacturing an integrated circuit using the cell of the present invention is as shown in FIG.

First, the attribute data of PC3, PC4 and other cells shown in FIG. 1 (element arrangement, input / output terminal positions,
(Operation speed) is registered in advance in an auxiliary storage device of a large-scale computer for supporting integrated circuit design (FIG. 24A).

Thereafter, the data of the cell registered in the auxiliary storage device is read, and a signal application form outside the cell is designated (FIG. 24B). Thereby, the connection relation (netlist) of the cell is obtained.

Next, based on this netlist, the positions and wirings of a plurality of cells on the chip are designated (FIG. 24).
c).

Next, a pattern is transferred onto a semiconductor substrate based on the layout pattern information. At this time,
Light or electron beam or X-ray lithography can be used (FIG. 24d). Thereby, an integrated circuit can be manufactured.

The output amplifier (I5) in the cell of FIG.
Various circuits as shown in FIG. 6 are conceivable.

FIG. 6a is a simple CMOS inverter. However, while the gate width of the pMOS is designed to be about 1.5 to 2 times the gate width of the nMOS in the ordinary CMOS inverter, the gate width of the nMOS (M21) is set to be larger than that of the pMOS (M22) in the present invention. are doing. This low level of the node N3 (see FIG. 1) is lowered to the ground level, the high level is because not increased only to V _CC -V _T.

Here, V _CC is a power supply voltage. V _T is nMOS
(M13 to M16). Therefore, the rise and fall times of the output terminal (22) can be made substantially equal by setting the logic threshold value of this CMOS inverter low. Typically, nMOS (M
13 to M16, assuming that the gate width in FIG.
The gate width of the OS (M21) is set to about 2 W, and pMO
The gate width of S (M22) is set to about 1.5W.

FIG. 6B shows a pM having a small gate width in FIG. 6A.
OS (M25) is added. This pMOS is
After the inverters M23 and M24 discharge their outputs, the node N3 is charged to the power supply voltage and the CM including M24 and M23 is charged.
A steady current can be prevented from flowing through the OS inverter.

FIG. 6C shows a further improved CMOS inverter. FIG. 6C is the same as FIG. 6B in that a pMOS (M29) having a small gate width is provided at the input terminal of the amplifier circuit, but the gate terminal of M29 is M28,
The difference is that it is connected to the output circuit of the inverter consisting of M30. This configuration uses M26 for driving the output terminal,
An inverter composed of M27 and an inverter composed of M28 and M30 for driving the gate terminal of M29 are provided independently. Thus, there is an advantage that the feedback to the gate terminal of M29 is performed at high speed even when a large load capacitance is connected to the output terminal. As a result, the input terminal of the amplifier circuit is charged / discharged within a short period of time, so that there is an advantage that power consumption is reduced.

Although the above description has been made mainly with reference to the cell PC3 in FIG. 1 as an example, the internal circuits of the cell capable of performing the same operation include those shown in FIGS. In FIG.
1 shows a configuration of a cell used in the present invention. Among them, the tree-type logic section is a section constituting the central logic of the present cell. A symbol such as "Y" indicates a circuit that connects at least two active elements and selects one of the two inputs (see FIG. 7). The cell input can be directly connected to the tree logic unit, but the logic conversion circuit A
Alternatively, the data may be input via a conversion circuit such as a logic conversion circuit C. The output of the tree-type logic unit is output to the output terminal via the logic conversion circuit B or directly. However, it is desirable that either the logic conversion circuit A or the logic conversion circuit B has an amplification circuit to separate input / output signals and amplify the signals.

As shown in FIG. 8, there are many variations in the configuration of the tree-type logic unit. First, the function to select one of the forked branches indicated by the symbol “Y” is PC3
As shown in FIG. 1, an nMOS can be used. FIG. 8A shows this as an n / n type. In this case, complementary signals such as c and cN are required as signals for controlling the gate. The n / n one-input type shown in FIG.
An inverter is provided inside the cell so that only one external control signal is provided. This has the advantage that wiring outside the cell can be reduced. In the next n / p type, one of the n / n type nMOSs is a pMOS, and one of the two signal paths is selected only by inputting the same signal to the gate. This simplifies the wiring in the cell. However, in this circuit, the amplitude of the signal output to the output terminal d is as small as V _CC -V _TN -V _TP (where V _TN is the threshold voltage of the nMOS and V _TP is the threshold voltage of the pMOS). Therefore, the operation speed is slow. p / p type is n /
This is an n-type nMOS changed to a pMOS. In the C-type, an nMOS and a pMOS are arranged in parallel so that the output swings to the full power supply voltage. It has the advantage of operating at high speed even at low voltages, but has the disadvantage of having a large number of elements.

FIG. 8 shows the tree shape of the logic part.
Various variations are conceivable as shown in FIG. A plurality of cells selected from these are registered in a cell library to form a cell library. 2-
One tree is required when configuring a two-input logic circuit. The 4-1 tree b can realize all logic circuits with three inputs or less. The 2-1 tree and the 4-1 tree b are basic in that sense, and are desirably included in the cell library. In the 4-1 tree b, the control signals of two "Y" symbols connected to the open drain terminal can be controlled independently. On the other hand, the PC 4 shown in FIG. 1 has a difference that both are driven by a common control line.
The 4-1 tree b has more logic functions that can be configured, but requires a larger area for wiring outside the cell because of the large number of input terminals.

The 6-2 tree of FIG. 8B is the PC3 of FIG.
Are provided, and there is an advantage that the wiring outside the cell can be reduced.

When designing a semiconductor integrated circuit using the cells shown in FIGS. 1, 7 and 8, the positions of the input / output terminals of the cells are determined, the layout of the mask patterns is performed in advance, and the logic Do the design. In this case, the logic design determines the connection relationship between cells so as to realize a target logic function. This can be efficiently performed by the logic generation tool. Next, cells are arranged and wired by the standard cell method based on the connection relation (net list) of the cells. FIG. 9 shows an embodiment in which cells are arranged and wired according to the present invention. The cells are arranged in a strip shape, and a wiring region is provided in parallel with the cells to perform wiring between the cells. In this figure, the wiring inside the cell is performed only by the first layer wiring, the horizontal wiring is performed by the second layer wiring, and the vertical wiring is performed by the third layer wiring.
Perform with layer wiring.

In the integrated circuit using the cell according to the embodiment of the present invention, the ratio of the pMOS to the total number of transistors is as low as about 1/6. For this reason, the inventors have found a problem that using the conventional layout for CMOS as it is results in a large waste of area. This situation is shown in FIG.
As shown in FIG. As shown in FIG. 10, in the conventional layout method, it is assumed that the pMOS is always paired with the nMOS, and the pMOS columns are traditionally arranged in parallel along the nMOS columns. However, in this case, FIG.
As shown in (1), when the cell of the present invention is laid out, a useless space is created.

In order to avoid this, in the present embodiment shown in FIG. 9, cells are arranged in a band-like region, and the nMOS region and the pMOS region are arranged so as to appear alternately in this band-like region.
More specifically, in the layout of each cell, the width is determined to a predetermined size, an nMOS is arranged at an upper part, and a pMOS is arranged at a lower part. A cell having a complicated logic has a larger number of nMOSs, but is arranged so as to have a longer length in the vertical direction. By doing so, the width of the transistor region is kept substantially constant, and the wiring region is also kept substantially constant. Since there is no useless area unlike the related art, the efficiency of the cell area is high.

In the logic design shown in FIG. 9, the design can be automated by using a logic automatic generation tool. The logic automatic generation tool is a device for automatically generating a netlist of cells using logic functions as input information. By incorporating the cell library of FIG. 1 into this automatic logic generation tool, the performance of the generated logic circuit is greatly improved.

In the above embodiment, the wiring inside the cell is performed by the first layer wiring, and the wiring outside the cell is performed by using the second layer and the third layer wiring. Actually, it goes without saying that the second and third layer wirings may be used for the wiring in the cell. In such a case, the second layer wiring cannot be used as the cell outside wiring only at the place where the second layer wiring is used as the intracell wiring.

Further, the first layer wiring can be used as the inter-cell wiring. However, this can be performed only in a place where the first layer wiring is not used in the intra-cell wiring.

An example of a gate array integrated circuit according to the present invention will be described below. The difference from the standard cell system of the above-described embodiment is that transistors are regularly arranged in a gate array, and only a wiring layer is customized for each application to realize an integrated circuit.

FIG. 12 shows an embodiment of a gate array integrated circuit according to the present invention. The gate array basic cells shown on the left side of FIG. 12 are spread all over the chip. Wiring between transistors using one or a plurality of the basic cells realizes a cell having a more complicated logic function. Here, the basic cell refers to a repetition unit of an element arrangement that has been spread in advance, and is not the cell PC3 in FIG.
A cell is selected from the cells shown in FIG. 8 and registered as a cell library. That is, FIG.
An example is shown in which a full adder is realized by connecting −2 tree cells (see FIG. 8).

The basic cell of this embodiment has been specifically designed to realize an integrated circuit efficiently. In the gate array, the basic cells are determined in advance, so that an integrated circuit can be realized in a short time only by designing and manufacturing the wiring layer. However, since the basic cells are fixed, only transistors of a predetermined size are used. There is a restriction that you can not. On the other hand, as is apparent from FIG.
3, PC4 requires about 5 times as many nMOSs as pMOSs. Therefore, when the conventional basic cell as shown in FIG. 13 is used, the pMOS portion remains unused. Therefore, waste of area is large. Further, since a pMOS having a small gate width (M25 in FIG. 6B) cannot be realized, a large pMOS must be used instead. Therefore, there is a problem that it is difficult to discharge the input terminal of FIG. 6B. Therefore, the operation becomes unstable or the operation speed becomes slow. Further, since the ratio between the pMOS and the nMOS of the CMOS inverter cannot be optimally designed, there is a problem that the operation speed is further reduced.
The basic cell (the left part of FIG. 12) of the present embodiment is conceived based on such analysis by the inventors. The basic cell of this gate array is composed of six nMOSs having a large gate width.
, Two pMOSs having a large gate width, and one pMOS having a small gate width. With this basic cell,
Since the ratio between the nMOS and the pMOS in the basic cell substantially matches the ratio between the nMOS and the pMOS in the cell PC3 in FIG. 1, there is no waste of area. Further, by configuring a CMOS inverter of an amplifying unit using two nMOSs connected in parallel and two pMOSs connected in parallel, an optimal (high-speed operation) gate shown in FIG. The width is decided. Furthermore, the gate width p is small.
By pre-loading the MOS on the basic cell, FIG.
Can be realized. Therefore,
Current consumption during standby can be reduced. FIG.
In the conventional basic cell shown in FIG. 3, such a pMOS having a small gate width cannot be formed. Therefore, the power consumption during standby increases.

Further, if the basic cells shown in FIG. 12 are used, SRAM memory cells can be realized with good area efficiency. FIG. 14 shows an example in which such an SRAM memory cell is realized on the basic cell of the present invention. By realizing a highly integrated SRAM on a gate array, a high-performance system LSI in which a memory and a logic circuit are mounted on the same chip can be realized in a short time. The reason why the basic cell shown in FIG. 12 is suitable for mounting an SRAM will be described below.
A circuit as shown in FIG. 14 is most often used for an SRAM memory cell. As can be seen, the nMOS is 4
And two pMOSs. Of these, the nMOS (M2, M3), which is a drive transistor for storing data, is usually designed to have a gate width about twice that of the nMOS (M1, M4) of the transfer transistor. This means that when reading,
This is to prevent the stored information from being erased. For this reason, one driving transistor is actually formed of two nMOSs connected in parallel, so that substantially six nMOSs and two pMOSs are required. This corresponds to the configuration of the basic cell shown in FIG. 23 (6 nMOS, large pMOS
Two, one small pMOS. Small pMOS is SRAM
), And one basic cell can efficiently realize a 1-bit SRAM memory cell as shown in FIG. On the other hand, when a conventional gate array basic cell for CMOS is used, the area is required to be twice or more. Thus, an SRAM having twice the storage capacity can be realized by using the basic cell shown in FIG. Accordingly, an LSI in which a large-capacity SRAM and a high-performance and compact logic circuit are integrated on the same chip can be realized.

In addition to FIG. 12, a gate array basic cell suitable for the design method of the present digital circuit is shown in FIG. The configuration of FIG. 15 is almost the same as the configuration of FIG. The difference is that the number of nMOSs is increased by two and that two small pMOSs are mounted.
One basic cell can realize a 1-bit 2-port RAM memory cell. This is shown in FIG.

FIG. 17 shows an example of another gate array basic cell. The feature of this basic cell is the nMOS for logic.
And the direction in which the drain current flows between the nMOS and the pMOS for the inverter is rotated by 90 degrees. Since the gates of the inverter nMOS and pMOS are arranged close to each other, a feature is that a CMOS inverter can be easily configured. Another feature of the basic cell is that two nMOS gates serving as logic trees are connected in advance by gate electrodes. Therefore, there is a feature that a cell in which two trees are paired as shown in the 8-2 tree in FIG. 8B can be efficiently laid out. FIG. 18 shows an example in which a 6-2 tree (FIG. 8B) is laid out for one basic cell. Further, a cell in which two output terminals are taken out from the same tree as shown in the 6-4 tree of FIG. 8B can be realized by one basic cell, so that the area efficiency is also good. This cell also has a large nMOS and a small nMOS.
Since an MOS and a small pMOS are included, an SRAM memory cell can be efficiently configured. A memory cell for 2 bits can be realized by one basic cell.

Next, an example will be described in which a multiplier for performing multiplication of 8 bits × 8 bits is realized using the cell library of FIG. 1 or FIG.

FIG. 19 is an overall connection diagram of the present multiplier.
The configuration is a conventionally known carry save adder method. In this multiplier, all signal lines are complementary (that is,
A signal is transmitted by a pair of a signal and its inverted signal). This is because an inverted signal is input to the gate terminals of the pair of nMOSs constituting the tree, so that generating the inverted signal without using an inverter circuit operates faster. Even if such two inverted signals are generated, the circuit scale does not double. This is because there is a portion that can be shared between the signal and the circuit that generates the inverted signal (see 4-2 tree b in FIG. 21).

FIG. 20 shows that the multiplier is frequently used.
Full adder (PFA) with partial product generation circuit shown in FIG.
Is a 2-bit adder (ADD). In the full adder with a partial product generation circuit shown in FIG. 20, a logical function is realized by using two 4-1 trees c and two 4-2 trees c. This logic function is shown in the lower diagram of FIG. The full adder with a partial product generation unit is configured to perform high-speed generation of a partial product of a multiplier and addition of one bit in one stage. In the 2-bit adder of FIG. 21, a 2-bit adder is configured using 4-2 trees d, 4-2 trees b, and 6-4 trees. This is designed to particularly shorten the time during which the carry signal to the upper bit is generated after the carry signal C from the lower bit and its inverted signal CN are input.

In this embodiment, cells that output complementary signals are used (the above-mentioned PFA and ADD). In these, the circuit shown in FIG. 22 can be used in place of the output circuit shown in FIG. X and XN are input signals to this output circuit. For example, X changes from low to high,
Consider the case where XN changes from high to low. Since X is driven by the nMOS pass transistor in the preceding stage, X rises only to V _CC -V _T. At this time, since XN becomes low, M35 is turned on. As a result, the potential of X rises to _VCC . Therefore, M31, M
A steady current hardly flows through the 32 inverters. In this circuit, since a complementary signal is used, there is no need to take out a feedback signal from an output terminal.
S (M35, M36) is turned on at an early timing. Therefore, there is a feature that high-speed operation is possible even at a low voltage.

FIG. 23 shows an example of the configuration of a microprocessor using the cells of the embodiment of FIG. The instruction fetched from the main memory by the instruction fetch unit by the access by the address is decoded by the instruction decoder, and the instruction is decoded by the instruction decoder.
The instruction is executed by controlling the U, the general-purpose register, and the multiplier. In particular, the cell shown in FIG. 1 is equally applicable to a random logic such as an instruction decoder or a data path such as an ALU. By using the cell shown in FIG. 1, the microprocessor can be made more compact and can operate at high speed. Therefore, there is a great effect on improving the performance and reducing the size of various devices using the microprocessor.

Next, a method for realizing a high-performance integrated circuit in a shorter time than the gate array described in the above embodiment will be disclosed. In advance, PC3 (or PC
4) is spread over the chips in an array. After that, the connection netlist of the PC 3 is determined according to the application, and the second and third layer wirings are manufactured in accordance with the list to obtain a target integrated circuit. According to this method, an integrated circuit can be realized only by performing the wiring of the second and third layers after the logical design (determination of the netlist and the determination of the inter-cell wiring). To make an equivalent with a conventional gate array, the first layer,
Although it was necessary to perform wiring of three layers of the second layer and the third layer,
In the present invention, only two layers of wiring are required. Therefore, an integrated circuit can be realized in a short time. This is possible because the cell PC3 (or PC4) is extremely multifunctional as shown in FIG. 2, and one type of cell can realize a sufficient logical function.

[0101]

According to the present invention, a high-speed and high-integration integrated circuit can be realized in a short time. The number of transistors in the logic circuit can be reduced to about one half of that of the conventional CMOS circuit. For this reason, the area of the integrated circuit can be made smaller than before. Power consumption is also reduced. Further, in the same area, more circuits can be integrated. It is possible to realize more functions than this, and to achieve higher speed by utilizing parallel processing. In the integrated circuit of the present invention, the number of circuit stages in the critical path of the circuit can be reduced, and therefore, a higher-speed operation can be performed. In addition, since the delay time per circuit is high, high-speed operation is also possible. Therefore, a high-density and high-speed digital integrated circuit can be realized by using the present invention. In particular, this is an application-specific integrated circuit.
(ASIC), a compact and high-speed gate array, a standard cell integrated circuit, a cell-based integrated circuit, and the like can be realized. Also, a high-performance microprocessor, microcontroller, signal processing LSI, memory, and the like can be realized. Further, according to the present invention, a logic circuit and an SRAM can be efficiently mounted on a gate array, so that a high-performance system LSI can be realized in a short development period. Further, since the number of cells may be small in the cell library of the present invention, the time required for preparing the cell library is shorter than before. Therefore, the latest microfabrication technology can be applied to gate arrays and standard cell integrated circuits,
It is also suitable for high integration and high speed. Thus, the performance of the integrated circuit and the system using the same can be greatly improved. As described above, the industrial value of the present invention is extremely large.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a cell library including cells according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a logical function that can be realized by a cell according to an embodiment of the present invention.

FIG. 3 is a diagram showing a simple logic function realized by using two cells according to an embodiment of the present invention.

FIG. 4 is a diagram illustrating the implementation of a complex logic function using two cells according to an embodiment of the present invention.

FIG. 5 is a diagram showing a cell library using a conventional pass transistor circuit as a cell, and showing an example in which a simple logic function is realized using the cell.

FIG. 6 is a diagram illustrating an output inverter used in a cell according to an embodiment of the present invention.

FIG. 7 is a diagram illustrating an integrated circuit using a cell having a tree-type logic unit according to an embodiment of the present invention.

FIG. 8 is a diagram illustrating a configuration of a cell having a tree-type logic unit according to an embodiment of the present invention.

FIG. 9 is a diagram showing an example in which cells according to an embodiment of the present invention are arranged and wired as standard cells.

FIG. 10 is a diagram showing the layout and wiring of a conventional CMOS standard cell.

FIG. 11 is a diagram showing a configuration of the arrangement and wiring when the cell internal circuit of the present invention is arranged according to a conventional arrangement and wiring method.

FIG. 12 is a layout diagram when a cell having a tree-type logic unit according to an embodiment of the present invention is used as a gate array basic cell.

FIG. 13 is a layout diagram of a basic cell of a conventional CMOS gate array.

FIG. 14 is a layout diagram in the case where an SRAM memory cell is configured using the basic cell of FIG. 12;

FIG. 15 is a diagram showing a configuration of another gate array basic cell according to an embodiment of the present invention.

16 shows a two-port SRAM using the basic cell of FIG.
FIG. 3 is a layout diagram when a memory cell is configured.

FIG. 17 is a diagram showing a configuration of another gate array basic cell according to an embodiment of the present invention.

FIG. 18 is a cross-sectional view of the gate array basic cell shown in FIG.
FIG. 4 is a layout diagram when a two-tree cell is configured.

FIG. 19 is a diagram illustrating an 8 × 8-bit multiplier using a cell having a tree-type logic unit according to an embodiment of the present invention.

20 is a diagram illustrating a configuration of a full adder with a partial product generation unit used for the multiplier of FIG. 19;

21 is a diagram illustrating a configuration of a 2-bit adder used for the multiplier of FIG.

FIG. 22 is a diagram showing a configuration of an output circuit that can be used when output signals of cells are complementary according to an embodiment of the present invention.

FIG. 23 is a diagram showing a configuration of a data processing device using cells according to an embodiment of the present invention.

FIG. 24 is a diagram schematically illustrating a method of manufacturing an integrated circuit using cells according to an embodiment of the present invention.

[Explanation of symbols]

M1 to 36: MOSFET, N1, N2: internal nodes,
V _CC : power supply voltage, GND: ground potential.

Claims (14)

[Claims] 1. A design method for designing a semiconductor integrated circuit including a first logic circuit and a second logic circuit having a basic logic function different from the basic logic function of the first logic circuit, comprising: Are interconnected and call a first cell including a plurality of circuit elements having a predetermined arrangement from a cell library in which the plurality of cells are registered, based on a basic logic function of the first logic circuit, By specifying the signal application mode to the first cell and specifying the signal application mode to the first cell based on the basic logical function of the second logic circuit, the plurality of first A method of designing a semiconductor integrated circuit that determines an interconnect for each of cells. 2. The method according to claim 1, wherein the first cell has already been laid out in a mask pattern, and the cell library has at least an arrangement of the circuit elements, an input terminal position, and an output terminal of the first cell. A method for designing a semiconductor integrated circuit in which information on the position of a semiconductor integrated circuit is registered. 3. The design method of a semiconductor integrated circuit according to claim 1, wherein a position on the chip and a wiring layout of the plurality of first cells for which the interconnections have been determined are specified. 4. The method according to claim 1, wherein each of the plurality of first cells is a two-branch connection circuit. 5. The method according to claim 1, wherein each of the plurality of first cells includes a first, a second, a third and a fourth active element, a first and a second node,
Second, third, fourth, fifth, sixth, and seventh input terminals;
An output terminal, a first and a second impurity region, a first gate electrode of the first active element is connected to the first input terminal to which a first signal is input, A second gate electrode of the second active element is connected to the second input terminal to which a second signal is input, and a third gate electrode of the third active element is configured to receive a third signal. The fourth active element is connected to the third input terminal, the fourth gate electrode of the fourth active element is connected to the fourth input terminal to which a fourth signal is input, and the first active element is The source / drain path of the device is connected between the first node and the seventh input terminal, and the source / drain path of the second active element is connected to the first node and the second input terminal. A source / drain path of the third active element, the source / drain path of the third active element, A source / drain path of the fourth active element is connected between the second node and the fifth input terminal; a first source / drain path of the fourth active element is connected between the second node and the fifth input terminal; Is connected to the output terminal; the first impurity region is a first region sandwiched between the first gate electrode and the second gate electrode; and the first gate And a second and third region not interposed between the electrode and the second gate electrode, wherein the second impurity region is formed between the third gate electrode and the fourth gate electrode. A fourth region interposed therebetween, and fifth and sixth regions not interposed between the third gate electrode and the fourth gate electrode, wherein the first node comprises: The second node is connected to the first area, and the second node is connected to the second area and the fourth area. The fifth input terminal is connected to the fifth region, the sixth input terminal is connected to the sixth region, and the seventh input terminal is connected to the third region. For designing a semiconductor integrated circuit connected to a semiconductor device. 6. The method for designing a semiconductor integrated circuit according to claim 5, wherein said second signal has a phase opposite to said first signal, and said fourth signal has a phase opposite to said third signal. 7. The device according to claim 1, wherein each of the plurality of first cells includes a first, a second, a third, and a fourth active element, a first and a second inverter, and a first and a second inverter. , A first, a second, a third, a fourth, and a fifth input terminal, an output terminal, and a first and a second impurity region. The gate electrode is connected to the first input terminal to which a first signal is input. The second gate electrode of the second active element is connected to the first input terminal via the first inverter. A third gate electrode of the third active element is connected to the second input terminal to which a second signal is input; and a fourth gate electrode of the fourth active element is A source / drain path of the first active element, connected to the second input terminal via the second inverter; , A source / drain path of the second active element is connected between the first node and the second node. The source / drain path of the second active element is connected between the first node and the fifth input terminal. A source / drain path of the third active element is connected between the second node and the fourth input terminal; a source / drain path of the fourth active element is connected to the second A first node connected between the node and the third input terminal; a first node connected to the output terminal; a first impurity region including the first gate electrode and the second gate electrode And a second region and a third region that are not interposed between the first gate electrode and the second gate electrode. The region is sandwiched between the third gate electrode and the fourth gate electrode A fourth region, and fifth and sixth regions that are not sandwiched between the third gate electrode and the fourth gate electrode, wherein the first node is the first region The second node is connected to the second region and the fourth region, the third input terminal is connected to the fifth region, and the fourth input terminal Is connected to the sixth region, and the fifth input terminal is connected to the third region. 8. The method of designing a semiconductor integrated circuit according to claim 5, wherein said first node is connected to said output terminal via an inverter. 9. A semiconductor device comprising: a first logic circuit; and a second logic circuit realizing a basic logic function different from the basic logic function of the first logic circuit, wherein the first logic circuit and the second logic circuit are Each of the circuit elements includes a plurality of circuit elements, the plurality of circuit elements are arranged in the same manner in the first logic circuit and the second logic circuit, and the connection between the plurality of circuit elements is performed by the first logic circuit and the second logic circuit. A plurality of first signals corresponding to a basic logic function of the first logic circuit are input to a plurality of circuit elements common to the logic circuits and included in the first logic circuit, Are input with a plurality of second signals corresponding to the basic logic function of the second logic circuit, and the input form of the plurality of first signals to the first logic circuit Input form of the plurality of second signals to the second logic circuit The difference, the semiconductor integrated circuit differs from the basic logic functions of the first logic circuit and the second logic circuit is realized. 10. The semiconductor integrated circuit according to claim 9, wherein the plurality of first signals and the plurality of second signals are an input signal from another logic circuit or an outside of the semiconductor integrated circuit, or a first power supply of the semiconductor integrated circuit. A semiconductor integrated circuit having a potential or a second power supply potential; 11. The semiconductor device according to claim 9, wherein the plurality of circuit elements included in the first logic circuit and the second logic circuit are interconnected by a first-layer wiring of the semiconductor integrated circuit. A semiconductor integrated circuit in which input of first and second signals to a plurality of circuit elements included in one logic circuit and the second logic circuit is performed using wiring of a second or higher layer of the semiconductor integrated circuit. 12. The semiconductor integrated circuit according to claim 9, wherein said first logic circuit and said second logic circuit are two-branch connection circuits. 13. The semiconductor integrated circuit according to claim 9, wherein a basic logic function of said first logic circuit is a logical product and a basic logic function of said second logic circuit is a logical sum. circuit. 14. A semiconductor integrated circuit in which a circuit realizing a first logical function and a circuit realizing a second logical function are realized by a common internal circuit.