JP2001196386A - Field-effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a field-effect transistor which can reduce a voltage required for pinch-off and prevent a variance of voltage required for pinch-off between samples. SOLUTION: This field-effect transistor is provided with a compound semiconductor multilayered thin film having a GaAs substrate 1 and a GaInP channel layer 3, and an AlInP buffer layer 2a or an AlGaInP buffer layer is provided between the GaAs substrate 1 and GaInP channel layer 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor, and more particularly to a field effect transistor capable of reducing the voltage required for pinch-off and preventing the voltage required for pinch-off between samples.

[0002]

2. Description of the Related Art A semiconductor device having a compound semiconductor multilayer structure has excellent characteristics such as high electron mobility and wide band gap. For this reason, various semiconductor devices utilizing this characteristic have been developed, and one of them is a field effect transistor such as a metal-semiconductor field effect transistor (MESFET) or a high electron mobility transistor (HEMT).

In recent years, among these field-effect transistors, field-effect transistors having an AlGaAs buffer layer provided between a GaAs substrate and a GaInP channel layer have been developed.

FIG. 4 shows this field effect transistor.
After the A1 GaAs buffer layer 2c, the GaInP channel layer 3, the A1 GaAs Schottky contact layer 4, the GaAs layer 5, and the GaAs ohmic contact layer 6 are formed on the semi-insulating GaAs substrate 1, recess etching is performed by photolithography. To form a gate electrode 8, a source electrode 7, and a drain electrode 9, thereby forming a MESFET.

Since such a field effect transistor has a wide band gap of a channel layer and an excellent gate withstand voltage, it is expected to be applied to a base station of a cellular phone, a satellite communication system, and the like.

[0006]

However, the above-mentioned conventional field-effect transistor has an A1 GaAs buffer layer 2
When the GaInP channel layer 3 is formed on
Since it has a peII (staggered type) structure, TypeI
As compared with the structure, the electric affinity of the conduction band of the A1GaAs buffer layer 2c near the interface is very close to or less than the Fermi level, and the A1GaAs buffer layer 2c near the interface is very small.
c has a problem that charge is easily charged (K
wan-Shik Kim, Jong Bong L
ee, and Byung-Doo Choe; App
1ed Physics Letters, vo1.
65, (1994) p451).

As a result, in the conventional field-effect transistor, a leakage current is apt to occur due to the carriers 10 accumulated at the interface between the GaInP channel layer 3 and the A1GaAs buffer layer 2c, and the voltage required for pinch-off increases, or pinch-off between samples occurs. There has been a problem that the required voltage varies.

Accordingly, it is an object of the present invention to provide a field effect transistor which can reduce the voltage required for pinch-off and can prevent variations in the voltage required for pinch-off between samples.

[0009]

SUMMARY OF THE INVENTION The present invention provides the following field effect transistor to achieve the above object. [1] A field effect transistor including a compound semiconductor multilayer thin film having a GaAs substrate and a GaInP channel layer, wherein an AlInP buffer layer is provided between the GaAs substrate and the GaInP channel layer. Field effect transistor.

[2] The field effect transistor according to [1], wherein the AlInP buffer layer is doped with carbon at a predetermined concentration.

[3] The AlInP buffer layer is
Has a carbon concentration of 2 × 10¹⁶~ 3 × 10 ¹⁸cm^-3Is
The field effect transistor according to [2].

[4] The field effect transistor according to any one of [1] to [3], wherein the GaAs substrate is semi-insulating.

[5] The GaInP channel layer is doped with Si, Se, and Te at a predetermined concentration [1].
Field-effect transistor according to any one of [1] to [4].

[6] A field effect transistor provided with a compound semiconductor multilayer thin film having a GaAs substrate and a GaInP channel layer, wherein the GaAs substrate and the G
A field-effect transistor comprising an AlGaInP buffer layer provided between an aInP channel layer.

[7] The field effect transistor according to [6], wherein the AlGaInP buffer layer is doped with carbon at a predetermined concentration.

[8] The field effect transistor according to [7], wherein the AlGaInP buffer layer has a carbon concentration of 2 × 10 ^{16 to} 3 × 10 ¹⁸ cm ⁻³ .

[9] The field effect transistor according to [6] to [8], wherein the GaAs substrate is a semi-insulating substrate.

[10] The GaInP channel layer comprises:
The field effect transistor according to [6] to [9], wherein Si, Se, and Te are doped at a predetermined concentration.

As described above, the field effect transistor of the present invention is not a A1GaAs layer but an A1GaAs layer as a buffer layer between a GaAs substrate and a GaInP channel layer.
1InP layer or A1GaInP layer is provided.
The InP layer and the A1GaInP layer have a wider band gap than the GaInP channel layer, and the band junction type at the interface between the buffer layer and the channel layer surely has a Type I structure unlike the case where the A1GaAs layer is used as the buffer layer.

For this reason, in the field-effect transistor of the present invention, the GaInP channel layer always has a higher electron affinity, does not accumulate carriers on the buffer layer side, and can reduce the voltage required for pinch-off. Variations in voltage required for pinch-off between samples can be prevented.

[0021]

Embodiments of the present invention will be specifically described below with reference to the drawings.

1. First Embodiment FIG. 1 is an explanatory view schematically showing a field-effect transistor according to a first embodiment of the present invention.

As shown in FIG. 1, a field effect transistor according to the first embodiment of the present invention
And a field-effect transistor including a compound semiconductor multilayer thin film having a GaInP channel layer 3 and GaInP channel layer 3.
Al between the As substrate 1 and the GaInP channel layer 3
An InP buffer layer 2a is provided.

Further, the field effect transistor of the present invention comprises:
As other elements, an A1 GaAs Schottky contact layer 4 formed on a GaInP channel layer 3 in order and a Ga
An As layer 5 and a GaAs ohmic contact layer 6 are provided. After forming these layers, recess etching is performed by photolithography or the like as in the case of the conventional field effect transistor to form the gate electrode 8, the source electrode 7, and the drain electrode 9.

Here, the GaAs used in the present invention is used.
The s substrate 1 is preferably semi-insulating.

The GaIn used in the present invention is
The P channel layer 3 is preferably formed by doping Si, Se, and Te at a predetermined concentration.

Further, A1I used in the present invention
The nP buffer layer 2a is preferably formed by doping carbon. When the buffer layer is formed by the MOVPE method or the like, depending on the conditions (for example, when the supply amount of PH ₃ is set large for stoichiometry control), the buffer layer may become n-type without high resistance or semi-insulating property. However, by doping carbon, the resistance of such a buffer layer can be increased. The doping carbon concentration for increasing the resistance of the buffer layer is 2 × 10 ^{16 to} 3 × 10 ¹⁸ cm ³
Is preferred.

1. Second Embodiment FIG. 3 is an explanatory diagram schematically showing a field-effect transistor according to a second embodiment of the present invention.

The same parts as those in FIG. 1 are denoted by the same reference numerals, and duplicate description is omitted.
Is formed of AlGaInP. Otherwise, it is manufactured in the same manner as in the first embodiment.

[0030]

EXAMPLES The present invention will be described in more detail with reference to the following Examples, which should not be construed as limiting the present invention.

Example 1 A reduced pressure MOVPE machine was used as a semiconductor manufacturing apparatus, and TMA (trimethylaluminum) and TEG were used as raw materials.
(Triethyl gallium), TMI (trimethyl indium), PH ₃ (phosphine), AsH ₃ (arsine) and Si ₂ H ₆ (disilane), an i-A1 InP buffer layer (thickness 200 mm) is formed on the GaAs substrate 1. Si
Doped (2 × 10 ¹⁷ cm ⁻³ ) n-GaInP channel layer (170 mm thick) and Si-doped (5 × 10 ¹⁶ cm ⁻³ )
^-3 ) An n-A1GaAs Schottky contact layer was formed in this order to obtain a compound semiconductor multilayer thin film.

Since only the pinch-off performance test was performed this time, the GaAs Schottky contact layer shown in FIG. 1 was not formed.

Example 2 i-A1GaInP was used as a buffer layer on a GaAs substrate.
Example 1 except that a layer (thickness: 200 mm) was formed.
In the same manner as in the above, a compound semiconductor multilayer thin film was obtained.

Comparative Example 1 A compound semiconductor multilayer thin film was obtained in the same manner as in Example 1, except that an i-AlGaAs layer (thickness: 200 mm) was formed as a buffer layer on a GaAs substrate.

FIG. 2 shows the results of the evaluation test. The compound semiconductor multilayer thin films obtained in Examples 1 and 2 and Comparative Example 1 were evaluated for pinch-off performance by the following evaluation method. Note that the voltage at which the field effect transistor pinches off means an applied voltage when the carrier concentration is 1 × 10 ¹⁵ cm ⁻³ .

1. Evaluation Method A change in carrier concentration with respect to an applied voltage was measured by a CV method using a mercury probe to evaluate pinch-off performance.

2. Evaluation Results As shown in FIG. 3, the sheet carrier concentration of the channel layer was almost the same in Example 1 and the compound semiconductor multilayer thin film of Comparative Example 1. However, in the compound semiconductor multilayer thin film of Comparative Example 1, when the voltage was applied to about 1.5 V, the carrier concentration began to gradually decrease, and an applied voltage of 2.20 (V) was required to finally pinch off. .

On the other hand, in the compound semiconductor multilayer thin film of Example 1, the carrier concentration rapidly decreased at an applied voltage of about 1 V, and completely pinched off at 1.12 V. Example 2
The same result was obtained in the case of the compound semiconductor multilayer thin film.

[0039]

As described above, according to the field effect transistor of the present invention, since the A1InP layer or the A1GaInP layer is used as the buffer layer, the accumulation of carriers between the channel layer and the buffer layer can be suppressed. Can be reduced, and variations in the voltage required for pinch-off between samples can be prevented.

[0040]

[Brief description of the drawings]

FIG. 1 is an explanatory view schematically showing a field-effect transistor according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an applied voltage-carrier concentration curve by a CV method of the compound semiconductor multilayer thin films obtained in Example 1 and Comparative Example 1 of the present invention.

FIG. 3 is an explanatory diagram schematically showing a field effect transistor according to a second embodiment of the present invention.

FIG. 4 is a cross-sectional view schematically illustrating an example of a conventional field-effect transistor.

[Explanation of symbols]

 1: GaAs substrate 2a: A1InP buffer layer 2b: A1GaInP buffer layer 2c: A1GaAs buffer layer 3: GaInP channel layer 4: A1GaAs Schottky contact layer 5: GaAs layer 6: GaAs ohmic contact layer 7: source electrode 8: gate electrode 9 ： Drain electrode 10 ： Interface carrier

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Kazuto Takano 3550 Kida Yomachi, Tsuchiura-shi, Ibaraki Hitachi Cable, Ltd. Advanced Research Center F-term (reference) 5F102 FA00 GJ05 GK04 GL04

Claims (10)

[Claims] 1. A field effect transistor comprising a compound semiconductor multilayer thin film having a GaAs substrate and a GaInP channel layer, wherein an AlInP buffer layer is provided between the GaAs substrate and the GaInP channel layer. Field-effect transistor. 2. The field effect transistor according to claim 1, wherein said AlInP buffer layer is doped with carbon at a predetermined concentration. 3. The AlInP buffer layer has a carbon concentration of 2 × 10 ^{16 to} 3 × 10 ¹⁸ cm ^-3.
3. The field-effect transistor according to claim 1. 4. The field effect transistor according to claim 1, wherein said GaAs substrate is semi-insulating. 5. The GaInP channel layer is doped with Si, Se, and Te at a predetermined concentration.
3. The field-effect transistor according to claim 1. 6. A field-effect transistor comprising a compound semiconductor multilayer thin film having a GaAs substrate and a GaInP channel layer, wherein an AlGaInP buffer layer is provided between the GaAs substrate and the GaInP channel layer. Field-effect transistor. 7. The field effect transistor according to claim 6, wherein said AlGaInP buffer layer is doped with carbon at a predetermined concentration. 8. The field effect transistor according to claim 7, wherein said AlGaInP buffer layer has a carbon concentration of 2 × 10 ^{16 to} 3 × 10 ¹⁸ cm ^-3 . 9. The field effect transistor according to claim 6, wherein said GaAs substrate is semi-insulating. 10. The GaInP channel layer is doped with Si, Se, Te at a predetermined concentration.
10. The field effect transistor according to 9.