JP2001194426A - Device for tester inspection, semiconductor integrated circuit device and method for inspection of tester - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device, for tester inspection, by which whether a voltage and a signal are supplied normally to a device to be evaluated can be determined simply, by using a tester for a prescribed semiconductor integrated circuit device. SOLUTION: The device for tester inspection has the outer shape of a package, which is nearly identical to that of a semiconductor integrated circuit device to be evaluated by the tester. The device has the arrangement structure of an external terminal, which is nearly identical to that of the semiconductor integrated-circuit device. The device can be connected to the tester in the same manner as the semiconductor integrated circuit device. A resistance which has a prescribed resistance value is installed across the power-supply terminal and the grounding terminal of the device. In a state where a device body is connected to the tester and that a power-supply voltage is applied to the power-supply terminal, a current expected value, across the power-supply terminal and the grounding terminal, which is calculated approximately on the basis of the value of the power-supply voltage to be applied and on the basis of the resistance value of the resistance, is compared with a measured current value. Whether the power-supply voltage which is applied by the tester is normal is determined.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device used for testing a tester for a predetermined semiconductor integrated circuit device, a semiconductor integrated circuit device, and a method for testing a tester.

[0002]

2. Description of the Related Art In the manufacture of semiconductor integrated circuit devices such as DRAMs, SRAMs, and flash memories, in order to ensure good quality, evaluation (inspection) of the devices is generally performed during or after manufacturing. Done. As one of the evaluation methods, there has been conventionally known a test capable of detecting an output signal from an output terminal in a state where a power supply voltage is applied to a power supply terminal of the device and determining whether the device quality is good or not. In performing such a test, a tester that detects an output signal from the device while supplying a signal of a predetermined level to an input terminal while a power supply voltage is applied to a power supply terminal of the device is used.

FIG. 7 shows a semiconductor memory device as a conventional typical semiconductor integrated circuit device. The semiconductor memory device 50 has power supply pins 51 and 54 and ground pins 55 and 58 as external terminals, and a read control pin 52 and an address pin 5 for inputting and outputting control signals and data.
3. It has a write control pin 56 and a data input / output pin 57. When the device 50 is used, the power supply pins 51,
Binary signals are input to pins other than the ground pin 55 and the ground pins 55 and 58. In the semiconductor memory device 50, only one address pin 53 is provided, so that 2-bit data can be read and written.

When a test for evaluating the semiconductor memory device 50 is performed, a tester 60 as shown in FIG. 8 is used. The tester 60 includes a power supply, GND, read control,
Internal wiring for write control, address specification, and data input / output
(Reference numerals 61, 62, 63, 64, 65, 66, respectively)
) Is electrically connected to the semiconductor memory device 50 (not shown in FIG. 8) mounted on the socket 70. A power supply and a binary signal are supplied from the tester 60 to the semiconductor memory device 50 through these wirings. At this time, data write and read operations can be performed by a combination of supplied signals.

Then, the binary signal output from the input / output pin 57 of the semiconductor memory device 50 is read by the tester 60, and based on the level of this signal, the semiconductor memory device 50 is read.
Can be checked whether it is operating normally.
Normally, when the output signal from the semiconductor memory device 50 deviates from an expected value, it is determined that the semiconductor memory device 50 is not operating normally.

[0006]

By the way, actually,
The reason that the output signal from the semiconductor memory device 50 deviates from the expected value is the tester 60 itself and the socket 7 which is a part thereof.
It may be caused by an abnormality other than the evaluation target including 0 or wiring. For example, when wires electrically connected to the pins of the semiconductor memory device 50 are short-circuited, that is, when there is an abnormality on the tester 60 side, a desired signal is not supplied to the semiconductor memory device 50. Therefore, the semiconductor memory device 50 outputs a signal that is contrary to the expected value. As described above, in the test using the tester 60 as described above, it is determined whether the detected abnormality is due to the abnormality of the tester 60 or the semiconductor storage device 50 to be evaluated. There was a problem that it was difficult. In addition, when the output signal matches the expected value, it is determined to be "pass", so that the test is not necessarily performed correctly. Further, since an abnormality on the tester 60 side may occur due to deterioration of performance due to long-term use of the apparatus, there is a method for easily inspecting the tester 60 in addition to the periodic inspection of the tester 60. Is desirable.

In Japanese Patent Application Laid-Open No. H11-2658, for example, it is detected whether or not the applied power supply voltage is within a predetermined range, and when the applied power supply voltage is out of the predetermined range, a predetermined level is detected. A power supply voltage determination circuit that outputs a signal, one end of which is connected to a resistor connected to each signal terminal, and the other end of the resistor is connected between the power supply or ground, and the detection signal from the power supply voltage determination circuit By providing a switching transistor that conducts and pulls up or pulls down each of the signal terminals, a power supply voltage is determined inside the device, and a semiconductor integrated circuit device that can determine the quality of a product only by applying a DC voltage is provided. It has been disclosed. However, in such a semiconductor integrated circuit device, since the determination of the power supply voltage is performed inside the device, there is a possibility that a sufficient power supply from the outside cannot be ensured, and since the determination is performed only for the power supply voltage, An abnormality in the supply of a plurality of signals via a plurality of input terminals cannot be confirmed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned technical problems, and uses a tester for a predetermined semiconductor integrated circuit device to normally supply a voltage and a signal to a device to be evaluated. It is an object of the present invention to provide a tester inspection device, a semiconductor integrated circuit device, and a method for inspecting a tester, which can easily determine whether or not there is a tester.

[0009]

According to a first aspect of the present invention, a tester for a predetermined semiconductor integrated circuit device has substantially the same package outer shape and external terminal arrangement structure as a semiconductor integrated circuit device to be evaluated. A tester inspection device connectable to a tester like the semiconductor integrated circuit device,
A resistor having a predetermined resistance value is interposed between the power supply terminal and the ground terminal of the device, and the device body is connected to the tester, and a power supply voltage is applied to the power supply terminal. The power supply voltage applied by the tester is compared with the expected current value between the power supply terminal and the ground terminal, which is estimated from the value of the applied power supply voltage and the resistance value of the resistor, and the measured current value. Is configured to be able to determine whether or not is normal.

According to a second aspect of the present invention, there is provided a semiconductor integrated circuit device having substantially the same package outer shape and external terminal arrangement structure as a semiconductor integrated circuit device to be evaluated by a tester for a predetermined semiconductor integrated circuit device. A tester inspection device connectable to a tester similarly to an apparatus, comprising a plurality of input terminals to which a signal of a predetermined level is supplied from the tester, and a NAND from a plurality of signals supplied through the input terminals. A NAND circuit is provided, the device body is connected to the tester, and a power supply voltage is applied to a power supply terminal of the device, based on a combination of a plurality of signals supplied through the input terminal. NAND
The tester is configured to compare the expected output value of the circuit with the detected output value of the NAND circuit to determine whether or not the signal supplied to the input terminal by the tester is normal. It is a characteristic.

Further, according to a third invention of the present application, in a semiconductor integrated circuit device to be evaluated by a tester for a predetermined semiconductor integrated circuit device, a control signal for a control signal supplied from the tester at a predetermined level is provided. A plurality of input terminals are provided, and a NAND circuit is provided for taking a NAND from a plurality of control signals supplied via the control signal input terminals. The apparatus main body is connected to the tester, and a power supply terminal of the apparatus is provided. In the state where the power supply voltage is applied, the expected output value of the NAND circuit based on the combination of the plurality of control signals supplied through the control signal input terminal is compared with the detected output value of the NAND circuit. The tester is configured to be able to determine whether the control signal supplied to the input terminal is normal or not.

Further, in a fourth aspect of the present invention, there is provided a NOR circuit for taking NOR from a plurality of control signals supplied through the control signal input terminal.
The test operation of the tester is reset in response to the output of the R circuit.

Further, a fifth invention of the present application is a method for inspecting a tester for a predetermined semiconductor integrated circuit device using the tester inspection device according to claim 1 or 2, wherein the tester inspection is performed. While the device is connected to the tester, a power supply voltage is applied to a power supply terminal of the device,
The current value between the power terminal and the ground terminal where the resistor having the predetermined resistance value is interposed is measured, and the measured current value and the resistance value of the resistor and the power voltage value applied by the tester are used. It is characterized by comparing the estimated current expected value with the estimated current value to determine whether the power supply voltage is normally applied to the power supply terminal by the tester.

According to a sixth aspect of the present invention, there is provided a method for testing a tester for a predetermined semiconductor integrated circuit device using the tester testing device according to claim 1 or 2, wherein the device body is A signal is supplied to a plurality of input terminals of the device in a state where a power supply voltage is applied to a power supply terminal of the device, connected to the tester, and a NAND is generated from a control signal supplied through each of the input terminals. NA to take
A signal output through the ND circuit is detected, and an output expected value obtained based on a combination of signals supplied through the input terminals is compared with a detected output signal. Is determined whether or not the signal supplied to the terminal is normal.

[0015]

Embodiments of the present invention will be described below with reference to the accompanying drawings. Embodiment 1 FIG. FIG. 1 is a plan view showing a device for testing a tester for a semiconductor integrated circuit device according to a first embodiment of the present invention. This device 10 has the same package outer shape as the typical semiconductor memory device 50 shown in FIG. 7, and is provided with a plurality of external terminals along the device body. The device 10 has power supply pins 1 and 4, ground (GND) pins 5 and 8, first, second and third input pins 2, 3, and 6, and an output pin 7 as external terminals. . These pins correspond to the eight pins provided in the semiconductor memory device 50, respectively. Device 10
The power supply pins 1 and 4 and the GND pins 5 and 8 are connected to the power supply pins 51 and 54 and the GND pins 55 and 5 of the semiconductor memory device 50, respectively.
8, the device 10 has the same arrangement structure of these pins as the pins of the semiconductor memory device 50. The first, second, and third input pins 2, 3, and 6 of the device 10 correspond to pins used only for signal input, such as control pins and address pins, of the semiconductor memory device 50. The output pin 7 corresponds to the input / output pin 57 of the semiconductor memory device 50. The first and second
2 and 3 are supplied with a binary signal (ie, “0” or “1”), and an output pin 7 outputs a binary signal.

As described above, the package outer shape of the device 10 and the arrangement of the external terminals are changed according to the semiconductor memory device 5.
0, the semiconductor memory device 50
Can be realized. In the following description,
The device 10 is called a dummy device, and correspondingly, the semiconductor storage device 50 is called a real device.

FIG. 2 shows a connection relationship between the power supply pins 1 and 4 and the GND pins 5 and 8 inside the dummy device 10. The power supply pins 1 and 4 and the GND pins 5 and 8 are connected by resistors. 11 are connected. Also, FIG.
It represents the relationship between the first, second and third input pins 2, 3 and 6 and the output pin 7 inside the dummy device 10, and the relationship between the input pins 2, 3 and 6 and the output pin 7 And a NAND circuit 13 for taking NAND from signals supplied through three input pins 2, 3 and 6. The NAND circuit 13 outputs “0” when all the signals from the input pins are “1”, and outputs “1” otherwise.

The dummy device 10 is a real device 5
It has the same package outer shape as that of the conventional semiconductor integrated circuit device, and has a chip (not shown) on which a silicon wafer has been processed, similarly to a typical semiconductor integrated circuit device of the related art. The chip inside the device is provided with a resistor 11 shown in FIG. 2, a transistor constituting the NAND circuit 13 of FIG. 3, various pins, and pads for connecting the internal chip. The elements to be formed on the chip have a very simple configuration.Even when transistors and wiring are formed on the chip, advanced miniaturization technology is not particularly required, and the size of the transistor must be included in the package. May be larger if possible.
Thereby, the dummy device 10 is replaced with the real device 5.
The dummy device 10 can be realized by a simpler wafer process as compared with the case of 0, and is advantageous in terms of yield.

In this embodiment, a tester for a predetermined semiconductor integrated circuit device is inspected using the dummy device 10. As this tester, the same tester 60 (see FIG. 8) described in the related art is used.
0 is the semiconductor memory device 50 to be evaluated by the tester 60.
Is set to the tester 60 in the same manner as described above. That is, the dummy device 10 is mounted on the socket 70 connected to the tester 60 via various wirings as shown in FIG.

Next, a simple operation of the dummy device 10 connected to the tester 60 for a semiconductor integrated circuit device will be described with reference to FIG. The voltage V is applied to the power pins 1 and 4 of the dummy device 10 using the tester 60.
Apply dd. As described above, the power supply pins 1, 4
Is connected to GND pins 5 and 8 via a resistor 11 (having a resistance value R). In this case, when the power supply current Idd is roughly calculated, Becomes The estimated value is compared with the actually measured current value to determine whether or not the power supply voltage of the tester 60 is abnormal.

In this embodiment, the signals supplied from the tester 60 to the first, second and third input pins 2, 3 and 6 are changed while the power supply voltage is applied.
In each case, the signal output from the output pin 7 is checked. When the signal output from the output pin 7 is different from the expected output value, it is determined that an abnormality exists on the tester 60 side. Table 1 shows the above input pins 2 and 3
6 and 7 show the relationship between the signals supplied to the second and sixth and the expected output values.
As described above, a binary signal is supplied to each of the input pins, and the binary signals supplied from the first, second, and third input pins 2, 3, and 6 are output through the NAND circuit 13 to the output pin. 7 is output as a binary signal. Note that H in the table represents "1", while L represents "0". table
1: Relationship between input signal and expected output value Based on this relationship, if an abnormality is observed when using types A to C, it is determined that there is a short circuit between the power supply and the input or between the output and GND. If an abnormality is sometimes seen, it is determined that there is a short circuit between GND and the input or between the power supply and the output.

FIG. 4 is a flowchart of a test process of the tester 60 using the dummy device 10. In this inspection process, the power supply voltage Vdd is first applied from the tester 60 to the power supply pins 1 and 4 of the dummy device 10 in a state where the dummy device 10 is mounted on the socket 70 of the tester 60 (# 10). Thereby, the dummy device 10
A current flows from the power supply pins 1 and 4 into the device. As described above, the power supply pins 1, 4 and the GND pins 5,
A resistor 11 is interposed between the resistor 11 and the resistor 8, and a desired magnitude of a current flowing inside the device is determined using the resistance value R of the resistor 11 and the voltage Vdd applied from the tester 60. In step # 11, it is determined whether or not a desired voltage is applied from the tester 60 to the power supply pins 1 and 4 by measuring a current flowing in the device and comparing the measured current with a desired magnitude. If the measured current greatly deviates from the desired value as a result of # 11, the tester 60
, It is determined that the desired voltage has not been applied, and the inspection result is NG. On the other hand, when the measured current substantially matches the desired magnitude, the process proceeds to # 12.

In # 12, the first, second, and third dummy devices 10 are placed in a state where the power supply voltage is applied from the tester 60.
To the input pins 2, 3 and 6 of FIG. At this time, dummy device 1
Since the 0 output pin 7 takes an input NAND, the expected value of the signal output from the output pin 7 is determined based on the combination of the signals. In # 13, the signal output from the output pin 7 is compared with its expected value. If the output signal deviates from the expected value, the test result is NG. For example, when the first and second input pins 2 and 3 are short-circuited in a part of the tester 60 and only the same signal is given, the output expected value is H in the tests of types A and B in Table 1 ,
The output signal from the dummy device 10 becomes L and is determined to be NG. On the other hand, if the output signal matches the expected value in # 13, the path is determined. ♯ If it is determined to be NG in the process of 11 and 13, the tester 6
It is determined that there is an abnormality of 0.

As described above, if the dummy device 10 is used, the current value measured between the power supply pins 1 and 4 and the GND pins 5 and 8 with the power supply voltage applied by the tester 60 is roughly estimated in advance. By comparing with the expected value obtained, it is possible to determine whether or not there is an abnormality related to the supply of the power supply voltage on the tester 60 side, and to determine whether the input pins 2, 3, 6
, The output signal detected from the output pin 7 is compared with an expected output value based on a combination of the signals to determine whether there is an abnormality in the signal supply on the tester 60 side. Can be. As a result, the tester 60 can be easily inspected,
Anomalies can be found relatively easily. This effect can be seen periodically during the shipping test process during mass production, for example.
It is very effective if used (for example, for each lot).

Hereinafter, another embodiment of the present invention will be described.
This will be described in detail. Embodiment 2 FIG. FIGS. 5A and 5B are circuit diagrams each showing a part of the configuration in the semiconductor integrated circuit device according to the second embodiment of the present invention. This semiconductor integrated circuit device 20
Is a dynamic RAM capable of performing a data holding operation as well as reading and storing data. In the second embodiment, a circuit configuration for a tester test such as the tester test device according to the first embodiment is incorporated in the semiconductor integrated circuit device 20. The signal processing is performed between a standard mode in which an input signal is processed based on a normal operation as a DRAM and a test mode in which the input signal is processed based on a tester inspection operation.
It can be arbitrarily switched.

As can be seen from FIG. 5 (a), the semiconductor integrated circuit device 20 has three input pins, and a signal input via the input pins is an internal signal in the standard mode. Used for control. The semiconductor integrated circuit device 20 includes a NAND circuit 22 for performing NAND using signals from these input pins, and a NOR circuit 22.
A NOR circuit 23 is provided. FIG.
As can be seen from (b), the semiconductor integrated circuit device 20 is provided with inverter circuits 27 and 28 for inverting a signal to be output from an arbitrarily selected output pin to the outside. Although only two inverter circuits are shown in FIG. 5B, in reality, the same number of inverter circuits are provided corresponding to the number of output pins of the semiconductor integrated circuit device 20.

When the semiconductor integrated circuit device 20 is evaluated, a tester 60 capable of applying a power supply voltage to the device 20 and detecting an output signal from the device 20 to judge the quality of the device 20 is shown in FIG. Used as shown. With the semiconductor integrated circuit device 20 mounted on the tester 60, a TM (test mode) signal is input via an address bus by using an address key, and a test mode is set. When the test mode is set, NAND is taken from three input signals in the NAND circuit 22,
Detected as an output signal. In this case, the expected output value based on the combination of the input signals as shown in Table 1 in the first embodiment is compared with the actually detected output signal.
At this time, if the output signal deviates from the expected output value, tester 6
It is determined that an abnormality exists on the 0 side. Further, in the second embodiment, when all the three input signals are L (“0”) at the time of setting the test mode, it is not necessary to consider this case. Then, the inspection work of the tester 60 is reset. As a result, operations not required by the tester 60 can be omitted, and the time required for testing the tester 60 can be reduced.

Further, at the time of setting the test mode, it is possible to select an arbitrary input / output pin by a combination of the address pins and invert the output signal thereof. This allows
Output pins can be individually checked. still,
In this case, it is not necessary to use all the address pins.

As described above, by providing a configuration in which the test mode can be set in the semiconductor integrated circuit device 20, an abnormality in the signal supply on the tester 40 side is determined even at the module stage, and the tester 60 Inspection becomes possible.

Embodiment 3 6 (a) and 6 (b) show a tester inspection device 30 (dummy device) and a generally known semiconductor integrated circuit device 40 (400mil 54pin TSOP (II)) according to Embodiment 3 of the present invention, respectively. 128MSD
FIG. 3 is a plan view of a RAM (8M × 16)). The tester inspection device 30 has the same package outer shape as that of the semiconductor integrated circuit device 40 which is an actual device, similarly to the case of the first embodiment, and has power supply pins (Vdd), GND as external terminals. Pins (Vss), input pins and output pins. The power supply pin and the GND pin are arranged in the same manner as the real device, and the input pins are the control pins of the real device.
(/ CS, / RAS, / CAS, / WE, CLK, CK
E, DQMU, DQML) and address pins (A0 to A1)
The output pins are arranged corresponding to the input / output pins (DQ0 to DQ15) of the actual device.
The tester inspection device 30 having such an outer shape and a pin arrangement can be mounted in a 128 MS DRAM socket.

As in the first embodiment, the power supply pin of the tester inspection device 30 is connected to GND.
A resistor is provided between the pins. This allows
By measuring the current flowing between the power supply pin and the GND pin, it is possible to confirm whether a desired voltage is applied to the power supply voltage. The output from the output pin of the tester test device 30 is a NAND of 22 inputs. In addition, without being limited to the NAND, any circuit (logic) may be used as long as it can be confirmed that the signals supplied to the respective input pins are independent. In this case, the relationship between the input signal and the expected output value needs to have a combination suitable for the circuit.

The present invention is not limited to the illustrated embodiment, and it goes without saying that various improvements and design changes can be made without departing from the spirit of the present invention. For example, in the above-described embodiment, a semiconductor memory device is described as a semiconductor integrated circuit device. However, the present invention is not limited to this, and a device for testing a tester and a semiconductor integrated circuit device including the same can be used as a general semiconductor integrated circuit device. Applicable to

[0033]

According to the first aspect of the present invention, a tester for a predetermined semiconductor integrated circuit device has substantially the same package outer shape and external terminal arrangement structure as a semiconductor integrated circuit device to be evaluated. A tester inspection device connectable to a tester similarly to a semiconductor integrated circuit device, wherein a resistor having a predetermined resistance value is interposed between a power supply terminal and a ground terminal of the device, and the device body is Connected to the tester, in a state where the power supply voltage is applied to the power supply terminal, a current expectation value between the power supply terminal and the ground terminal, which is estimated from a value of the applied power supply voltage and a resistance value of the resistor; The tester can be easily tested by comparing the measured current value with the measured current value to determine whether the power supply voltage applied by the tester is normally supplied. It can, also, it is possible to find an abnormality in the supply of the power supply voltage applied by the tester relatively easily.

According to the invention of claim 2 of the present application, a tester for a predetermined semiconductor integrated circuit device has substantially the same package outer shape and external terminal arrangement structure as a semiconductor integrated circuit device to be evaluated. A tester inspection device that can be connected to a tester similarly to a semiconductor integrated circuit device,
The tester has a plurality of input terminals to which a signal of a predetermined level is supplied from the tester, and a NAND circuit which takes a NAND from the plurality of signals supplied through the input terminals is provided. In a state where a power supply voltage is applied to a power supply terminal of the device, an output expected value of the NAND circuit based on a combination of a plurality of signals supplied through the input terminal and an output value of the detected NAND circuit are calculated. In comparison, the tester is configured to be able to determine whether or not the signal supplied to the input terminal is normal, so that the tester can be easily inspected. It is relatively easy to find out about anomalies in the supply of water.

Further, according to the third aspect of the present invention, in a semiconductor integrated circuit device to be evaluated by a tester for a predetermined semiconductor integrated circuit device, a control signal for supplying a control signal of a predetermined level from the tester is provided. A plurality of input terminals, and a NAND circuit that takes NAND from a plurality of control signals supplied through the control signal input terminal is provided. The apparatus main body is connected to the tester, and a power supply of the apparatus is provided. With the power supply voltage applied to the terminal, the expected output value of the NAND circuit based on a combination of a plurality of control signals supplied through the control signal input terminal and the detected output value of the NAND circuit In comparison, the tester is configured to be able to determine whether the control signal supplied to the input terminal is normal or not, so that the tester can be easily inspected. It can, also, it is possible to find an abnormality in the supply of the signal by the tester relatively easily.

Further, according to the invention of claim 4 of the present application, there is provided a NOR circuit which takes NOR from a plurality of control signals supplied through the control signal input terminal. In response to the output of the tester, the test operation of the tester is reset, so that the operation not required by the tester can be omitted, and the time required for the tester inspection can be shortened.

According to a fifth aspect of the present invention, there is provided a method for testing a tester for a predetermined semiconductor integrated circuit device using the tester testing device according to the first or second aspect, In a state where the tester inspection device is connected to the tester, a power supply voltage is applied to a power supply terminal of the device, and a current between the power supply terminal and the ground terminal in which the resistor having the predetermined resistance value is interposed. The measured current value is compared with the measured current value and the expected current value estimated from the resistance value of the resistor and the power supply voltage value applied by the tester. In order to determine whether or not the voltage is normally applied, the tester can be easily inspected, and it is relatively easy to find an abnormality in the supply of the power supply voltage applied by the tester. It is possible.

According to a sixth aspect of the present invention, there is provided a method for inspecting a tester for a predetermined semiconductor integrated circuit device using the tester inspecting device according to the first or second aspect, A device main body is connected to the tester, a signal is supplied to a plurality of input terminals of the device in a state where a power supply voltage is applied to a power supply terminal of the device, and a control signal supplied through each of the input terminals From NAND
, And a signal output from the NAND circuit is compared with an expected output value obtained based on a combination of signals supplied through the input terminals, and a detected output signal. The tester can easily inspect the tester to determine whether the signal supplied to the input terminal is normal, and it is relatively easy to find an abnormality in the signal supply by the tester. It is.

[Brief description of the drawings]

FIG. 1 is a plan view showing a tester inspection device according to Embodiment 1 of the present invention.

FIG. 2 is a diagram showing a connection relationship between a power supply pin and a ground pin in the tester inspection device.

FIG. 3 is a diagram showing a connection relationship between input pins and output pins in the tester inspection device.

FIG. 4 is a flowchart of an inspection process using the tester inspection device.

FIG. 5A is a circuit diagram showing a part of a configuration in a semiconductor integrated circuit device according to a second embodiment of the present invention; (B)
FIG. 3 is a circuit diagram showing another part of the configuration inside the semiconductor integrated circuit device.

FIG. 6 (a) is a plan view showing a tester inspection device according to Embodiment 3 of the present invention. FIG. 1B is a plan view showing a typical semiconductor integrated circuit device.

FIG. 7 is a simplified plan view showing a conventional semiconductor integrated circuit device.

FIG. 8 is an explanatory diagram showing a state in which a semiconductor integrated circuit device is evaluated using a tester.

[Explanation of symbols]

1, 4 power supply pin, 2 first input pin, 3 second input pin, 5, 8 GND pin, 6 third input pin, 7 output pin, 10, 30 tester inspection device, 20 semiconductor integrated circuit device

Claims (6)

[Claims] 1. A tester for a predetermined semiconductor integrated circuit device has substantially the same package outer shape and external terminal arrangement structure as a semiconductor integrated circuit device to be evaluated, and can be connected to a tester similarly to the semiconductor integrated circuit device. Wherein a resistor having a predetermined resistance value is interposed between a power terminal and a ground terminal of the device, a device body is connected to the tester, and the power terminal When the power supply voltage is applied to the power supply voltage, the expected current value between the power supply terminal and the ground terminal, which is estimated from the value of the applied power supply voltage and the resistance value of the resistor, is compared with the measured current value. A tester inspection device for a semiconductor integrated circuit device, which is configured to determine whether or not a power supply voltage applied by the tester is normal. 2. A tester for a predetermined semiconductor integrated circuit device has substantially the same package outer shape and external terminal arrangement structure as a semiconductor integrated circuit device to be evaluated, and can be connected to the tester similarly to the semiconductor integrated circuit device. A tester inspection device, comprising: a plurality of input terminals to which a signal of a predetermined level is supplied from the tester; and a NAND circuit that takes a NAND from the plurality of signals supplied through the input terminals. A NAN based on a combination of a plurality of signals supplied through the input terminal in a state where a device body is connected to the tester and a power supply voltage is applied to a power supply terminal of the device.
The tester is configured to compare the expected output value of the D circuit with the detected output value of the NAND circuit to determine whether or not the signal supplied to the input terminal by the tester is normal. A tester inspection device for a semiconductor integrated circuit device, characterized in that: 3. A semiconductor integrated circuit device to be evaluated by a tester for a predetermined semiconductor integrated circuit device, comprising: a plurality of control signal input terminals to which a control signal of a predetermined level is supplied from the tester; From a plurality of control signals supplied through input terminals for
A NAND circuit for taking ND is provided. A plurality of devices supplied through an input terminal for the control signal in a state where a device main body is connected to the tester and a power supply voltage is applied to a power supply terminal of the device. By comparing the expected output value of the NAND circuit based on the combination of the control signals with the detected output value of the NAND circuit, it can be determined whether or not the control signal supplied to the input terminal by the tester is normal. A semiconductor integrated circuit device characterized by being configured as described above. 4. A NOR circuit for taking a NOR from a plurality of control signals supplied through an input terminal for the control signal, and performing an inspection operation of the tester in response to an output of the NOR circuit. 4. The semiconductor integrated circuit device according to claim 3, wherein the device is reset. 5. A method for inspecting a tester for a predetermined semiconductor integrated circuit device using the tester inspection device according to claim 1 or 2, wherein the tester inspection device is connected to the tester. A power supply voltage is applied to a power supply terminal of the device, and a current value between a power supply terminal and a ground terminal in which the resistor having the predetermined resistance value is interposed is measured. By comparing the resistance value of the resistor and the expected current value estimated from the power supply voltage value applied by the tester, it is determined whether or not the power supply voltage is normally applied to the power supply terminal by the tester. A method for testing a tester for a semiconductor integrated circuit device. 6. A method for inspecting a tester for a predetermined semiconductor integrated circuit device using the tester inspection device according to claim 1 or 2, wherein a device main body is connected to the tester. A signal is supplied to a plurality of input terminals of the device while a power supply voltage is applied to the power supply terminal.
A signal output through a NAND circuit that takes a D signal is detected, and an expected output value obtained based on a combination of signals supplied through the input terminals is compared with a detected output signal. A method for testing a tester for a semiconductor integrated circuit device, comprising: determining whether a signal supplied to an input terminal is normal.