JP2001189765A - Data slicer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data slicer which can take out an optimum digital signal against the fluctuation of the state of a demodulation signal. SOLUTION: The data slicer 30 is constituted of a reference voltage holding circuit 32 generating and holding reference voltage based on the demodulation signal and a voltage comparison circuit 31 comparing the demodulation signal with reference voltage and outputting a comparison result. The slicer slices the demodulation signal by reference voltage and converts it into the digital signal. The reference voltage holding circuit 31 is provided with a time constant circuit constituted of a resistance circuit 40 and a capacitor 34, a charging/ discharging switch circuit 35 interrupting a charging/discharging control route charging/discharging the capacitor 34 through the resistance circuit 40, a charging/discharging control circuit 38 controlling the on/off of the charging/ discharging switch circuit 35 and a time constant control circuit 37 which sets the time constant of the time constant circuit to an optimum value at every lapse time based in lapse time after the demodulation signal is inputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread spectrum technique, for example, in a wireless communication apparatus in a data transmission system related to Bluetooth or the like, a demodulated signal is sliced by a reference voltage and converted into a digital signal. It relates to a data slicer.

[0002]

2. Description of the Related Art In recent years, automobile telephones, mobile telephones and wireless LA
2. Description of the Related Art In a communication device used in a wireless network system such as an N (local area network), a communication system using a spread spectrum technique which is excellent in secrecy and confidentiality has attracted attention.

[0003] Spread spectrum technology uses a code that does not depend on a data signal to spread the signal over a frequency band wider than the frequency bandwidth required for data transmission.
This is for transmitting data to be transmitted.

In general, in a communication system using a spread spectrum technique, an input baseband signal such as voice is modulated on a transmission side and input to a spreading circuit (modulation circuit). After being used and spread spectrum, it is transmitted to the communication partner as a high-frequency signal. On the receiving side, the spread spectrum signal received from the communication partner is demodulated (despread) using the same spreading code as that on the transmitting side.

At this time, since the demodulation cannot be performed if the spreading codes are different, the communication system using the spread spectrum technique is hardly affected by an interference wave due to multipath or the like. There is an advantage that demodulation can be performed.

A communication system using such a spread spectrum technique includes a direct spread (Direct Spread).
Method and frequency hopping (Frequency Ho)
pping) method. In the direct spreading method, spreading is performed while multiplying a narrow band modulated wave by a spreading code, and a certain continuous frequency band is used uniformly. On the other hand, in the frequency hopping method, a signal is spread within a frequency band by randomly switching the frequency of a carrier wave when performing communication with a communication partner using a spreading code.

FIG. 3 is a diagram for explaining a conventional radio communication apparatus. FIG. 3 (a) is a main block diagram showing a schematic configuration, and FIG. 3 (b) shows a transmission frequency spectrum. FIG. The conventional wireless communication apparatus of FIG. 3 uses the frequency hopping method as a communication method using a spread spectrum technique. A conventional wireless communication device will be described below with reference to FIG.

FIG. 3A shows a conventional wireless communication device 10.
Has the following circuit configuration. A reception unit including a band-pass filter (BPF) 13, a high-frequency amplifier 14, a mixer 15, a demodulation circuit 20, and a data slicer 130 is connected to a reception-side contact 12a of the switch circuit 12 to which the antenna 11 is connected. A transmission unit including a transmission circuit 17 and a modulation circuit 16 is connected to the transmission-side contact 12b of the switch circuit 12, and a CPU (Central Processing Unit)
19 connected to a PLL (Phase Locked).
Loop) The frequency synthesizer 18 is provided with the mixer 15
And the modulation circuit 16.

Next, the conventional radio communication apparatus 1 shown in FIG.
The operation of 0 will be described. The switch circuit 12 to which the antenna 11 is connected switches to the reception contact 12a at the time of reception, connects the antenna 11 and the bandpass filter 13, and switches to the transmission contact 12b at the time of transmission. The transmission circuit 17 is connected.

On the receiving side, the spread spectrum signal from the communication partner side is transmitted from the antenna 11 to the switch circuit 12.
Of the bandpass filter 13 via the receiving side contact 12a
The band pass filter 13 passes only the frequency of the used frequency band, is amplified by the high frequency amplifier 14, is frequency-converted by the mixer 15, is demodulated by the demodulation circuit 20, and is demodulated by the data slicer 130.
Is converted into a digital signal.

On the transmitting side, an input baseband signal such as voice, which is transmission data, is spread spectrum by a modulating circuit 16 and then transmitted by a transmitting circuit 17 as a high frequency signal via a transmitting side contact 12b of the switch circuit 12. It is transmitted from the antenna 11 to the communication partner.

FIG. 3A shows a conventional wireless communication apparatus 10.
Is a communication system using spread spectrum technology.
The frequency hopping method is used, and this frequency hopping is performed by the CPU 19 based on a program by the PLL.
By controlling the frequency synthesizer 18, the frequency from the PLL frequency synthesizer 18 is hopped, and is transmitted as a high frequency signal from the transmission circuit 17 to the communication partner side from the antenna 11 via the transmission side contact 12 b of the switch circuit 12. As shown in the transmission frequency spectrum of FIG. 3B, the transmission frequencies are spread evenly over the entire use frequency band.

FIG. 4 is a schematic circuit diagram of a conventional data slicer in the conventional wireless communication device 10 of FIG. A conventional data slicer will be described below with reference to FIG.

The conventional data slicer 130 has the following circuit configuration. The output of the demodulation circuit 20 is connected to the (+) side input of the comparator (voltage comparison circuit) 131 and to the (−) side input of the comparator 131 via the reference voltage holding circuit 132. The reference voltage holding circuit 132 includes a resistor 136 and a charge / discharge switch circuit 135.
Are connected in series, and one of the resistors 136 is connected to the demodulation circuit 20.
And one of the charge / discharge switch circuits 135 is connected to the (−) side input of the comparator 131.
Further, a capacitor 134 is connected between a connection point between one of the charge / discharge switch circuits 135 and the (−) side input of the comparator 131 and the ground. The charge / discharge control circuit 133 is connected to the charge / discharge switch circuit 135.

Next, the conventional data slicer 130 shown in FIG.
The operation of will be described. The charge / discharge control circuit 133 controls on / off of the charge / discharge switch circuit 135,
When the charge / discharge switch circuit 135 is on, the resistor 136 and the capacitor 134 are short-circuited, and the capacitor 134 is charged via the resistor 136 by the demodulation signal output from the demodulation circuit 20. When the charge / discharge switch circuit 135 is turned off while the capacitor 134 is charged, the resistor 136 and the capacitor 134 are opened, and the charged voltage of the capacitor 134 is maintained. The charge voltage stored in the capacitor 134 is used as the comparator 13
1 reference voltage.

The comparator 131 compares the reference voltage of the (−) side input with the voltage level of the demodulated signal of the (+) side input, and determines whether the voltage level of the demodulated signal is high or low. Output as a signal.

[0017]

The time constant when the capacitor 134 is charged via the resistor 136 by the demodulated signal output from the demodulation circuit 20 is the time constant of the resistor 136 in the conventional data slicer 130 shown in FIG. And the capacitance of the capacitor 134, and the time constant is fixed. In order to eliminate the ripple of the charging voltage of the capacitor 134, that is, the reference voltage of the (−) side input of the comparator 131, it is necessary to increase the time constant. However, when the time constant is increased, the followability of the reference voltage to the head of the demodulated signal is deteriorated, and the data slicer 130 cannot accurately convert the demodulated signal into a digital signal.

Conversely, if the time constant is reduced in order to make the reference voltage follow the leading part of the demodulated signal,
The charging voltage of the capacitor 134, that is, the comparator 13
Ripple occurs in the reference voltage of the (−) side input of No. 1 and this reference voltage cannot be stably held.
No. 30 has a problem that the demodulated signal cannot be accurately converted to a digital signal.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to control the time constant of the reference voltage holding circuit 132 by varying the time constant according to the state of the demodulated signal. Another object of the present invention is to provide a data slicer capable of extracting an optimal digital signal.

[0020]

A data slicer according to the present invention comprises: a reference voltage holding circuit for generating and holding a reference voltage based on a demodulated signal in a data transmission system; and comparing the demodulated signal with the reference voltage. A data comparison circuit that slices the demodulated signal with the reference voltage and converts the signal into a digital signal, wherein the reference voltage holding circuit includes a time constant circuit including a resistor circuit and a capacitor; A charge / discharge switch circuit for interrupting a charge / discharge current path through which a signal charges / discharges the capacitor via the resistor circuit; a charge / discharge control circuit for controlling on / off of the charge / discharge switch circuit; A time constant control circuit that sets the time constant of the time constant circuit to an optimum value for each elapsed time based on the elapsed time after the setting. It is an feature.

Further, the resistance circuit of the data slicer of the present invention comprises a plurality of resistors and a plurality of switch circuits, and the time constant control circuit turns on / off the plurality of switch circuits, The time constant of the time constant circuit is controlled by changing the charge / discharge current path.

Further, the resistance circuit of the data slicer according to the present invention is characterized by comprising a plurality of resistors connected in series and a plurality of switch circuits connected in parallel to the plurality of resistors.

The demodulated signal comprises a periodic continuous signal (for example, a preamble signal) and a discontinuous signal (for example, a data signal), and the time constant control circuit of the data slicer according to the present invention comprises: In a signal input period, control is performed such that the time constant of the time constant circuit is reduced during a specified time at the beginning of input, and the time constant of the time constant circuit is increased after the specified time has elapsed. It is.

Further, the charge / discharge control circuit of the data slicer according to the present invention turns on the charge / discharge switch circuit during an input period of a periodic continuous signal (for example, a preamble signal) of the demodulated signal and outputs a discontinuous signal (for example, During the input period of the data signal, the charge / discharge switch circuit is controlled to be turned off.

[0025]

FIG. 1 is a schematic circuit diagram of a data slicer according to one embodiment of the present invention, and FIG. 2 is a waveform diagram showing the operation of the data slicer according to one embodiment of the present invention. It is. A data slicer according to an embodiment of the present invention will be described below with reference to FIG.

The data slicer 30 according to the embodiment of the present invention shown in FIG. 1 has the following circuit configuration. The output of the demodulation circuit 20 is connected to the (+) side input of a comparator (voltage comparison circuit) 31 and the reference voltage holding circuit 3
2 is connected to the (−) side input of the comparator 31.

The reference voltage holding circuit 32 has a resistance circuit 40 and a charge / discharge switch circuit 35 connected in series.
Is connected to the output of the demodulation circuit 20, and one of the charge / discharge switch circuits 35 is connected to the (-) side input of the comparator 31. Further, the charge / discharge switch circuit 35
A capacitor 34 is connected between a connection point between one of the two and the (−) side input of the comparator 31 and the ground. The charge / discharge control circuit 33 is connected to the charge / discharge switch circuit 35.

In the resistor circuit 40, a resistor 41 and a resistor 42 are connected in series, one of the resistors 42 is connected to the output of the demodulation circuit 20, and one of the resistors 41 is connected to a charge / discharge switch circuit 35.
It is connected to the. Further, a switch circuit 43 is connected in parallel to the resistor 42, and a time constant control circuit 37 is connected to the switch circuit 43.

In one embodiment of the present invention, the resistance circuit 40
Is composed of two resistors, a resistor 41 and a resistor 42, and one switch circuit of a switch circuit 43 connected in parallel to the resistor 42. However, the present invention is not limited to this. It consists of a plurality of connected resistors and a plurality of switch circuits connected in parallel to the plurality of resistors,
The time constant control circuit 37 may be connected to the plurality of switch circuits.

In one embodiment of the present invention, the resistor circuit 40 includes a resistor 41 and a resistor 42 connected in series,
2 is connected in parallel with the switch circuit 43. However, the present invention is not limited to this. The resistor circuit includes a plurality of resistors and a plurality of switch circuits. The time constant control circuit 37 turns on and off the plurality of switch circuits,
Any circuit that can control the time constant of the time constant circuit by changing the charge / discharge current path of the resistance circuit 40 may be used.

In one embodiment of the present invention, the output of the demodulation circuit 20 is connected to the (+) side input of the comparator 31, and the reference voltage holding circuit 32 is connected to the (−) side input of the comparator 31. However, without being limited to this, the reference voltage holding circuit 32 may be connected to the (+) side input of the comparator 31, and the output of the demodulation circuit 20 may be connected to the (−) side input of the comparator 31.

Next, the operation of the data slicer 30 according to the embodiment of the present invention shown in FIG. 1 will be described. The charge / discharge control circuit 33 controls on / off of the charge / discharge switch circuit 35, and when the charge / discharge switch circuit 35 is on,
The resistance circuit 40 and the capacitor 34 are short-circuited, and the capacitor 34 is charged via the resistance circuit 40 by the demodulated signal output from the demodulation circuit 20. When the charge / discharge switch circuit 35 is turned off while the capacitor 34 is charged, the resistor circuit 40 and the capacitor 34 are opened, and the charged voltage of the capacitor 34 is maintained. The charging voltage held in the capacitor 34 becomes a reference voltage of the comparator 31.

The comparator 31 compares the voltage level of the reference voltage of the (−) side input with the voltage level of the demodulated signal of the (+) side input, and determines whether the voltage level of the demodulated signal is high or low. Output as a signal.

The time constant control circuit 37 includes a switch circuit 43
When the switch circuit 43 is off, the resistor 42 is opened, and the resistance value of the resistor circuit 40 becomes a value obtained by adding the resistors 41 and 42. The time constants of the resistors 41 and 4
The time constant is determined by the value obtained by adding the resistance value of 2 and the capacitance value of the capacitor 34, and the time constant becomes large. When the switch circuit 43 is on, the resistor 42 is short-circuited, the resistance value of the resistor circuit 40 is the value of only the resistor 41, and the time constant of the resistor circuit 40 and the capacitor 34 is equal to the value of the resistor 41 only and the capacitor. The time constant is determined by the capacitance value of No. 34.

That is, the time constant control circuit 37 controls the on / off of the switch circuit 43 to change the time constant composed of the resistor circuit 40 and the capacitor 34. When the switch circuit 43 is off, The time constant increases, and when the switch circuit 43 is on, the time constant decreases.

Next, the operation of the data slicer 30 of FIG. 1 will be described in more detail with reference to the waveform diagram of FIG. 2 showing the operation of the data slicer according to one embodiment of the present invention. In FIG. 2, (a) is a demodulated signal Vin + of the (+) side input of the comparator 31, (b) is a reference voltage Vin- of the (−) side input of the comparator 31, and (c) is a reference voltage of the demodulated signal Vin +. (D) shows the output digital signal V of the comparator 31.
The respective waveforms of “out” and “out” are shown with a common time axis on the horizontal axis. The switch circuit 43 is represented as SW1, and the charge / discharge switch circuit 35 is represented as SW2. Hereinafter, description will be given along the time axis.

(1) Operation during period t0 to t1 (SW1
(ON, SW2 ON, small time constant) At time t0, a periodic continuous signal (for example, a preamble signal) that is a demodulated signal Vin + is input. The switch circuit 43 (SW1) is turned on by the time constant control circuit 37,
The resistor 42 is short-circuited, and the resistance value of the resistor circuit 40 is
And the time constant composed of the resistor circuit 40 and the capacitor 34 is determined by the value of only the resistor 41 and the capacitance value of the capacitor 34, and the time constant becomes smaller.

The charge / discharge control circuit 33 turns on the charge / discharge switch circuit 35 (SW2), short-circuits the resistor circuit 40 and the capacitor 34, and charges the capacitor 34 via the resistor circuit 40 with the demodulated signal Vin +. The charging voltage of the capacitor 34, that is, the reference voltage Vin− of the (−) side input of the comparator 31 increases, and becomes substantially stable by time t1. During this period, as described above, the time constant is small, so that the reference voltage Vin− increases in a short period.
The reference voltage Vin has a ripple. The comparator 31 compares the voltage level of the reference voltage Vin− of the (−) side input with the voltage level of the demodulated signal Vin + of the (+) side input, and outputs a digital signal Vout.

(2) Operation during period t1 to t2 (SW1
OFF, SW2 ON, large time constant) A periodic continuous signal (for example, a preamble signal) that is the demodulated signal Vin + is continuously input. The switch circuit 43 (SW1) is turned off by the time constant control circuit 37, the resistor 42 is opened, the resistance value of the resistor circuit 40 becomes a value obtained by adding the resistors 41 and 42, and the resistor circuit 40 and the capacitor 3
The time constant consisting of 4 is determined by the value obtained by adding the resistors 41 and 42 and the capacitance value of the capacitor 34, and the time constant becomes large.

The charge / discharge switch circuit 35 (SW2) is kept on by the charge / discharge control circuit 33, and the resistance circuit 4
0 and the capacitor 34 are short-circuited, and the demodulated signal Vin +
As a result, the capacitor 34 is charged via the resistor circuit 40, and the charged voltage of the capacitor 34, that is, the reference voltage Vin− of the (−) side input of the comparator 31 continues in a stable state. As described above, since the time constant is large during this period, the reference voltage Vin- has no ripple. The comparator 31 compares the voltage level of the reference voltage Vin− of the (−) side input with the voltage level of the demodulated signal Vin + of the (+) side input, and outputs a digital signal Vout.

(3) Operation from period t2 (SW2 off) At time t2, the demodulated signal Vin + changes from a periodic continuous signal (for example, a preamble signal) to a discontinuous signal (for example, a data signal). At time t2, the charge / discharge switch circuit 35 (SW2) is turned off, and the resistance circuit 40 and the capacitor 3
4 is released and the charging voltage of the capacitor 34, that is, the reference voltage Vin− of the (−) side input of the comparator 31 is:
Next, it is held until the charge / discharge switch circuit 35 (SW2) is turned on.

[0042]

According to the data slicer of the present invention, a reference voltage holding circuit that generates and holds a reference voltage based on a demodulated signal in a data transmission system, compares the demodulated signal with the reference voltage, and outputs a comparison result A data comparison circuit that slices the demodulated signal with the reference voltage and converts the signal into a digital signal, wherein the reference voltage holding circuit includes a time constant circuit including a resistor circuit and a capacitor; A charge / discharge switch circuit for interrupting a charge / discharge current path for charging / discharging the capacitor via the resistor circuit, a charge / discharge control circuit for controlling on / off of the charge / discharge switch circuit, and the demodulation signal being input A time constant control circuit that sets a time constant of the time constant circuit to an optimal value for each elapsed time based on a later elapsed time. Is shall.

Therefore, the time constant of the time constant circuit in the reference voltage holding circuit is set to an optimum value for each elapsed time based on the elapsed time after the input of the demodulated signal. Therefore, an optimum reference voltage can be obtained and an optimum digital signal can be always taken out.

According to the data slicer of the present invention,
The resistor circuit includes a plurality of resistors and a plurality of switch circuits, and the time constant control circuit turns on / off the plurality of switch circuits and changes a charge / discharge current path of the resistor circuit. The time constant of the time constant circuit is controlled.

Therefore, the demodulated signal is obtained by configuring the resistance circuit in the time constant circuit with a plurality of resistors and a plurality of switch circuits, and changing the time constant in a plurality of stages by turning on and off the plurality of switch circuits. , The time constant of the time constant circuit in the reference voltage holding circuit can be set to an optimal value more delicately for each elapsed time, so that the state of the demodulated signal changes over time. Also in this case, a more optimal reference voltage can be obtained, and an optimal digital signal can be always taken out.

According to the data slicer of the present invention,
The resistor circuit includes a plurality of resistors connected in series and a plurality of switch circuits connected in parallel to the plurality of resistors.

Therefore, setting the time constant of the time constant circuit in the reference voltage holding circuit to an optimum value for each elapsed time based on the elapsed time after the input of the demodulated signal,
It can be implemented with a simple circuit configuration.

According to the data slicer of the present invention,
The demodulated signal is composed of a periodic continuous signal (for example, a preamble signal) and a discontinuous signal (for example, a data signal). The control is performed such that the time constant of the time constant circuit is reduced, and the time constant of the time constant circuit is increased after the lapse of the specified time.

Therefore, in the period during which the periodic continuous signal is input, the time constant of the time constant circuit is reduced during the specified time period at the beginning of the input, so that the reference voltage can be adjusted with respect to the head of the periodic continuous signal. Can quickly follow the appropriate value. In addition, in the period in which the periodic continuous signal is input, after the lapse of the specified time, that is, after the reference voltage follows the appropriate value, the time constant of the time constant circuit is increased, so that there is no ripple. A reference voltage can be obtained. Therefore, even when the demodulated signal is composed of a periodic continuous signal and a discontinuous signal, an optimal reference voltage can be obtained, and an optimal digital signal can always be extracted.

According to the data slicer of the present invention,
The charge / discharge control circuit turns on the charge / discharge switch circuit during an input period of a periodic continuous signal (for example, a preamble signal) of the demodulated signal, and turns on the charge / discharge switch during an input period of a discontinuous signal (for example, a data signal). The circuit is controlled to be turned off.

Therefore, after the periodic continuous signal is input during the periodic continuous signal period of the demodulated signal and an optimum reference voltage is obtained, the discontinuous signal period is cut off during the discontinuous signal period. In addition, it is possible to prevent the ripple of the reference voltage due to the discontinuous signal. Therefore, even when the demodulated signal is composed of a periodic continuous signal and a discontinuous signal,
An optimal reference voltage can be obtained, and an optimal digital signal can be always taken out.

[Brief description of the drawings]

FIG. 1 is a schematic circuit diagram of a data slicer according to an embodiment of the present invention.

FIG. 2 is a waveform chart showing an operation of the data slicer according to one embodiment of the present invention.

FIG. 3 is a diagram illustrating a conventional wireless communication device;
(A) is a main part block circuit diagram showing a schematic configuration,
(B) is a diagram showing a transmission frequency spectrum.

FIG. 4 is a schematic circuit diagram of a conventional data slicer.

[Explanation of symbols]

 Reference Signs List 20 demodulation circuit 30 data slicer 31 comparator (voltage comparison circuit) 32 reference voltage holding circuit 33 charge / discharge control circuit 34 capacitor 35 charge / discharge switch circuit 37 time constant control circuit 40 resistance circuit 41, 42 resistor 43 switch circuit

Claims (5)

[Claims] A reference voltage holding circuit for generating and holding a reference voltage based on a demodulated signal in a data transmission system;
A data comparison circuit configured to compare the demodulated signal with the reference voltage and output a comparison result, wherein the data slicer converts the demodulated signal into a digital signal by slicing the demodulated signal with the reference voltage. A time constant circuit including a resistor circuit and a capacitor, a charge / discharge switch circuit for interrupting a charge / discharge current path through which the demodulated signal charges / discharges the capacitor via the resistor circuit, and turns on / off the charge / discharge switch circuit. A charge / discharge control circuit for controlling, and a time constant control circuit for setting a time constant of the time constant circuit to an optimal value for each elapsed time based on an elapsed time after the demodulation signal is input,
A data slicer comprising: 2. The resistance circuit includes a plurality of resistors and a plurality of switch circuits. The time constant control circuit turns on and off the plurality of switch circuits, and sets a charge / discharge current path of the resistance circuit. 2. The data slicer according to claim 1, wherein a time constant of said time constant circuit is controlled by changing. 3. The data slicer according to claim 2, wherein the resistor circuit includes a plurality of resistors connected in series and a plurality of switch circuits connected in parallel to the plurality of resistors. 4. The demodulated signal is composed of a periodic continuous signal and a discontinuous signal, and the time constant control circuit controls the time constant during a period of input of the periodic continuous signal within a specified time of initial input. 4. The data slicer according to claim 1, wherein a control is performed such that a time constant of the circuit is reduced and a time constant of the time constant circuit is increased after the predetermined time has elapsed. 5. The charge / discharge control circuit according to claim 1, wherein the charge / discharge switch circuit is turned on during an input period of the periodic continuous signal of the demodulated signal, and is turned off during an input period of the discontinuous signal. 5. The data slicer according to claim 4, wherein the data slicer is controlled.