JP2001189324A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device of low parasitic capacity which is superior in high-frequency characteristics. SOLUTION: Related to an HEMT substrate 15, an n+-GaAs contact layer 14 on an n-AlGaAs electron supply layer 13 is selectively removed, to form a recess channel 23. A polyparaxylilene film 16 of the dielectric constant of about 2.4 is formed on the n+-GaAs contact layer 14, while an opening part 18b is formed above the recess channel 23. A Ti/Pt/Au gate electrode 24a of T-type structure which is Schottky-junctioned to the n-AlGaAs electron supply layer 13 via the opening part 18b is formed in the recess channel 23. Related to the HEMT of recess gate structure, the polyparaxylilene film 16 of dielectric constant about 2.4 is used as an insulating film near the Ti/Pt/Au gate electrode 24a of a T-type structure.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a HEMT (High Electron Mob).
ility Transistor (High Electron Mobility Transistor), MESFET (Metal Semiconductor)
conductor Field Effect Tra
The present invention relates to a field-effect semiconductor device such as a metal-semiconductor field-effect transistor (nsistor).

[0002]

2. Description of the Related Art In recent years, with the demand for high-speed computer systems, the demand for high-speed integrated circuit devices has increased. In particular, compound semiconductors such as GaAs (gallium arsenide) have a large electron mobility as compared with Si (silicon), and therefore, application to integrated circuit devices is greatly expected.

As a method for forming a fine and low-resistance gate electrode in a conventional field effect transistor such as HEMT or MESFET, a method described in Japanese Patent Application Laid-Open No. Hei 5-326564 has been proposed. Hereinafter, a method of manufacturing the MESFET having the recess gate structure according to the above proposal will be described with reference to FIGS.
This will be described with reference to the cross-sectional views of FIG.

In each figure, reference numeral 31 denotes a semi-insulating GaAs substrate, reference numeral 32 denotes a GaAs buffer layer, and reference numeral 3 denotes a GaAs buffer layer.
Reference numerals 3a and 33b denote n-GaAs layers, reference numerals 34a and 34b denote n-AlGaAs layers, reference numeral 35 denotes an n ⁺ -GaAs layer, reference numeral 36 denotes a SiON (silicon oxynitride) film, reference numeral 37 denotes a photoresist, and reference numeral 38 denotes a first. Recess
The groove, reference numeral 39 is a SiO ₂ (silicon dioxide) sidewall, reference numeral 40 is a second recess groove, and reference numeral 41 is Ti / Pt.
/ Au gate electrode, reference numeral 42a is AuGe / Ni / Au
The gate electrode, reference numeral 42b indicates an AuGe / Ni / Au source electrode, and the reference numeral 42b indicates an AuGe / Ni / Au drain electrode.

First, as shown in FIG. 14, a GaAs buffer layer 32, an n-type
GaAs layer 33a, n-AlGaAs layer 34a, n-G
aAs layer 33b, n-AlGaAs layer 34b, and n ⁺
After the epitaxial growth of the GaAs layer 35,
On this n ⁺ -GaAs layer 35, a SiON film 36 is
Deposit 00 nm.

Next, as shown in FIG.
After coating and forming a photoresist 37 on the iON film 36,
An opening pattern having a diameter of 0.5 μm is formed in a region where a gate electrode is to be formed. Subsequently, using the photoresist 37 having this opening pattern as a mask, R1E (Reactive Ion Etc) is used.
hing; reactive ion etching) to form the SiON film 3
6 is selectively anisotropically etched, and furthermore, n ⁺ -GaAs
The layer 35 and the n-AlGaAs layer 34b are selectively anisotropically etched. Thus, the n-AlGaAs layer 34 on the n-GaAs layer 33b is provided in the region where the gate electrode is to be formed.
a and the n ⁺ -GaAs layer 35 is selectively removed from the first
Is formed.

Next, as shown in FIG. 16, after removing the photoresist 37, plasma CVD (Chemical V) is performed.
apor Deposition; by chemical vapor deposition), SiO ₂
A film is deposited to a thickness of 400 nm. Then, the SiO ₂ film is anisotropically etched by R1E to form the first recess groove 3.
8, a SiO ₂ film is left on the sidewall of
An iO ₂ side wall 39 is formed.

[0008] Next, as shown in FIG.
Using the N film 36 and the SiO ₂ side wall 39 as a mask, the n-GaAs layer 33b and the n-AlGaAs layer 34
a is selectively etched away to form an undercut of about 0.1 μm under the SiO ₂ sidewall 39.
Thus, the n-GaAs layer 33b on the n-GaAs layer 33a and the n-AlGaAs
A second recess groove 40 where the layer 34a is selectively removed is formed.

Next, as shown in FIG. 18, a Ti film, a Pt film, and an Au film are sequentially deposited on the entire surface of the substrate to form a Ti film.
After forming the / Pt / Au laminated film, the Ti / Pt / Au
The u laminated film is selectively etched by ion milling. Thus, in the second recess groove 40, nG
A mushroom-type Ti / Pt / Au gate electrode 41 for Schottky connection is formed on the aAs layer 33a.

Finally, as shown in FIG.
After removing the N film 36, an AuGe film, Ni
A film and an Au film are sequentially deposited to form AuGe / Ni / Au.
A laminated film is formed. Thus, the AuGe / Ni / A that is ohmicly connected to the Ti / Pt / Au gate electrode 41 is formed.
uGe electrode 42a, and AuGe / Ni / Au connected ohmicly on the n ⁺ -GaAs layer 35 on both sides of the AuGe / Ni / Au gate electrode 42a.
A source electrode 42b and an AuGe / Ni / Au drain electrode 42c are formed.

As described above, a MESFET having a Ti / Pt / Au gate electrode 41 having a fine gate length defined by the interval between the SiO ₂ side walls 39 formed on the side wall of the first recess groove 38 is provided. Complete.

[0012] than in the manufacturing method of the gate electrode in a field effect transistor, such as a conventional MESFET as described, the opening condition of the photoresist 37 as shown in FIG. 15, an anisotropic etching condition by RlE the SiON film 36, n ⁺ -GaAs layer 35 and n-AlGaAs layer 34
b) Anisotropic etching conditions by RIE, and FIG.
By making full use of the conditions for depositing the SiO ₂ side wall 39 and the conditions for anisotropic etching with RIE as shown in FIG. 5, the gate length of the Ti / Pt / Au gate electrode 41 can be reduced.

[0013]

However, in the above-mentioned conventional method for manufacturing a field-effect transistor, the SiON film 36 and the SiO ₂ side wall 3 are used as insulating films.
9 or the like. These SiO-based insulating films have a relatively high relative dielectric constant.
For example, the relative dielectric constant of the SiON film varies depending on the ratio of O (oxygen) and N (nitrogen), but is about 4 to 6. Also,
The relative dielectric constant of the SiO ₂ film is about 3.9.

As long as the insulating film having a high relative dielectric constant is used in the vicinity of the gate electrode, it is inevitable that the parasitic capacitance becomes large. Therefore, in order to improve the high frequency characteristics of the field effect transistor, Even if the gate length is shortened or a semiconductor material having high mobility is used, there is a limit in improving the high frequency characteristics of the field effect transistor.

The present invention has been made in view of the above problems, and has as its object to provide a semiconductor device having a small parasitic capacitance and excellent high-frequency characteristics.

[0016]

The above object is achieved by the following semiconductor device according to the present invention. That is, claim 1
Is a semiconductor device having a semiconductor substrate, an insulating film formed on the semiconductor substrate, and a gate electrode formed on the semiconductor substrate through an opening formed in the insulating film, The insulating film has a relative dielectric constant of 1 to 3.5.

As described above, in the semiconductor device according to the first aspect, the relative dielectric constant of the insulating film near the gate electrode formed on the semiconductor substrate is 1 to 3.5, so that the normal dielectric film near the gate electrode is formed. Since the dielectric constant is smaller than the relative dielectric constant of the SiO-based insulating film used as the insulating film, the parasitic capacitance is reduced and the high-frequency characteristics of the semiconductor device are improved.

In the semiconductor device according to the first aspect, the insulating film having a relative dielectric constant of 1 to 3.5 is preferably an organic dielectric film containing carbon (C) atoms. Examples of such an organic dielectric film containing carbon atoms include a polyimide film (with a relative dielectric constant of about 3.0 to 3.5), a polyparaxylylene film (with a relative dielectric constant of about 2.4), and benzocyclobutene. There is an organic dielectric film such as a film (relative permittivity of about 2.0).

As the insulating film having a relative dielectric constant of 1 to 3.5, a dielectric film containing fluorine (F) atoms is also suitable.
Examples of such a dielectric film containing a fluorine atom include an inorganic dielectric film such as a SiOF (silicon oxyfluoride) film.

Further, as the insulating film having a relative dielectric constant of 1 to 3.5, a dielectric film containing boron (B) atoms is also suitable.
Examples of such a dielectric film containing boron atoms include, for example, SiOB obtained by replacing fluorine in the above-mentioned SiOF film with boron.
There is an inorganic dielectric film such as a film.

According to a fifth aspect of the present invention, in the semiconductor device according to any one of the first to fourth aspects, the gate electrode has a T-type structure.

As described above, in the semiconductor device according to the fifth aspect, the gate electrode has a T-type structure, that is, since the gate electrode has a T-shaped cross section, the gate resistance is reduced. The high frequency characteristics of the device are improved.

[0023]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
An embodiment of the present invention will be described. (First Embodiment) FIG. 1 is a schematic sectional view showing a HEMT having a recess gate structure according to a first embodiment of the present invention. FIGS. 2 to 7 each show a method of manufacturing the HEMT having a recess gate structure shown in FIG. FIG. 4 is a process cross-sectional view for explaining FIG.

As shown in FIG. 1, in the HEMT having the recess gate structure according to the present embodiment, a semi-insulating Ga
On a As substrate 11, a high-purity GaAs channel layer 12, n
The HEMT substrate 15 is formed by sequentially laminating the -AlGaAs electron supply layer 13 and the n ⁺ -GaAs contact layer 14.

In the HEMT substrate 15,
The n ⁺ -GaAs contact layer 14 on the n-AlGaAs electron supply layer 13 is selectively removed to form a recess groove 19 having a diameter of about 0.7 μm. A polyparaxylylene film 16 having a thickness of about 200 nm and a relative dielectric constant of about 2.4 is formed on the n ⁺ -GaAs contact layer 14 of the HEMT substrate 15. An opening 18b having a diameter of 0.5 μm is formed in the polyparaxylylene film 16 above the recess groove 19. That is, the diameter of the opening 18 b is smaller than the diameter of the recess groove 19.

The opening 18b of the polyparaxylylene film 16 is filled with a Ti / Pt / Au laminated film in which a Ti film, a Pt film, and an Au film are sequentially laminated. Ti / Pt / Au gate electrode 20a for Schottky connection to n-AlGaAs electron supply layer 13
Are formed.

Although not shown, Ti / Pt / A
An AuGe / Ni / Au source electrode and Au are formed on the n ⁺ -GaAs contact layer 14 sandwiching the u gate electrode 20a.
Ge / Ni / Au drain electrodes are formed in ohmic connection.

As described above, in the recess groove 19, n-
T for Schottky connection to the AlGaAs electron supply layer 13
In the HEMT having the recess gate structure in which the i / Pt / Au gate electrode 20a is formed, the Ti / Pt / Au
As the insulating film near the u gate electrode 20a, the relative dielectric constant is 2.
This embodiment is characterized in that about four polyparaxylylene films 16 are used.

Next, the HE of the recess gate structure shown in FIG.
The method of manufacturing the MT will be described with reference to FIGS. First, as shown in FIG. 2, a semi-insulating GaAs substrate 11 is formed.
On top, a high-purity GaAs channel layer 12 and n-AlGaAs
s electron supply layer 13 and n ⁺ -GaAs contact layer 1
4 are epitaxially grown. Thus, the HE layer in which these layers are stacked on the semi-insulating GaAs substrate 11
An MT substrate 15 is formed.

Subsequently, the n ⁺ -G
After spin-coating a polyparaxylylene polymer on the aAs contact layer 14, curing is performed at a temperature of 250 ° C. for 5 minutes. Thus, a polyparaxylylene film 16 having a thickness of about 200 nm and a relative dielectric constant of about 2.4 is formed on the n ⁺ -GaAs contact layer 14.

Next, as shown in FIG. 3, an electron resist 17 is applied and formed on the entire surface of the polyparaxylylene film 16, and then, a 0.5 μm Opening 18a is formed.

Then, as shown in FIG. 4, using the electronic resist 17 having the opening 18a as a mask,
1E, the polyparaxylylene film 16 is selectively anisotropically etched to form an opening 18b exposing the surface of the n ⁺ -GaAs contact layer 14.

Next, as shown in FIG. 5, using the electron resist 17 and the polyparaxylylene film 16 as a mask,
The n ⁺ -GaAs contact layer 14 is selectively etched away using a citric acid-based etchant. At this time, the etching is also advanced in the lateral direction so that an undercut is formed below the polyparaxylylene film 16. Thus, the n ⁺ -GaAs on the n-AlGaAs electron supply layer 13 is provided in the region where the gate electrode is to be formed on the HEMT substrate 15.
recess groove 19 from which s-contact layer 14 is selectively removed
To form

Next, as shown in FIG. 6, a Ti film, a Pt film, and an Au film are sequentially vapor-deposited on the entire surface of the substrate, and are deposited on the n-AlGaAs electron supply layer 13 and the electron resist 17 in the opening 18. A Ti / Pt / Au laminated film 20 is formed.

Next, as shown in FIG. 7, an unnecessary Ti over the electron resist 17 is formed by using an organic solvent.
The / Pt / Au laminated film 20 is removed. Thus, nA
A Ti / Pt / Au gate electrode 20a for Schottky connection with the n-AlGaAs electron supply layer 13 is formed in the recess groove 19 where the n ⁺ -GaAs contact layer 14 on the lGaAs electron supply layer 13 is selectively removed.

Finally, although not shown, the polyparaxylylene film 16 is selectively removed to form the n ⁺ -GaAs contact layer 14 sandwiching the Ti / Pt / Au gate electrode 20a.
After exposing the surface, the n ⁺ -GaAs contact layer 1
On Au, an AuGe / Ni / Au source electrode and an AuGe / Ni / Au drain electrode which are connected to each other ohmicly are formed.

As described above, the Ti / Pt / Au gate electrode 20a for Schottky connection with the n-AlGaAs electron supply layer 13 is formed in the recess groove 19, and the vicinity of the Ti / Pt / Au gate electrode 20a is formed. A HEMT having a recess gate structure using a polyparaxylylene film 16 having a relative dielectric constant of about 2.4 as an insulating film is completed.

As described above, according to the present embodiment, the polyparaxylylene film 16 having a relative dielectric constant of about 2.4 is used as the insulating film near the Ti / Pt / Au gate electrode 20a in the HEMT having the recess gate structure. Therefore, when compared with the case where a conventional SiO-based insulating film having a high relative dielectric constant such as a SiO ₂ film or a SiON film is used,
Since the parasitic capacitance is reduced, the high frequency characteristics of the HEMT can be improved.

(Second Embodiment) FIG. 8 is a schematic sectional view showing a HEMT having a recess gate structure according to a second embodiment of the present invention. FIGS. 9 to 13 are HEMTs having the recess gate structure shown in FIG. FIG. 9 is a process cross-sectional view for describing the manufacturing method of the device. The same elements as those of the HEMT shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

As shown in FIG. 8, the HEMT having the recess gate structure according to the present embodiment has substantially the same configuration as the HEMT having the recess gate structure shown in FIG. 1 of the first embodiment. , Ti / Pt in FIG.
Instead of the / Au gate electrode 20a, a T-type Ti / Pt / Au gate electrode having a T-shaped cross section is provided. Therefore, description of other configurations common to the first embodiment will be omitted.

Next, the HE of the recess gate structure shown in FIG.
The method of manufacturing the MT will be described with reference to FIGS. First, as shown in FIG. 9, FIG.
To semi-insulating GaAs in the same manner as shown in FIGS.
On a substrate 11, a high-purity GaAs channel layer 12, n-A
The HEMT is formed by sequentially epitaxially growing the lGaAs electron supply layer 13 and the n ⁺ -GaAs contact layer 14.
A substrate 15 is formed, and n ⁺ -Ga of the HEMT substrate 15 is formed.
After a polyparaxylylene film 16 having a thickness of about 200 nm and a relative dielectric constant of about 2.4 is formed on the As contact layer 14, the polyparaxylylene film 16 is selectively anisotropically etched to obtain n An opening 18b exposing the surface of the ⁺ -GaAs contact layer 14 is formed.

Next, as shown in FIG. 10, an image reversal resist 21 is applied on the entire surface of the substrate, and then an opening 22 having a reverse taper shape is formed in a gate electrode formation region including the opening 18b.

Next, as shown in FIG. 11, the image reversal resist 21 and the polyparaxylylene film 1 are formed.
Using a citric acid-based etchant with 6 as a mask,
The n ⁺ -GaAs contact layer 14 is selectively removed by etching. At this time, the etching is also advanced in the lateral direction so that an undercut is formed below the polyparaxylylene film 16. Thus, the n-AlGaAs electron supply layer 13 is formed in the region where the gate electrode is to be formed on the HEMT substrate 15.
A recess groove 23 in which the upper n ⁺ -GaAs contact layer 14 is selectively removed is formed.

Next, as shown in FIG. 12, a Ti film, a Pt film, and an Au film are sequentially deposited on the entire surface of the substrate to form a film on the n-AlGaAs electron supply layer 13 in the opening 18b and around the opening 18b. Ti / P is formed on the polyparaxylylene film 16 and the image reversal resist 21 respectively.
A t / Au laminated film 24 is formed.

Next, as shown in FIG. 13, the unnecessary Ti / Pt / Au laminated film 24 thereon is removed together with the image reversal resist 21 using an organic solvent.
Thus, n ⁺ − on the n-AlGaAs electron supply layer 13
The Schottky connection to the n-AlGaAs electron supply layer 13 is formed in the recess groove 23 where the GaAs contact layer 14 is selectively removed, and the upper part thereof is expanded to the polyparaxylylene film 16 around the opening 18b. A Ti / Pt / Au gate electrode 24a having a mold structure is formed.

Finally, although not shown, the polyparaxylylene film 16 is selectively removed to obtain a T-type Ti / P
After exposing the surface of the n ⁺ -GaAs contact layer 14 sandwiching the t / Au gate electrode 24a, AuGe / Ni which is ohmic-connected on the n ⁺ -GaAs contact layer 14 is formed.
/ Au source electrode and AuGe / Ni / Au drain electrode are formed respectively.

In this way, a T-type Ti / Pt / Au gate electrode 24a for Schottky connection with the n-AlGaAs electron supply layer 13 is formed in the recess groove 23, and the T-type Ti electrode is formed. A HEMT having a recess gate structure using a polyparaxylylene film 16 having a relative dielectric constant of about 2.4 as an insulating film near the / Pt / Au gate electrode 24a is completed.

As described above, according to the present embodiment, the polyparaxylylene film 16 having a relative dielectric constant of about 2.4 is used as the insulating film near the Ti / Pt / Au gate electrode 24a in the HEMT having the recess gate structure. Accordingly, as in the case of the first embodiment, the parasitic capacitance is reduced, the high-frequency characteristics of the HEMT can be improved, and the Ti / Pt / Au gate electrode 24a has a large cross-sectional area. Since the gate structure is reduced by having the mold structure, the high frequency characteristics of the HEMT can be further improved.

In the first and second embodiments, the polyparaxylylene film 16 having a relative dielectric constant of about 2.4 is used as an insulating film near the Ti / Pt / Au gate electrodes 20a and 24a. However, the present invention is not limited to the polyparaxylylene film 16. Instead of the polyparaxylylene film 16, for example, a polyimide film having a relative dielectric constant of about 3.0 to 3.5, a relative dielectric constant of 2.0 An organic low dielectric constant film such as a benzocyclobutene film may be used. Furthermore,
Instead of these organic low dielectric constant films, an inorganic low dielectric constant film such as a SiOF film containing a fluorine atom or an SiOB film containing a boron atom may be used.

In the first and second embodiments, the case of the HEMT having the recess gate structure is described. However, the present invention is not limited to the recess gate structure. Further, the present invention is not limited to the HEMT, and can be widely applied to semiconductor devices including other types of field effect transistors such as MESFETs.

[0051]

As described in detail above, according to the semiconductor device of the present invention, the following effects can be obtained. That is, according to the semiconductor device of the first aspect,
Since the relative dielectric constant of the insulating film near the gate electrode formed on the semiconductor substrate is 1 to 3.5, the relative dielectric constant of the SiO-based insulating film used as the normal insulating film near the gate electrode is higher. Therefore, the parasitic capacitance is reduced, and the high-frequency characteristics of the semiconductor device can be improved.

According to the semiconductor device of the fifth aspect, since the gate electrode has a T-type structure, the gate resistance is reduced, so that the high frequency characteristics of the semiconductor device can be further improved.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a HEMT having a recess gate structure according to a first embodiment of the present invention.

FIG. 2 is a process sectional view (part 1) for describing the method of manufacturing the HEMT having the recess gate structure shown in FIG.

FIG. 3 is a process sectional view (part 2) for describing the method of manufacturing the HEMT having the recess gate structure shown in FIG.

FIG. 4 is a process sectional view (part 3) for describing the method of manufacturing the HEMT having the recess gate structure shown in FIG.

FIG. 5 is a process sectional view (part 4) for describing the method of manufacturing the HEMT having the recess gate structure shown in FIG.

FIG. 6 is a process sectional view (part 5) for describing the method of manufacturing the HEMT having the recess gate structure shown in FIG.

FIG. 7 is a process sectional view (part 6) for describing the method of manufacturing the HEMT having the recess gate structure shown in FIG.

FIG. 8 is a schematic sectional view showing a HEMT having a recess gate structure according to a second embodiment of the present invention.

FIG. 9 is a process sectional view (part 1) for describing the method of manufacturing the HEMT having the recess gate structure shown in FIG.

FIG. 10 is a process sectional view (part 2) for describing the method of manufacturing the HEMT having the recess gate structure shown in FIG.

FIG. 11 is a process sectional view (part 3) for describing the method of manufacturing the HEMT having the recess gate structure shown in FIG.

FIG. 12 is a process sectional view (part 4) for describing the method for manufacturing the HEMT having the recess gate structure shown in FIG.

FIG. 13 is a process sectional view (part 5) for describing the method of manufacturing the HEMT having the recess gate structure shown in FIG.

FIG. 14 is a process sectional view (part 1) for describing a method of manufacturing a conventional MESFET having a recess gate structure.

FIG. 15 is a process sectional view (part 2) for describing the method of manufacturing the conventional MESFET having the recess gate structure.

FIG. 16 is a process sectional view (part 3) for describing the conventional method of manufacturing the MESFET having the recess gate structure.

FIG. 17 is a process sectional view (part 4) for describing the conventional method of manufacturing the MESFET having the recess gate structure.

FIG. 18 is a process sectional view (part 5) for describing the method of manufacturing the conventional MESFET having the recess gate structure.

FIG. 19 is a process sectional view (part 6) for describing the method of manufacturing the conventional MESFET having the recess gate structure.

[Explanation of symbols]

Reference Signs List 11 semi-insulating GaAs substrate 12 high-purity GaAs channel layer 13 n-AlGaAs electron supply layer 14 n ⁺ -GaAs contact layer 15 HEMT substrate 16 polyparaxylylene film 17 electron resist 18 a opening 18 b opening 19 recess groove 20 Ti / Pt / Au laminated film 20a Ti / Pt / Au gate electrode 21 image reversal resist 22 opening 23 recess groove 24 Ti / Pt / Au laminated film 24a T-type Ti / Pt / Au gate electrode 31 semi-insulating GaAs substrate 32 GaAs buffer layer 33 an n-GaAs layer 33 b n-GaAs layer 34 an n-AlGaAs layer 34 b n-AlGaAs layer 35 n ⁺ -GaAs layer 36 SiON film 37 photoresist 38 first recess groove 39 SiO ₂ sidewall 40 second recess Groove 1 Ti / Pt / Au gate electrode 42a AuGe / Ni / Au gate electrode 42b AuGe / Ni / Au source electrode 42c AuGe / Ni / Au drain electrode

 ──────────────────────────────────────────────────続 き Continuing on the front page F term (reference)

Claims (5)

[Claims] 1. A semiconductor device comprising: a semiconductor substrate; an insulating film formed on the semiconductor substrate; and a gate electrode formed on the semiconductor substrate via an opening formed in the insulating film. The semiconductor device according to claim 1, wherein a relative dielectric constant of the insulating film is 1 to 3.5. 2. The semiconductor device according to claim 1, wherein said insulating film is an organic dielectric film containing carbon atoms. 3. The semiconductor device according to claim 1, wherein said insulating film is a dielectric film containing fluorine atoms. 4. The semiconductor device according to claim 1, wherein said insulating film is a dielectric film containing boron atoms. 5. The semiconductor device according to claim 1, wherein said gate electrode has a T-type structure.