JP2001186581A - Fault detector and fault detection method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the traffic of actual communication data such as user data, to easily extend communication channel and to specify fault location by restraining the number of fault detection slots required for detecting the fault as much as possible, even when the number of communication paths, such as a bus, is extended. SOLUTION: This fault detector has respective electronic circuit sections 111-114, which are interconnected by an in-group bus 116 which frame data having one fault detection slot for every frame are transmitted, and a control section 115 that controls the electronic circuit sections 111-114 via the bus 116. An insertion means 212 inserts prescribed data to the slot to attain a prescribed pattern in the case of connection of the fault detection slot, the frame data are received by a transmission reception means 201 via the in-group bus 116, looped back to the in-group bus 116, and when the pattern of the reception frame data by the transmission reception means 211 is not a specific pattern, the in-group bus 116 is discriminated as being anomalous.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system in which electronic circuits are connected by a communication path (transmission path) such as a bus, for example, a communication failure such as a disconnection in a base station apparatus in a mobile communication system. The present invention relates to a failure detection device and a failure detection method for detecting a failure.

[0002]

2. Description of the Related Art Conventionally, as this type of fault detecting apparatus and fault detecting method, there is one described in Japanese Patent Application Laid-Open No. Hei 6-197391.

FIG. 4 is a block diagram showing a configuration of a conventional fault detecting device.

[0004] The fault detecting device 400 shown in FIG. 4 includes a line control circuit 401, an address setting circuit 402, a communication path memory 403, a write counter 404, a data setting circuit 405, and a data selection circuit 406. And a circuit 407.

In such a configuration, the communication path memory 4
When performing line switching of input / output data by controlling writing / reading of data to / from the
However, according to the call setting information included in the input data (of the frame configuration), the unused time slot of the input data is referred to the data setting circuit 405 as a failure detection time slot (hereinafter referred to as a failure detection slot). ), And performs timing control for setting data of another used time slot in the failure detection slot.

The data setting circuit 405 transfers and writes input data including data set by the timing control to the communication path memory 403. The writing of this data is executed while being incremented by the write counter 404 in the storage area of the address set by the address setting circuit 402 controlled by the line control circuit 401.

Next, under the control of the line control circuit 401, the data selection circuit 406 selects and reads out the read data of the fault detection slot from the read data read from the communication path memory 403.

Next, a comparison circuit 407 compares the extracted data with known data, and
In step 1, a failure is detected by detecting that the comparison result is different.

[0009]

However, in the conventional apparatus, it is assumed that there is only one communication path. If the number of communication paths increases, the number of fault detections corresponding to the number of the communication paths increases. Therefore, there is a problem that as the number of slots for failure detection increases, the number of time slots into which actual communication data such as user data is inserted decreases, and communication traffic decreases.

As described above, since communication traffic is reduced, there is a problem that a communication path such as a bus expansion cannot be easily added.

Further, although the occurrence of a fault can be detected by the fault detection slot, there is a problem that the fault location cannot be specified.

The present invention has been made in view of the above point. Even when a communication path such as a bus is added, the number of fault detection slots required for fault detection is suppressed as much as possible. It is an object of the present invention to provide a fault detecting device and a fault detecting method which can improve the traffic of actual communication data, thereby easily add a communication path, and can further specify a fault location. .

[0013]

According to the present invention, there is provided a fault detecting apparatus comprising: a plurality of electronic circuits connected by a first transmission line through which frame data having a first fault detecting slot for each frame is transmitted at a constant period; A first electronic circuit group having a master control means for controlling a predetermined operation of the electronic circuit via the first transmission line, and a first failure detection slot provided in the master control means, First insertion means for inserting predetermined data into the first failure detection slot so as to form a first specific pattern; and the master control means, wherein the inserted frame data is transmitted via the first transmission path. Transmitting / receiving means for transmitting and receiving the data, and second transmitting / receiving means provided in the electronic circuit for looping back the frame data after insertion received via the first transmission path to the first transmission path. If the data pattern connecting the first failure detection slot in the frame data after the loop back received by the first transmission / reception means is not the first specific pattern, it is determined that the first transmission path is abnormal. And a first determination unit that performs the determination.

According to this configuration, even if a transmission line for connecting an electronic circuit is added, only one fault detection slot is required for one frame, so that the number of fault detection slots required for the fault detection is suppressed. Thereby, traffic of actual communication data such as user data can be improved, transmission lines can be easily added, and a failure of the transmission lines in the electronic circuit group can be specified. be able to.

The fault detecting device according to the present invention comprises a plurality of second inserting means for inserting predetermined data so as to form a second specific pattern when the second fault detecting slots set for each frame are connected. The data pattern provided in each of the electronic circuits, wherein the second failure detection slot in the inserted frame data received by the first transmission / reception means via the first transmission path is connected to the second specific pattern If not, the configuration is adopted in the above configuration including the second determination unit that determines that the electronic circuit using the frame of the corresponding cycle is abnormal.

According to this configuration, even when the failure of each electronic circuit is detected, one failure detection slot is provided in one frame.
The number of fault detection slots required for the fault detection can be reduced, thereby improving the traffic of actual communication data such as user data and easily adding a transmission path. Can be
Further, it is possible to identify a failure in each electronic circuit.

The fault detecting device according to the present invention comprises a plurality of electronic circuits connected by a second transmission line, and slave control means for controlling a predetermined operation of the electronic circuit via the second transmission line. The slave control means includes a second group of electronic circuits connected to the master control means by a third transmission line, and the first insertion pattern of the master control means causes the data having the first specific pattern to be a first failure detection slot. A third transmission / reception means for receiving the frame data inserted in the first transmission path through the third transmission path, and a data pattern in which the first failure detection slot in the received frame data is connected to the first specific pattern. Otherwise, a third determination means for determining that the third transmission path or the master control means is abnormal is provided.

According to this configuration, even when a failure is detected in the transmission path between the electronic circuit groups and the master control means of each electronic circuit group, only one failure detection slot is required for one frame. The number of fault detection slots required for detection can be reduced, whereby the traffic of actual communication data such as user data can be improved, and the number of transmission paths can be easily increased.
The transmission path between the electronic circuit groups and the failure detection of the master control unit of each electronic circuit group can be specified.

In the fault detecting device according to the present invention, when the third determining means determines that the first specific pattern is normal, the fault detecting device converts the frame data received via the third transmission line into the third specific pattern. Transmitting / receiving means transmits to the respective electronic circuits of the second electronic circuit group via the second transmission path, and the second transmitting / receiving means of these electronic circuits loops back to the second transmission path after receiving the frame data; If the data pattern connecting the first failure detection slots in the frame data after the loop back received by the third transmitting / receiving means is not the first specific pattern, the first determination of the second electronic circuit group is performed. The means adopts a configuration that determines that the second transmission path is abnormal.

According to this configuration, the failure detection of the transmission path in the electronic circuit group can be performed based on the frame data transmitted from another electronic circuit group via the transmission path.

In the above structure, when the third determining means determines that there is an abnormality, the failure detecting apparatus may include a data linking the first failure detecting slot in the frame data received via the third transmission line. Interpolating means for complementing the pattern so as to be a first specific pattern is provided, and the third frame data is transmitted to the respective electronic circuits of the second electronic circuit group via the second transmission path by the third transmitting / receiving means. Use a configuration to send.

According to this configuration, the failure detection of the transmission path in the electronic circuit group can be performed by the frame data transmitted from another electronic circuit group via the transmission path, and the frame data is erroneously detected. However, it is possible to perform the above-described failure detection by setting it in an appropriate state.

In the above configuration, the fault detecting device according to the present invention, when the frame data is transmitted only from the master control unit to the slave control unit via the third transmission path, is transmitted to the master control unit and the slave control unit. The control means is connected by a fourth transmission line, and the slave control means is provided with a first insertion means, and the data having a third specific pattern is inserted into the first failure detection slot by the first insertion means. A data pattern in which the third transmission / reception means has a function of transmitting the frame data to the fourth transmission path, and the first failure detection slot received by the first transmission / reception means via the fourth transmission path is connected. However, a configuration is adopted in which the master control unit includes a fourth determination unit that determines that the slave control unit is abnormal unless the third specific pattern is used.

According to this configuration, the failure detection of the slave control means of the electronic circuit group can be performed based on the frame data transmitted from another electronic circuit group via the transmission path.

The fault detecting device of the present invention has a configuration in which the specific pattern is an alternating pattern in the above configuration.

According to this configuration, it becomes easy to insert the pattern data into the first or second failure detection slot, and it is easy to determine the pattern match.

[0027] The base station apparatus of the present invention employs a configuration including a fault detection device having the same configuration as any of the above.

According to this configuration, in the base station apparatus,
The same operation and effect as any of the above can be obtained.

The mobile communication system of the present invention employs a configuration including the fault detection device having the above configuration.

According to this configuration, in the mobile communication system, the same operation and effect as any of the above can be obtained.

A fault detecting method according to the present invention comprises: a plurality of electronic circuits connected by a first transmission path through which frame data having a first failure detection slot for each frame is transmitted at a constant period; A first electronic circuit group having a master control means for controlling a predetermined operation of the electronic circuit via the first electronic circuit group.
After the predetermined data is inserted into the first failure detection slot by the master control means so that the specified pattern is obtained, the frame data after the insertion is received by the plurality of electronic circuits via the first transmission path. If the data pattern connecting the first failure detection slot in the frame data received by the master control means after the loopback is not the first specific pattern, the first transmission path is looped back to the first transmission path. The transmission path is determined to be abnormal.

According to this method, even if a transmission line for connecting an electronic circuit is added, only one fault detection slot is required for one frame, so that the number of fault detection slots required for the fault detection is suppressed. Thereby, traffic of actual communication data such as user data can be improved, transmission lines can be easily added, and a failure of the transmission lines in the electronic circuit group can be specified. be able to.

In the fault detecting method according to the present invention, in the above-described method, predetermined data is set in each of the electronic circuits so that a second specific pattern is formed when the second fault detecting slots set for each frame are connected. And the frame data after the insertion is received by the master control means via the first transmission path,
If the data pattern connecting the second failure detection slots in the received frame data is not the second specific pattern, the electronic circuit using the frame of the cycle is determined to be abnormal.

According to this method, even when a failure of each electronic circuit is detected, one frame has one failure detection slot.
The number of fault detection slots required for the fault detection can be reduced, thereby improving the traffic of actual communication data such as user data and easily adding a transmission path. Can be
Further, it is possible to identify a failure in each electronic circuit.

The fault detecting method according to the present invention, in the above method, comprises a plurality of electronic circuits connected by a second transmission line, and a slave control means for controlling a predetermined operation of the electronic circuit via the second transmission line. The slave control means includes a second electronic circuit group connected to the master control means via a third transmission line, and the master control means causes the data having the first specific pattern to be stored in the first failure detection slot. The inserted frame data is received by the slave control means via the third transmission path, and the data pattern in which the first failure detection slot in the received frame data is connected to the first specific pattern is If not, the third transmission path or the master control means is determined to be abnormal.

According to this method, even when a fault is detected in the transmission path between the electronic circuit groups and the master control means of each electronic circuit group, only one fault detection slot is required for one frame. The number of fault detection slots required for detection can be reduced, whereby the traffic of actual communication data such as user data can be improved, and the number of transmission paths can be easily increased.
The transmission path between the electronic circuit groups and the failure detection of the master control unit of each electronic circuit group can be specified.

In the fault detection method according to the present invention, in the above method, when it is determined that the third transmission path and the master control means are normal, the slave control means transmits the frame data received via the third transmission path. To the respective electronic circuits of the second group of electronic circuits via the second transmission line, and these electronic circuits loop back to the second transmission line after receiving the frame data. If the data pattern connecting the first failure detection slots in the frame data received by the control means is not the first specific pattern, it is determined that the second transmission path is abnormal.

According to this method, it is possible to detect a failure in a transmission path in an electronic circuit group by using frame data transmitted from another electronic circuit group via the transmission path.

In the fault detection method according to the present invention, in the above method, when the third transmission path or the master control means is determined to be abnormal, the slave control means transmits the frame data received via the third transmission path. Of the first failure detection slot in the first pattern is complemented to be the first specific pattern, and the complemented frame data is
The signal is transmitted to each electronic circuit of the second electronic circuit group via the transmission path.

According to this method, it is possible to detect a failure in a transmission line in an electronic circuit group by using frame data transmitted from another electronic circuit group via the transmission line, and the frame data is erroneously detected. However, it is possible to perform the above-described failure detection by setting it in an appropriate state.

The fault detecting method according to the present invention is characterized in that, in the above method, when the frame data is transmitted only from the master control means to the slave control means via the third transmission path, the master control means and the slave Control means are connected by a fourth transmission line, and predetermined data is inserted into the first failure detection slot by the slave control means so as to have a third specific pattern when the first failure detection slots are connected, The master control means receives the frame data after the insertion via the fourth transmission path, and the data pattern connecting the first failure detection slot in the received frame data is the third specific pattern. If not, the slave control means is determined to be abnormal.

According to this method, the failure detection of the electronic circuit group can be performed by the frame data transmitted from another electronic circuit group via the transmission line.

[0043]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(Embodiment) FIG. 1 is a block diagram showing the configuration of a fault detection system to which a fault detection device according to an embodiment of the present invention is applied.

The fault detection system shown in FIG. 1 is, for example, a base station device of a mobile communication system, and detects a fault such as disconnection of an internal circuit or a bus signal line. The three electronic circuit groups 101 to 103 are connected by buses (inter-group buses) 104 and 105.

The first electronic circuit group 101 includes first to first electronic circuits defined by a system formed on a card substrate or the like.
Fourth electronic circuit units 111 to 114 and these electronic circuit units 1
A master control unit 115 that controls 11 to 114 as defined by the system is connected to a bus (intra-group bus) 116.

Similarly, the second electronic circuit group 102 includes first to fourth electronic circuit sections 121 to 124 and these electronic circuit sections 12 to 124.
A master control unit 125 for controlling 1 to 124 is connected by a bus (intra-group bus) 126.

Similarly, the third electronic circuit group 103 includes first to fourth electronic circuit units 131 to 134 and these electronic circuit units 13 to 134.
A slave control unit 135 for controlling 1 to 134 is connected by a bus (intra-group bus) 136.

The master control units 115 and 125 and the slave control unit 135 serve as control units for the electronic circuit units 111 to 1.
14, 121 to 124 and 131 to 134 are common functions. However, as will be described later, in a failure detection function which is a feature of the present embodiment, the relationship between the master and the slave is determined. The slave control unit 135 and the master control unit 115
A control line 141 necessary for fault detection is connected, and a slave control unit 135 and a master control unit 125 are connected by the control line 142.

FIG. 2 shows the failure detection function, and its configuration will be described. That is, FIG. 2 is a block diagram showing a configuration of the fault detection device according to the embodiment of the present invention.

As shown in FIG. 2, each of the electronic circuit units 111 to
Each of 114, 121 to 124, 131 to 134 includes a transmission / reception unit 201 and a failure detection pattern insertion unit 202.

Master control units 115 and 125 include transmission / reception unit 211, failure detection pattern insertion unit 212, intra-group bus failure determination unit 213, and electronic circuit unit failure determination unit 2.
14 and a control unit failure determination means 215.

The slave control unit 135 includes a failure detection pattern insertion unit 232, a transmission / reception unit 231, an intra-group bus failure determination unit 233, and an electronic circuit unit failure determination unit 234.
, An inter-group bus failure determination unit 236 and an interpolation unit 237.

Fault detection that can be performed by such a configuration function includes detection of faults in the buses 116, 126, and 136 in each group (bus fault detection in the group) and detection of electronic circuits 111 to 11 in each group.
4, 121 to 124, 131 to 134 (electronic circuit unit failure detection), each group bus 104, 105 failure detection (inter-group bus failure detection), and master control unit 115, 1
25 or failure detection of the slave control unit 135 (control unit failure detection).

Here, the bus transmission data used for performing such various failure detections is shown in FIG. 3 and will be described.

The bus transmission data 301 shown in FIG.
During normal operation of the system 100,
4, 105 and the intra-group buses 116, 126, 136. In this example, one frame is 512 bytes.
A digital signal (user data) of "1" or "0" is inserted into each of the slots S00 to S511.

The slots S501 to S511 define a guard band for the next frame, slot S499 is defined as a first failure detection slot, and slot S500 is defined as a second failure detection slot.

The first failure detection slot S499 is used for intra-group bus failure detection, inter-group bus failure detection, and control unit failure detection, and the second failure detection slot S500 is used for electronic circuit unit failure detection. Is being used.

Next, the operation of the failure detection will be described.
However, the first electronic circuit group 101 and the second electronic circuit group 102
The first electronic circuit group 1
01 will be described as a representative.

First, the first and second electronic circuit groups 101,
The operation of the intra-group bus failure detection 102 will be described.

First, in the first electronic circuit group 101,
Failure detection pattern insertion means 2 of first master control unit 115
12, the bus transmission data 301 shown in FIG.
First failure detection slot S defined for each frame
499, data of “1” and “0” are alternately inserted for each frame as a failure detection pattern, and the inserted bus transmission data 301 is transmitted / received by the transmission / reception unit 211.
The signals are output to the electronic circuit units 111 to 114 via the intra-group bus 116.

The output bus transmission data 301 is
After being received by the transmission / reception means 201 of each of the electronic circuit units 111 to 114, a loopback is returned again from here to the intra-group bus 116, and the loopback bus transmission data 301 is transmitted to the master control unit 115. Transmission / reception means 2
11 is received.

The received bus transmission data 301 is
It is output to the intra-group bus failure determination means 213. Here, if the received failure detection pattern is an alternating pattern of "1" and "0", it is determined that the intra-group bus 116 is normal and the alternating pattern If not, it is determined to be abnormal.

Next, the first to third electronic circuit groups 101 to 10
The operation of electronic circuit unit failure detection 3 will be described.

First, in the first electronic circuit group 101, the failure detection pattern inserting means 202 of each of the electronic circuit units 111 to 114 inserts the second failure detection slot S 500 defined for each frame of the bus transmission data 301 into the second failure detection slot S 500. At the timing determined for each of the electronic circuit units 111 to 114,
Data “1” and “0” are inserted as a failure detection pattern.

As shown in FIG. 3B, the first electronic circuit unit 111 inserts “1” of the failure detection pattern data into the second failure detection slot S500 of the frame 0, as shown in FIG. The second electronic circuit unit 11
2 inserts “0” into frame 3, inserts “1” into frame 3 by third electronic circuit unit 113, and inserts “4” into frame 4
Then, “0” is inserted by the fourth electronic circuit unit 114.

Next, the frame 5 is set so that the fault detection pattern data for each of the electronic circuit units 111 to 114 is alternated.
Is inserted by the first electronic circuit unit 111,
"1" is inserted into the frame 6 by the second electronic circuit unit 112, "0" is inserted into the frame 7 by the third electronic circuit unit 113, and the fourth electronic circuit unit 1 is inserted into the frame 4.
14 inserts "1". Thereafter, "1" and "0" are similarly inserted into each frame so as to be alternated.

The inserted bus transmission data 301 is output by the transmission / reception means 202 to the master control unit 115 via the intra-group bus 116.

The output bus transmission data 301 is
After being received by the transmission / reception unit 211 of the master control unit 115, it is output to the electronic circuit unit failure determination unit 214, where the received failure detection pattern is
If an alternating pattern of “1” and “0” is obtained in the frame cycle of each 114, it is determined that the electronic circuit units 111 to 114 are normal. It is determined to be abnormal.

That is, an abnormal electronic circuit unit (for example, 111) can be detected from a corresponding frame that does not have an alternating pattern of “1” and “0”.

Similarly, in the third electronic circuit group 103, the electronic circuit unit failure detection is performed. In the third electronic circuit group 103, the electronic circuit unit failure determination means 234 of the slave control unit 135 detects the failure. Done.

Next, the failure detection of the inter-group buses 104 and 105, the failure detection of each of the master control units 115 and 116, and the third
The operation of the electronic circuit group 101 for detecting an intra-group bus failure will be described.

First, the failure detection pattern insertion means 212 of the first master control unit 115 of the first electronic circuit group 101 stores “1” in the first failure detection slot S499 defined for each frame of the bus transmission data 301. "And" 0 "are alternately inserted for each frame as a failure detection pattern, and the inserted bus transmission data 301 is transmitted / received by the transmission / reception means 211 to the third group via the inter-group bus 104.
It is output to the slave control unit 135 of the electronic circuit group 103.

The output bus transmission data 301 is
After being received by the transmission / reception unit 231 of the slave control unit 135, it is output to the inter-group bus failure determination unit 236, where
If the received failure detection pattern is an alternating pattern of “1” and “0”, it is determined that the first master control unit 115 or the inter-group bus 104 is normal, and if not, it is abnormal. Is determined.

If the determination is normal, the bus transmission data 301 into which the failure detection pattern has been inserted is output to each of the electronic circuit units 131 to 134 via the intra-group bus 136, and each of the electronic circuit units 131 to 134 is output. Is looped back to the intra-group bus 136 by the transmission / reception means 201 of the slave control unit 1.
35 of the transmission / reception means 231.

The received bus transmission data 301 is
It is output to the intra-group bus failure determination means 233, and the failure detection pattern in the bus transmission data 301 is "1".
If the pattern is an alternating pattern of “0” and “0”, it is determined that the intra-group bus 136 is normal, and if not, the pattern is determined to be abnormal.

On the other hand, if the judgment by the inter-group bus fault judging means 236 is abnormal, the interpolating means 237 outputs the bus transmission data 30 received via the inter-group bus 104.
One of the failure detection patterns is complemented by the alternating pattern, and the complemented bus transmission data 301 is output to the intra-group bus 136 via the transmission / reception means 231. Thereafter, the normal / abnormal state of the intra-group bus 136 is determined by the same processing as described above. Is determined.

By complementing and inserting the pattern as described above, the data transmission and reception in the third electronic circuit group 103 is synchronized with the transmission and reception timing of the first or second electronic circuit group 101 or 102, and the data is transmitted and received in the group. The failure of the bus 136 can be detected, and the failure of the intra-group bus 136 of the third electronic circuit group 103 can be detected without being affected by the failure of the inter-group buses 104 and 105.

Further, the failure detection of the second master control unit 116 and the inter-group bus 105 is performed in the same manner as described above.

Next, the operation of the slave control unit 135 for detecting a failure will be described.

First, the failure detection pattern insertion means 232 of the slave control unit 135 causes the bus transmission data 301
First failure detection slot S defined for each frame
499, data of “1” and “0” are alternately inserted for each frame as a failure detection pattern, and the inserted bus transmission data 301 is transmitted / received by the transmission / reception unit 231.
The signal is output to the master control unit 115 or 125 of the first or second electronic circuit group 101 or 102 via the control line 141 or 142.

The output bus transmission data 301 is
After being received by the transmission / reception unit 211 of the master control unit 115 or 125, it is output to the control unit failure determination unit 215, where the received failure detection patterns are “1” and “0”.
If the pattern is an alternating pattern, it is determined that the slave control unit 135 is normal. If the pattern is not an alternating pattern, the slave control unit 135 is determined to be abnormal.

In the above description, the failure detection pattern is an alternating pattern. However, another predetermined pattern (specific pattern) may be used.

As described above, according to the fault detecting device of the present embodiment, only two fault detecting slots need to be set in one frame, so that even if a communication path such as a bus is added, The number of fault detection slots required for fault detection can be reduced, whereby the traffic of actual communication data such as user data can be improved, and the number of communication paths can be easily increased (bus expansion). Can be.

Further, it is possible to individually detect faults in a bus in the electronic circuit group, a plurality of electronic circuits connected by the bus, a control unit of the electronic circuit, and a connection bus between the circuit groups. , It is possible to specify a failure point.

[0086]

As described above, according to the present invention,
Even if a communication path such as a bus is added, the traffic of actual communication data such as user data can be improved by minimizing the number of fault detection slots required for fault detection, thereby enabling the communication path to be improved. Can be easily added, and a failure point can be specified.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a fault detection system to which a fault detection device according to an embodiment of the present invention is applied;

FIG. 2 is a block diagram showing a configuration of a fault detection device according to the embodiment.

FIG. 3 is a frame configuration diagram of bus transmission data for performing various types of failure detection by the failure detection device according to the embodiment.

FIG. 4 is a block diagram showing a configuration of a conventional failure detection device.

[Explanation of symbols]

101-103 Electronic circuit group 104, 105 Inter-group bus 111-114, 121-124, 131-134 Electronic circuit 115, 125 Master control unit 116, 126, 136 In-group bus 135 Slave control unit 141, 142 Control line 201, 211, 231 transmission / reception means 202, 212, 232 failure detection pattern insertion means 213, 233 intra-group bus failure determination means 214, 234 electronic circuit section failure determination means 215 control section failure determination means 236 inter-group bus failure determination means 237 interpolation means

Claims (15)

[Claims] 1. A plurality of electronic circuits connected by a first transmission path through which frame data having a first failure detection slot for each frame is transmitted at a constant period, and said electronic circuit via said first transmission path A first electronic circuit group having a master control means for controlling the predetermined operation of the first and the first control means, the first electronic circuit group being provided in the master control means, so as to form a first specific pattern when the first failure detection slot is connected. First insertion means for inserting predetermined data into the failure detection slot; first transmission / reception means provided in the master control means for transmitting and receiving the frame data after the insertion via the first transmission path;
A second transmission / reception unit provided in the electronic circuit, for looping back the inserted frame data received via the first transmission line to the first transmission line, and the loop received by the first transmission / reception unit If the data pattern connecting the first failure detection slots in the frame data after the back is not the first specific pattern, the first transmission means determines that the first transmission path is abnormal. Characteristic failure detection device. 2. A plurality of electronic circuits each including a second insertion unit for inserting predetermined data so as to form a second specific pattern when connecting second failure detection slots set for each frame. And a data pattern in which the second failure detection slots in the inserted frame data received by the first transmission / reception means via the first transmission path are connected,
2. The failure detection device according to claim 1, further comprising a second determination unit configured to determine that an electronic circuit using the frame of the corresponding cycle is abnormal if the frame is not the second specific pattern. 3. A semiconductor device comprising: a plurality of electronic circuits connected by a second transmission path; and slave control means for controlling a predetermined operation of the electronic circuit via the second transmission path. Means comprising a second group of electronic circuits connected by a third transmission path, wherein frame data in which data of a first specific pattern is inserted into a first failure detection slot by first insertion means of the master control means. A third transmission / reception means for receiving the first failure detection slot via the third transmission path, and a data pattern connecting the first failure detection slot in the received frame data is not the first specific pattern. 3. The fault detecting device according to claim 1, further comprising: a third determining unit that determines that the transmission path or the master control unit is abnormal. 4. When the third determination means determines that the first specific pattern is normal, the third transmission / reception means transmits the frame data received via the third transmission path via the second transmission path. After transmitting the frame data, the second transmission / reception means of the second electronic circuit group loops back to the second transmission path after receiving the frame data, and the second transmission / reception means receives the frame data. If the data pattern connecting the first failure detection slots in the frame data after loopback is not the first specific pattern, the second
4. The failure detection device according to claim 3, wherein the first determination unit of the electronic circuit group determines that the second transmission path is abnormal. 5. A data pattern obtained by connecting a first failure detection slot in frame data received via a third transmission line when the third determination unit determines that the data is abnormal, as a first specific pattern. 5. An interpolation means for complementing the data, and the third transmitting / receiving means transmits the frame data after the complementation to each electronic circuit of the second electronic circuit group via the second transmission path. The fault detection device according to the above. 6. When the frame data is transmitted only from the master control unit to the slave control unit via the third transmission line, the master control unit and the slave control unit are connected by a fourth transmission line. In addition, the slave control means includes a first insertion means, and the third transmission / reception means transmits the frame data in which the data having the third specific pattern is inserted into the first failure detection slot by the first insertion means. A data pattern having a function of transmitting to the fourth transmission path and connecting the first failure detection slot received by the first transmission / reception means via the fourth transmission path;
6. The fault detecting device according to claim 3, wherein the master control means includes a fourth determination means for determining that the slave control means is abnormal unless the specific pattern is a specific pattern. 7. The fault detecting device according to claim 1, wherein the specific pattern is an alternating pattern. 8. A base station device comprising the fault detection device according to claim 1. 9. A mobile communication system comprising the base station apparatus according to claim 8. 10. A plurality of electronic circuits connected by a first transmission line through which frame data having a first failure detection slot for each frame is transmitted at a constant period, and said electronic circuit via said first transmission line. In the first electronic circuit group having master control means for controlling the predetermined operation, the predetermined data is stored in the first failure detection slot so as to form a first specific pattern when the first failure detection slot is connected. The frame data is inserted by the master control means, and the frame data after the insertion is received by the plurality of electronic circuits via the first transmission path, and then looped back to the first transmission path. If the data pattern connecting the first failure detection slots in the frame data received in step 1 is not the first specific pattern, it is determined that the first transmission path is abnormal. A failure detection method. 11. When each of the second failure detection slots set for each frame is connected, predetermined data is inserted in each of the electronic circuits so as to have a second specific pattern, and the frame data after the insertion is inserted. If the data pattern received by the master control means via the first transmission path and the second failure detection slot in the received frame data is not the second specific pattern, the frame of this cycle is The failure detection method according to claim 10, wherein the electronic circuit that uses is determined to be abnormal. 12. A plurality of electronic circuits connected by a second transmission path, and slave control means for controlling a predetermined operation of the electronic circuit via the second transmission path, wherein the slave control means controls the master circuit. Second means connected to the means by a third transmission line
An electronic circuit group, wherein the master control means receives frame data in which data serving as a first specific pattern has been inserted into a first failure detection slot by the slave control means via the third transmission line; If the data pattern connecting the first failure detection slots in the received frame data is not the first specific pattern, the third transmission path or the master control means determines that the data is abnormal. The fault detection method according to claim 10 or 11, wherein the fault is detected. 13. When the third transmission path and the master control means are determined to be normal, the slave control means transmits the frame data received via the third transmission path to the second transmission path via the second transmission path. 2 to each of the electronic circuits in the electronic circuit group, and after these electronic circuits receive the frame data,
Loop back to the transmission line, and after the loop back, the first in the frame data received by the slave control means.
The data pattern connecting the failure detection slots is the first data pattern.
13. The failure detection method according to claim 12, wherein the second transmission path is determined to be abnormal unless the specific pattern is a specific pattern. 14. When the third transmission path or the master control means is determined to be abnormal, the slave control means connects the first failure detection slot in the frame data received via the third transmission path. The data pattern is complemented so as to be a first specific pattern, and the complemented frame data is transmitted to each electronic circuit of a second electronic circuit group via the second transmission path. 14. The failure detection method according to item 13. 15. When the frame data is transmitted only from the master control means to the slave control means via the third transmission path, the master control means and the slave control means are connected by a fourth transmission path. The slave control means inserts predetermined data into the first failure detection slot so as to have a third specific pattern when the first failure detection slot is connected, and inserts the frame data after the insertion into the fourth failure detection slot. The master control means receives the data via the transmission line, and if the data pattern connecting the first failure detection slot in the received frame data is not the third specific pattern, it is determined that the slave control means is abnormal. 15. The failure detection method according to claim 10, wherein the determination is performed.