JP2001174786A - Driving method for semiconductor display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a driving method for a semiconductor display device capable of displaying a sharp and high definition image without flickers, vertical and lateral stripes visually recognized by a user. SOLUTION: This is a driving method for semiconductor display device characterized in that video signals inputted to each pixel electrode of plural pixels are reversed in polarity with respect to the potential of the counter electrodes for every frame period, and the frame periods differ in length frame period by frame period.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a driving method suitable for a semiconductor display device using a display medium such as a liquid crystal.
In particular, the present invention relates to a driving method of an active matrix liquid crystal display device.

[0002]

2. Description of the Related Art In recent years, an element formed by using a semiconductor thin film on an insulating substrate, for example, a thin film transistor (TFT)
The technology for making is rapidly developing. The reason is that demand for semiconductor display devices (typically, active matrix liquid crystal display devices) has been increasing.

An active matrix type liquid crystal display device is
An image is displayed by controlling charges applied to several tens to several millions of pixels arranged in a matrix by a switching element (pixel TFT) of a pixel constituted by a TFT.

[0004] In this specification, a pixel means a switching element (pixel TFT), a pixel electrode connected to the switching element, a counter electrode, and a liquid crystal provided between the pixel electrode and the counter electrode. It is mainly composed of

A typical example of a display operation of a liquid crystal panel included in an active matrix type liquid crystal display device will be briefly described below with reference to FIG. FIG. 15A is a top view of an active matrix liquid crystal display device.
(B) is a diagram showing an arrangement of pixels.

[0006] The source signal line drive circuit 203 and the source signal lines S1 to S6 are connected. Further, the gate signal line driving circuit 204 and the gate signal lines G1 to G5 are connected. Then, the source signal lines S1 to S6 and the gate signal line G
A plurality of pixels 206 are provided in a portion surrounded by 1 to G5. The pixel 206 is provided with a pixel TFT 201 and a pixel electrode 202. Note that the number of source signal lines and gate signal lines is not limited to this value.

A video signal is input to the source signal line S1 according to a signal from a shift register circuit (not shown) in the source signal line drive circuit 203. Further, a selection signal is input to the gate signal line G1 from the gate signal line driving circuit 204, and the pixel TFT of the pixel (1, 1) at the intersection of the gate signal line G1 and the source signal line S1 is turned on. I do. Then, the video signal input to the source signal line S1 is input to the pixel electrode of the pixel (1, 1). The liquid crystal is driven by the potential of the input video signal, the amount of transmitted light is controlled, and a part of the image (pixels (1,
1) is displayed.

Next, while the state in which an image is displayed on the pixel (1, 1) is held by a storage capacitor (not shown) or the like, at the next moment, the shift register circuit 203 in the source signal line driving circuit 203 (Not shown), a video signal is input to the source signal line S2. The storage capacity is
This is a capacitor for holding the potential of the video signal input to the gate electrode of the pixel TFT for a certain period.

The selection signal from the gate signal line driving circuit 204 remains input to the gate signal line G1, and the selection signal of the pixel (1, 2) at the portion where the gate signal line G1 and the source signal line S2 intersect. The pixel TFT is turned on. Then, the potential of the video signal of the source signal line S2 changes to the pixel (1,
Input to the pixel electrode of 2). The liquid crystal is driven by the potential of the input video signal, and the amount of transmitted light is controlled so that the pixel (1, 2) has a part of the image (pixel (1, 2)) like the pixel (1, 1). Corresponding image) is displayed.

Such display operations are sequentially performed, and the pixels (1, 1) (1, 2) connected to the gate signal line G1 are displayed.
(1, 3) (1, 4) (1, 5) (1, 6) Part of the image is displayed one after another. During this time, the selection signal continues to be input to the gate signal line G1.

When the video signal is input to all the pixels connected to the gate signal line G1, the selection signal is not input to the gate signal line G1, and subsequently, the selection signal is input only to the gate signal line G2. Is done. Then, the pixels (2, 1) (2, 2) connected to the gate signal line G2
(2, 3) (2, 4) (2, 5) (2, 6) Display a part of the image one after another. During this time, the selection signal is continuously input to the gate signal line G2.

One image is displayed on the pixel portion 205 by sequentially repeating the above-described operation on all the gate signal lines. The period during which this one image is displayed is called one frame period. Note that a period in which one image is displayed in the pixel portion 205 and a vertical blanking period may be combined to form a frame period. Then, all the pixels hold the state in which the image is displayed by a storage capacitor (not shown) or the like until the pixel TFT of each pixel is turned on again.

[0013]

Generally, in a liquid crystal panel using a TFT or the like as a switching element, in order to prevent deterioration of the liquid crystal, the polarity of the potential of a signal input to each pixel is set to the potential of a common electrode (common potential). Invert (AC drive) as a reference. As a method of AC drive, frame inversion drive, source line inversion drive, gate line inversion drive,
Dot inversion driving is exemplified. Hereinafter, each driving method will be described.

FIG. 16A shows a polarity pattern of each pixel in the frame inversion driving. In the drawings showing the polarity patterns in this specification (FIGS. 16, 3, and 5), when the potential of the video signal input to the pixel is positive with respect to the common potential, “+” is used. Shown, if negative, "-"
Indicated by. The polarity pattern shown in FIG. 16 corresponds to the pixel arrangement shown in FIG.

In this specification, a video signal having a positive polarity means a video signal having a potential higher than a common potential. The video signal having a negative polarity means a video signal having a potential lower than the common potential.

In addition, in the scanning method, an odd-numbered gate signal line and an even-numbered gate signal line are scanned twice (two fields) in one screen (one frame); There is a non-interlace scan in which the first and even-numbered gate signal lines are sequentially scanned without any separation. Here, an example using non-interless scan will be mainly described.

The feature of the frame inversion drive is that a video signal of the same polarity is input to all pixels within an arbitrary one frame period (polarity pattern), and is input to all pixels in the next one frame period. (Polarity pattern) for inverting the polarity of the video signal to be displayed. That is, when focusing only on the polarity pattern, this is a driving method in which two types of polarity patterns (a polarity pattern and a polarity pattern) are repeatedly displayed every frame period.

Next, source line inversion driving will be described. FIG. 16B shows a polarity pattern of a pixel in source line inversion driving.

As shown in FIG. 16 (B), the feature of the source line inversion drive is that in any one frame period,
The video signal of the same polarity is input to all the pixels connected to the same source signal line, and the video signal of the opposite polarity is input between the pixels connected to the adjacent source signal line. is there.

In the next one frame period, a video signal having a polarity opposite to that of the video signal input in the immediately preceding one frame period is input to each source signal line. Therefore, if the polarity pattern in any one frame period is a polarity pattern, the polarity pattern in the next one frame period is a polarity pattern.

Next, the gate line inversion driving will be described. FIG. 16C shows a polarity pattern in the gate line inversion driving.

As shown in FIG. 16C, in one arbitrary frame period, video signals having the same polarity are input to all the pixels connected to the same gate signal line.
This means that video signals of opposite polarities are input between pixels connected to adjacent gate signal lines.

In the next one frame period, a video signal having a polarity opposite to that of the video signal input in the immediately preceding one frame period is input to the pixel connected to each gate signal line. Therefore, if the polarity pattern in any one frame period is a polarity pattern,
The polarity pattern in the next one frame period is a polarity pattern.

That is, similar to the above-described source line inversion driving, this is a driving method in which two types of polarity patterns (a polarity pattern and a polarity pattern) are repeatedly displayed every frame period.

Next, the dot inversion driving will be described. Although the polarity pattern is not shown in the dot inversion drive,
This is a method in which the polarity of a video signal input to a pixel is inverted between all adjacent pixels. Then, in any one frame period, a video signal having a polarity opposite to that of the video signal input in the immediately preceding one frame period is input to each pixel. That is, this is a driving method in which two types of polarity patterns are repeatedly displayed every frame period.

The AC driving described above is a useful method for preventing the deterioration of the liquid crystal. However, when the above-described AC drive is used, the screen may flicker or vertical or horizontal stripes may be visually recognized.

This is because even if the same gradation display is to be performed in each pixel, the brightness of the screen is slightly different between the display when the polarity of the input video signal is positive and the display when the polarity is negative. It is thought to be a reason. Hereinafter, the frame inversion drive will be described in detail as an example.

FIG. 17 shows a timing chart when the active matrix type liquid crystal display device shown in FIG. 15 is driven by frame inversion. FIG. 17 is a timing chart in the case where the active matrix type liquid crystal display device displays white when normally black and black when normally white. A period during which the selection signal is input to one gate signal line is defined as one line period, and a period from when the selection signal is input to all gate signal lines until one image is displayed is defined as one frame period.

When a video signal and a selection signal are input to the source signal line S1 and the gate signal line G1, respectively, a pixel (1,...) Provided at the intersection of the source signal line S1 and the gate signal line G1 1), a video signal having a positive polarity is input. Then, in the pixel (1, 1), the potential given to the pixel electrode by the input video signal is ideally kept held for one frame period by a storage capacitor or the like.

However, in practice, when the potential of the gate signal line G1 shifts to a potential for turning off the pixel TFT at the end of one line period, the potential of the pixel electrode also changes to the gate signal line G.
There is a case where the potential of 1 is pulled by ΔV in the direction of shifting. This phenomenon is called field through, and ΔV
Is called a penetration voltage.

ΔV is given by the following equation.

[0032]

[Formula 1] ΔV = V × Cgd / (Cgd + Clc + Cs)

V is the amplitude of the potential of the gate electrode; Cgd is the capacitance between the gate electrode and the drain region of the pixel TFT;
c is the capacity of the liquid crystal between the pixel electrode and the counter electrode, and Cs is the storage capacity.

In the timing chart shown in FIG. 17, the actual potential of the pixel electrode in the pixel (1, 1) is shown by a solid line, and the ideal potential of the pixel electrode without considering the field-through is shown by a dotted line. In the first frame period, a video signal having a positive polarity is input to the pixel (1, 1). FIG.
In the case of the first frame period shown in (1), the potential of the gate signal line changes in the negative direction at the same time when one line period ends,
In addition, the potential of the pixel electrode of the pixel (1, 1) actually changes in the negative direction by the penetration voltage. In FIG. 17, the piercing voltage in the first frame period is indicated as ΔV1.

Next, in the second frame period, a negative polarity video signal having a polarity opposite to that of the first frame period is input to the pixel (1, 1). When the first line period in the second frame period ends, the gate signal line G1
Changes in the negative direction. And at the same time the pixel (1,
Actually, the potential of the pixel electrode 1) also changes in the negative direction by the penetration voltage. In FIG. 17, the penetration voltage in the second frame period is indicated as ΔV2.

In FIG. 17, the first frame period is the first frame period.
The drive voltage after the end of the line period is V1, and the drive voltage after the end of the first line period in the second frame period is V2.
As shown. Note that in this specification, a driving voltage refers to a potential difference between a potential of a pixel electrode and a common potential.

The drive voltage V1 and the drive voltage V2 are ΔV1 +
It will have a voltage difference of ΔV2. Therefore, the brightness of the screen at the pixel (1, 1) is different between the first frame period and the second frame period.

Therefore, a method of lowering the value of the common potential so that the values of the driving voltage V1 and the driving voltage V2 become the same can be considered.

However, the capacitance Cgd between the gate electrode and the drain region of the pixel TFT differs between when a video signal having a positive polarity is input to the pixel and when a video signal having a negative polarity is input to the pixel. , Their values are different. Further, the capacitance Clc of the liquid crystal between the pixel electrode and the counter electrode also varies depending on the potential of the video signal input to the pixel. for that reason,
Since the values of Cgd and Clc are different for each frame period, the values of the penetration voltage ΔV are also different for each frame period. Therefore, even if the value of the common potential is changed, there is a frame period in which the potential difference between the positive potential video signal and the negative polarity video signal input to each pixel is different from the common potential. .

This is a phenomenon that can occur not only in the pixel (1, 1) but also in all the pixels. The brightness of the pixel may vary depending on the polarity of the video signal input to the pixel.

Therefore, in the frame inversion drive, the brightness of the image displayed in the first frame period and the brightness of the image displayed in the second frame period are different, and the image is visually recognized as a flicker by an observer. In particular, remarkable flicker was confirmed in the halftone display.

Similarly, in the case of the source line inversion drive, the gate line inversion drive, and the dot inversion drive, the pixel to which the positive polarity video signal is input and the pixel to which the negative polarity video signal is input are displayed. Brightness is different. for that reason,
Vertical stripes were displayed on the screen by the source line inversion drive, and horizontal stripes were displayed by the gate line inversion drive. In the dot inversion driving, vertical stripes or horizontal stripes appeared depending on the image displayed on the screen.

It is considered effective to increase the frame frequency in order to prevent the screen from flickering and the vertical or horizontal stripes from being seen by the observer due to the AC drive. However, in order to increase the frame frequency, it is necessary to increase the driving frequency of the driving circuit, particularly the driving frequency of the source signal line driving circuit. When the driving frequency of the source signal line driving circuit is increased, the operation speed of the TFT included in the source signal line driving circuit cannot correspond to the driving frequency of the source signal line driving circuit.
Or there could be difficulties in reliability.

Therefore, the present invention has been made in view of the above,
An object of the present invention is to provide a driving method of a semiconductor display device capable of displaying a clear and high-definition image without a viewer seeing flickers, vertical stripes, and horizontal stripes.

[0045]

According to the present invention, when a semiconductor display device is driven, its frame period is randomly changed every frame period. In other words, the driving is performed such that the length of an arbitrary one frame period and the length of the one frame period immediately after the arbitrary one frame period are always different at random. The difference between the lengths of adjacent frame periods needs to be long and random so that flickers, vertical stripes, and horizontal stripes are not visually recognized by an observer.
In addition, when a moving image is displayed, it is necessary to shorten the frame period so that smooth display of the moving image is not hindered by a difference in length between adjacent frame periods.

By using the above configuration, it is possible to prevent flicker, vertical stripes, and horizontal stripes on the screen, which are visually recognized by the observer, while suppressing the frequency of the drive circuit when performing the AC drive. . Further, the deterioration of the liquid crystal can be suppressed by the AC driving.

The configuration of the present invention will be described below.

According to the present invention, there is provided a semiconductor display device having a plurality of pixels including a plurality of pixel TFTs and a plurality of pixel electrodes, a counter electrode, and a liquid crystal provided between the plurality of pixel electrodes and the counter electrode. In the driving method, a video signal is input to the plurality of pixel electrodes via the plurality of pixel TFTs, and the video signal input to the plurality of pixel electrodes is a potential of the counter electrode every one frame period. The driving method of the semiconductor display device is characterized in that the polarity is inverted on the basis of, and the length of the frame period differs for each frame period.

According to the present invention, a plurality of pixels including a plurality of pixel TFTs and a plurality of pixel electrodes, a plurality of source signal lines, a plurality of gate signal lines, a counter electrode, the plurality of pixel electrodes and the counter electrode are provided. In the method for driving a semiconductor display device having a liquid crystal provided between the plurality of pixel signal TFTs, switching of the plurality of pixel TFTs is controlled by a selection signal input to the plurality of gate signal lines, and the plurality of source signal lines are connected to the plurality of source signal lines. The input video signal is output from the plurality of pixel TFTs.
And the video signal input to the plurality of pixel electrodes via the pixel electrode is inverted in polarity with respect to the potential of the counter electrode every frame period, and And a method for driving a semiconductor display device characterized in that the length of the frame period is different.

According to the present invention, a plurality of pixels including a plurality of pixel TFTs and a plurality of pixel electrodes, a plurality of source signal lines, a plurality of gate signal lines, a counter electrode, the plurality of pixel electrodes and the counter electrode are provided. In the method for driving a semiconductor display device having a liquid crystal provided between the plurality of pixel signal TFTs, switching of the plurality of pixel TFTs is controlled by a selection signal input to the plurality of gate signal lines, and the plurality of source signal lines are connected to the plurality of source signal lines. The input video signal is output from the plurality of pixel TFTs.
Is input to the plurality of pixel electrodes via the pixel signal, the polarity of the video signal input to each of the plurality of source signal lines,
During one frame period, the polarity of a video signal input to an adjacent source signal line among the plurality of source signal lines is always the same with reference to the potential of the counter electrode. And the video signals input to the plurality of source signal lines have their polarities inverted every frame period with respect to the potential of the counter electrode. And a method for driving a semiconductor display device characterized in that the length of the frame period is different.

According to the present invention, a plurality of pixels including a plurality of pixel TFTs and a plurality of pixel electrodes, a plurality of source signal lines, a plurality of gate signal lines, a counter electrode, the plurality of pixel electrodes and the counter electrode are provided. In the method for driving a semiconductor display device having a liquid crystal provided between the plurality of pixel signal TFTs, switching of the plurality of pixel TFTs is controlled by a selection signal input to the plurality of gate signal lines, and the plurality of source signal lines are connected to the plurality of source signal lines. The input video signal is output from the plurality of pixel TFTs.
The polarities of all video signals input to the plurality of pixel electrodes via the plurality of source signal lines have the same polarity with respect to the potential of the counter electrode during one line period. In an adjacent line period, the polarities of the video signals input to the plurality of source signal lines are inverted with respect to the potential of the counter electrode, and the video signals input to the plurality of source signal lines are inverted. The polarity of the signal is inverted every frame period with reference to the potential of the counter electrode, and the length of the frame period is different every frame period. Provided.

According to the present invention, a plurality of pixels including a plurality of pixel TFTs and a plurality of pixel electrodes, a plurality of source signal lines, a plurality of gate signal lines, a counter electrode, the plurality of pixel electrodes and the counter electrode are provided. In the method for driving a semiconductor display device having a liquid crystal provided between the plurality of pixel signal TFTs, switching of the plurality of pixel TFTs is controlled by a selection signal input to the plurality of gate signal lines, and the plurality of source signal lines are connected to the plurality of source signal lines. The input video signal is output from the plurality of pixel TFTs.
Are input to the plurality of pixel electrodes through one frame period, all video signals input to the plurality of pixel electrodes during one frame period always have the same polarity with reference to the potential of the counter electrode, The video signals input to the plurality of pixel electrodes are such that the polarity is inverted for each frame period with reference to the potential of the counter electrode, and the length of the frame period differs for each frame period. A method for driving a semiconductor display device is provided.

The length of the frame period may be randomly different for each frame period.

[0054]

BEST MODE FOR CARRYING OUT THE INVENTION

The driving method according to the present invention will be described below.

FIG. 1 shows a configuration of an active matrix type liquid crystal display device using the driving method of the present invention. FIG. 1A is a top view of an active matrix liquid crystal display device, and FIG. 1B is a diagram illustrating an arrangement of pixels.

Reference numeral 101 denotes a source signal line driving circuit, 102 denotes a gate signal line driving circuit, and 103 denotes a pixel portion.
Source signal lines S1 to Sx connected to the source signal line driving circuit 101 and gate signal lines G1 to Gy connected to the gate signal line driving circuit 102 are provided on the pixel portion 103. In the pixel portion 103, the pixel 104 is provided in a portion surrounded by the source signal lines S1 to Sx and the gate signal lines G1 to Gy. And the pixel 104
Is provided with a pixel TFT 105 and a pixel electrode 106.

FIG. 2 shows a timing chart when the active matrix type liquid crystal display device shown in FIG. 1 is driven by frame inversion. FIG. 2 shows white display when the active matrix type liquid crystal display device is normally black,
6 is a timing chart in a case where normally white is displayed in black.

In the first frame period, first, a selection signal is input from the gate signal line driving circuit 102 to the gate signal line G1. As a result, all pixels (1, 1), (1, 2)... (1,
In x), the pixel TFT is turned on.

Then, a video signal is input to the source signal line S1 according to a signal from a shift register circuit or the like (not shown) in the source signal line driving circuit 101. In the first frame period, the video signal has a positive polarity with reference to the common potential. Then, the video signal input to the source signal line S1 is input to the pixel electrode of the pixel (1, 1). The liquid crystal is driven by the potential of the input video signal, the amount of transmitted light is controlled, and the pixels (1,
In 1), a part of the image (the image corresponding to the pixels (1, 1)) is displayed.

At the next moment, the state in which an image is displayed on the pixel (1, 1) is held by a holding capacitor (not shown) or the like. (Not shown), a video signal having a positive polarity is input to the source signal line S2.

The selection signal from the gate signal line drive circuit 102 remains input to the gate signal line G1, and the pixel (1, 2) at the intersection of the gate signal line G1 and the source signal line S2 Are in an ON state. Therefore, the potential of the video signal input to the source signal line S2 is input to the pixel electrodes of the pixels (1, 2). The liquid crystal is driven by the potential of the input video signal, and the amount of transmitted light is controlled, and the pixel (1, 2) corresponds to a part of the image (corresponding to the pixel (1, 2)) like the pixel (1, 1). Image) is displayed.

Such a display operation is sequentially performed, and all the pixels (1, 1) connected to the gate signal line G1,
(1, 2)... (1, x) are input with a video signal having a positive polarity, and display a part of an image one after another. During this time, the selection signal continues to be input to the gate signal line G1.

When a positive polarity video signal is input to all the pixels connected to the gate signal line G1, no selection signal is input to the gate signal line G1, and the first line period ends. . Subsequently, the second line period starts, and the selection signal is input only to the gate signal line G2. Then, video signals having a positive polarity are sequentially input to all the pixels (2, 1) (2, 2)... (2, x) connected to the gate signal line G2, and a part of the image is respectively input. Display one after another. During this time, the selection signal is continuously input to the gate signal line G2.

By repeating the above-described operation sequentially on all the gate signal lines, video signals having a positive polarity are sequentially input to all the pixels, and one image is displayed on the pixel portion 103. The period during which this one image is displayed is the first frame period. Note that the period during which one image is displayed on the pixel portion 103 and the vertical retrace period are combined.
One frame period may be used. Then, all the pixels are turned on until the pixel TFT of each pixel is turned on again.
The state in which the image is displayed is stored in a storage capacitor (not shown) or the like.

Next, a second frame period is started, and first, a selection signal is input from the gate signal line driving circuit 102 to the gate signal line G1. As a result, all the pixels (1, 1), (1, 2),... Connected to the gate signal line G1.
At (1, x), the pixel TFT is turned on.

Then, a video signal is input to the source signal line S1 according to a signal from a shift register circuit or the like (not shown) in the source signal line driving circuit 101. In the second frame period, the video signal has a negative polarity with respect to the common potential. Then, the video signal input to the source signal line S1 is input to the pixel electrode of the pixel (1, 1). The liquid crystal is driven by the potential of the input video signal, the amount of transmitted light is controlled, and a part of an image (an image corresponding to the pixel (1, 1)) is displayed on the pixel (1, 1).

At the next moment, the state in which an image is displayed on the pixel (1, 1) is held by a storage capacitor (not shown) or the like. (Not shown), a video signal having a negative polarity is input to the source signal line S2.

The selection signal from the gate signal line driving circuit 102 remains input to the gate signal line G1, and the pixel (1, 2) at the intersection of the gate signal line G1 and the source signal line S2 Are in an ON state. Therefore, the potential of the video signal input to the source signal line S2 is input to the pixel electrodes of the pixels (1, 2). The liquid crystal is driven by the potential of the input video signal, and the amount of transmitted light is controlled, and the pixel (1, 2) corresponds to a part of the image (corresponding to the pixel (1, 2)) like the pixel (1, 1). Image) is displayed.

Such a display operation is performed sequentially, so that all the pixels (1, 1) connected to the gate signal line G1,
(1, 2)... A video signal having a negative polarity is input to (1, x), and a part of the image is displayed one after another. During this time, the selection signal continues to be input to the gate signal line G1.

When a negative polarity video signal is input to all the pixels connected to the gate signal line G1, no selection signal is input to the gate signal line G1, and the first line period ends. . Subsequently, the second line period starts, and the selection signal is input only to the gate signal line G2. Then, video signals having a negative polarity are sequentially input to all the pixels (2, 1) (2, 2)... (2, x) connected to the gate signal line G2, and a part of the image is respectively input. Display one after another. During this time, the selection signal is continuously input to the gate signal line G2.

By repeating the above-described operation sequentially on all the gate signal lines, video signals having a negative polarity are sequentially input to all the pixels, and one image is displayed on the pixel portion 103. The period during which this one image is displayed is the second frame period. Note that the period during which one image is displayed on the pixel portion 103 and the vertical retrace period are combined.
One frame period may be used. Then, all the pixels are turned on until the pixel TFT of each pixel is turned on again.
The state in which the image is displayed is stored in a storage capacitor (not shown) or the like.

Similarly, the above operation is performed in the third frame period and the fourth frame period. Note that the polarity of the video signal input to each pixel is positive in the third frame period, and the polarity of the video signal input to each pixel is negative in the fourth frame period.

FIG. 3 shows a polarity pattern of each pixel in the frame inversion driving. Note that the polarity pattern shown in FIG. 3 corresponds to the pixel arrangement shown in FIG.

In addition, in the scanning method, in one screen (one frame), an odd-numbered gate signal line and an even-numbered gate signal line are scanned twice (two fields), and an odd-numbered gate signal line and an odd-numbered gate signal line are scanned. There is a non-interlace scan in which the first and even-numbered gate signal lines are sequentially scanned without any separation. Here, an example using non-interless scan will be mainly described.

In the first and third frame periods, a video signal having a positive polarity is input to all the pixels, and the polarity pattern of the pixel is represented by a polarity pattern A. In the second and third frame periods, negative polarity video signals are input to all the pixels, and the polarity pattern of the pixels is represented by the polarity pattern B. That is, focusing only on the polarity pattern, two types of polarity patterns (polarity pattern A and polarity pattern B) are repeatedly displayed for each frame period.

In the present embodiment, the polarity pattern of the pixels in the first and third frame periods is the polarity pattern A, and the polarity pattern of the pixels in the second and third frame periods is the polarity pattern B. The present invention is not limited to this configuration. Conversely, the polarity pattern of the pixel in the second and third frame periods is a polarity pattern A,
The polarity pattern of the pixels in the first and third frame periods may be the polarity pattern B.

In the present invention, the lengths of the frame periods are not all the same, and the lengths of the frame periods are made to be different at random. In other words, the frame period is randomly changed every frame period. That is, driving is performed such that the length of an arbitrary one frame period is always different from the length of one frame period immediately after the arbitrary one frame period.

It is necessary that the difference between the lengths of the adjacent frame periods is long and random so that flickers, vertical stripes, and horizontal stripes are not visually recognized by an observer.
In addition, when a moving image is displayed, it is necessary to shorten the frame period so that smooth display of the moving image is not hindered by a difference in length between adjacent frame periods.

Further, it is necessary to set the shortest frame period to a length that allows the potential of the video signal to be applied to the pixel electrode of each pixel.

By using the above configuration, it is possible to prevent flickering, vertical stripes, and horizontal stripes on the screen, which are visually recognized by the observer, while suppressing the frequency of the driving circuit when performing the AC driving. Further, the deterioration of the liquid crystal can be suppressed by the AC driving.

Next, FIG. 4 is a timing chart when the active matrix type liquid crystal display device shown in FIG. 1 is driven by source line inversion driving. FIG. 4 is a timing chart when the active matrix type liquid crystal display device displays white when normally black and black when normally white.

In the first frame period, first, a selection signal is input from the gate signal line driving circuit 102 to the gate signal line G1. As a result, all pixels (1, 1), (1, 2)... (1,
In x), the pixel TFT is turned on.

Then, a video signal is input to the source signal line S1 according to a signal from a shift register circuit or the like (not shown) in the source signal line driving circuit 101. It is assumed that the video signal input to the source signal line S1 in the first frame period has a positive polarity with reference to the common potential. Then, the video signal input to the source signal line S1 is input to the pixel electrode of the pixel (1, 1). The liquid crystal is driven by the potential of the input video signal, the amount of transmitted light is controlled, and a part of an image (an image corresponding to the pixel (1, 1)) is displayed on the pixel (1, 1).

At the next moment, the state in which an image is displayed on the pixel (1, 1) is held by a holding capacitor (not shown) or the like. (Not shown), a video signal having a negative polarity is input to the source signal line S2.

The selection signal from the gate signal line drive circuit 102 remains input to the gate signal line G1, and the pixel (1, 2) at the portion where the gate signal line G1 intersects with the source signal line S2 Are in an ON state. Therefore, the potential of the video signal input to the source signal line S2 is input to the pixel electrodes of the pixels (1, 2). The liquid crystal is driven by the potential of the input video signal, and the amount of transmitted light is controlled, and the pixel (1, 2) corresponds to a part of the image (corresponding to the pixel (1, 2)) like the pixel (1, 1). Image) is displayed.

Such display operations are sequentially performed, and the pixels (1, 1) and (1, 2) connected to the gate signal line G1.
.. (1, x), a video signal having a positive polarity and a video signal having a negative polarity are alternately input, and display a part of an image one after another. During this time, the gate signal line G1
Is continuously receiving a selection signal.

When the video signal is input to all the pixels connected to the gate signal line G1, the selection signal is not input to the gate signal line G1, and the first line period ends. Subsequently, the second line period starts, and the selection signal is input only to the gate signal line G2. Then, all the pixels (2, 1) connected to the gate signal line G2
(2, 2)... (2, x), the pixel TFT is turned on.

As in the case of the first line period, a video signal having a positive polarity and a video signal having a negative polarity are alternately input to the source signal lines S1 to Sx in order, and a part of the image is respectively received. Are displayed one after another. During this time, the selection signal is continuously input to the gate signal line G2.

By repeating the above-described operation sequentially on all the gate signal lines, video signals are input to all the pixels, and one image is displayed on the pixel portion 103. The period during which this one image is displayed is the first frame period. Note that a period in which one image is displayed in the pixel portion 103 and a vertical blanking period may be combined into one frame period. And all the pixels are again the pixels T of each pixel.
Until the FT is turned on, the state in which the image is displayed is held by a storage capacitor (not shown) or the like.

Next, the second frame period is started, and first, a selection signal is input from the gate signal line driving circuit 102 to the gate signal line G1. As a result, all the pixels (1, 1), (1, 2),... Connected to the gate signal line G1.
At (1, x), the pixel TFT is turned on.

Then, a video signal is input to the source signal line S1 in accordance with a signal from a shift register circuit or the like (not shown) in the source signal line driving circuit 101. In the second frame period, the video signal input to the source signal line S1 has a negative polarity with respect to the common potential. Then, the video signal input to the source signal line S1 is
Input to the pixel electrode of pixel (1, 1). The liquid crystal is driven by the potential of the input video signal, the amount of transmitted light is controlled, and a part of the image (pixel (1, 1)) is applied to pixel (1, 1).
Is displayed.

At the next moment, the state in which an image is displayed on the pixel (1, 1) is held by a holding capacitor (not shown) or the like. (Not shown), a video signal having a positive polarity is input to the source signal line S2.

The selection signal from the gate signal line driving circuit 102 remains input to the gate signal line G1, and the pixel (1, 2) at the portion where the gate signal line G1 intersects with the source signal line S2 Are in an ON state. Therefore, the potential of the positive polarity video signal input to the source signal line S2 is input to the pixel electrodes of the pixels (1, 2). The liquid crystal is driven by the potential of the input video signal, and the amount of transmitted light is controlled, and the pixel (1, 2) corresponds to a part of the image (corresponding to the pixel (1, 2)) like the pixel (1, 1). Image) is displayed.

Such display operations are sequentially performed, so that all the pixels (1, 1) connected to the gate signal line G1,
(1, x), a video signal having a positive polarity and a video signal having a negative polarity are alternately input to (1, x),
Each part of the image is displayed one after another. During this time, the selection signal continues to be input to the gate signal line G1.

When the video signal is input to all the pixels connected to the gate signal line G1, the selection signal is not input to the gate signal line G1, and the first line period ends. Subsequently, the second line period starts, and the selection signal is input only to the gate signal line G2. Then, as in the first line period, all pixels (2, 1) (2, 2)... (2, x) connected to the gate signal line G2
Then, a video signal having a positive polarity and a video signal having a negative polarity are alternately input, and a part of an image is displayed one after another. During this time, the selection signal is continuously input to the gate signal line G2.

By repeating the above-described operation sequentially on all the gate signal lines, video signals are sequentially input to all the pixels, and one image is displayed on the pixel portion 103.
The period during which this one image is displayed is the frame period. Note that a period in which one image is displayed in the pixel portion 103 and a vertical blanking period may be combined into one frame period. And all the pixels are again the pixels TF of each pixel.
Until T is turned on, the state in which the image is displayed is held by a storage capacitor (not shown) or the like.

[0098] Similarly, the above-described operation is performed in the third frame period and the fourth frame period. Note that the polarity of the video signal input to each pixel in the third frame period is the same as the polarity of the video signal input to each pixel in the first frame period. The polarity of the video signal input to each pixel in the fourth frame period is
The polarity is the same as the polarity of the video signal input to each pixel in the second frame period. The polarity of the video signal input to each pixel during the first frame period is opposite to the polarity of the video signal input to each pixel during the second frame period.

FIG. 5 shows a polarity pattern of each pixel in the source line inversion driving. Note that the polarity pattern shown in FIG. 5 corresponds to the pixel arrangement shown in FIG.

In addition, in the scanning method, in one screen (one frame), an odd-numbered gate signal line and an even-numbered gate signal line are divided into two times (two fields) for scanning, and an odd number gate signal line is used for scanning. There is a non-interlace scan in which the first and even-numbered gate signal lines are sequentially scanned without any separation. Here, an example using non-interless scan will be mainly described.

In the first to fourth frame periods, video signals of the same polarity are input to all the pixels connected to the same source signal line. Pixels connected to adjacent source signal lines receive video signals of opposite polarities. Further, the polarity of the video signal input to each pixel is inverted every frame period, and has the opposite polarity.

In the first and third frame periods, the polarity pattern of the pixel is represented by the polarity pattern C. In the second and third frame periods, the polarity pattern of the pixel is represented by a polarity pattern D. That is, focusing only on the polarity pattern, two types of polarity patterns (polarity pattern C and polarity pattern D) are repeatedly displayed for each frame period.

In the present embodiment, the polarity pattern of the pixels in the first and third frame periods is the polarity pattern C, and the polarity pattern of the pixels in the second and third frame periods is the polarity pattern D. The present invention is not limited to this configuration. Conversely, the polarity pattern of the pixel in the second and third frame periods is defined as a polarity pattern C,
The polarity pattern of the pixels in the first and third frame periods may be the polarity pattern D.

In the present invention, the lengths of the frame periods are not all the same, but the lengths of the frame periods are made to be different at random. In other words, the frame period is randomly changed every frame period. That is, driving is performed such that the length of an arbitrary one frame period is always different from the length of one frame period immediately after the arbitrary one frame period.

It is necessary that the difference between the lengths of adjacent frame periods is long and random so that flickers, vertical stripes and horizontal stripes are not visually recognized by an observer.
In addition, when a moving image is displayed, it is necessary to shorten the frame period so that smooth display of the moving image is not hindered by a difference in length between adjacent frame periods.

It is necessary to set the shortest frame period to a length that allows the potential of the video signal to be applied to the pixel electrode of each pixel.

By using the above configuration, it is possible to prevent flicker, vertical stripes, and horizontal stripes on the screen, which are visually recognized by the observer, while suppressing the frequency of the drive circuit when performing the AC drive. Further, the deterioration of the liquid crystal can be suppressed by the AC driving.

In this embodiment, the case where the frame inversion drive is performed and the case where the source line inversion is performed have been described. However, the present invention is not limited to the two AC drive operations. The above-described configuration of the present invention can be applied to the gate line inversion drive and the dot inversion drive.

That is, in the gate line inversion drive or the dot inversion drive, the lengths of the frame periods are not made equal to each other, and the lengths of the frame periods are made different at random. The difference between the lengths of adjacent frame periods is long enough to prevent flicker, vertical stripes, and horizontal stripes from being visually recognized by an observer, and is random. Then, when a moving image is displayed, the length is shortened to such an extent that a smooth moving image display is not hindered by a difference in length between adjacent frame periods.

It is necessary to set the shortest frame period to a length that allows the potential of the video signal to be applied to the pixel electrode of each pixel.

Further, the length of each frame period may be determined by using random numbers and chaos.

By using the above configuration, it is possible to prevent flickering, vertical stripes, and horizontal stripes on the screen visually recognized by the observer while suppressing the frequency of the driving circuit when performing the AC driving. Further, the deterioration of the liquid crystal can be suppressed by the AC driving.

The present invention can be applied not only to the case where pixels are arranged in a stripe pattern, but also to the case where pixels are arranged in a delta. Note that the delta arrangement means an arrangement of pixels in which the interior angle of a triangle formed by the centers of any three adjacent pixels does not become a right angle. In this specification, a pixel means a region surrounded by a source signal line and a gate signal line.

[0114]

EXAMPLES Examples of the present invention will be described below.

(Embodiment 1) In this embodiment, a description will be given of what frequency is used to drive each frame period in the alternating drive method of the present invention, taking source line inversion drive as an example.

The polarity pattern in the source line inversion driving is represented by a polarity pattern C and a polarity pattern D as shown in FIG. Focusing only on the polarity patterns, two types of polarity patterns (polarity pattern C and polarity pattern D) are repeatedly displayed for each frame period.

For example, a polarity pattern in an odd-numbered frame period is a polarity pattern C, and a polarity pattern in an even-numbered frame period is a polarity pattern D.

In this embodiment, the frame frequencies from the first frame period to the n-th frame period are 60 Hz, 62 Hz, 58 Hz, 55 Hz,.
z. However, the present invention is not limited to this value.

In the present invention, the lengths of the frame periods are not made equal to each other, and the lengths of the frame periods are made to be different at random. The difference between the lengths of the adjacent frame periods may be long enough so that the observer does not see flicker, vertical stripes, and horizontal stripes and is random. In addition, the difference between the lengths of adjacent frame periods may be shortened to such an extent that display of a smooth moving image is not hindered.

It is necessary to set the shortest frame period to a length that allows the potential of the video signal to be applied to the pixel electrode of each pixel.

By using the above configuration, it is possible to prevent flickering, vertical stripes, and horizontal stripes on the screen, which are visually recognized by an observer, while suppressing the frequency of the driving circuit when performing the AC driving. Further, the deterioration of the liquid crystal can be suppressed by the AC driving.

Embodiment 2 In this embodiment, an example of a method for manufacturing a liquid crystal panel of a semiconductor display device of the present invention will be described with reference to FIGS. Here, the pixel T of the pixel portion
A method for manufacturing an FT and a TFT of a driver circuit (a source signal line driver circuit, a gate signal line driver circuit, a D / A conversion circuit, and the like) provided around the pixel portion over the same substrate will be described in detail. However, for the sake of simplicity, a CMOS circuit, which is a basic circuit such as a shift register circuit, a buffer circuit, and a D / A conversion circuit, and an n-channel TFT are illustrated in the driving circuit.

In FIG. 6A, a low alkali glass substrate or a quartz substrate can be used as a substrate (active matrix substrate) 6001. In this embodiment, a low alkali glass substrate was used. In this case, one more than the glass strain point
The heat treatment may be performed in advance at a temperature as low as about 0 to 20 ° C. A base film 6002 such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on a surface of the substrate 6001 where a TFT is to be formed, in order to prevent impurity diffusion from the substrate 6001. For example, plasma C
A silicon oxynitride film formed from SiH ₄ , NH ₃ , and N ₂ O is formed to a thickness of 100 nm by the VD method, and a silicon oxynitride film formed from SiH ₄ and N ₂ O is similarly formed to a thickness of 200 nm.

Next, 20 to 150 nm (preferably 30 nm)
Semiconductor film 60 having an amorphous structure with a thickness of
03a is formed by a known method such as a plasma CVD method or a sputtering method. In this embodiment, an amorphous silicon film is formed to a thickness of 55 nm by a plasma CVD method. As the semiconductor film having an amorphous structure, there are an amorphous semiconductor film and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be used.
In addition, since the base film 6002 and the amorphous silicon film 6003a can be formed by the same film formation method, both may be formed continuously. After the formation of the base film, it is possible to prevent the surface from being contaminated by not once exposing it to the atmosphere, thereby reducing the variation in the characteristics of the TFT to be manufactured and the fluctuation of the threshold voltage. (FIG. 6 (A))

Then, the amorphous silicon film 6003a is converted to the crystalline silicon film 6003a using a known crystallization technique.
b is formed. For example, a laser crystallization method or a thermal crystallization method (solid phase growth method) may be applied. At the time of laser crystallization, a continuous emission excimer laser may be used. Here, a crystalline silicon film 6003b was formed by a crystallization method using a catalytic element according to the technique disclosed in Japanese Patent Application Laid-Open No. Hei 7-130652. Prior to the crystallization step, depending on the hydrogen content of the amorphous silicon film, 400 to 500
Heat treatment at ℃ for about 1 hour to reduce hydrogen content to 5 atom%
It is desirable to crystallize after the following. When the amorphous silicon film is crystallized, the rearrangement of atoms occurs and the density of the amorphous silicon film is increased. Also decreased by about 1 to 15%. (FIG. 6 (B))

Then, the crystalline silicon film 6003b is divided into islands to form island-like semiconductor layers 6004 to 6007. After that, a mask layer 6008 made of a silicon oxide film having a thickness of 50 to 100 nm is formed by a plasma CVD method or a sputtering method. (FIG. 6 (C))

Then, a resist mask 6009 is provided, and n
Island-shaped semiconductor layers 6005 to 6 forming a channel type TFT
1 × 10 for the purpose of controlling the threshold voltage over the entire surface of 007
Boron (B) was added as an impurity element imparting p-type at a concentration of about ^{16 to} 5 × 10 ¹⁷ atoms / cm ³ . Boron (B) may be added by an ion doping method, or may be added simultaneously with the formation of the amorphous silicon film. Although addition of boron (B) is not always necessary here, the semiconductor layer 6010 to which boron (B) is added is added.
6012 was preferably formed to keep the threshold voltage of the n-channel TFT within a predetermined range.
(FIG. 6 (D))

LDD area of n-channel type TFT of drive circuit
In order to form the region, the impurity element imparting n-type
It is selectively added to the semiconductor layers 6010 and 6011. That
Therefore, the resist masks 6013 to 6016 are
Formed. As an impurity element imparting n-type, phosphorus
(P) or arsenic (As) may be used.
Phosphine (PH) to add (P)_Three)
An ion doping method was applied. Impurity region 60 formed
The phosphorus (P) concentration of 17, 6018 is 2 × 10¹⁶~ 5 × 1
0¹⁹atoms / cm^ThreeShould be within the range. In this specification,
Included in impurity regions 6017 to 6019 formed here
(N) ^-) And table
You. Further, the impurity region 6019 forms a storage capacitor of the pixel.
Semiconductor layer for forming the same concentration in this region.
Phosphorus (P) was added. (FIG. 7 (A))

Next, a step of removing the mask layer 6008 with hydrofluoric acid or the like to activate the impurity element added in FIGS. 6D and 7A is performed. The activation can be performed by a heat treatment at 500 to 600 ° C. for 1 to 4 hours in a nitrogen atmosphere or a laser activation method. Further, both may be performed in combination. In this embodiment, a KrF excimer laser beam (wavelength 248) is used by using a laser activation method.
nm) to form a linear beam and generate an oscillation frequency of 5 to 5 nm.
50 Hz, energy density 100 to 500 mJ / cm ²
The overlap ratio of the linear beam is 80 to 98%
To process the entire surface of the substrate on which the island-shaped semiconductor layer was formed. There are no particular restrictions on the laser light irradiation conditions, and the conditions may be determined appropriately by the practitioner. Activation may be performed using a continuous light excimer laser.

Then, a gate insulating film 6020 is formed of an insulating film containing silicon with a thickness of 10 to 150 nm by a plasma CVD method or a sputtering method. For example, 12
A silicon oxynitride film is formed with a thickness of 0 nm. As the gate insulating film, another insulating film containing silicon may be used as a single layer or a stacked structure. (FIG. 7 (B))

Next, a first conductive layer is formed to form a gate electrode. The first conductive layer may be formed as a single layer, or may be formed as a two-layer or three-layer structure as necessary. In this embodiment, a conductive layer (A) 6021 made of a conductive nitride metal film and a conductive layer (B) 6022 made of a metal film are stacked. Conductive layer (B) 602
2 is an element selected from tantalum (Ta), titanium (Ti), molybdenum (Mo), and tungsten (W), an alloy containing the above elements as a main component, or an alloy film combining the above elements (typically, The conductive layer (A) 6021 may be formed of tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN), or molybdenum nitride (MoN). Form. The conductive layer (A) 6021 is used as an alternative material.
Tungsten silicide, titanium silicide, or molybdenum silicide may be used. The conductive layer (B) may have a low impurity concentration in order to reduce the resistance, and it is particularly preferable that the oxygen concentration be 30 ppm or less. For example, tungsten (W) has an oxygen concentration of 30.
A specific resistance of 20 μΩcm or less could be realized by setting the content to ppm or less.

The conductive layer (A) 6021 has a thickness of 10 to 50 nm.
(Preferably 20 to 30 nm), and the conductive layer (B) 60
22 is 200 to 400 nm (preferably 250 to 350 nm)
nm). In this embodiment, the conductive layer (A) 60
A 21 nm-thick tantalum nitride film was used for 21, and a 350 nm-thick Ta film was used for the conductive layer (B) 6022, both of which were formed by sputtering. In the film formation by the sputtering method, if an appropriate amount of Xe or Kr is added to Ar of the gas for sputtering, the internal stress of the film to be formed can be relaxed and the film can be prevented from peeling. Although not shown, it is effective to form a silicon film doped with phosphorus (P) with a thickness of about 2 to 20 nm under the conductive layer (A) 6021. Thereby, the adhesion of the conductive film formed thereon is improved and oxidation is prevented, and at the same time, a small amount of the alkali metal element contained in the conductive layer (A) or the conductive layer (B) diffuses into the gate insulating film 6020. Can be prevented.
(FIG. 7 (C))

Next, resist masks 6023 to 6027
Are formed, and a conductive layer (A) 6021 and a conductive layer (B) 602 are formed.
2 and the gate electrodes 6028-60
31 and a capacitor wiring 6032 are formed. Gate electrode 602
8 to 6031 and the capacitor wiring 6032 are formed integrally with 6028a to 6032a made of a conductive layer (A) and 6028b to 6032b made of a conductive layer (B). At this time, a gate electrode 6029 formed in the driver circuit,
6030 is formed so as to overlap with part of the impurity regions 6017 and 6018 with the gate insulating film 6020 interposed therebetween.
(FIG. 7 (D))

Next, in order to form a source region and a drain region of the p-channel TFT of the driver circuit, a step of adding an impurity element imparting p-type is performed. Here, the impurity region is formed in a self-aligned manner using the gate electrode 6028 as a mask. At this time, the n-channel TFT
Are formed with a resist mask 6033. Then, an impurity region 6034 was formed by an ion doping method using diborane (B ₂ H ₆ ). The boron (B) concentration in this region is set to 3 × 10 ^{20 to} 3 × 10 ²¹ atoms / cm ³ . In this specification, the concentration of the impurity element imparting p-type contained in the impurity region 6034 formed here is expressed as (p ⁺ ). (FIG. 8A)

Next, in the n-channel TFT, an impurity region functioning as a source region or a drain region was formed. Resist masks 6035 to 6037 were formed, and impurity regions 6038 to 6042 were formed by adding an impurity element imparting n-type. This is performed by an ion doping method using phosphine (PH ₃ ), and the phosphorus (P) concentration in this region is set to 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / c.
It was m ^3. In this specification, the concentration of the impurity element imparting n-type contained in the impurity regions 6038 to 6042 formed here is expressed as (n ⁺ ). (FIG. 8 (B))

Although the impurity regions 6038 to 6042 contain phosphorus (P) or boron (B) already added in the previous step, phosphorus (P) is added at a sufficiently high concentration. Therefore, it is not necessary to consider the influence of phosphorus (P) or boron (B) added in the previous step.
Further, the concentration of phosphorus (P) added to impurity region 6038 is 1/2 to the concentration of boron (B) added in FIG.
Since it was 1/3, p-type conductivity was ensured and there was no effect on the characteristics of the TFT.

The L of the n-channel TFT in the pixel portion is
An n-type impurity-imparting process for forming a DD region was performed. Here, an impurity element imparting n-type in a self-aligned manner is added by an ion doping method using the gate electrode 6031 as a mask. The concentration of phosphorus (P) to be added is 1 × 1
0 ^{16 to} 5 × 10 ¹⁸ atoms / cm ^3, which is substantially lower than that of the impurity element added in FIGS. 7A, 8A, and 8B. Has an impurity region 6
Only 043 and 6044 are formed. In this specification,
The concentration of the impurity element imparting n-type contained in the impurity regions 6043 and 6044 is represented by (n ⁻ ). (FIG. 8
(C))

Thereafter, a heat treatment step is performed to activate the n-type or p-type imparting impurity element added at each concentration. This step can be performed by a furnace annealing method, a laser annealing method, or a rapid thermal annealing method (RTA method). Here, the activation step was performed by the furnace annealing method. The heat treatment is performed in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less, at 400 to 800 ° C, typically 500 to 600 ° C.
In this embodiment, the heat treatment was performed at 550 ° C. for 4 hours. When a substrate having heat resistance such as a quartz substrate is used as the substrate 6001,
The heat treatment may be performed for a long time, and the activation of the impurity element and the junction between the impurity region to which the impurity element is added and the channel formation region can be favorably formed.

In this heat treatment, the gate electrode 6028
Film 602 forming the capacitor wiring 6032 and the capacitor wiring 6032
For 8b to 6032b, conductive layers (C) 6028c to 6032c are formed with a thickness of 5 to 80 nm from the surface. For example, when the conductive layers (B) 6028b to 6032b are tungsten (W), tungsten nitride (WN) is formed, and when the conductive layers (B) 6028b to 6032b are tantalum (Ta), tantalum nitride (Ta) is formed.
N) can be formed. In the present invention, a laminate of a silicon (Si) film, a WN film and a W film,
The gate electrode may be formed using a stacked film of a W film having i, a stacked film of a W film and a W film having Si, and Si, a W film having Mo, or a Ta film having Mo. The conductive layers (C) 6028c to 6032c are
The gate electrodes 6028 to 6031 can be similarly formed by exposing the gate electrodes 6028 to 6031 to a plasma atmosphere containing nitrogen using nitrogen or ammonia. Further, heat treatment was performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% of hydrogen to hydrogenate the island-shaped semiconductor layer. In this step, dangling bonds in the semiconductor layer are terminated by thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma or hydrogen converted into plasma) may be performed.

When the island-like semiconductor layer was formed from an amorphous silicon film by a crystallization method using a catalyst element, a trace amount of the catalyst element remained in the island-like semiconductor layer. Of course, it is possible to complete the TFT in such a state,
It was more preferable to remove the remaining catalyst element from at least the channel formation region. One of the means for removing the catalytic element is a means utilizing the gettering action of phosphorus (P). The concentration of phosphorus (P) necessary for gettering is substantially the same as that of the impurity region (n ⁺ ) formed in FIG. 8B, and the heat treatment in the activation step performed here causes the n-channel TFT and the p-type. The catalyst element could be gettered from the channel forming region of the channel type TFT. (FIG. 8 (D))

When the activation and hydrogenation steps are completed,
A second conductive film serving as a gate wiring is formed. This second conductive film is formed by adding a conductive layer (D) mainly composed of aluminum (Al) or copper (Cu), which is a low-resistance material, to titanium (T
i) or a conductive layer (E) made of tantalum (Ta), tungsten (W), or molybdenum (Mo). In this embodiment, titanium (Ti) is contained in an amount of 0.1 to 2% by weight.
The aluminum (Al) film containing the conductive film was formed as a conductive layer (D) 6045, and the titanium (Ti) film was formed as a conductive layer (E) 6046. The conductive layer (D) 6045 has a thickness of 200 to 400 nm.
(Preferably 250 to 350 nm), and the conductive layer (E) 6046 is 50 to 200 (preferably 100 to
150 nm). (FIG. 9A)

Then, a conductive layer (E) 6046 and a conductive layer (D) are formed to form a gate wiring connected to the gate electrode.
6045 and the gate wiring 604
7, 6048 and a capacitor wiring 6049 were formed. In the etching treatment, first, a part of the conductive layer (D) is removed from the surface of the conductive layer (E) by a dry etching method using a mixed gas of SiCl ₄ , Cl ₂ and BCl _3, and then a phosphoric acid-based etching solution is used. Conductive layer (D) by wet etching
As a result, the gate wiring could be formed while maintaining the selectivity with the base.

The first interlayer insulating film 6050 is 500 to 15
A contact hole which is formed of a silicon oxide film or a silicon oxynitride film with a thickness of 00 nm and reaches a source region or a drain region formed in each of the island-shaped semiconductor layers is formed.
Then, drain wirings 6055 to 6058 are formed. Although not shown, in this embodiment, this electrode is
A three-layer laminated film in which 0 nm, an aluminum film containing Ti, 300 nm, and a Ti film, 150 nm, were continuously formed by a sputtering method.

Next, as the passivation film 6059, a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film is 50 to 500 nm (typically, 100 to 3 nm).
(00 nm). When hydrogenation was performed in this state, favorable results were obtained with respect to the improvement of TFT characteristics. For example, in an atmosphere containing 3 to 100% hydrogen, 3
It is good to perform heat treatment at 00 to 450 ° C. for 1 to 12 hours,
Alternatively, the same effect was obtained by using the plasma hydrogenation method. Here, at a position where a contact hole for connecting the pixel electrode and the drain wiring is formed later,
An opening may be formed in the passivation film 6059. (FIG. 9 (C))

Thereafter, a second interlayer insulating film 6060 made of an organic resin is formed to a thickness of 1.0 to 1.5 μm. As the organic resin, polyimide, acrylic, polyamide,
Polyimide amide, BCB (benzocyclobutene) and the like can be used. Here, a polyimide of a type that is thermally polymerized after being applied to the substrate and baked at 300 ° C. is used. Then, a contact hole reaching the drain wiring 6058 is formed in the second interlayer insulating film 6060, and pixel electrodes 6061 and 6062 are formed. As the pixel electrode, a transparent conductive film may be used for a transmission type liquid crystal display device, and a metal film may be used for a reflection type liquid crystal display device. In this embodiment, in order to obtain a transmissive liquid crystal display device, an indium tin oxide (ITO) film has a thickness of 100 n.
m was formed by a sputtering method. (FIG. 10)

Thus, the TFT of the driving circuit is formed on the same substrate.
And a substrate having pixel TFTs in the pixel portion. The driving circuit includes a p-channel TFT 6101,
A first n-channel TFT 6102, a second n-channel TFT 6103, a pixel TFT 6104 in the pixel portion, and a storage capacitor 6105 were formed. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

In the p-channel TFT 6101 of the driver circuit, a channel formation region 610 is formed in the island-shaped semiconductor layer 6004.
6, source regions 6107a and 6107b, and drain regions 6108a and 6108b. In the first n-channel TFT 6102, an L overlapping the channel formation region 6109 and the gate electrode 6029 in the island-shaped semiconductor layer 6005.
DD region 6110 (hereinafter, such an LDD region is referred to as Lov
, Source region 6111 and drain region 6112
have. The length of the Lov region in the channel length direction is 0.5 to 3.0 μm, preferably 1.0 to 1.5 μm. The second n-channel TFT 6103 includes a channel formation region 6113, LDD regions 6114 and 6115, a source region 6116, and a drain region 6117 in the island-shaped semiconductor layer 6006. This LDD region is an LDD region that does not overlap with the Lov region and the gate electrode 6030 (hereinafter referred to as an LDD region).
Such an LDD region is referred to as Loff).
The length of the Loff region in the channel length direction is 0.3 to 2.
0 μm, preferably 0.5 to 1.5 μm. Pixel T
In the FT 6104, channel formation regions 6118 and 6119 and Loff regions 6120 to 61 are formed in the island-shaped semiconductor layer 6007.
23, a source or drain region 6124-6126. The length of the Loff region in the channel length direction is 0.
It is 5-3.0 μm, preferably 1.5-2.5 μm. Further, the capacitor wirings 6032 and 6049, an insulating film made of the same material as the gate insulating film, and a pixel TFT 6104
From the semiconductor layer 6127 to which the impurity element imparting n-type is added.
105 is formed. In FIG. 10, the pixel TFT 610
4 has a double gate structure, but may have a single gate structure or a multi-gate structure provided with a plurality of gate electrodes.

As described above, in the present embodiment, the TFTs constituting each circuit according to the specifications required by the pixel TFT and the driving circuit.
By optimizing the structure of the FT, it is possible to improve the operation performance and reliability of the semiconductor display device. Further, the gate electrode is formed from a conductive material having heat resistance, thereby facilitating activation of the LDD region, the source region, and the drain region. By forming the gate wiring from a low-resistance material, the wiring resistance can be sufficiently reduced. Therefore, the present invention can be applied to a semiconductor display device having a pixel portion size (screen size) of 4 inches or more.

In this embodiment, the transmission type liquid crystal panel has been described. However, the present invention is not limited to this, and can be used for a reflective liquid crystal panel.

Embodiment 3 The present invention can be used for various semiconductor display devices (active matrix type liquid crystal displays). That is, the present invention can be applied to all electronic devices incorporating such a semiconductor display device as a display medium.

Examples of such electronic devices include a video camera, a digital camera, a projector (rear or front type), a head mounted display (goggle type display), a game machine, a car navigation, a personal computer, and a portable information terminal (mobile computer). , A mobile phone or an electronic book).
Examples of these are shown in FIG. 11, FIG. 12, and FIG.

FIG. 11A shows a display, which includes a housing 2001, a support base 2002, a display portion 2003, and the like.
The present invention can be applied to the display portion 2003 and other signal control circuits.

FIG. 11B shows a video camera, which includes a main body 2101, a display section 2102, an audio input section 2103, operation switches 2104, a battery 2105, and an image receiving section 210.
6. The present invention can be applied to the display portion 2102, the audio input portion 2103, and other signal control circuits.

FIG. 11C shows a part of the head-mounted display (one side on the right), and includes a main body 2201, a signal cable 2202, a head fixing band 2203, and a display section 220.
4, including an optical system 2205, a display device 2206, and the like. The present invention can be applied to the display device 2205 and other signal control circuits.

FIG. 11D shows a player using a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 2301, a display section 2302, and a speaker section 230.
3, a recording medium 2304, and operation switches 2305. This apparatus uses a DVD (Dig) as a recording medium.
It is possible to enjoy listening to music, watching movies, playing games, and using the Internet using an IT (Versatile Disc), CD, or the like. The present invention can be applied to the display portion 2302 and other signal control circuits.

FIG. 11E shows a personal computer, which includes a main body 2401, a video input section 2402, and a display section 24.
03, a keyboard 2404. The present invention can be applied to the video input unit 2402, the display unit 2403, and other signal control circuits.

FIG. 11F shows a goggle type display, which comprises a main body 2501, a display section 2502, and an arm section 250.
3 The present invention can be applied to the display portion 2502 and other signal control circuits.

FIG. 12A shows a front type projector, which comprises a light source optical system, a display device 7601 and a screen 7602. The present invention can be applied to a display device.

FIG. 12B shows a rear projector, in which a main body 7701, a light source optical system and a display device 7702,
Mirror 7703, mirror 7704, screen 7705
It consists of. The present invention can be applied to a display device.

FIG. 12C shows the light source optical system and the display device 760 shown in FIGS. 12A and 12B.
1 is a diagram showing an example of the structure of 7702. FIG. The light source optical system and the display devices 7601 and 7702 are
01, mirrors 7802, 7804 to 7806, dichroic mirror 7803, optical system 7807, display device 78
08, a phase difference plate 7809, and a projection optical system 7810. The projection optical system 7810 includes a plurality of optical lenses provided with a projection lens. This configuration corresponds to the display 78
It is called a three-plate type because it uses three 08s. In addition, the practitioner may appropriately place an optical lens or a film having a polarizing function on the optical path indicated by the arrow in FIG.
A film for adjusting the phase difference, an IR film, or the like may be provided.

FIG. 12D is a diagram showing an example of the structure of the light source optical system 7801 in FIG. 12C. In the present embodiment, the light source optical system 7801 includes a reflector 7811, a light source 7812, and lens arrays 7813 and 7813.
814, a polarization conversion element 7815, and a condenser lens 7816. Note that the light source optical system shown in FIG. 12D is an example and is not limited to this configuration. For example, a practitioner may appropriately provide an optical lens, a film having a polarizing function, a film for adjusting a phase difference, an IR film, or the like to the light source optical system.

FIG. 12 (C) shows an example of a three-plate type, while FIG. 13 (A) shows an example of a single-plate type. FIG.
The light source optical system and the display device illustrated in FIG. 1A include a light source optical system 7901, a display device 7902, a projection optical system 7903, and a retardation plate 7904. The projection optical system 7903 is
It is composed of a plurality of optical lenses provided with a projection lens. The light source optical system and the display device shown in FIG.
12A and 12B can be applied to the light source optical system and the display devices 7601 and 7702. Further, as the light source optical system 7901, the light source optical system illustrated in FIG. Note that the display device 7902 is provided with a color filter (not shown) to colorize a display image.

Further, the light source optical system and display device shown in FIG. 13B is an application example of FIG. 13A, and uses a rotating color filter disk 7905 of RGB instead of providing a color filter. The display image is colorized. The light source optical system and the display device illustrated in FIG. 13B can be applied to the light source optical system and the display devices 7601 and 7702 in FIGS. 12A and 12B.

The light source optical system and the display device shown in FIG. 13C are called a color filterless single plate type. In this method, a microlens array 7915 is provided on a display device 7916, and a dichroic mirror (green) 7 is provided.
912, a dichroic mirror (red) 7913, and a dichroic mirror (blue) 7914 are used to colorize the display image. The projection optical system 7917 includes a plurality of optical lenses provided with a projection lens. The light source optical system and the display device shown in FIG.
(B) Light source optical system and display devices 7601 and 7 in FIG.
702. As the light source optical system 7911, an optical system using a coupling lens and a collimator lens in addition to the light source may be used.

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in various fields. Further, the electronic apparatus according to the present embodiment can be realized by using any combination of the first, second, and fourth embodiments.

(Embodiment 4) In the active matrix type liquid crystal display device of the present invention described above, it is possible to use various liquid crystals other than the nematic liquid crystal. For example, in 1998,
SID, "Characteristics and Driving Scheme of Polyme
r-Stabilized Monostable FLCD Exhibiting Fast Respo
nse Time and High Contrast Ratio with Gray-Scale C
apability "by H. Furue et al., 1997, SID DIGEST,
841, "A Full-Color Thresholdless Antiferroelectric
LCD Exhibiting Wide Viewing Angle with Fast Respo
nseTime "by T. Yoshida et al., 1996, J. Mater. C
hem. 6 (4), 671-673, "Thresholdless antiferroelectr
icity in liquid crystals and its application to di
It is possible to use the liquid crystals disclosed in splays "by S. Inui et al. and US Pat. No. 5,594,569.

Ferroelectric liquid crystal (FLC) showing an isotropic phase-cholesteric phase-chiral smectic C phase transition series
FIG. 14 shows the electro-optical characteristics of a monostable FLC in which the cholesteric phase-chiral smectic C phase transition is performed while applying a DC voltage and the cone edge is almost aligned with the rubbing direction. The display mode using the ferroelectric liquid crystal as shown in FIG. 14 is called “Half-V switching mode”. The vertical axis of the graph shown in FIG. 14 is the transmittance (arbitrary unit), and the horizontal axis is the applied voltage. "Hal
For the fV-shaped switching mode, see Terada et al.
Half-V switching mode FLCD ", 46th
Proceedings of the JSCE Lecture Meeting, March 1999
Moon, p. 1316, and Yoshihara et al., "Time-Division Full-Color LCD with Ferroelectric Liquid Crystal", Liquid Crystal Vol. 3, No. 19, 1992.
See page 0 for details.

As shown in FIG. 14, it is understood that the use of such a ferroelectric mixed liquid crystal enables low-voltage driving and gradation display. A ferroelectric liquid crystal exhibiting such electro-optical characteristics can be used in the active matrix type liquid crystal display device of the present invention.

A liquid crystal exhibiting an antiferroelectric phase in a certain temperature range is called an antiferroelectric liquid crystal (AFLC). As a mixed liquid crystal having an antiferroelectric liquid crystal, there is a so-called thresholdless antiferroelectric mixed liquid crystal exhibiting an electro-optical response characteristic in which transmittance changes continuously with an electric field. This thresholdless antiferroelectric mixed liquid crystal has a so-called V-shaped electro-optical response characteristic, and its driving voltage is about ± 2.5 V.
Some (cell thicknesses of about 1 μm to 2 μm) have been found.

In general, a thresholdless antiferroelectric mixed liquid crystal has a large spontaneous polarization and a high dielectric constant of the liquid crystal itself. Therefore, when a thresholdless antiferroelectric mixed liquid crystal is used in an active matrix type liquid crystal display device, a relatively large storage capacitor is required for a pixel. Therefore, it is preferable to use a thresholdless antiferroelectric mixed liquid crystal having a small spontaneous polarization.

By using such a thresholdless antiferroelectric mixed liquid crystal in the active matrix type liquid crystal display device of the present invention, low-voltage driving can be realized.
Low power consumption is realized.

[0172]

According to the invention of the present application, it is possible to prevent flicker, vertical stripes and horizontal stripes on the screen visually recognized by the observer while performing the AC drive, while suppressing the frequency of the drive circuit. Become. Further, the deterioration of the liquid crystal can be suppressed by the AC driving.

[Brief description of the drawings]

FIG. 1 is a top view of an active matrix liquid crystal display device and a diagram showing an arrangement of pixels.

FIG. 2 is a timing chart of frame inversion driving according to the present invention.

FIG. 3 is a diagram showing a polarity pattern of pixels in frame inversion driving according to the present invention.

FIG. 4 is a timing chart of source line inversion driving according to the present invention.

FIG. 5 is a diagram showing a polarity pattern of a pixel in source line inversion driving according to the present invention.

FIG. 6 is a diagram showing a manufacturing process of an active matrix liquid crystal display device.

FIG. 7 is a diagram illustrating a manufacturing process of an active matrix liquid crystal display device.

FIG. 8 is a diagram illustrating a manufacturing process of an active matrix liquid crystal display device.

FIG. 9 is a diagram illustrating a manufacturing process of an active matrix liquid crystal display device.

FIG. 10 is a diagram illustrating a manufacturing process of an active matrix liquid crystal display device.

FIG. 11 is a diagram of an electronic device to which the present invention is applied.

FIG. 12 is a view of a projector to which the present invention is applied.

FIG. 13 is a view of a projector to which the present invention is applied.

FIG. 14 is a graph showing characteristics of light transmittance with respect to an applied voltage of a thresholdless antiferroelectric mixed liquid crystal.

15A and 15B are a top view of an active matrix liquid crystal display device and a diagram showing an arrangement of pixels.

FIG. 16 is a diagram showing a polarity pattern in AC driving.

FIG. 17 is a timing chart of a conventional frame inversion drive.

[Explanation of symbols]

 101 Source signal line driving circuit 102 Gate signal line driving circuit 103 Pixel section 104 Pixel 105 Pixel TFT 106 Pixel electrode

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H093 NA16 NA33 NC16 NC34 ND10 NF05 NF17 5C006 AA01 AA22 AC27 AC28 AC30 AF42 AF44 AF51 BA12 BB15 BC03 BC12 BF03 BF24 EA01 EC11 FA22 FA23 FA34 5C080 AA10 BB05 CC11 DD05EE06 JJ04 JJ05 JJ06 5C094 AA03 AA05 BA03 BA43 CA19 EA03 EA06 EA07 GA10 HA03

Claims (6)

[Claims] 1. A method for driving a semiconductor display device comprising: a plurality of pixels including a plurality of pixel TFTs and a plurality of pixel electrodes; a counter electrode; and a liquid crystal provided between the plurality of pixel electrodes and the counter electrode. In the above, a video signal is input to the plurality of pixel electrodes via the plurality of pixel TFTs, and a video signal input to the plurality of pixel electrodes is based on the potential of the counter electrode every frame period. Wherein the polarity is inverted, and the length of the frame period is different for each frame period. 2. A plurality of pixels including a plurality of pixel TFTs and a plurality of pixel electrodes, a plurality of source signal lines, a plurality of gate signal lines, a counter electrode, and a portion between the plurality of pixel electrodes and the counter electrode. In the method for driving a semiconductor display device having a liquid crystal provided in the semiconductor device, switching of the plurality of pixel TFTs is controlled by a selection signal input to the plurality of gate signal lines, and input to the plurality of source signal lines. The video signal is input to the plurality of pixel electrodes via the plurality of pixel TFTs, and the video signal input to the plurality of pixel electrodes has a polarity based on the potential of the counter electrode every frame period. Wherein the length of the frame period is different for each frame period. 3. A plurality of pixels including a plurality of pixel TFTs and a plurality of pixel electrodes, a plurality of source signal lines, a plurality of gate signal lines, a counter electrode, and a portion between the plurality of pixel electrodes and the counter electrode. In the method for driving a semiconductor display device having a liquid crystal provided in the semiconductor device, switching of the plurality of pixel TFTs is controlled by a selection signal input to the plurality of gate signal lines, and input to the plurality of source signal lines. The video signal is input to the plurality of pixel electrodes via the plurality of pixel TFTs, and the polarity of the video signal input to each of the plurality of source signal lines is equal to the potential of the counter electrode during one frame period. The polarity of a video signal input to an adjacent source signal line among the plurality of source signal lines is always based on the potential of the counter electrode. The video signals input to the plurality of source signal lines have polarities inverted every frame period with reference to the potential of the counter electrode, A driving method for a semiconductor display device, wherein the lengths of the semiconductor display devices are different. 4. A plurality of pixels including a plurality of pixel TFTs and a plurality of pixel electrodes, a plurality of source signal lines, a plurality of gate signal lines, a counter electrode, and a portion between the plurality of pixel electrodes and the counter electrode. In the method for driving a semiconductor display device having a liquid crystal provided in the semiconductor device, switching of the plurality of pixel TFTs is controlled by a selection signal input to the plurality of gate signal lines, and input to the plurality of source signal lines. Video signals are input to the plurality of pixel electrodes via the plurality of pixel TFTs, and the polarity of all video signals input to the plurality of source signal lines is the potential of the counter electrode during one line period. The polarities of the video signals input to the plurality of source signal lines in adjacent line periods are mutually the same with respect to the potential of the counter electrode. The polarity of the video signal input to the plurality of source signal lines is inverted every frame period with reference to the potential of the counter electrode, and the length of the frame period is changed every frame period. A method for driving a semiconductor display device, wherein 5. A plurality of pixels including a plurality of pixel TFTs and a plurality of pixel electrodes, a plurality of source signal lines, a plurality of gate signal lines, a counter electrode, and a portion between the plurality of pixel electrodes and the counter electrode. In the method for driving a semiconductor display device having a liquid crystal provided in the semiconductor device, switching of the plurality of pixel TFTs is controlled by a selection signal input to the plurality of gate signal lines, and input to the plurality of source signal lines. Video signals are input to the plurality of pixel electrodes via the plurality of pixel TFTs. During one frame period, all video signals input to the plurality of pixel electrodes are based on the potential of the counter electrode. The video signal input to the plurality of pixel electrodes has a polarity that is inverted every frame period with reference to the potential of the counter electrode, A method for driving a semiconductor display device, wherein the length of a frame period is different for each frame period. 6. The driving method of a semiconductor display device according to claim 1, wherein the length of the frame period is randomly different for each frame period.