JP2001168269A - Mounting structure of semiconductor device, laminated circuit module, and method of manufacturing semiconductor device mounting structure - Google Patents

Mounting structure of semiconductor device, laminated circuit module, and method of manufacturing semiconductor device mounting structure

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Publication number
JP2001168269A
JP2001168269A JP34868999A JP34868999A JP2001168269A JP 2001168269 A JP2001168269 A JP 2001168269A JP 34868999 A JP34868999 A JP 34868999A JP 34868999 A JP34868999 A JP 34868999A JP 2001168269 A JP2001168269 A JP 2001168269A
Authority
JP
Japan
Prior art keywords
mounting structure
electrode
wiring
insulating layer
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP34868999A
Other languages
Japanese (ja)
Other versions
JP4320492B2 (en
Inventor
Takuya Sasaya
卓也 笹谷
Shinichiro Kawakita
晋一郎 川北
Nobuaki Kawahara
伸章 川原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
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Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to JP34868999A priority Critical patent/JP4320492B2/en
Publication of JP2001168269A publication Critical patent/JP2001168269A/en
Application granted granted Critical
Publication of JP4320492B2 publication Critical patent/JP4320492B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
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    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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    • H01L2924/151—Die mounting substrate
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    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
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    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA

Abstract

PROBLEM TO BE SOLVED: To compactly mount a semiconductor device on a wiring board so as to improve other parts in mounting efficiency. SOLUTION: Interlayer through-electrodes 18 and bump electrodes 19 are formed on a multilayer wiring board that serves as a base, and a semiconductor device 17 is mounted in a flip chip mounting manner, and thermosetting resin is applied thereon, then thermally cured, and ground to set the semiconductor device 17 as thick as prescribed, and an interlayer connection electrode 18 is exposed. A wiring electrode 21 is formed, thermosetting resin is applied thereon, and a multilayer board 13 is placed on the thermosetting resin, and the thermosetting resin is cured as a pressure is applied on the multilayer board 13, and the wiring electrode 21 and the multilayer wring board 13 are electrically connected together. Mounting structures 14 can be laminated in layers so as to be a laminated circuit module. A surface-mpounting device can be mounted on all the surfaces of the multilayer wiring boards 12 and 13, and a compact laminated circuit module of moderate thickness can be formed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、下地となる配線基
板もしくは他の実装構造体の上に積層形成する半導体素
子の実装構造および積層型回路モジュールならびに半導
体素子の実装構造の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting structure of a semiconductor element and a stacked circuit module formed on a wiring substrate or another mounting structure serving as a base, and a method of manufacturing a mounting structure of a semiconductor element.

【０００２】[0002]

【発明が解決しようとする課題】近年、電子回路は、搭
載部品の小型化や接続電極の狭ピッチ化と使用する配線
基板の高密度化により小型化が進んできており、ベアチ
ップを用いたフリップチップ実装と高密度集積配線基板
を用いることで回路の実装サイズは、ほぼ搭載部品自体
の占有面積（フットプリント面積）と同等の面積となる
までになってきている。したがって、これ以上の小型化
を図るためには、回路構成部品（ベアチップ）を縦方向
に積層した三次元的な積層実装構造を採用する必要があ
る。In recent years, electronic circuits have been miniaturized due to miniaturization of mounted components, narrowing of pitches of connection electrodes and densification of wiring boards to be used, and flip circuits using bare chips have been developed. By using chip mounting and a high-density integrated wiring board, the mounting size of the circuit has become almost equal to the area occupied by the mounted components themselves (footprint area). Therefore, in order to achieve further miniaturization, it is necessary to adopt a three-dimensional stacked mounting structure in which circuit components (bare chips) are stacked in the vertical direction.

【０００３】この場合、ベアチップを用いた実装方式で
は、例えば、次の文献に系統的にまとめられてい
る。『"A Review of 3-D Packaging Technology" IEEE
Transactions on components,packaging,and manufactu
ring technology-part B,vol.21,No.1,Feb.1998 』In this case, the mounting method using a bare chip is systematically summarized in, for example, the following document. "" A Review of 3-D Packaging Technology "IEEE
Transactions on components, packaging, and manufactu
ring technology-part B, vol.21, No.1, Feb.1998 』

【０００４】これには、例えば図１１（ａ），（ｂ）に
示すような構成のものが開示されている。これらは、半
導体素子としてのベアチップを直接積層して形成するタ
イプのものである。同図（ａ）のものは、複数のベアチ
ップ１のそれぞれに、表裏面を貫通する電極として貫通
電極２を形成しておき、これらのベアチップ１を積層す
ることにより貫通電極２を上下のベアチップ１との間で
も電気的に接続するようにしたものである。これによ
り、貫通電極２を通じて互いに電気的に接続された状態
で複数のベアチップ１を積層した構成としたものであ
る。また、同図（ｂ）に示すものでは、ベアチップ１の
側面に端面電極３を設けてベアチップ１を直接積層した
状態で端面電極３により互いに電気的に接続された状態
となるようにして形成したものである。[0004] For example, a configuration as shown in FIGS. 11A and 11B is disclosed. These are of the type formed by directly laminating bare chips as semiconductor elements. In FIG. 1A, a through electrode 2 is formed on each of a plurality of bare chips 1 as an electrode that penetrates the front and back surfaces, and these bare chips 1 are laminated to form a through electrode 2 on the upper and lower bare chips 1. Is also electrically connected between them. Thus, the plurality of bare chips 1 are stacked in a state where they are electrically connected to each other through the through electrodes 2. Further, in FIG. 1B, the end face electrodes 3 are provided on the side surfaces of the bare chip 1, and the bare chips 1 are formed in such a manner that they are directly connected to each other by the end face electrodes 3 in a state of being directly laminated. Things.

【０００５】一方、図１２に示すものは、ベアチップ１
を直接積層するのではなく、中継基板４を介して積層す
るようにしたものである。すなわち、ベアチップ１をそ
れぞれ中継基板４にフリップチップ実装したものを積層
する場合に、各層の中継基板４に形成した配線パターン
５間を電気的に接続すると共に層間距離を所定の間隔に
保持させるスペーサとしての機能を兼ね備えた柱状の層
間接続電極６により接続した状態で積層することにより
構成したものである。On the other hand, the one shown in FIG.
Are not laminated directly, but are laminated via the relay board 4. That is, when stacking the bare chips 1 each mounted on the relay substrate 4 by flip-chip bonding, a spacer for electrically connecting the wiring patterns 5 formed on the relay substrate 4 of each layer and maintaining the interlayer distance at a predetermined interval. Are stacked in a state where they are connected by a columnar interlayer connection electrode 6 which also has the function of

【０００６】上述のような積層型回路モジュールを形成
する場合に、それらのシステムを構成する回路の多く
は、複数のＩＣやＬＳＩを含む構成とされることが一般
的であり、その結果、搭載する半導体チップは異種、異
形のものが採用される場合が一般的な構成となる。した
がって、このような積層型回路モジュールを安価に提供
するためには、特殊な半導体チップではなく、その積層
回路型モジュールの仕様を満たす範囲内でできるだけ既
存のＩＣやＬＳＩを用いることや、複雑な実装プロセス
を使用しないということが製造工程上で要求される。When forming the above-mentioned stacked circuit modules, most of the circuits constituting those systems generally include a plurality of ICs and LSIs. In general, different types of semiconductor chips are used. Therefore, in order to provide such a laminated circuit module at low cost, it is necessary to use an existing IC or LSI as much as possible within a range satisfying the specifications of the laminated circuit module, instead of using a special semiconductor chip, It is required in the manufacturing process not to use a mounting process.

【０００７】また、既存のＩＣやＬＳＩの各半導体チッ
プに形成されている電極パッドは、ワイヤボンディング
により接続するものに対応して形成されているものが多
く、前述したような表裏面を貫通する特殊な電極２や端
面電極３などは必ずしも形成されているわけではない。
しかも、そのような半導体チップは、必ずしもウエハ状
態で入手できるとは限らないため、チップ状態で供給さ
れる場合にはそのような特殊な電極２や端面電極３を形
成するなどの追加工程を実施すること自体が非情に困難
な場合が発生してくる。In addition, many electrode pads formed on each semiconductor chip of existing ICs and LSIs are formed corresponding to those connected by wire bonding, and penetrate the front and back surfaces as described above. The special electrode 2 and the end face electrode 3 are not always formed.
In addition, since such a semiconductor chip is not always available in a wafer state, when supplied in a chip state, additional steps such as forming such special electrodes 2 and end electrodes 3 are performed. In some cases, it is extremely difficult to do it.

【０００８】以上の点から、このような従来の技術の範
囲では、積層型回路モジュールを小型化しようとする場
合に発生する不具合もしくは技術的課題として次のよう
な点があげられる。第１に、積層したチップ間の電気的
接続を、チップに貫通電極を形成したり端面電極を設け
て行なうので、チップ外形や電極レイアウトが同一なも
のにしか対応できなくなる不具合がある。[0008] From the above points, in the range of such conventional technology, the following problems are raised as problems or technical problems that occur when trying to reduce the size of the multilayer circuit module. First, since electrical connection between the stacked chips is performed by forming a through electrode or providing an end face electrode on the chip, there is a problem that only the same chip outer shape and electrode layout can be used.

【０００９】第２に、チップにそのような貫通電極や端
面電極を設ける構成自体が特殊な製造工程を必要とする
ものとなり、チップの製造工程が複雑化してしまう不具
合がある。第３に、実装プロセスにおいては、例えば貫
通電極を形成するなどウエハレベルでの処理が必要とな
るため、チップ状態で供給される場合には対応すること
ができなくなる不具合がある。Second, the configuration itself of providing such a penetrating electrode or end surface electrode on a chip requires a special manufacturing process, and there is a problem that the manufacturing process of the chip becomes complicated. Third, in the mounting process, processing at the wafer level is required, for example, by forming through electrodes, so that there is a problem that it is not possible to cope with the case where the semiconductor device is supplied in a chip state.

【００１０】一方、中継基板４となる回路基板にベアチ
ップ１を実装し、その中継基板４を積層していく方法で
は、異種・異形のベアチップへの適応が可能であるが、
この場合には次のような問題が生ずる。第１に、中継基
板４を用いる必要があるから、積層構造を形成する場合
にその中継基板４の板厚分だけ全体の高さ寸法が大きく
なり、実装可能な積層の層数に制約が生ずる。On the other hand, the method of mounting the bare chip 1 on a circuit board to be the relay board 4 and laminating the relay board 4 can be applied to different types and different shapes of bare chips.
In this case, the following problem occurs. First, since it is necessary to use the relay board 4, when forming a laminated structure, the overall height dimension is increased by the thickness of the relay board 4, and the number of stackable layers that can be mounted is restricted. .

【００１１】第２に、ベアチップのフリップチップ実装
を適用する場合（ワイヤーボンディングを用いると実装
サイズが大きくなる）、フリップチップ実装に対応した
高価な高密度配線基板が中継基板として必要になり、コ
ストが上昇してしまう。第３に、フリップチップ実装構
造を採用するために、ベアチップにバンプ電極を設けて
おく必要があり、前述と同様の技術的課題が発生する。Second, when the flip chip mounting of bare chips is applied (the mounting size is increased by using wire bonding), an expensive high-density wiring board corresponding to the flip chip mounting is required as a relay board, and the cost is reduced. Will rise. Third, in order to adopt the flip chip mounting structure, it is necessary to provide bump electrodes on the bare chip, and the same technical problem as described above occurs.

【００１２】本発明は、上記事情に鑑みてなされたもの
で、その目的は、半導体素子にバンプ電極の形成や層間
貫通電極形成などの特殊な加工工程を付加することな
く、異種・異形のチップを複数実装することができ、し
かも複数積層して回路モジュールを形成する場合でも中
継基板などを用いないで厚さ寸法を極力薄くすることが
でき、積層効率を高めることができるようにした半導体
素子の実装構造および積層型回路モジュールならびに半
導体素子の実装構造の製造方法を提供することにある。The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor device having a heterogeneous / irregular chip without adding a special processing step such as formation of a bump electrode or an interlayer through electrode. A semiconductor element that can be mounted in a plurality of layers, and even when a circuit module is formed by laminating a plurality of layers, the thickness dimension can be reduced as much as possible without using a relay board or the like, and the stacking efficiency can be increased. It is an object of the present invention to provide a mounting structure, a stacked circuit module, and a method of manufacturing a mounting structure of a semiconductor element.

【００１３】[0013]

【課題を解決するための手段】請求項１の発明によれ
ば、下地となる配線基板あるいは他の実装構造の上に電
気的に接続した半導体素子および層間接続電極を含んだ
状態に素子用絶縁層が形成されている構成としているの
で、その上部に直接上部配線基板を積層する構成とした
り、あるいは同じような構成の実装構造を積層すること
ができ、その場合でも、全体の高さ寸法を必要最小限に
することができる。そして、半導体素子を下地となる配
線基板の接続電極部に電気的に接続する構成であるから
半導体素子自体に特殊な加工を施す必要もなく、設計自
由度の高い実装構造を得ることができるようになる。ま
た、素子用絶縁層に層間接続電極を埋め込んた状態に形
成しているので、この上に直接他の半導体素子を実装す
ることができ、中継基板を必要としない構成で積層型の
構成とすることができる。According to the first aspect of the present invention, there is provided an insulating device for a device including a semiconductor device and an interlayer connecting electrode electrically connected to a wiring substrate or another mounting structure serving as a base. Since the layer is formed, the upper wiring board can be laminated directly on top of it, or a similar mounting structure can be laminated. It can be minimized. Further, since the semiconductor element is electrically connected to the connection electrode portion of the underlying wiring board, there is no need to perform special processing on the semiconductor element itself, so that a mounting structure with high design flexibility can be obtained. become. In addition, since the interlayer connection electrode is formed in a state in which the interlayer connection electrode is embedded in the element insulating layer, another semiconductor element can be directly mounted on the element connection layer. be able to.

【００１４】請求項２の発明によれば、上記請求項１の
発明の構成において、素子用絶縁層の上部に配線電極が
内部に形成された配線用絶縁層を積層した構成としてい
るので、配線用絶縁層の上部に設ける配線基板あるいは
他の実装構造などの配線パターンの位置と素子用絶縁層
中に形成している層間接続電極の位置とにずれがある場
合でも、配線用絶縁層を介在させることで簡単に接続す
ることができるようになる。この配線用絶縁層は、配線
電極を含む程度の厚さ寸法で形成できるので、配線基板
などの中継基板を設ける必要がなく、厚さ寸法を薄くし
た状態に形成することができる。According to a second aspect of the present invention, in the configuration of the first aspect of the present invention, a wiring insulating layer having a wiring electrode formed therein is laminated on the element insulating layer. Even if the position of the wiring pattern on the wiring board or other mounting structure provided on the insulating layer for the device and the position of the interlayer connection electrode formed in the insulating layer for the device are misaligned, the wiring insulating layer is interposed. By doing so, you can easily connect. Since the wiring insulating layer can be formed to have a thickness that includes the wiring electrodes, there is no need to provide a relay substrate such as a wiring substrate, and the wiring insulating layer can be formed in a reduced thickness.

【００１５】また、素子用絶縁層の表面に半導体素子の
裏面側が露出する場合でも配線用絶縁層によりこれを覆
うようにすることができ、上部に配置される配線基板や
他の実装構造に対して電気的な絶縁状態を保持すること
ができる。さらには、上部に配設する他の実装構造に使
用する半導体素子の実装に際して自由度の高い配線パタ
ーンを提供することもできる。Further, even when the back surface side of the semiconductor element is exposed on the surface of the element insulating layer, the semiconductor element can be covered with the wiring insulating layer, so that it can be mounted on a wiring board or other mounting structure disposed above. Thus, an electrical insulation state can be maintained. Further, it is possible to provide a wiring pattern having a high degree of freedom when mounting a semiconductor element used for another mounting structure provided on the upper part.

【００１６】請求項３の発明によれば、上下に配置され
る下地となる配線基板あるいは他の実装構造のうちの一
方に、その接続電極部に電気的に接続した半導体素子お
よび層間接続電極を含んだ状態に素子用絶縁層が形成さ
れている構成としているので、その上部に直接他方の配
線基板あるいは実装構造を積層する構成とすることがで
きる。そして、これによって、上下に配線基板を設ける
場合には、その配線基板の全面に渡って他の素子を実装
することが可能であり、素子用絶縁層内に実装している
半導体装置の占有面積に制約を受けることなく広い範囲
に高密度で実装する面積を得ることができるようにな
る。According to the third aspect of the present invention, the semiconductor element and the interlayer connection electrode electrically connected to the connection electrode portion are provided on one of the underlying wiring board and another mounting structure which are disposed vertically. Since the element insulating layer is formed in such a state, the other wiring board or the mounting structure can be directly stacked on the element insulating layer. In this way, when a wiring board is provided above and below, other elements can be mounted over the entire surface of the wiring board, and the occupied area of the semiconductor device mounted in the element insulating layer can be increased. Therefore, it is possible to obtain an area for high-density mounting over a wide range without any restrictions.

【００１７】請求項４の発明によれば、上下に配置され
る下地となる配線基板あるいは他の実装構造のうちの一
方に、その接続電極部に電気的に接続した半導体素子お
よび層間接続電極を含んだ状態に素子用絶縁層が形成さ
れると共に、配線電極を含んだ状態で配線用絶縁層が形
成された構成としているので、その上部に直接他方の配
線基板あるいは実装構造を積層する構成とすることがで
きる。これによって、上下に配線基板を設ける場合に
は、その配線基板の全面に渡って他の素子を実装するこ
とが可能であり、素子用絶縁層内に実装している半導体
装置の占有面積に制約を受けることなく広い範囲に高密
度で実装する面積を得ることができるようになる。According to the fourth aspect of the present invention, the semiconductor element and the interlayer connection electrode electrically connected to the connection electrode portion are provided on one of the underlying wiring board and another mounting structure arranged vertically. Since the element insulating layer is formed in a state including the wiring electrode and the wiring insulating layer is formed in a state including the wiring electrode, the other wiring board or the mounting structure is directly laminated on the upper part thereof. can do. Thus, when wiring substrates are provided above and below, other elements can be mounted over the entire surface of the wiring substrate, and the area occupied by the semiconductor device mounted in the element insulating layer is limited. Thus, it is possible to obtain a high-density mounting area in a wide range without receiving the light.

【００１８】また、この構成によって配線用絶縁層の上
部に設ける配線基板の配線パターンの位置と素子用絶縁
層中に形成している層間接続電極の位置とにずれがある
場合でも、配線用絶縁層を介在させることで簡単に接続
することができるようになる。この配線用絶縁層は、配
線電極を含む程度の厚さ寸法で形成できるので、配線基
板などの中継基板を設ける必要がなく、厚さ寸法を薄く
した状態に形成することができる。さらに、素子用絶縁
層の表面に半導体素子の裏面側が露出する場合でも配線
用絶縁層によりこれを覆うようにすることができ、上部
に配置される配線基板に対して電気的な絶縁状態を保持
することができる。Further, even if there is a deviation between the position of the wiring pattern of the wiring board provided above the insulating layer for wiring and the position of the interlayer connection electrode formed in the insulating layer for the device, the above structure can be used. The connection can be easily achieved by interposing the layer. Since the wiring insulating layer can be formed to have a thickness that includes the wiring electrodes, there is no need to provide a relay substrate such as a wiring substrate, and the wiring insulating layer can be formed in a reduced thickness. Furthermore, even when the back side of the semiconductor element is exposed on the surface of the element insulating layer, the semiconductor element can be covered with the wiring insulating layer, and the electrical insulation state is maintained with respect to the wiring board disposed above. can do.

【００１９】請求項５の発明によれば、請求項２または
４の発明において、配線用絶縁層を熱硬化性樹脂により
形成しているので、配線電極を埋め込み加工する場合に
作業性が良くなると共に、熱硬化処理をした後に研削な
どの処理をする際に加工性が向上する。According to the invention of claim 5, in the invention of claim 2 or 4, the workability is improved when the wiring electrode is embedded because the wiring insulating layer is formed of a thermosetting resin. At the same time, the workability is improved when performing a process such as grinding after the thermosetting process.

【００２０】請求項６の発明によれば、請求項１ないし
５の発明において、素子用絶縁層を熱硬化性樹脂により
形成しているので、半導体素子および層間接続電極を埋
め込み加工する場合に作業性が良くなると共に、熱硬化
処理をした後に研削などの処理をする際に加工性が向上
し、しかも、半導体素子の耐湿性を向上することができ
るなどの特性を得ることができる。According to the invention of claim 6, in the invention of claims 1 to 5, the insulating layer for the element is formed of a thermosetting resin. In addition to the improved properties, it is possible to obtain characteristics such as improved workability when performing a process such as grinding after the thermosetting process, and furthermore, it is possible to improve the moisture resistance of the semiconductor element.

【００２１】請求項７の発明によれば、請求項１ないし
６の発明において、半導体素子をベアチップとしてフリ
ップチップ実装する構成としているので、狭い面積でコ
ンパクトに実装でき、しかも、絶縁体で周囲を取り囲む
ようにするので、ベアチップの動作の信頼性の向上を図
ることもできる。According to the seventh aspect of the present invention, in the first to sixth aspects of the present invention, since the semiconductor element is flip-chip mounted as a bare chip, the semiconductor element can be mounted compactly in a small area, and the periphery can be surrounded by an insulator. Since it is surrounded, the reliability of the operation of the bare chip can be improved.

【００２２】請求項８の発明によれば、請求項７の発明
において、ベアチップをバンプ電極を介して下地に電気
的に接続するので、ベアチップ側あるいは下地の接続電
極部側のいずれかにあらかじめバンプ電極を形成してお
くことにより実装することができる。この場合、ベアチ
ップ側にバンプ電極を形成する後工程を付加することが
難しい場合でも、下地側にバンプ電極を形成することで
対応することができるので、製造工程が困難になること
はない。According to the invention of claim 8, in the invention of claim 7, since the bare chip is electrically connected to the base through the bump electrode, the bump is previously provided on either the bare chip side or the connection electrode portion side of the base. It can be mounted by forming electrodes. In this case, even if it is difficult to add a post-process for forming the bump electrode on the bare chip side, it is possible to cope with the problem by forming the bump electrode on the base side, so that the manufacturing process does not become difficult.

【００２３】請求項１１の発明によれば、下地としての
下部配線基板に、請求項１または２に記載の半導体素子
の実装構造が少なくとも１階層分形成され、この上に上
部配線基板の配線パターンが形成された部分を実装構造
の層間接続電極もしくは配線用電極と対向する状態で電
気的に接続して設ける構成としているので、上下に配設
する配線基板は、それらの表面に他の回路素子を実装す
る場合に全面に渡って使用することができるようにな
り、半導体素子の実装面積による制約を受けなくなるの
で、実装効率を高めたコンパクトな構成を実現すること
ができるようになる。According to the eleventh aspect of the present invention, the mounting structure of the semiconductor element according to the first or second aspect is formed on at least one layer on the lower wiring substrate as a base, and the wiring pattern of the upper wiring substrate is formed thereon. Is formed so as to be electrically connected in a state facing the interlayer connection electrode or the wiring electrode of the mounting structure, so that the wiring boards disposed vertically are provided with other circuit elements on their surfaces. Can be used over the entire surface when mounting, and there is no restriction due to the mounting area of the semiconductor element, so that a compact configuration with high mounting efficiency can be realized.

【００２４】請求項１２の発明によれば、上記請求項１
１の発明において、半導体素子の実装構造を２階層分以
上設ける構成の場合に、少なくとも上部配線基板と接す
る位置に形成される階層の半導体素子の実装構造を、そ
の上部配線基板を下地として形成しているので、これに
より、上下に配置する配線基板と素子用絶縁層との応力
などを緩和して全体として半導体素子が受ける応力を抑
制した構成とすることができるようになる。According to the twelfth aspect, the first aspect is provided.
In the invention of the first aspect, in the case where the mounting structure of the semiconductor element is provided for two or more layers, the mounting structure of the semiconductor element of the layer formed at least at a position in contact with the upper wiring board is formed using the upper wiring board as a base. Accordingly, it is possible to achieve a configuration in which the stress applied to the semiconductor element as a whole is suppressed by relaxing the stress and the like between the wiring substrate arranged vertically and the element insulating layer.

【００２５】請求項１３の発明によれば、素子実装工程
にて下地としての配線基板もしくは他の実装構造の上に
半導体素子を電気的に接続して固定し、層間接続電極形
成工程にて下地の上に層間接続電極を形成し、素子用絶
縁層形成工程にて層間接続電極および半導体素子を覆う
状態に絶縁体を配置形成し、この後、研削工程にて絶縁
体の下地と反対側の面を研削処理してその研削面に層間
接続電極を露出させた状態として素子用絶縁層を形成す
るので、下地に固定する半導体素子のサイズや種類など
に制約を受けることなく実装でき、しかも素子用絶縁層
に半導体素子を埋め込むようにして形成しているので、
この上部に配線基板もしくは他の実装構造を直接設ける
ことができ、全体の厚さ寸法を半導体素子の厚さ寸法程
度に抑制して実装効率を高めることができる。また、素
子実装工程の後に層間接続電極形成工程を実施するの
で、下地への半導体素子の実装の際に、下地に層間接続
電極がない状態で行なえるので、作業性が高いという利
点がある。According to the thirteenth aspect of the present invention, the semiconductor element is electrically connected and fixed on a wiring board or another mounting structure as a base in the element mounting step, and the base is formed in the interlayer connection electrode forming step. An interlayer connection electrode is formed thereon, and an insulator is arranged and formed so as to cover the interlayer connection electrode and the semiconductor element in a device insulating layer forming step. Since the element insulating layer is formed by grinding the surface and exposing the interlayer connection electrode on the ground surface, it can be mounted without being restricted by the size and type of the semiconductor element to be fixed on the underlayer. Since the semiconductor element is formed so as to be embedded in the insulating layer for
A wiring board or other mounting structure can be directly provided on this upper portion, and the total thickness dimension can be suppressed to about the thickness dimension of the semiconductor element, thereby increasing the mounting efficiency. Further, since the interlayer connection electrode forming step is performed after the element mounting step, the semiconductor element can be mounted on the base without the interlayer connection electrode on the base, so that there is an advantage that workability is high.

【００２６】請求項１４の発明によれば、上述の請求項
１３の発明の製造工程に対して、層間接続電極形成工程
を素子実装工程に先だって実施するようにしているの
で、例えば、半導体素子を実装する際に必要となるバン
プ電極などを下地側に形成する場合には層間接続電極の
形成と同時あるいは続いて実施することができ、また、
半導体素子を実装した状態で層間接続電極の形成が困難
となる場合などにおいては、このようにすることで確実
に製造することができるようになる。According to a fourteenth aspect of the present invention, the step of forming an interlayer connection electrode is performed prior to the element mounting step in the manufacturing step of the thirteenth aspect of the present invention. In the case where bump electrodes and the like required for mounting are formed on the base side, they can be performed simultaneously with or subsequent to the formation of interlayer connection electrodes.
In a case where it is difficult to form an interlayer connection electrode in a state where the semiconductor element is mounted, the manufacturing can be surely performed in this manner.

【００２７】請求項１５の発明によれば、上記請求項１
３および１４の発明において、研削工程を、半導体素子
も同時に研削しながら素子用絶縁層を形成するようにし
ているので、半導体素子としての実装時の厚さ寸法が完
成時の厚さ寸法よりも厚い状態で割れや欠けなどの発生
を防止しながら取り扱い易い状態で実装作業を行なうこ
とができ、この後絶縁層が周囲に充填された状態で研削
により必要な厚さ寸法まで調整することができ、薄く研
削する際に割れや欠けの発生を極力防止することができ
るようになる。According to the fifteenth aspect, the first aspect is provided.
In the inventions of 3 and 14, the grinding step is such that the element insulating layer is formed while simultaneously grinding the semiconductor element, so that the thickness dimension when mounted as a semiconductor element is smaller than the thickness dimension when completed. Mounting work can be performed in an easy-to-handle state while preventing the occurrence of cracks and chips in a thick state.After that, it can be adjusted to the required thickness by grinding with the insulating layer filled around. In addition, the occurrence of cracks and chips during thin grinding can be prevented as much as possible.

【００２８】請求項１６の発明によれば、請求項１３な
いし１５の発明において、配線用電極形成工程にて素子
用絶縁層の上に配線用電極を形成し、配線用絶縁層形成
工程にて配線用電極の一部を残した状態で他の部分を覆
うようにして絶縁体を充填して配線用絶縁層を形成する
ので、素子用絶縁層と上部に設ける層とを確実に絶縁し
た状態で配線用電極を設けることができ、半導体素子を
同時に研削している場合にもその面が配線用絶縁層によ
り覆うことができる。また、配線用電極を設けること
で、層間接続用電極では配置できない半導体素子の上部
側への配線を行なうことができるので、上部側に配設す
る配線基板あるいは他の実装構造との接続の自由度を高
めて設計性や実装性を高めることができるようになる。According to the invention of claim 16, in the invention of claims 13 to 15, the wiring electrode is formed on the element insulating layer in the wiring electrode forming step, and the wiring electrode is formed in the wiring insulating layer forming step. A state in which the insulating layer is formed by filling the insulator so as to cover the other part while leaving a part of the wiring electrode, so that the element insulating layer and the layer provided on the upper part are surely insulated. In this case, the wiring electrode can be provided, and even when the semiconductor element is simultaneously ground, its surface can be covered with the wiring insulating layer. Further, by providing the wiring electrode, wiring can be performed to the upper side of the semiconductor element which cannot be arranged by the interlayer connection electrode, so that the connection to the wiring board disposed on the upper side or another mounting structure can be freely performed. The degree of design can be increased to improve designability and mountability.

【００２９】請求項１７の発明によれば、上記した請求
項１６の発明において、配線用絶縁層形成工程を、絶縁
体としての熱硬化性樹脂を配線用電極の上から塗布する
樹脂塗布工程、塗布された樹脂面を平板により押しつぶ
して配線用電極の一部が露出する状態に処理する押圧処
理工程、熱硬化処理を行なって樹脂を硬化させる熱処理
工程、および平板を除去する平板除去工程を順次実施す
ることにより行なうようにしたので、素子用絶縁層の形
成の工程のように熱硬化処理を行なってから研削などの
処理により配線用電極の一部を露出させる方法と異な
り、工程を簡略化して迅速且つ安価に実施することがで
きるようになる。According to a seventeenth aspect of the present invention, in the above-mentioned sixteenth aspect, the wiring insulating layer forming step includes a resin application step of applying a thermosetting resin as an insulator from above the wiring electrode. A pressing step of crushing the applied resin surface with a flat plate to expose a part of the wiring electrode, a heat treatment step of performing a thermosetting treatment to cure the resin, and a flat plate removing step of removing the flat plate are sequentially performed. Unlike the method of performing a thermosetting treatment and then exposing a part of the wiring electrode by a process such as grinding as in the process of forming an insulating layer for an element, the process is simplified. And can be implemented quickly and inexpensively.

【００３０】請求項１８の発明によれば、請求項１６の
発明において、配線用絶縁層の上部に設ける層が配線基
板である場合に、配線用絶縁層形成工程を、絶縁体とし
ての熱硬化性樹脂を配線用電極の上から塗布する樹脂塗
布工程、塗布された樹脂面を配線基板により押しつぶし
て配線用電極の一部が露出する状態に処理する押圧処理
工程、および熱硬化処理を行なって硬化させる熱処理工
程により行なうので、配線基板を平板としてそのまま押
圧処理工程から熱処理工程に移行すれば実装構造を形成
でき、製造工程をより簡略化することができる。According to the eighteenth aspect of the present invention, in the case of the sixteenth aspect, when the layer provided on the wiring insulating layer is a wiring board, the step of forming the wiring insulating layer is performed by thermosetting as an insulator. A resin application step of applying a conductive resin from above the wiring electrodes, a pressing processing step of crushing the applied resin surface with a wiring board to expose a part of the wiring electrodes, and a thermosetting treatment. Since the hardening is performed by the heat treatment process, the mounting structure can be formed by shifting the pressing process from the pressing process to the heat treatment process using the wiring board as a flat plate, and the manufacturing process can be further simplified.

【００３１】請求項１９の発明によれば、請求項１６の
発明において、配線用絶縁層の上部に設ける層が他の半
導体素子の実装構造である場合に、配線用絶縁層形成工
程を、絶縁体としての熱硬化性樹脂を前記配線用電極の
上から塗布する樹脂塗布工程、塗布された樹脂面に他の
半導体素子の実装構造における素子用絶縁層の面を対向
させて押しつぶして配線用電極の一部が露出する状態に
処理する押圧処理工程、および熱硬化処理を行なって硬
化させる熱処理工程により行なうので、例えば、同様に
して下地上に形成した２つの半導体素子の実装構造の上
面同士を配線用絶縁層により接続することができ、配線
用絶縁層形成工程を１回少なくして形成することができ
ると共に、その配線用絶縁層を中心として両側に対称的
な配置とすることにより、応力による半導体素子への歪
みを緩和することができるようになる。According to the nineteenth aspect of the invention, in the invention of the sixteenth aspect, when the layer provided on the wiring insulating layer has a mounting structure of another semiconductor element, the step of forming the wiring insulating layer is performed by the insulating step. A resin application step of applying a thermosetting resin as a body from above the wiring electrode, and crushing the applied resin surface with the surface of the element insulating layer in the mounting structure of another semiconductor element facing the resin surface. Of the mounting structure of the two semiconductor elements formed on the base in the same manner, for example, by performing a pressing step of processing a part of the semiconductor element to be exposed and a heat-treating step of performing a heat-curing treatment and curing the same. It can be connected by the wiring insulating layer, can be formed by reducing the wiring insulating layer forming step once, and has a symmetrical arrangement on both sides around the wiring insulating layer. More, it is possible to relax the strain in the semiconductor element due to stress.

【００３２】請求項２０の発明によれば、請求項１３な
いし１９の発明において、素子実装工程で半導体素子を
下地の上に電気的に接続するときにバンプ電極が必要と
なる場合には、バンプ電極形成工程を素子実装工程より
も前に実施して下地の上にバンプ電極を形成するので、
バンプ電極が形成されていない半導体素子を実装する場
合に下地に形成したバンプ電極を介してフリップチップ
実装をすることができるようになり、半導体素子側への
バンプ電極形成の加工工程が不要となり、例えばチップ
状態で供給されるものであってもそのまま使用すること
ができ、実装する半導体素子に制約が少なくなり設計の
自由度を高めることができると共に、作業性を高めるこ
とができるようになる。According to a twentieth aspect of the present invention, in the invention of the thirteenth to nineteenth aspects, when a bump electrode is required when the semiconductor element is electrically connected to the base in the element mounting step, the bump electrode is required. Since the electrode forming step is performed before the element mounting step and the bump electrode is formed on the base,
When mounting a semiconductor element on which no bump electrode is formed, flip-chip mounting can be performed via the bump electrode formed on the base, and a processing step of forming a bump electrode on the semiconductor element side is not required. For example, even if supplied in the form of a chip, it can be used as it is, and the restrictions on the semiconductor element to be mounted are reduced, the degree of freedom in design can be increased, and the workability can be improved.

【００３３】請求項２１の発明によれば、上記請求項２
０の発明において、バンプ形成工程を、層間接続電極形
成工程の実施時にバンプ電極を同時に形成するので、工
程数を増やすことなく安価で且つ迅速にバンプ電極の形
成を行なうことができるようになる。According to the twenty-first aspect, the second aspect is provided.
In the invention of No. 0, since the bump electrode is formed simultaneously with the step of forming the interlayer connection electrode, the bump electrode can be formed inexpensively and quickly without increasing the number of steps.

【００３４】請求項２２の発明によれば、請求項１３な
いし２１の発明において、層間接続電極形成工程では、
層間接続電極をその形成面から上方に向けて錐状もしく
は錐台状に形成するので、断面が例えば円形状や四角形
状をなす形状の層間接続電極とした場合に、円錐状、円
錐台状あるいは角錐状、角錐台状として形成することに
なり、高さ寸法が底面の幅寸法に比べて大きくなる場合
でも倒れにくく座屈しにくい安定した状態に形成するこ
とができ、素子用樹脂層の形成工程において変形を防止
して精度良く上面側に露出させる構成とすることができ
る。According to a twenty-second aspect, in the thirteenth to twenty-first aspects, the step of forming an interlayer connection electrode includes the steps of:
Since the interlayer connection electrode is formed in the shape of a cone or a truncated cone facing upward from its formation surface, when the cross-section is an interlayer connection electrode having a circular or square shape, for example, a conical shape, a truncated conical shape or Since it is formed as a pyramid or a truncated pyramid, even when the height dimension is larger than the width dimension of the bottom surface, it can be formed in a stable state that it is hard to fall down and buckle, and the element resin layer forming step In such a case, it is possible to adopt a configuration in which deformation is prevented and the upper surface is accurately exposed.

【００３５】請求項２３の発明によれば、請求項１３な
いし２１の発明において、層間接続電極形成工程では、
下地の上に金属超微粒子を堆積させる方法により前記層
間接続電極を形成するので、めっきなどのウェットな処
理を用いないでドライな状態で層間接続電極を形成する
ことができ、半導体素子を実装した状態でも半導体素子
に悪影響を及ぼすことなく実施できる。このような金属
超微粒子を堆積させる方法としては、例えば、真空冶金
株式会社により開発されたＪＰＳ（Jet Printing Syste
m ；超微粒子による乾式直接描画法）がある。According to a twenty-third aspect of the present invention, in the thirteenth to twenty-first aspects, the step of forming an interlayer connection electrode comprises the steps of:
Since the interlayer connection electrode is formed by a method of depositing ultrafine metal particles on the base, the interlayer connection electrode can be formed in a dry state without using a wet process such as plating, and the semiconductor element is mounted. Even in the state, it can be implemented without adversely affecting the semiconductor element. As a method for depositing such metal ultrafine particles, for example, a JPS (Jet Printing System) developed by Vacuum Metallurgy Co., Ltd.
m; dry direct drawing method using ultrafine particles).

【００３６】また、層間接続電極の形成方法としては、
請求項２４の発明のように、下地の上にスタッドバンプ
を複数個積層形成する方法や、請求項２５の発明のよう
に、下地の上に金属ワイヤをボンディングにより立設す
る方法などがある。そして、配線用電極についても、同
様の方法にて形成することができる。The method for forming the interlayer connection electrode is as follows.
A twenty-fourth aspect of the present invention includes a method of laminating a plurality of stud bumps on an underlayer, and a twenty-fifth aspect of the present invention, in which a metal wire is erected on an underlayer by bonding. The wiring electrodes can be formed in the same manner.

【００３７】請求項２７の発明によれば、請求項２０な
いし２６の発明において、バンプ電極形成工程では、バ
ンプ電極を形成面から上方に向けて錐状もしくは錐台状
に形成しているので、請求項２２の発明と同様の効果を
得ることができる。According to the twenty-seventh aspect of the present invention, in the twentieth to twenty-sixth aspects, in the bump electrode forming step, the bump electrodes are formed in a conical shape or a truncated cone shape upward from the forming surface. The same effect as that of the twenty-second aspect can be obtained.

【００３８】また、バンプ電極の形成についても、請求
項２８の発明のように、金属微粒子を堆積させる方法で
形成したり、請求項２９の発明のように、スタッドバン
プを下地の表面に形成する方法で設けたり、あるいは請
求項３０の発明のように、導電性ペーストを印刷するこ
とにより設けることができる。Further, the bump electrodes are formed by a method of depositing fine metal particles, as in the twenty-eighth aspect of the present invention, or stud bumps are formed on the surface of the base, as in the twenty-ninth aspect of the present invention. It can be provided by a method or by printing a conductive paste as in the invention of claim 30.

【００３９】請求項３１の発明によれば、請求項１７な
いし３０の発明において、素子用絶縁層形成工程では、
素子用絶縁層として熱硬化性樹脂を用いる場合に、熱硬
化処理をその熱硬化性樹脂のガラス転移温度よりも低い
温度で行なうので、熱硬化性樹脂が軟化して変形するの
を抑制した状態で熱硬化処理を行なえ、内部に埋め込み
実装している半導体素子の実装状態に悪影響を及ぼすの
を防止しながら素子用絶縁層を形成することができる。According to a thirty-first aspect of the present invention, in any one of the seventeenth to thirty-third aspects, the step of forming the element insulating layer comprises
When a thermosetting resin is used as the element insulating layer, the thermosetting process is performed at a temperature lower than the glass transition temperature of the thermosetting resin, so that the thermosetting resin is prevented from being softened and deformed. In this case, a thermosetting treatment can be performed, and the element insulating layer can be formed while preventing the mounting state of the semiconductor element embedded and mounted therein from being adversely affected.

【００４０】[0040]

【発明の実施の形態】（第１の実施形態）以下、本発明
の第１の実施形態として、上下に配線基板を用いてその
間に半導体素子の実装構造を１階層分形成して回路モジ
ュールを構成した場合について図１ないし図４を参照し
ながら説明する。なお、この構成では、各配線基板の表
面には他のＩＣやディスクリート素子などの面実装部品
が実装されるようになっている。DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) Hereinafter, as a first embodiment of the present invention, a circuit module is formed by using a wiring board on the upper and lower sides and forming a mounting structure of a semiconductor element for one layer therebetween. The configuration will be described with reference to FIGS. In this configuration, surface mount components such as other ICs and discrete elements are mounted on the surface of each wiring board.

【００４１】本実施形態における半導体素子の実装構造
としての回路モジュール１１は、図２（ｃ）に示す模式
的な断面図のように構成されている。すなわち、回路モ
ジュール１１は、上下に配置する配線基板として多層配
線基板１２，１３を用い、これらの多層配線基板１２，
１３の間に本発明の基本構成であるところの半導体素子
の実装構造（以下、単に実装構造と称する）１４が形成
された構成である。以下、この構成について詳述すると
共に、その製造方法について説明する。The circuit module 11 as the mounting structure of the semiconductor device according to the present embodiment is configured as shown in a schematic cross-sectional view shown in FIG. That is, the circuit module 11 uses the multilayer wiring boards 12 and 13 as the wiring boards arranged vertically,
13 is a configuration in which a semiconductor element mounting structure (hereinafter simply referred to as a mounting structure) 14 which is a basic configuration of the present invention is formed. Hereinafter, this configuration will be described in detail, and a manufacturing method thereof will be described.

【００４２】２枚の多層配線基板１２，１３は、例え
ば、厚さ寸法がそれぞれ０．６〜０．８ｍｍ程度で、内
部には複数層の導体層が所定の配線パターンに形成さ
れ、表裏に露出している配線パターン１２ａ，１３ａに
接続されている。この実装構造１４は、素子用絶縁層と
しての第１層の樹脂層１５と配線用絶縁層としての第２
層の樹脂層１６との２層構造となっている。Each of the two multilayer wiring boards 12 and 13 has, for example, a thickness of about 0.6 to 0.8 mm, and has a plurality of conductor layers formed therein in a predetermined wiring pattern. It is connected to the exposed wiring patterns 12a and 13a. The mounting structure 14 includes a first resin layer 15 as an element insulating layer and a second resin layer 15 as a wiring insulating layer.
It has a two-layer structure with the resin layer 16 as a layer.

【００４３】第１層の樹脂層１５は、下地である多層配
線基板１２に形成されており、これには、ＩＣやＬＳＩ
などの集積回路が作りこまれた半導体素子としてのベア
チップ１７および層間接続電極１８が埋め込み形成され
ている。また、第２層の樹脂層１６には、その表裏に貫
通するように配線電極２１が埋め込み形成されている。
第１層の樹脂層１５の厚さ寸法は、例えば１００μｍ程
度に形成さてており、第２層の樹脂層１６の厚さ寸法は
例えば５０μｍ程度に形成されている。The first resin layer 15 is formed on the underlying multilayer wiring board 12, and includes an IC and an LSI.
A bare chip 17 and an interlayer connection electrode 18 as a semiconductor element in which an integrated circuit such as the above is formed are embedded. In the second resin layer 16, a wiring electrode 21 is buried so as to penetrate the front and back surfaces thereof.
The thickness of the first resin layer 15 is, for example, about 100 μm, and the thickness of the second resin layer 16 is, for example, about 50 μm.

【００４４】この第１層の樹脂層１５において、ベアチ
ップ１７は多層配線基板１２にフリップチップ実装され
ている。ベアチップ１７の固定は、多層配線基板１２側
に形成したバンプ電極１９を介して電気的に接続される
と共に、異方導電ペースト２０を用いて固定している。
また、層間接続電極１８は、第１層の樹脂層１５の表裏
を貫通するように形成されており、多層配線基板１２と
１３との間の電気的接続を行うように設けられている。In the first resin layer 15, the bare chip 17 is flip-chip mounted on the multilayer wiring board 12. The bare chip 17 is fixed electrically using a bump electrode 19 formed on the multilayer wiring board 12 side and is fixed using an anisotropic conductive paste 20.
Further, the interlayer connection electrode 18 is formed so as to penetrate the front and back of the first resin layer 15, and is provided so as to make an electrical connection between the multilayer wiring boards 12 and 13.

【００４５】なお、後述するように、第１層の樹脂層１
５の上面は、研削によりベアチップ１７と層間接続電極
１８とが露出するようにして所定厚さ寸法まで除去され
た結果、平坦な面として形成されている。したがって、
ベアチップ１７の裏面の半導体部分が露出した状態とな
っている。As will be described later, the first resin layer 1
The upper surface of 5 is formed as a flat surface as a result of removing the bare chip 17 and the interlayer connection electrode 18 to a predetermined thickness dimension by grinding so as to be exposed. Therefore,
The semiconductor portion on the back surface of the bare chip 17 is exposed.

【００４６】次に、第２層の樹脂層１６において、配線
電極２１は、第２層の樹脂層１６の表裏を貫通するよう
に形成されており、第１層の樹脂層１５の表面に露出し
ている層間接続電極１８と上部に配置される多層配線基
板１３との間を電気的に接続するように配設されてい
る。Next, in the second resin layer 16, the wiring electrodes 21 are formed so as to penetrate the front and back of the second resin layer 16, and are exposed on the surface of the first resin layer 15. It is arranged so as to electrically connect between the inter-layer connection electrode 18 and the multilayer wiring board 13 arranged thereon.

【００４７】上述のように構成された回路モジュール１
１は、実装構造１５を２枚の多層配線基板１２，１３で
挟んだ状態の構造に形成され、その厚さ寸法は、例えば
１．５ｍｍ前後として得ることができる。そして、この
回路モジュール１１には、その下面側１１ａおよび上面
側１１ｂのそれぞれに、内部の実装構造１５には実装す
ることができない他のＩＣやディスクリート素子などの
面実装部品が実装される。The circuit module 1 configured as described above
1 is formed in a structure in which the mounting structure 15 is sandwiched between two multilayer wiring boards 12 and 13, and its thickness dimension can be obtained, for example, about 1.5 mm. In the circuit module 11, surface mounting components such as other ICs and discrete elements which cannot be mounted on the internal mounting structure 15 are mounted on the lower surface 11a and the upper surface 11b, respectively.

【００４８】上述のように構成しているので、ベアチッ
プ１７が実装されている部分が回路モジュール１１の表
面に露出しない構成とすることができ、ディスクリート
部品を実装する面積を回路モジュール１１の基板面全面
を利用して行えるようになり、全体の実装効率を高める
ことができると共に、設計の自由度を高めることができ
るようになる。With the above configuration, the portion where the bare chip 17 is mounted is not exposed on the surface of the circuit module 11, and the area for mounting the discrete components is reduced by the surface area of the substrate of the circuit module 11. The entire surface can be used, so that the overall mounting efficiency can be improved and the degree of freedom in design can be increased.

【００４９】次に、上記した回路モジュール１１の製造
方法について、図３の工程フロー図および図１、図２の
各工程における断面構造図ならびに図４を参照しながら
説明する。図３に示す工程フロー図では、半導体素子の
実装構造１４の概略的な製造工程について示している。Next, a method of manufacturing the above-described circuit module 11 will be described with reference to the process flow chart of FIG. 3, the cross-sectional structure diagram in each of the steps of FIGS. 1 and 2, and FIG. The process flow diagram shown in FIG. 3 shows a schematic manufacturing process of the semiconductor element mounting structure 14.

【００５０】なお、回路モジュール１１の製造において
は、例えば複数個を一度に製造することができるよう
に、多層配線基板１２，１３が複数個分（例えば６個
分）の回路モジュール１１の大きさに形成されており、
出来上がったものをダイシングなどの方法で切り離して
最終的に回路モジュール１１として得る。In the manufacture of the circuit module 11, the size of the circuit module 11 having a plurality of (for example, six) multilayer wiring boards 12 and 13 is set so that a plurality of the circuit modules 11 can be manufactured at a time. Is formed in,
The completed product is separated by a method such as dicing to finally obtain a circuit module 11.

【００５１】以下の説明では、図３の工程フロー図にし
たがって、１個分の回路モジュール１１の製造工程を次
の７つの工程に分けて述べる。（１）下地準備工程Ｓ
１、（２）層間接続電極形成工程Ｓ２、（３）チップ実
装工程Ｓ３、（４）第１層の樹脂層形成工程Ｓ４、
（５）研削工程Ｓ５、（６）配線電極形成工程Ｓ６、
（７）第２層の樹脂層形成工程Ｓ７である。In the following description, the manufacturing process of one circuit module 11 will be divided into the following seven processes according to the process flow chart of FIG. (1) Base preparation step S
1, (2) interlayer connection electrode forming step S2, (3) chip mounting step S3, (4) first resin layer forming step S4,
(5) grinding step S5, (6) wiring electrode forming step S6,
(7) Second resin layer forming step S7.

【００５２】（１）下地準備工程Ｓ１ まず回路モジュール１１を形成するための下地として用
いる多層配線基板１２、１３を準備する。多層配線基板
１２は、片面をベアチップ１７をフリップチップ実装す
るのに対応した配線パターンにレイアウトし、その裏面
（下面側）には、入出力電極パッドやディスクリート部
品実装用パッドなどを配した配線パターンにレイアウト
し、内部の配線用導体パターン層を介して接続する。同
様に、多層配線基板１３についてもその表裏に必要な配
線パターンを形成すると共に、内部の配線用導体パター
ン層を介して接続する。(1) Base preparation step S1 First, multilayer wiring boards 12 and 13 to be used as bases for forming the circuit module 11 are prepared. The multilayer wiring board 12 has one surface laid out in a wiring pattern corresponding to the flip chip mounting of the bare chip 17, and a wiring pattern in which input / output electrode pads and pads for mounting discrete components are arranged on the back surface (lower surface side). And connected via an internal wiring conductor pattern layer. Similarly, with respect to the multilayer wiring board 13 as well, necessary wiring patterns are formed on the front and back, and the connection is made via the internal wiring conductor pattern layer.

【００５３】（２）層間接続電極形成工程Ｓ２ 次に、多層配線基板１２上に層間接続電極１８およびバ
ンプ電極１９を形成する。これらの電極１８および１９
は、ここでは後述するＪＰＳ法（Jet PrintingSystem
；金属超微粒子を用いてパターンを直猫する方法）
で、多層配線基板１２の上面にＡｕ（金）を電極材料と
して形成する。(2) Interlayer Connection Electrode Forming Step S2 Next, an interlayer connection electrode 18 and a bump electrode 19 are formed on the multilayer wiring board 12. These electrodes 18 and 19
Is a JPS method (Jet Printing System
A method of straightening a pattern using ultrafine metal particles)
Then, Au (gold) is formed on the upper surface of the multilayer wiring board 12 as an electrode material.

【００５４】ここで、形成する層間接続電極１８の高さ
寸法は、例えば１００μｍ以上で２００μｍ以下の範囲
程度に設定し、バンプ電極１９の高さ寸法は、例えば２
０μｍから１００μｍの範囲程度に設定している。ま
た、形成する層間接続電極１８およびバンプ電極１９は
いずれも円錐状もしくは円錐台状となるように堆積させ
る条件を調整して形成している。Here, the height of the interlayer connection electrode 18 to be formed is set, for example, in the range of 100 μm or more and 200 μm or less, and the height of the bump electrode 19 is, for example, 2 μm.
The thickness is set in the range of about 0 μm to 100 μm. The interlayer connection electrode 18 and the bump electrode 19 to be formed are formed by adjusting the conditions for deposition so as to have a conical shape or a truncated conical shape.

【００５５】次に、ＪＰＳ法について、図４を参照して
簡単に説明する。図はＪＰＳ法による金属超微粒子の直
接描画をする装置の概略的構成を示している。装置の構
成は成膜室３１と超微粒子生成室３２とに分けられてお
り、それらの間に金属超微粒子を搬送する搬送管３３が
連結されている。Next, the JPS method will be briefly described with reference to FIG. The figure shows a schematic configuration of an apparatus for directly drawing ultrafine metal particles by the JPS method. The configuration of the apparatus is divided into a film forming chamber 31 and an ultrafine particle generation chamber 32, and a transport pipe 33 for transporting ultrafine metal particles is connected between them.

【００５６】成膜室３１および超微粒子生成室３２には
排気用の配管３４が接続されており、内部を減圧するた
めのロータリーポンプ（ＲＰ）３５およびメカニカル・
ブースター・ポンプ（ＭＢＰ）３６が接続されている。
この場合、成膜室３１は、例えば内部を１３．３Ｐａ
（０．１ｔｏｒｒ）程度まで減圧して電極形成を行うよ
うになっている。また、超微粒子生成室３２は、例えば
内部を２気圧程度まで加圧した状態に保持して金属超微
粒子を生成する。このため、超微粒子生成室３２は、Ｈ
ｅなどの不活性ガスを充填して加圧するようにガス供給
用の配管３７が接続されている（Ｈｅガス流量は、例え
ば１分あたり４０リットルである）。An exhaust pipe 34 is connected to the film forming chamber 31 and the ultra-fine particle generating chamber 32, and a rotary pump (RP) 35 for reducing the pressure inside and a mechanical pump
A booster pump (MBP) 36 is connected.
In this case, the inside of the film forming chamber 31 is, for example, 13.3 Pa.
The pressure is reduced to about (0.1 torr) to form an electrode. The ultra-fine particle generation chamber 32 generates metal ultra-fine particles while keeping the inside thereof pressurized to about 2 atm, for example. For this reason, the ultrafine particle generation chamber 32
A gas supply pipe 37 is connected so as to fill and pressurize with an inert gas such as e (the He gas flow rate is, for example, 40 liters per minute).

【００５７】さて、成膜室３１には、電極形成の試料を
載置するためのＸＹステージ３８が配設されており、電
極形成時に面内をＸＹ方向に移動可能であり、また軸方
向（Ｚ方向）にも移動可能に構成され、内部にはヒータ
を備えていて所定の基板温度に設定することができる。
このＸＹステージ３８には、搬送管３３の先端のノズル
３３ａが例えば４００μｍ程度の距離で対向するように
配置されている。ノズル３３ａの径は例えば１００μｍ
程度である。An XY stage 38 for mounting a sample on which an electrode is to be formed is provided in the film forming chamber 31. The XY stage 38 can be moved in the XY direction in the plane when the electrode is formed, and can be moved in the axial direction ( (Z direction), and has a heater inside to set a predetermined substrate temperature.
On the XY stage 38, a nozzle 33a at the tip of the transport pipe 33 is disposed so as to face the distance of, for example, about 400 μm. The diameter of the nozzle 33a is, for example, 100 μm
It is about.

【００５８】超微粒子生成室３２においては、電極材料
であるＡｕを溶融するためのルツボ３９が加熱装置３９
ａにより１５００〜１６００℃の範囲（例えば、１５５
０℃）で加熱可能に設けられている。ここで加熱されて
蒸発したＡｕは搬送管３１を通じて減圧された成膜室３
１側に流入して、減圧されることで超微粒子となってノ
ズル３３ａから圧力差により噴出し、ＸＹステージ３８
に載置された試料の表面に付着して堆積する。In the ultrafine particle generation chamber 32, a crucible 39 for melting Au as an electrode material is provided with a heating device 39.
a range from 1500 to 1600 ° C. (for example, 155
0 ° C.). Here, Au evaporated by heating is formed in the film forming chamber 3 under reduced pressure through the transfer pipe 31.
The XY stage 38 flows into the XY stage 38 by being decompressed into ultra-fine particles, which are ejected from the nozzle 33a due to a pressure difference.
Adheres to and accumulates on the surface of the sample placed on the substrate.

【００５９】なお、ノズル３３ａは、図示しないヒータ
により例えば３００℃程度に加熱されている。この装置
においては、上記構成および条件を採用することによ
り、例えば、描画速度３〜１０ｍｍ／秒で堆積速度は１
０μｍ／秒程度である。また、ＸＹステージ３８の位置
決め精度は±２μｍ程度である。上述のＪＰＳ法による
層間接続電極１８およびバンプ電極１９の形成は、すべ
てドライプロセスとして実施できるので、前処理や後処
理などの工程が全体として簡単にすることができる。The nozzle 33a is heated to, for example, about 300 ° C. by a heater (not shown). In this apparatus, by adopting the above configuration and conditions, for example, the drawing speed is 3 to 10 mm / sec and the deposition speed is 1
It is about 0 μm / sec. The positioning accuracy of the XY stage 38 is about ± 2 μm. Since the formation of the interlayer connection electrodes 18 and the bump electrodes 19 by the above-described JPS method can be all performed as a dry process, the steps such as pre-processing and post-processing can be simplified as a whole.

【００６０】（３）チップ実装工程Ｓ３ 次に、図１（ｂ）に示すように、ベアチップ１７を多層
配線基板１２に実装する。ここで、バンプ電極１９はＡ
ｕ（金）であるからはんだリフロー処理はできなので、
フリップチップ実装するには、例えば異方性導電ペース
ト２０を用いて行う。多層配線基板１２のベアチップ１
７を実装する部分に異方導伝ペースト２０を塗布して載
置する。この状態で１個のバンプ電極１９あたり数百〜
千数百ｍＮ（ミリニュートン）の力を加えながら加熱し
て、異方導電ペースト２０を熱硬化させる。硬化温度
は、例えば１２０℃〜１４０℃としている。(3) Chip Mounting Step S3 Next, as shown in FIG. 1B, the bare chip 17 is mounted on the multilayer wiring board 12. Here, the bump electrode 19 is A
Since it is u (gold), solder reflow processing can be performed.
Flip chip mounting is performed using, for example, an anisotropic conductive paste 20. Bare chip 1 of multilayer wiring board 12
7. Anisotropic conductive paste 20 is applied to the portion where 7 is to be mounted and placed. In this state, several hundreds to
Heating is performed while applying a force of a thousand and several hundred mN (millinewton) to thermally cure the anisotropic conductive paste 20. The curing temperature is, for example, 120C to 140C.

【００６１】なお、ベアチップ１７の厚さ寸法は、例え
ば１５ｃｍ径のウエハなどのものでは３００μｍ〜６０
０μｍ程度の厚さであり、チップ状態で供給される場合
に、薄くとも３００μｍ程度であるのが一般的である。
また、ウエハ状態での厚さが比較的厚いものでも、チッ
プに切断する前に研削して薄くする場合もある。The thickness of the bare chip 17 is, for example, 300 μm to 60 μm for a wafer having a diameter of 15 cm.
The thickness is about 0 μm, and when supplied in a chip state, it is generally at least about 300 μm.
Further, even if the thickness is relatively large in a wafer state, it may be thinned by grinding before cutting into chips.

【００６２】（４）第１層の樹脂層形成工程Ｓ４ 次に、図１（ｃ）に示すように、フリップチップ実装し
たベアチップ１７と層間接続電極１８とを熱硬化性樹脂
４０で埋め込んで第１層の樹脂層１５を形成する。層間
接続電極１８が形成されている面に、エポキシ系の熱硬
化性樹脂４０を塗布し、例えば、１２０〜１４０℃の範
囲の熱処理温度で熱硬化させる。この場合、塗布作業
は、エポキシ系熱硬化性樹脂４０がベアチップ１７や層
間接続電極１８を完全に覆うようにして行う。(4) First Layer Resin Layer Forming Step S4 Next, as shown in FIG. 1 (c), the bare chip 17 and the interlayer connection electrode 18 mounted on the flip chip are embedded with a thermosetting resin 40 to form a first resin layer. One resin layer 15 is formed. An epoxy-based thermosetting resin 40 is applied to the surface on which the interlayer connection electrodes 18 are formed, and is thermoset at a heat treatment temperature in the range of, for example, 120 to 140 ° C. In this case, the coating operation is performed such that the epoxy-based thermosetting resin 40 completely covers the bare chip 17 and the interlayer connection electrode 18.

【００６３】エポキシ系熱硬化性樹脂４０の選択は、一
連の製造工程中の加圧・加熱などの処理に対して十分な
耐性を持つものを基準とする。なお、この実施形態にお
いては、エポキシ系熱硬化性樹脂４０として、ガラス転
移温度が１４０℃以上の材料を用いており、ガラス転移
温度以下の温度で熱硬化処理を行っている。The selection of the epoxy-based thermosetting resin 40 is based on a resin having sufficient resistance to treatments such as pressure and heating during a series of manufacturing steps. In this embodiment, a material having a glass transition temperature of 140 ° C. or higher is used as the epoxy thermosetting resin 40, and the thermosetting treatment is performed at a temperature lower than the glass transition temperature.

【００６４】これにより、エポキシ系熱硬化性樹脂４０
が熱硬化する際に、軟化して塑性変形したり、ベアチッ
プ１７に予想外の応力を与えるのを防止できる。また、
熱硬化処理の処理時間は、処理温度に依存するが、例え
ば数分から２０分程度の範囲で設定する。この熱処理温
度と熱処理時間との関係は、温度を高く設定することで
短時間にできるが、ベアチップ１７に与える応力も大き
くなることが予想されるため、それらのことを考慮した
上で、適切な温度と時間に設定することが必要となる。Thus, the epoxy thermosetting resin 40
When thermally hardened, it is possible to prevent softening and plastic deformation and unexpected stress on the bare chip 17. Also,
The processing time of the thermosetting treatment depends on the processing temperature, but is set, for example, in a range from several minutes to about 20 minutes. The relationship between the heat treatment temperature and the heat treatment time can be shortened by setting the temperature high, but it is expected that the stress applied to the bare chip 17 will also increase. It is necessary to set the temperature and time.

【００６５】（５）研削工程Ｓ５ 次に、図１（ｄ）に示すように、ベアチップ１７と層間
接続電極１８を埋め込んだ樹脂層４０を研削して第１層
の樹脂層１５を形成する。ここでは、研削機械を用いて
樹脂層４０を表面から研削してゆき、ベアチップ１７と
層間接続電極１８が露出した後、ベアチップ１７の厚み
が１００μｍ程度になるまで研削する。このとき同時に
層間接続電極１８も研削しており、初期的に形成した高
さ寸法に比べて低い高さとなる。(5) Grinding Step S5 Next, as shown in FIG. 1D, the resin layer 40 in which the bare chip 17 and the interlayer connection electrode 18 are embedded is ground to form the first resin layer 15. Here, the resin layer 40 is ground from the surface using a grinding machine, and after the bare chip 17 and the interlayer connection electrode 18 are exposed, grinding is performed until the thickness of the bare chip 17 becomes about 100 μm. At this time, the interlayer connection electrode 18 is also ground at the same time, and the height becomes lower than the height dimension initially formed.

【００６６】研削後の樹脂層４０表面には、ベアチップ
１７の背面と層間接続電極１８が露出した状態となる。
これにより、樹脂層４０の表裏面を貫通する層間接続電
極１８を形成できると共に、ベアチップ１７を埋め込ん
だ第１層の樹脂層１５を形成できる。なお、ベアチップ
１７の厚さ寸法が薄いもの（例えば１００μｍ程度の厚
さ寸法）として実装工程Ｓ４で実装している場合には、
層間接続電極１８のみを露出させた状態となることもあ
る。The back surface of the bare chip 17 and the interlayer connection electrode 18 are exposed on the surface of the resin layer 40 after the grinding.
Thereby, the interlayer connection electrode 18 penetrating the front and back surfaces of the resin layer 40 can be formed, and the first resin layer 15 in which the bare chip 17 is embedded can be formed. When the bare chip 17 is mounted in the mounting step S4 as a thin one (for example, a thickness of about 100 μm),
In some cases, only the interlayer connection electrode 18 is exposed.

【００６７】（６）配線電極形成工程Ｓ６ 次に、図２（ａ）に示すように、第１層の樹脂層１５の
表面に配線用電極２１を形成する。ここでは、研削した
第１層の樹脂層１５の層間接続電極１８の露出部分に配
線電極２１として多層配線基板１３と接続するための柱
状電極２１ａと引き回し配線２１ｂを前述同様のＪＰＳ
法で形成する。(6) Wiring Electrode Forming Step S6 Next, as shown in FIG. 2A, a wiring electrode 21 is formed on the surface of the first resin layer 15. Here, the columnar electrode 21a for connecting to the multilayer wiring board 13 as the wiring electrode 21 and the lead-out wiring 21b are formed on the ground exposed portion of the interlayer resin electrode 15 of the first resin layer 15 by the same JPS as described above.
It is formed by a method.

【００６８】配線電極２１の高さ寸法は、柱状部分のア
スペクト比が１以下となるように設定することが望まし
い。これは、後工程で配線電極２１部分を加圧する際
に、倒れたり座屈するのを防止するためである。なお、
この実施形態においては、高さ寸法を４０〜６０μｍ範
囲で設定している。It is desirable that the height dimension of the wiring electrode 21 is set so that the aspect ratio of the columnar portion is 1 or less. This is to prevent the wiring electrode 21 from falling down or buckling when being pressed in a later step. In addition,
In this embodiment, the height is set in the range of 40 to 60 μm.

【００６９】（７）第２層の樹脂層形成工程Ｓ７ 続いて、図２（ｂ）に示すように、配線電極２１を埋め
込んで第２層の樹脂層１６を形成する。研削した第１層
の樹脂層１５の表面上の配線電極２１を覆うようにエポ
キシ系熱硬化性樹脂４１を塗布し、他方の多層配線基板
１３で挟むようにして配線電極２１を押しつぶす。(7) Second Layer Resin Layer Forming Step S7 Subsequently, as shown in FIG. 2B, the second layer resin layer 16 is formed by embedding the wiring electrodes 21. An epoxy-based thermosetting resin 41 is applied so as to cover the wiring electrode 21 on the surface of the ground first resin layer 15, and the wiring electrode 21 is crushed so as to be sandwiched by the other multilayer wiring board 13.

【００７０】多層配線基板１３には、配線電極２１にあ
たる部分にあらかじめ接続用の電極パッドが形成されて
いるので、押しつぶしの処理を進めると配線電極２１と
電気的に接触するようになる。ここで、配線電極２１に
加える力は、配線電極の１個の柱状電極２１ａあたり１
Ｎ（ニュートン）程度とした。Since the connection electrode pad is formed in advance on the multilayer wiring board 13 at a portion corresponding to the wiring electrode 21, the crushing process proceeds to make electrical contact with the wiring electrode 21. Here, the force applied to the wiring electrode 21 is one per columnar electrode 21a of the wiring electrode.
It was about N (Newton).

【００７１】この際、研削した第１層の樹脂層１５表面
と多層配線基板１３の間に、熱硬化性樹脂４１が十分に
回りこんで隅々まで充填されるようにする。この状態
で、加熱しエポキシ系熱硬化性樹脂４１を硬化させる。
硬化温度は、１２０〜１４０℃程度とする。なお、加圧
・加熱の処理は、フリップチップボンダーを用いて同時
に行っている。At this time, the space between the ground surface of the resin layer 15 of the first layer and the multilayer wiring board 13 is sufficiently filled with the thermosetting resin 41 so as to be filled in every corner. In this state, the epoxy-based thermosetting resin 41 is cured by heating.
The curing temperature is about 120 to 140C. Note that the pressurizing and heating processes are performed simultaneously using a flip chip bonder.

【００７２】これにより、第２層の樹脂層１６は、多層
配線基板１３と密着した状態で、且つ電気的に接続され
た状態として形成され、図２（ｃ）に示すような構成の
回路モジュール１１を得ることができる。なお、上述の
製造工程では、フリップチップボンダーを用いているの
で、多層配線基板１３を樹脂層４１の面に載置する際
に、平行性、加圧機能および加熱機能を兼ね備えている
ことから処理工程を簡単且つ迅速に行うことができる。As a result, the second resin layer 16 is formed in a state in which the second resin layer 16 is in close contact with the multilayer wiring board 13 and is electrically connected thereto, and the circuit module having the structure as shown in FIG. 11 can be obtained. In the above-described manufacturing process, since the flip-chip bonder is used, when the multilayer wiring board 13 is mounted on the surface of the resin layer 41, it has a parallelism, a pressing function, and a heating function. The process can be performed simply and quickly.

【００７３】以上の工程Ｓ１〜Ｓ７を経ることにより、
２枚の多層配線基板１２，１３に、ベアチップ１７が埋
め込まれた第１層の樹脂層１５と配線電極２１が埋め込
まれた第２層の樹脂層１６が積層形成され、各樹脂層１
５，１６の間および多層配線基板１２，１３の間は、層
間接続電極１８および配線電極の柱状電極２１ａで接続
された構造として得ることができる。By going through the above steps S1 to S7,
A first resin layer 15 having a bare chip 17 embedded therein and a second resin layer 16 having a wiring electrode 21 embedded therein are laminated on two multilayer wiring boards 12 and 13.
5 and 16, and between the multilayer wiring boards 12 and 13 can be obtained as a structure connected by the interlayer connection electrode 18 and the columnar electrode 21a of the wiring electrode.

【００７４】この後、前述のように、ダイシング工程な
どを経て１個ずつの回路モジュール１１に分割し、最後
に多層配線基板１２，１３上に他の半導体素子やディス
クリート部品等の面実装部品を実装配置して回路モジュ
ール１１が完成する。Thereafter, as described above, the circuit module 11 is divided into individual circuit modules 11 through a dicing process and the like. Finally, other semiconductor elements and surface mount components such as discrete components are mounted on the multilayer wiring boards 12 and 13. The circuit module 11 is completed by mounting and arrangement.

【００７５】このような第１の実施形態によれば、上述
のようにして回路モジュール１１を構成するとともに製
造するので、全体構成として薄くコンパクトに形成で
き、しかも、基板表面に半導体素子の実装部分がなくな
るのでディスクリート部品の実装面積を最大にとること
ができ、実装密度の高い回路モジュール１１を得ること
ができる。According to the first embodiment, since the circuit module 11 is constructed and manufactured as described above, it can be formed thin and compact as a whole, and the mounting portion of the semiconductor element is mounted on the substrate surface. Therefore, the mounting area of the discrete components can be maximized, and the circuit module 11 having a high mounting density can be obtained.

【００７６】また、電極形成にＪＰＳ法を用いるので、
電極形成をドライ処理で簡単且つ迅速に寸法精度の良い
電極形成をすることができる。また、第１層の樹脂層１
５に層間接続電極１８を設けて接続するようにしている
ので、層間接続のためにビアの形成や埋込などの工程が
不要となりプロセスを簡素化することができる。Since the JPS method is used for forming the electrodes,
Electrodes can be formed easily and quickly with good dimensional accuracy by dry processing. Also, the first resin layer 1
Since the connection is provided by providing the interlayer connection electrode 18 in the step 5, processes such as formation and embedding of vias for interlayer connection become unnecessary, and the process can be simplified.

【００７７】さらに、第２層の樹脂層１６を設けて配線
電極２１を配設するので配線の自由度を高めて最適な配
線を行うことができる。第１層の樹脂層１５の形成過程
でベアチップ１７を同時に研削することができ、所望の
厚さ寸法にできる。このとき、ベアチップ１７はエポキ
シ系熱硬化性樹脂４０に埋め込まれた状態であるから、
チップの欠けや割れが発生するのを防止できる。そし
て、全体を樹脂層で埋め込む構成とするので、強度の点
で優れる。Furthermore, since the second layer of the resin layer 16 is provided and the wiring electrodes 21 are provided, the degree of freedom of wiring can be increased and optimum wiring can be performed. The bare chip 17 can be ground at the same time in the process of forming the first resin layer 15 and can have a desired thickness. At this time, since the bare chip 17 is embedded in the epoxy-based thermosetting resin 40,
Chips and cracks can be prevented from occurring. Since the entire structure is embedded in the resin layer, the strength is excellent.

【００７８】さらに、ベアチップボンダーを用いて多層
配線基板１３を実装構造１４に押圧、加熱する第２層の
樹脂層形成工程Ｓ７を実施するので、平坦性を精度良く
出しながら押しつぶしおよび加熱処理を迅速且つ簡単に
行える。Furthermore, since the second-layer resin layer forming step S7 of pressing and heating the multilayer wiring board 13 against the mounting structure 14 by using a bare chip bonder is performed, the crushing and the heat treatment can be rapidly performed while the flatness is accurately obtained. And easy to do.

【００７９】（第２の実施形態）図５ないし図７は、本
発明の第２の実施形態を示すもので、第１の実施形態と
異なるところは、実装構造体１４を２階層分形成した構
成としてさらに実装密度を向上させた積層型回路モジュ
ール５１に適用したところである。(Second Embodiment) FIGS. 5 to 7 show a second embodiment of the present invention. The difference from the first embodiment is that the mounting structure 14 is formed in two layers. The configuration has been applied to a laminated circuit module 51 whose mounting density has been further improved.

【００８０】図７（ｃ）は、積層型回路モジュール５１
の断面構成を示すもので、第１の実施形態における回路
モジュール１１の構成で、実装構造１４と上部側の多層
配線基板１３との間に新たに半導体素子の実装構造５２
を形成した構成である。この実装構造５２は、実装構造
１４とほぼ同等の構造を有しており、素子用絶縁層とし
ての第１層の樹脂層５３および配線用絶縁層としての第
２層の樹脂層５４が積層された構成である。FIG. 7C shows the laminated circuit module 51.
In the configuration of the circuit module 11 in the first embodiment, a semiconductor element mounting structure 52 is newly provided between the mounting structure 14 and the multilayer wiring board 13 on the upper side.
Is formed. The mounting structure 52 has substantially the same structure as the mounting structure 14, and a first resin layer 53 as an element insulating layer and a second resin layer 54 as a wiring insulating layer are laminated. Configuration.

【００８１】第１層の樹脂層５３には、実装構造１４の
上面に形成された層間接続用電極５５および配線パター
ン５６で接続されたバンプ電極５７が埋め込まれている
と共に、バンプ電極５７に異方性導電ペースト５８で固
定された半導体素子としてのベアチップ５９が埋め込み
形成されている。第２層の樹脂層５５には、配線電極６
０が埋め込み形成されている。層間接続電極５５および
配線電極６０は共に樹脂層５３および５５を貫通するよ
うに形成されており、層間の電気的な接続をしている。In the first resin layer 53, an interlayer connection electrode 55 formed on the upper surface of the mounting structure 14 and a bump electrode 57 connected by a wiring pattern 56 are buried. A bare chip 59 as a semiconductor element fixed by an isotropic conductive paste 58 is embedded and formed. The second resin layer 55 has a wiring electrode 6
0 is buried. Both the interlayer connection electrode 55 and the wiring electrode 60 are formed so as to penetrate the resin layers 53 and 55, and make electrical connection between the layers.

【００８２】そして、この上側に積層されている実装構
造５２の上面つまり、第２層の樹脂層５４の上に多層配
線基板１３が対向するようにして固定配置され、その配
線パターンは配線電極６０と電気的に接続され、２階層
分の実装構造が積層された積層型回路モジュール５１が
形成されている。The multilayer wiring board 13 is fixedly arranged on the upper surface of the mounting structure 52 laminated on the upper side, that is, on the second resin layer 54 so as to face the wiring layer 60. Are electrically connected to each other to form a stacked circuit module 51 in which two layers of mounting structures are stacked.

【００８３】次に、この積層型回路モジュール５１の製
造方法について簡単に説明する。なお、この第２の実施
形態における製造工程では、基本的には第１の実施形態
の製造工程と同じことを繰り返すことにより実装構造５
２を形成している。Next, a method of manufacturing the laminated circuit module 51 will be briefly described. In the manufacturing process according to the second embodiment, the mounting structure 5 is basically repeated by repeating the same process as the manufacturing process according to the first embodiment.
2 are formed.

【００８４】（１）配線電極形成工程Ｓ６ すなわち、図５（ａ）において、第１の実施形態と同様
にベアチップ１７と層間接続電極１８を埋め込んだ第１
層の樹脂層１５を多層配線基板１２上に形成する。更
に、第１の樹脂層１５の上に配線電極２１として柱状電
極２１ａと配線パターン２１ｂを形成する（第１の実施
形態の図２（ａ）に相当）。(1) Wiring Electrode Forming Step S6 That is, in FIG. 5A, as in the first embodiment, the first chip having the bare chip 17 and the interlayer connection electrode 18 embedded therein is formed.
A resin layer 15 is formed on the multilayer wiring board 12. Further, columnar electrodes 21a and wiring patterns 21b are formed as the wiring electrodes 21 on the first resin layer 15 (corresponding to FIG. 2A of the first embodiment).

【００８５】（２）第２層の樹脂層形成工程Ｓ７ この後、以下の工程を実施することにより実装構造５２
を形成する。まず、配線用絶縁層である第２層の樹脂層
１６を形成すべく、配線電極２１が形成された面を覆う
ようにエポキシ系熱硬化性樹脂４１を塗布する。次に、
離型材６１ａを塗布した平板ガラス６１を用意する。平
板ガラス６１は、平面度、平行度が優れたものが望まし
い。加圧時の変形をさける為、１ｍｍ程度の板厚を用い
ている。また離型材６１ａは、シリコン系の高耐熱のも
のを使用している。これは例えば鋳造で用いる離型材の
ようなものを用いる。(2) Second Layer Resin Layer Forming Step S7 Thereafter, the following steps are carried out to obtain the mounting structure 52
To form First, an epoxy-based thermosetting resin 41 is applied so as to cover the surface on which the wiring electrodes 21 are formed in order to form the second resin layer 16 which is a wiring insulating layer. next,
A flat glass 61 coated with a release material 61a is prepared. The flat glass 61 desirably has excellent flatness and parallelism. A plate thickness of about 1 mm is used to prevent deformation during pressurization. As the release material 61a, a silicon-based material having high heat resistance is used. This uses, for example, a release material used in casting.

【００８６】この平板ガラス６１で、図５（ｃ）に示す
ように、エポキシ系熱硬化性樹脂４１で覆われた配線電
極２１を押しつぶす。配線電極２１に加える力は、１個
の柱状電極２１ａあたり１Ｎ程度とした。この際、研削
した第１層の樹脂層１５の表面と平板ガラス６１の間
に、熱硬化性樹脂４１が充填されるようにする。この状
態で、加熱しエポキシ系熱硬化性樹脂４１を硬化させ、
第２の樹脂層１６を形成する。このときの熱硬化温度
は、１２０〜１４０℃程度とする。As shown in FIG. 5C, the wiring electrodes 21 covered with the epoxy thermosetting resin 41 are crushed by the flat glass 61. The force applied to the wiring electrode 21 was about 1 N per one columnar electrode 21a. At this time, the space between the ground surface of the first resin layer 15 and the flat glass 61 is filled with the thermosetting resin 41. In this state, heating is performed to cure the epoxy-based thermosetting resin 41,
The second resin layer 16 is formed. The thermosetting temperature at this time is about 120 to 140 ° C.

【００８７】第２層の樹脂層１６が硬化した後、同図
（ｄ）に示すように、平板ガラス６１を剥離する。剥離
後の樹脂層１６の表面には、配線電極２１の柱状電極２
１ａが露出する。なお、回路レイアウト上、更に配線電
極の積層が必要な場合には、図示はしないが、この樹脂
層の上に層間接続用柱状電極と配線を形成し、上記手法
で樹脂層で埋め込みを行うことで必要な配線電極のパタ
ーンを形成することができる。After the second resin layer 16 has hardened, the flat glass 61 is peeled off as shown in FIG. The columnar electrode 2 of the wiring electrode 21 is provided on the surface of the resin layer 16 after peeling.
1a is exposed. In the case where further lamination of wiring electrodes is required on the circuit layout, although not shown, a columnar electrode for interlayer connection and wiring are formed on this resin layer, and embedded in the resin layer by the above method. Thus, a necessary wiring electrode pattern can be formed.

【００８８】（３）層間接続電極形成工程Ｓ２ 次に、実装構造５２を形成すべく、図６（ａ）に示すよ
うに、層間接続電極５５、配線パターン５６およびバン
プ電極５７の形成を行う。これは、前述と同様にしてＪ
ＰＳ法を用いてＡｕ（金）を所定形状に堆積形成し、所
定寸法の円錐状をなす層間接続電極５５およびバンプ電
極５７と配線パターン５６を形成する。なお、この場合
には、実装構造１４の場合と異なり、多層配線基板１２
に形成しているような配線パターン５６も同時に形成す
る。(3) Interlayer Connection Electrode Forming Step S2 Next, in order to form the mounting structure 52, as shown in FIG. 6A, an interlayer connection electrode 55, a wiring pattern 56 and a bump electrode 57 are formed. This is similar to J
Au (gold) is deposited and formed in a predetermined shape using the PS method, and a conical interlayer connection electrode 55 and a bump electrode 57 having a predetermined size and a wiring pattern 56 are formed. In this case, unlike the case of the mounting structure 14, the multilayer wiring board 12
Is formed at the same time.

【００８９】（４）チップ実装工程Ｓ３ 次に、図６（ｂ）に示すように、ベアチップ５９を実装
する。前述と同様にして、ベアチップ５９をフェイスダ
ウンでバンプ電極５７と対向させた状態として異方性導
電ペースト５８により接着し、熱硬化処理をして固定す
る。(4) Chip Mounting Step S3 Next, as shown in FIG. 6B, a bare chip 59 is mounted. In the same manner as described above, the bare chip 59 is bonded face-down to the bump electrode 57 with an anisotropic conductive paste 58, and is fixed by a thermosetting treatment.

【００９０】（５）第１層の樹脂層形成工程Ｓ４ さらに、実施例１でベアチップの埋め込みを行ったのと
同様の方法で、同図（ｃ）に示すように、ベアチップ５
９をエポキシ系熱硬化樹脂６２で埋め込み、前述と同様
の熱処理条件にて熱硬化処理を行う。(5) First Resin Layer Forming Step S4 Further, in the same manner as in the case of embedding the bare chip in the first embodiment, as shown in FIG.
9 is buried in an epoxy-based thermosetting resin 62, and a thermosetting process is performed under the same heat treatment conditions as described above.

【００９１】（６）研削工程Ｓ５ 続いて、図７（ａ）に示すように、熱硬化された樹脂層
６２をベアチップ５９および層間接続電極５５と共に研
削し、層間接続電極５５を樹脂層６２の表面に露出させ
た状態とする。これにより、ベアチップ５９および層間
接続電極５５が埋め込まれた第１層の樹脂層５３が形成
される。(6) Grinding Step S5 Subsequently, as shown in FIG. 7A, the thermosetting resin layer 62 is ground together with the bare chip 59 and the interlayer connection electrode 55, and the interlayer connection electrode 55 is The surface is exposed. Thus, the first resin layer 53 in which the bare chip 59 and the interlayer connection electrode 55 are embedded is formed.

【００９２】（７）配線電極形成工程Ｓ６，第２層の樹
脂層形成工程Ｓ７ この後、前述同様にして配線電極形成工程Ｓ６を実施し
て、同図（ｂ）に示すように、配線電極６０をＪＰＳ法
により形成する。さらに、この上からエポキシ系熱硬化
性樹脂を塗布して多層配線基板１３により押しつぶしを
しながら熱処理を行って熱硬化させ、第２層の樹脂層５
４を形成する。(7) Wiring electrode forming step S6, second resin layer forming step S7 Thereafter, a wiring electrode forming step S6 is performed in the same manner as described above, and as shown in FIG. 60 is formed by the JPS method. Further, an epoxy-based thermosetting resin is applied from above and heat-treated while being crushed by the multilayer wiring board 13 to be thermoset, and the second resin layer 5 is formed.
4 is formed.

【００９３】以上により、実装構造１４および５２の２
階層分積層した構造の基板を形成することができる。こ
の後、前述同様にして、ディスクリート部品が多層配線
基板１２，１３の表裏面に面実装され、積層型回路モジ
ュール５１として形成することができる。As described above, 2 of mounting structures 14 and 52
A substrate having a structure in which layers are stacked in layers can be formed. Thereafter, the discrete components are surface-mounted on the front and back surfaces of the multilayer wiring boards 12 and 13 in the same manner as described above, and can be formed as the multilayer circuit module 51.

【００９４】このような、第２の実施形態によれば、２
階層分の半導体素子の実装構造１４および５２を積層形
成することで、中継基板などを用いないで厚さ寸法を薄
くして多層に形成することができ、実装効率を高めたも
のとすることができる。According to such a second embodiment, 2
By stacking the mounting structures 14 and 52 of the semiconductor element for the layer, the thickness can be reduced and the multilayer can be formed without using a relay board or the like, and the mounting efficiency can be improved. it can.

【００９５】なお、上記の実施形態では、実装構造１
４，５２の２階層分として積層型回路モジュール５１を
構成したが、さらに多層に実装構造を形成して積層型回
路モジュールを構成することもできる。この場合には、
上述した工程を繰り返し実施することで実装構造を積層
形成することができる。In the above embodiment, the mounting structure 1
Although the stacked circuit module 51 is configured as two layers of layers 4 and 52, a stacked circuit module may be formed by further forming a mounting structure in multiple layers. In this case,
By repeatedly performing the above-described steps, a stacked structure can be formed.

【００９６】（第３の実施形態）図８は、本発明の第３
の実施形態を示すもので、第２の実施形態と異なるとこ
ろは、多層配線基板１２，１３のそれぞれに実装構造１
４，５２を積層形成し、これらの上面側を対向するよう
にして接続固定し４層の実装構造を設ける構成の積層型
回路モジュール６３を形成したところである。(Third Embodiment) FIG. 8 shows a third embodiment of the present invention.
This embodiment is different from the second embodiment in that the mounting structure 1 is mounted on each of the multilayer wiring boards 12 and 13.
The stacked circuit module 63 has a structure in which the upper and lower sides of the circuit modules 4 and 52 are stacked and connected so that their upper surfaces are opposed to each other, and a four-layer mounting structure is provided.

【００９７】同図（ｂ）はその断面構成を示すもので、
積層型回路モジュール６３は、第２の実施形態において
図７（ａ）で示した構造のものを、多層配線基板１２お
よび１３のそれぞれに形成し、これらの第１の樹脂層５
３を対向させた状態でそれらの間に第２層の樹脂層５４
を共通の層として介在させるように接合した構成であ
る。FIG. 13B shows the cross-sectional structure.
In the multilayer circuit module 63, the structure shown in FIG. 7A in the second embodiment is formed on each of the multilayer wiring boards 12 and 13, and these first resin layers 5 are formed.
3 with the second resin layer 54 therebetween.
Are bonded so as to be interposed as a common layer.

【００９８】この場合、多層配線基板１２，１３に形成
する実装構造１４，５２などの積層階層数を増やし、ト
ータルの層厚が厚くなっていくと、積層した樹脂層の内
部応力によって多層配線基板１２，１３に反りが生じる
ことがある。この内部応力は、主に熱硬化性樹脂が硬化
する際の体積収縮と、多層配線基板と熱硬化性樹脂との
熱膨張係数の差に起因して発生する。In this case, the number of stacked layers such as the mounting structures 14 and 52 formed on the multilayer wiring substrates 12 and 13 is increased, and as the total layer thickness increases, the internal stress of the laminated resin layers causes 12 and 13 may be warped. The internal stress is mainly generated due to a volume shrinkage when the thermosetting resin is cured and a difference in thermal expansion coefficient between the multilayer wiring board and the thermosetting resin.

【００９９】この様に、多層配線基板１２，１３に反り
が発生する場合には、積層工程を実施する際のアライメ
ント作業が困難になる。この実施形態においては、その
ような多数の実装構造を形成する場合の反りを防止しな
がら行えるようにしており、以下簡単にその構造と製造
方法について説明する。As described above, when the multilayer wiring boards 12 and 13 are warped, it becomes difficult to perform the alignment work when performing the laminating step. In the present embodiment, such a large number of mounting structures can be formed while preventing warpage, and the structure and the manufacturing method will be briefly described below.

【０１００】第２の実施形態と同様の手法で多層配線基
板１２，１３のそれぞれに、ベアチップ１７，５９と層
間接続電極がそれぞれ埋め込み形成された実装構造１４
および第１層の樹脂層５３が形成された状態（図７
（ａ）の構成に相当）のものを形成する。The mounting structure 14 in which the bare chips 17 and 59 and the interlayer connection electrodes are embedded in the multilayer wiring boards 12 and 13 respectively in the same manner as in the second embodiment.
And a state where the first resin layer 53 is formed (FIG. 7).
(Corresponding to the configuration of (a)).

【０１０１】このとき、各多層配線基板１２，１３に形
成した実装構造１４，５２の全体の厚さ寸法をほぼ等し
く設定しておくことが望ましい。そして、上側の多層配
線基板１３側の第１層の樹脂層５３の表面に、層間接続
電極５５が露出した状態とされている（図８（ａ）参
照）。また、下側の多層配線基板１２の第１層の樹脂層
５３の上には、層間接続電極５５の上に、必要に応じて
引き回し配線電極６０が形成される（同図（ｂ）参
照）。この配線電極６０は、同じくＪＰＳ法で形成す
る。At this time, it is desirable that the entire thickness of the mounting structures 14 and 52 formed on the multilayer wiring boards 12 and 13 be set substantially equal. Then, the interlayer connection electrode 55 is exposed on the surface of the first resin layer 53 on the upper multilayer wiring board 13 side (see FIG. 8A). In addition, on the first resin layer 53 of the lower multilayer wiring substrate 12, a lead-out wiring electrode 60 is formed on the interlayer connection electrode 55 as necessary (see FIG. 2B). . This wiring electrode 60 is similarly formed by the JPS method.

【０１０２】次に多層配線基板１２，１３を相互の電気
的接続がとれるよう、層間接続電極５５と引き回し配線
電極６０とが適切な位置にくるようにアライメントし、
エポキシ系熱硬化性樹脂６４を介して張り合わせすると
共に、熱硬化処理を行うことで積層回路モジュール６３
を形成する。基板同士を張り合わせる際には、電極１個
あたり１Ｎ程度の荷重を加えて配線電極６０を押しつぶ
し、この後エポキシ系熱硬化性樹脂６４を熱硬化させ
る。Next, the multi-layered wiring boards 12 and 13 are aligned such that the interlayer connection electrode 55 and the lead-out wiring electrode 60 are located at appropriate positions so that mutual electrical connection can be obtained.
The laminated circuit module 63 is bonded through an epoxy-based thermosetting resin 64 and subjected to a thermosetting process.
To form When the substrates are bonded to each other, a load of about 1N is applied to each electrode to crush the wiring electrode 60, and then the epoxy-based thermosetting resin 64 is thermoset.

【０１０３】この様に、各配線基板に配線基板の反りが
発生しない範囲内で複数の実装構造を積層形成した後、
積層構造を形成した面同士を張り合わせることで、積層
階層数が多い積層回路モジュールに関しても多層配線基
板に反りを生じさせることなく形成することができる。As described above, after a plurality of mounting structures are laminated and formed on each wiring board within a range where warpage of the wiring board does not occur,
By laminating the surfaces on which the laminated structure is formed, even a laminated circuit module having a large number of laminated layers can be formed without warping the multilayer wiring board.

【０１０４】（第４の実施形態）図９は、本発明の第４
の実施形態を示すもので、上記各実施形態と異なるとこ
ろは、層間接続電極１８に変えて層間接続電極６５を形
成する場合の形成方法である。第１ないし第３の実施形
態においては、層間接続電極１８などはＪＰＳ法を用い
て形成する場合について説明した。(Fourth Embodiment) FIG. 9 shows a fourth embodiment of the present invention.
This embodiment is different from the above embodiments in a method of forming an interlayer connection electrode 65 in place of the interlayer connection electrode 18. In the first to third embodiments, the case where the interlayer connection electrode 18 and the like are formed by using the JPS method has been described.

【０１０５】ここでは、図９（ａ）に示した、バンプ電
極１９が形成された多層配線基板１２上に、ベアチップ
１７をフリップチップ実装し、この後、ワイヤボンディ
ングの技術を利用して金属ワイヤを垂直に形成して層間
接続電極６５を形成する。Here, the bare chip 17 is flip-chip mounted on the multilayer wiring board 12 on which the bump electrodes 19 are formed as shown in FIG. 9A, and thereafter, the metal wires are formed by using a wire bonding technique. Are formed vertically to form an interlayer connection electrode 65.

【０１０６】これにより、バンプ電極１９と同時に形成
する必要がないので、フリップチップ実装時には層間接
続電極６５が形成されていない状態で行え、作業性が向
上するようになる。なお、このように層間接続電極６５
の形成を行うことで作業工程の自由度を高めることがで
きるが、前述同様に、フリップチップ実装工程の前に層
間接続電極６５を形成することもできる。Thus, since it is not necessary to form the bump electrodes 19 at the same time, the flip-chip mounting can be performed in a state where the interlayer connection electrodes 65 are not formed, and the workability is improved. Note that, as described above, the interlayer connection electrode 65
In this case, the degree of freedom of the working process can be increased, but the interlayer connection electrode 65 can be formed before the flip-chip mounting process as described above.

【０１０７】このような第４の実施形態によれば、層間
接続電極６５の形成を既存の設備を用いて簡単に行なえ
ると共に、バンプ電極の形成とは別の工程で実施できる
ので、製造工程の自由度を高めることができると共に、
フリップチップ実装の作業性の向上を図るようにするこ
ともできる。According to the fourth embodiment, the formation of the interlayer connection electrode 65 can be easily performed using existing equipment, and can be performed in a step different from the formation of the bump electrode. Can increase the degree of freedom,
It is also possible to improve the workability of flip chip mounting.

【０１０８】（第５の実施形態）図１０は本発明の第５
の実施形態を示すもので、第４の実施形態と異なるとこ
ろは、同じく層間接続電極１８に代えて設ける層間接続
電極６６の形成方法である。この層間接続電極６６は、
ボールボンダーを用いたスタッドバンプ６６ａを例えば
３個積層して形成した例である。(Fifth Embodiment) FIG. 10 shows a fifth embodiment of the present invention.
This embodiment is different from the fourth embodiment in a method of forming an interlayer connection electrode 66 provided in place of the interlayer connection electrode 18. This interlayer connection electrode 66
This is an example in which three stud bumps 66a using a ball bonder are stacked, for example.

【０１０９】この第５の実施形態によっても第４の実施
形態と同様の作用効果を得ることができると共に、既存
の設備を用いて簡単且つ安価に形成することができるよ
うになる。According to the fifth embodiment, the same functions and effects as those of the fourth embodiment can be obtained, and the device can be formed easily and inexpensively using existing equipment.

【０１１０】本発明は、上記実施形態にのみ限定される
ものではなく、次のように変形また拡張できる。層間接
続電極、配線電極やバンプ電極は、Ａｕ（金）の代わり
にＣｕ（銅）やＡｌ（アルミニウム）など他の金属を用
いることもできる。The present invention is not limited to the above embodiment, but can be modified or expanded as follows. Other metals such as Cu (copper) and Al (aluminum) can be used for the interlayer connection electrode, the wiring electrode, and the bump electrode instead of Au (gold).

【０１１１】第２層の樹脂層を形成する際に、平板など
による押しつぶし処理を行なう代わりに、熱硬化処理を
行なった樹脂層を研削することにより第２層の樹脂層１
６を形成しても良い。When forming the second resin layer, instead of crushing with a flat plate or the like, the second resin layer is ground by grinding the heat-cured resin layer.
6 may be formed.

【０１１２】第１層の樹脂層１５と第２層の樹脂層１６
とは、同じ樹脂を用いてもよいし、異なる種類の樹脂を
用いても良い。それらの選択は、応力の関係や親和性あ
るいは電気的特性などの様々な観点から最適なものを用
いることができる。The first resin layer 15 and the second resin layer 16
The same means that the same resin may be used or different kinds of resins may be used. For their selection, optimal ones can be used from various viewpoints such as the relationship of stress, affinity, and electrical characteristics.

【０１１３】また、図示していないがフリップチップ用
のバンプ電極も、スタッドバンプや導電ペーストを印刷
法を用いて円錐状に形成した電極で代用することも可能
である。Although not shown, a bump electrode for a flip chip may be replaced with a stud bump or an electrode formed of a conductive paste in a conical shape by using a printing method.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の第１の実施形態を示す処理工程に対応
した模式的断面図（その１）FIG. 1 is a schematic cross-sectional view corresponding to a processing step according to a first embodiment of the present invention (part 1).

【図２】処理工程に対応した模式的断面図（その２）FIG. 2 is a schematic cross-sectional view corresponding to a processing step (part 2).

【図３】工程フロー図FIG. 3 is a process flow diagram.

【図４】電極形成用装置の原理説明図FIG. 4 is a diagram illustrating the principle of an electrode forming apparatus.

【図５】本発明の第２の実施形態を示す処理工程に対応
した模式的断面図（その１）FIG. 5 is a schematic cross-sectional view corresponding to a processing step according to a second embodiment of the present invention (part 1).

【図６】処理工程に対応した模式的断面図（その２）FIG. 6 is a schematic cross-sectional view corresponding to a processing step (part 2).

【図７】処理工程に対応した模式的断面図（その３）FIG. 7 is a schematic cross-sectional view corresponding to a processing step (part 3).

【図８】本発明の第３の実施形態を示す処理工程に対応
した模式的断面図FIG. 8 is a schematic cross-sectional view corresponding to a processing step according to a third embodiment of the present invention.

【図９】本発明の第４の実施形態を示す処理工程に対応
した模式的断面図FIG. 9 is a schematic cross-sectional view corresponding to a processing step according to a fourth embodiment of the present invention.

【図１０】本発明の第５の実施形態を示す処理工程に対
応した模式的断面図FIG. 10 is a schematic sectional view corresponding to a processing step showing a fifth embodiment of the present invention.

【図１１】従来例を示す模式的断面図FIG. 11 is a schematic sectional view showing a conventional example.

【図１２】異なる従来例を示す模式的断面図FIG. 12 is a schematic sectional view showing a different conventional example.

【符号の説明】[Explanation of symbols]

１１は回路モジュール、１２は多層配線基板（下地、配
線基板）、１３は多層配線基板（配線基板）、１４，５
２は半導体素子の実装構造、１５，５３は第１層の樹脂
層（素子用絶縁層）、１６，５４は第２層の樹脂層（配
線用絶縁層）、１７，５９はベアチップ（半導体素
子）、１８，５５，６５，６６は層間接続電極、１９，
５７はバンプ電極、２０，５８は異方性導電ペースト、
２１，６０は配線電極、３１は成膜室、３２は超微粒子
生成室、３３は搬送管、３３ａはノズル、３８はＸＹス
テージ、３９はるつぼ、４０，４１，６２，６４はエポ
キシ系熱硬化性樹脂、５１，６３は積層回路モジュー
ル、６１はガラス板、６１ａは離型材である。11 is a circuit module, 12 is a multilayer wiring board (base, wiring board), 13 is a multilayer wiring board (wiring board), 14, 5
2 is a semiconductor element mounting structure, 15 and 53 are first resin layers (insulating layers for elements), 16 and 54 are second resin layers (insulating layers for wiring), and 17 and 59 are bare chips (semiconductor elements). ), 18, 55, 65 and 66 are interlayer connection electrodes;
57 is a bump electrode, 20 and 58 are anisotropic conductive pastes,
21 and 60 are wiring electrodes, 31 is a film formation chamber, 32 is an ultrafine particle generation chamber, 33 is a transport tube, 33a is a nozzle, 38 is an XY stage, 39 is a crucible, and 40, 41, 62, and 64 are epoxy thermosettings. The conductive resin, 51 and 63 are laminated circuit modules, 61 is a glass plate, and 61a is a release material.

Claims (31)

【特許請求の範囲】[Claims] 【請求項１】 下地となる配線基板もしくは他の実装構
造の上に積層形成する半導体素子の実装構造において、 前記下地の接続電極部に電気的に接続した状態で固定さ
れる半導体素子と、 この半導体素子の少なくとも側面周囲を包囲するように
絶縁体で充填するように形成された素子用絶縁層と、 この素子用絶縁層中を貫通した状態に形成され前記下地
側とその反対の面側との間を電気的に導通させる層間接
続電極とを備えたことを特徴とする半導体素子の実装構
造。1. A mounting structure of a semiconductor element laminated and formed on a wiring substrate or another mounting structure serving as a base, wherein the semiconductor element is fixed in a state of being electrically connected to the connection electrode portion of the base. An element insulating layer formed so as to be filled with an insulator so as to surround at least the side surface periphery of the semiconductor element; and the base side and the opposite side formed so as to penetrate through the element insulating layer. And an interlayer connection electrode for electrically connecting between them. 【請求項２】 請求項１に記載の半導体素子の実装構造
において、 前記素子用絶縁層の上部に積層形成された配線用絶縁層
と、 この配線用絶縁層中を貫通して前記素子絶縁層側の前記
層間接続電極とその反対の面側とに電気的に導通可能な
配線電極とを備えたことを特徴とする半導体素子の実装
構造。2. The mounting structure of a semiconductor device according to claim 1, wherein the wiring insulating layer is formed on the device insulating layer, and the element insulating layer penetrates through the wiring insulating layer. A semiconductor device mounting structure, comprising: an inter-layer connection electrode on one side; and a wiring electrode that can be electrically connected to the opposite surface side. 【請求項３】 上下に配置される下地としての配線基板
もしくは他の実装構造の間に形成される半導体素子の実
装構造において、 前記下地の接続電極部に電気的に接続した状態で固定さ
れる半導体素子と、 この半導体素子の少なくとも側面周囲を包囲するように
絶縁体で充填するように形成された素子用絶縁層と、 この素子用絶縁層中を貫通した状態に形成され前記下地
側とその反対の面側との間を電気的に導通させる層間接
続電極とを備えたことを特徴とする半導体素子の実装構
造。3. A mounting structure of a semiconductor element formed between a wiring board or another mounting structure as a base disposed vertically, and fixed in a state of being electrically connected to the connection electrode portion of the base. A semiconductor element; an element insulating layer formed so as to be filled with an insulator so as to surround at least a side surface of the semiconductor element; and the base side formed through the element insulating layer so as to penetrate the element insulating layer. A mounting structure for a semiconductor element, comprising: an interlayer connection electrode for electrically connecting an opposite surface side. 【請求項４】 上下に配置される下地としての配線基板
もしくは他の実装構造の間に形成される半導体素子の実
装構造において、 前記下地の接続電極部に電気的に接続した状態で固定さ
れる半導体素子と、 この半導体素子の側面周囲を包囲するように絶縁体で充
填するように形成された素子用絶縁層と、 この素子用絶縁層中を貫通した状態に形成され前記下地
側とその反対の面側との間を電気的に導通させる層間接
続電極と、 前記素子用絶縁層の上部に積層形成された配線用絶縁層
と、 この配線用絶縁層中を貫通して前記素子絶縁層側の前記
層間接続電極とその反対の面側とに電気的に導通可能な
配線電極とを備えたことを特徴とする半導体素子の実装
構造。4. In a mounting structure of a semiconductor element formed between a wiring board or another mounting structure as a base arranged vertically, the semiconductor element is fixed in a state of being electrically connected to the connection electrode portion of the base. A semiconductor element; an element insulating layer formed to be filled with an insulator so as to surround the periphery of a side surface of the semiconductor element; and an underlayer formed opposite to the base side and formed in a state penetrating the element insulating layer. An inter-layer connection electrode for electrically conducting between the element insulating layer, a wiring insulating layer laminated and formed on the element insulating layer, And a wiring electrode that is electrically conductive on the interlayer connection electrode and on the opposite side. 【請求項５】 請求項２または４に記載の半導体素子の
実装構造において、 前記配線用絶縁層は、熱硬化性樹脂により形成されてい
ることを特徴とする半導体素子の実装構造。5. The mounting structure of a semiconductor device according to claim 2, wherein the wiring insulating layer is formed of a thermosetting resin. 【請求項６】 請求項１ないし５のいずれかに記載の半
導体素子の実装構造において、 前記素子用絶縁層は、熱硬化性樹脂により形成されてい
ることを特徴とする半導体素子の実装構造。6. The mounting structure for a semiconductor device according to claim 1, wherein the insulating layer for the device is formed of a thermosetting resin. 【請求項７】 請求項１ないし６のいずれかに記載の半
導体素子の実装構造において、 前記半導体素子は、ベアチップを用いると共に前記下地
に対してフリップチップ実装されていることを特徴とす
る半導体素子の実装構造。7. The semiconductor element mounting structure according to claim 1, wherein the semiconductor element uses a bare chip and is flip-chip mounted on the base. Mounting structure. 【請求項８】 請求項７に記載の半導体素子の実装構造
において、 前記ベアチップは、バンプ電極を介して前記下地に電気
的に接続されいてることを特徴とする半導体素子の実装
構造。8. The mounting structure of a semiconductor device according to claim 7, wherein the bare chip is electrically connected to the base via a bump electrode. 【請求項９】 請求項１ないし８のいずれかに記載の半
導体素子の実装構造において、 前記半導体素子は、異方導電ペーストにより前記下地に
実装されていることを特徴とする半導体素子の実装構
造。9. The mounting structure of a semiconductor device according to claim 1, wherein said semiconductor device is mounted on said base with an anisotropic conductive paste. . 【請求項１０】 請求項１ないし９のいずれかに記載の
半導体素子の実装構造において、 前記素子用絶縁層は、前記下地と反対側の面を研削面も
しくは研磨面として仕上げられ、前記半導体素子および
前記層間接続電極とが共に平坦な状態となるように形成
されていることを特徴とする半導体素子の実装構造。10. The semiconductor element mounting structure according to claim 1, wherein the element insulating layer is finished with a surface opposite to the base ground or polished. And a mounting structure of the semiconductor element, wherein both the interlayer connection electrodes are formed in a flat state. 【請求項１１】 下地としての下部配線基板と、 この下部配線基板上に形成された少なくとも１階層分の
請求項１または２に記載の半導体素子の実装構造と、 その最上部の実装構造の上部に配設され、配線パターン
が形成された部分が前記実装構造の層間接続電極もしく
は配線用電極と対向する状態で電気的に接続された上部
配線基板とを備えたことを特徴とする積層型回路モジュ
ール。11. A lower wiring board as a base, a mounting structure of the semiconductor element according to claim 1 or 2 for at least one layer formed on the lower wiring board, and an upper part of a mounting structure of an uppermost part thereof And an upper wiring board electrically connected in a state where a portion where a wiring pattern is formed is opposed to an interlayer connection electrode or a wiring electrode of the mounting structure. module. 【請求項１２】 請求項１１に記載の積層型回路モジュ
ールにおいて、 前記半導体素子の実装構造を２階層分以上設ける構成の
場合に、 少なくとも前記上部配線基板と接する位置に形成される
階層の前記半導体素子の実装構造は、その上部配線基板
を下地として形成されていることを特徴とする積層型回
路モジュール。12. The stacked circuit module according to claim 11, wherein in a configuration in which the mounting structure of the semiconductor element is provided for two or more layers, the semiconductor in a layer formed at least at a position in contact with the upper wiring board. A stacked circuit module, wherein an element mounting structure is formed using an upper wiring substrate as a base. 【請求項１３】 下地としての配線基板もしくは他の実
装構造の上に半導体素子を電気的に接続するようにして
固定する素子実装工程と、 前記下地の上に層間接続電極を形成する層間接続電極形
成工程と、 前記層間接続電極および前記半導体素子を覆う状態に絶
縁体を配置形成する素子用絶縁層形成工程と、 前記絶縁層形成工程により形成された絶縁体の層の前記
下地と反対側の面を研削処理してその研削面に前記層間
接続電極を露出させた状態として素子用絶縁層を形成す
る研削工程とを有することを特徴とする半導体素子の実
装構造の製造方法。13. An element mounting step of electrically connecting and fixing a semiconductor element on a wiring board or another mounting structure as a base, and an interlayer connection electrode for forming an interlayer connection electrode on the base. A forming step, an element insulating layer forming step of arranging and forming an insulator so as to cover the interlayer connection electrode and the semiconductor element, and an insulating layer formed in the insulating layer forming step on the side opposite to the base. Grinding the surface to form an element insulating layer with the interlayer connection electrode exposed on the ground surface. 【請求項１４】 下地としての配線基板もしくは他の実
装構造の上に層間接続電極を形成する層間接続電極形成
工程と、 前記下地の上に半導体素子を電気的に接続するようにし
て固定する素子実装工程と、 前記層間接続電極および前記半導体素子を覆う状態に絶
縁体を配置形成する素子用絶縁層形成工程と、 前記絶縁層形成工程により形成された絶縁体の層の前記
下地と反対側の面を研削処理してその研削面に前記層間
接続電極を露出させた状態として素子用絶縁層を形成す
る研削工程とを有することを特徴とする半導体素子の実
装構造の製造方法。14. An interlayer connection electrode forming step of forming an interlayer connection electrode on a wiring substrate or another mounting structure as a base, and an element for fixing a semiconductor element on the base so as to be electrically connected thereto. A mounting step; an element insulating layer forming step of arranging and forming an insulator so as to cover the interlayer connection electrode and the semiconductor element; Grinding the surface to form an element insulating layer with the interlayer connection electrode exposed on the ground surface. 【請求項１５】 請求項１３または１４に記載の半導体
素子の実装構造の製造方法において、 前記研削工程は、前記半導体素子も同時に研削しながら
前記素子用絶縁層を形成することを特徴とする半導体素
子の実装構造の製造方法。15. The semiconductor device according to claim 13, wherein in the grinding step, the element insulating layer is formed while simultaneously grinding the semiconductor element. A method for manufacturing an element mounting structure. 【請求項１６】 請求項１３ないし１５のいずれかに記
載の半導体素子の実装構造の製造方法において、 前記素子用絶縁層の上に配線用電極を形成する配線用電
極形成工程と、 前記配線用電極の一部を残した状態で他の部分を覆うよ
うにして絶縁体を充填して配線用絶縁層を形成する配線
用絶縁層形成工程とを有することを特徴とする半導体素
子の実装構造の製造方法。16. The method for manufacturing a mounting structure of a semiconductor device according to claim 13, wherein a wiring electrode forming step of forming a wiring electrode on the element insulating layer; A wiring insulating layer forming step of forming an insulating layer for wiring by filling an insulator so as to cover the other part while leaving a part of the electrode. Production method. 【請求項１７】 請求項１６に記載の半導体素子の実装
構造の製造方法において、 前記配線用絶縁層形成工程は、 前記絶縁体としての熱硬化性樹脂を前記配線用電極の上
から塗布する樹脂塗布工程と、 塗布された樹脂面を平板により押しつぶして前記配線用
電極の一部が露出する状態に処理する押圧処理工程と、 熱硬化処理を行なって硬化させる熱処理工程と、 前記平板を除去する平板除去工程とを有することを特徴
とする半導体素子の実装構造の製造方法。17. The method for manufacturing a mounting structure of a semiconductor device according to claim 16, wherein the wiring insulating layer forming step comprises: applying a thermosetting resin as the insulator from above the wiring electrode. A coating step; a pressing step of crushing the applied resin surface with a flat plate to expose a portion of the wiring electrode; a heat-treating step of performing a thermosetting process to cure; and removing the flat plate. A method for manufacturing a semiconductor element mounting structure, comprising: a flat plate removing step. 【請求項１８】 請求項１６に記載の半導体素子の実装
構造の製造方法において、 前記配線用絶縁層の上部に設ける層が配線基板である場
合に、 前記配線用絶縁層形成工程は、 前記絶縁体としての熱硬化性樹脂を前記配線用電極の上
から塗布する樹脂塗布工程と、 塗布された樹脂面を前記配線基板により押しつぶして前
記配線用電極の一部が露出する状態に処理する押圧処理
工程と、 熱硬化処理を行なって硬化させる熱処理工程とを有する
ことを特徴とする半導体素子の実装構造の製造方法。18. The method for manufacturing a semiconductor device mounting structure according to claim 16, wherein the layer provided on the wiring insulating layer is a wiring board; A resin application step of applying a thermosetting resin as a body from above the wiring electrode; and a pressing process of crushing the applied resin surface by the wiring substrate so that a part of the wiring electrode is exposed. A method for manufacturing a semiconductor element mounting structure, comprising: a heat treatment step of performing a heat curing treatment to cure the semiconductor device. 【請求項１９】 請求項１６に記載の半導体素子の実装
構造の製造方法において、 前記配線用絶縁層の上部に設ける層が他の半導体素子の
実装構造である場合に、 前記配線用絶縁層形成工程は、 前記絶縁体としての熱硬化性樹脂を前記配線用電極の上
から塗布する樹脂塗布工程と、 塗布された樹脂面に前記他の半導体素子の実装構造にお
ける素子用絶縁層の面を対向させて押しつぶして前記配
線用電極の一部が露出する状態に処理する押圧処理工程
と、 熱硬化処理を行なって硬化させる熱処理工程とを有する
ことを特徴とする半導体素子の実装構造の製造方法。19. The method for manufacturing a semiconductor device mounting structure according to claim 16, wherein the layer provided on the wiring insulating layer is another semiconductor device mounting structure, wherein the wiring insulating layer is formed. A resin coating step of applying a thermosetting resin as the insulator from above the wiring electrode; and a surface of the element insulating layer in the mounting structure of the another semiconductor element facing the applied resin surface. A method of manufacturing a mounting structure for a semiconductor element, comprising: a pressing step of crushing and crushing the wiring electrode so that a part of the wiring electrode is exposed; 【請求項２０】 請求項１３ないし１９のいずれかに記
載の半導体素子の実装構造の製造方法において、 前記素子実装工程で前記半導体素子を前記下地の上に電
気的に接続するときにバンプ電極が必要となる場合に
は、 前記素子実装工程よりも前に前記下地の上に前記バンプ
電極を形成するバンプ電極形成工程を実施することを特
徴とする半導体素子の実装構造の製造方法。20. The method for manufacturing a semiconductor device mounting structure according to claim 13, wherein the bump electrodes are electrically connected to the semiconductor element on the base in the element mounting step. If necessary, a method of manufacturing a semiconductor element mounting structure, comprising performing a bump electrode forming step of forming the bump electrode on the base before the element mounting step. 【請求項２１】 請求項２０に記載の半導体素子の実装
構造の製造方法において、 前記バンプ形成工程は、前記層間接続電極形成工程の実
施時に前記バンプ電極を同時に形成することを特徴とす
る半導体素子の実装構造の製造方法。21. The method according to claim 20, wherein in the bump forming step, the bump electrodes are simultaneously formed when the interlayer connection electrode forming step is performed. Manufacturing method of mounting structure. 【請求項２２】 請求項１３ないし２１のいずれかに記
載の半導体素子の実装構造の製造方法において、 前記層間接続電極形成工程では、前記層間接続電極をそ
の形成面から上方に向けて錐状もしくは錐台状に形成す
ることを特徴とする半導体素子の実装構造の製造方法。22. The method of manufacturing a semiconductor device mounting structure according to claim 13, wherein in the step of forming an interlayer connection electrode, the interlayer connection electrode is formed in a conical or upward shape from its forming surface. A method for manufacturing a mounting structure of a semiconductor device, wherein the mounting structure is formed in a frustum shape. 【請求項２３】 請求項１３ないし２１のいずれかに記
載の半導体素子の実装構造の製造方法において、 前記層間接続電極形成工程では、前記下地の上に金属超
微粒子を堆積させる方法により前記層間接続電極を形成
することを特徴とする半導体素子の実装構造の製造方
法。23. The method of manufacturing a semiconductor device mounting structure according to claim 13, wherein in said interlayer connection electrode forming step, said interlayer connection is formed by depositing ultrafine metal particles on said base. A method of manufacturing a semiconductor element mounting structure, comprising forming an electrode. 【請求項２４】 請求項１３ないし２１のいずれかに記
載の半導体素子の実装構造の製造方法において、 前記層間接続電極形成工程では、前記下地の上にスタッ
ドバンプを複数個積層形成することにより前記層間接続
電極を形成することを特徴とする半導体素子の実装構造
の製造方法。24. The method of manufacturing a semiconductor device mounting structure according to claim 13, wherein in the step of forming an interlayer connection electrode, a plurality of stud bumps are formed on the underlayer. A method for manufacturing a semiconductor element mounting structure, comprising forming an interlayer connection electrode. 【請求項２５】 請求項１３ないし２１のいずれかに記
載の半導体素子の実装構造の製造方法において、 前記層間接続電極形成工程では、前記下地の上に金属ワ
イヤをワイヤボンディング法により立設するようにして
前記層間接続電極を形成することを特徴とする半導体素
子の実装構造の製造方法。25. The method for manufacturing a semiconductor device mounting structure according to claim 13, wherein in the step of forming an interlayer connection electrode, a metal wire is erected on the base by a wire bonding method. Forming the interlayer connection electrode in the above manner. 【請求項２６】 請求項１６ないし２１のいずれかに記
載の半導体素子の実装構造の製造方法において、 前記配線用電極形成工程では、前記配線用電極の形成を
前記請求項２２ないし２５のいずれかに記載する前記層
間接続電極形成工程で前記層間接続電極を形成する方法
を用いて形成するようにしたことを特徴とする半導体素
子の実装構造の製造方法。26. The method of manufacturing a semiconductor device mounting structure according to claim 16, wherein in the wiring electrode forming step, the wiring electrode is formed. A method for manufacturing a mounting structure of a semiconductor element, characterized by using the method of forming the interlayer connection electrode in the step of forming the interlayer connection electrode described in (1). 【請求項２７】 請求項２０ないし２６のいずれかに記
載の半導体素子の実装構造の製造方法において、 前記バンプ電極形成工程では、前記バンプ電極をその形
成面から上方に向けて錐状もしくは錐台状に形成するこ
とを特徴とする半導体素子の実装構造の製造方法。27. The method for manufacturing a semiconductor device mounting structure according to claim 20, wherein in the bump electrode forming step, the bump electrode is formed in a conical shape or a truncated cone with the bump electrode facing upward from a surface on which the bump electrode is formed. A method for manufacturing a mounting structure of a semiconductor element, wherein the mounting structure is formed in a shape. 【請求項２８】 請求項２０ないし２７のいずれかに記
載の半導体素子の実装構造の製造方法において、 前記バンプ電極形成工程では、前記バンプ電極を金属微
粒子を堆積させる方法で形成していることを特徴とする
半導体素子の実装構造の製造方法。28. The method according to claim 20, wherein in the bump electrode forming step, the bump electrode is formed by a method of depositing fine metal particles. A method of manufacturing a semiconductor device mounting structure. 【請求項２９】 請求項２０ないし２７のいずれかに記
載の半導体素子の実装構造の製造方法において、 前記バンプ電極形成工程では、前記バンプ電極の形成を
スタッドバンプを前記下地の表面に形成する方法で設け
ていることを特徴とする半導体素子の実装構造の製造方
法。29. The method according to claim 20, wherein in the bump electrode forming step, the bump electrode is formed by forming a stud bump on the surface of the base. A method for manufacturing a mounting structure of a semiconductor element, comprising: 【請求項３０】 請求項２０ないし２７のいずれかに記
載の半導体素子の実装構造の製造方法において、 前記バンプ電極形成工程では、前記バンプ電極の形成を
導電性ペーストを印刷することにより形成することを特
徴とする半導体素子の実装構造の製造方法。30. The method according to claim 20, wherein in the bump electrode forming step, the bump electrode is formed by printing a conductive paste. A method for manufacturing a mounting structure of a semiconductor device, comprising: 【請求項３１】 請求項１７ないし３０のいずれかに記
載の半導体素子の実装構造の製造方法において、 前記素子用絶縁層形成工程では、前記素子用絶縁層とし
て前記熱硬化性樹脂を用いる場合に、熱硬化処理をその
熱硬化性樹脂のガラス転移温度よりも低い温度で行なう
ことを特徴とする半導体素子の実装構造の製造方法。31. The method for manufacturing a semiconductor device mounting structure according to claim 17, wherein in the device insulating layer forming step, the thermosetting resin is used as the device insulating layer. And a method of performing a thermosetting treatment at a temperature lower than a glass transition temperature of the thermosetting resin.
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