JP2001160001A - Semiconductor integrated circuit and method for synchronizing inter-chip storage part - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accelerate inter-chip corresponding processing rate by transferring data between chips. SOLUTION: A CPU chip module 10 is provided with a display data RAM 21 to be accessed by being designated by an address in a prescribed address range, a CPU 24 connected via a bus 27 with the RAM 21 for performing access via the bus 27 to the RAM 21, and a data transfer interface 23 connected with the bus 27 for judging that the designated address is within the prescribed address range, based on a signal on the bus 27 and outputting an address obtained by modifying the designated address and data on the bus 27 to the outside part. A peripheral chip module 30 is provided with a display data RAM 31 to be accessed by being designated by the address in the prescribed address range and a data transfer interface 33 which is connected via a bus 37 with the RAM 31 for address-designating the RAM 31 by the address transferred from the outside and performing access to the RAM 31.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having a data transfer circuit, and more particularly, to a semiconductor chip having an inter-chip serial data transfer circuit in a multi-chip module, and a method for synchronizing an inter-chip storage unit.

[0002]

2. Description of the Related Art In an LSI, as the circuit scale increases, the development period and the development cost increase and the chip yield decreases. To solve these problems,
2. Description of the Related Art A whole circuit is divided into a plurality of chips to form a multi-chip module (MCM).

[0003]

In the MCM, it is necessary to transfer the data to another chip in accordance with the data processing in a certain chip and store the received data in the other chip. , Causing a reduction in the data processing speed of the entire MCM.

[0004] When data is transferred in parallel between chips in the MCM, the number of input / output points increases and the yield of the MCM decreases. The configuration in which data is serially transferred between chips causes a further reduction in the data processing speed.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a semiconductor integrated circuit and an inter-chip memory capable of transferring data between chips and performing corresponding processing on both chips more quickly. It is an object of the present invention to provide a method of synchronizing a part.

[0006]

According to the first aspect of the present invention, there is provided a semiconductor integrated circuit, comprising: a storage unit designated and accessed by an address within a predetermined address range; a bus connected to the storage unit; A bus master that accesses the storage unit via the bus and a bus master that is connected to the bus and determines based on a signal on the bus that the designated address is within the predetermined address range and that the access is a write; , And a data transfer interface for outputting the specified address or its modified address and the data on the bus to the outside.

According to this semiconductor integrated circuit, when a bus master writes data in a storage unit in a chip, a designated address for the storage unit or an address and data obtained by modifying the specified address are transferred out of the chip via the data transfer interface. Therefore, it is possible for another chip to receive the data and automatically write the data in its storage unit, thereby making it possible to further speed up the corresponding processing by both chips. It works. Also, there is an effect that the software configuration can be simplified.

[0008] In the semiconductor integrated circuit according to the second aspect, the first aspect is provided.
In the above, the data transfer interface includes a coincidence determination circuit that determines whether or not the storage unit is addressed, and, when the coincidence determination circuit makes an affirmative determination and determines that the access is a write operation, A state circuit for outputting a control signal for sequentially transferring an address or a modified address thereof and data on the bus, a parallel / serial conversion circuit, and modifying the designated address or the designated address in response to the control signal And a selection circuit for sequentially selecting the selected address and the data and supplying the data to the parallel / serial conversion circuit.

According to this semiconductor integrated circuit, since data is serially transferred between the chips, the number of input / output points between the chips is reduced to improve the yield of all chips, and the transfer speed is reduced by the serial transfer. This disadvantage is reduced by the effect of the first aspect.

According to a third aspect of the present invention, there is provided a semiconductor integrated circuit.
Wherein the data transfer interface further includes an offset register, and an adding circuit for adding the contents of the offset register and the specified address to perform the modification.

According to this semiconductor integrated circuit, the automatic writing can be easily performed even if the address ranges of the corresponding storage sections of the two chips are different.

According to a fourth aspect of the present invention, there is provided a semiconductor integrated circuit, comprising: a storage unit designated and accessed by an address in a predetermined address range; a bus master connected to the storage unit by a bus and accessing the storage unit via the bus; Connected to the bus, based on a signal on the bus, when it is determined that the designated address is within the predetermined address range and the access is determined to be a read, the designated address or an address obtained by modifying the designated address; And a data transfer interface that waits for data to be transferred from the outside and supplies the transferred data to the bus.

According to this semiconductor integrated circuit, when the bus master reads data from the storage unit in the chip, the specified address for the storage unit or an address obtained by modifying the address is transferred to the outside of the chip via the data transfer interface. Therefore, it is possible for another chip to receive the data, automatically read out the data from the storage unit, and transfer the data, thereby speeding up the corresponding processing by both chips. It works. Also, there is an effect that the software configuration can be simplified.

According to a fifth aspect of the present invention, there is provided a semiconductor integrated circuit.
Wherein the data transfer interface releases the bus right of the bus master to the bus,
After the data is transferred from outside, the data is stored in the storage unit.

According to this semiconductor integrated circuit, data is read out from another chip by data reading in the chip, received by the hardware configuration, and read by the own chip. Of the storage unit can be updated so as to be the same as that of the other chips.

In the semiconductor integrated circuit of the present invention, a storage unit specified and accessed by an address in a predetermined address range, and the storage unit is connected to the storage unit by a bus, and the storage unit is addressed by an address transferred from the outside. A data transfer interface for designating and accessing the storage unit.

According to this semiconductor integrated circuit,
The above effects can be obtained by configuring a multi-chip module in combination with the semiconductor integrated circuit according to any one of the first to fifth aspects.

According to a seventh aspect of the present invention, there is provided a method of synchronizing an inter-chip storage unit, wherein a first semiconductor chip in which a bus master, a first storage unit, and a first data transfer interface are connected to each other via a bus; A chip system in which a second data transfer interface has a second semiconductor chip connected to each other via a bus, and wherein the first data transfer interface and the second data transfer interface are connected to each other. The bus master accesses the first storage unit in response to the bus master accessing the first storage unit.
The second storage unit is also accessed via the data transfer interface.

According to this method, the access operation to the storage unit in the second chip is automatically performed in response to the access operation to the storage unit in the first chip. Even if they are separated, it is possible to increase the speed of performing the corresponding processing by both chips. Also, there is an effect that the software configuration can be simplified.

Other objects, configurations and effects of the present invention will become apparent from the following description.

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] FIG. 1 is a block diagram schematically showing a multichip module 10 according to a first embodiment of the present invention.

The multi-chip module 10 has a CPU chip 20 and a peripheral control chip 30, and an external keyboard 11 and display 12 are connected to the peripheral control chip 30. The contents of the display data RAM 31 provided in the peripheral control chip 30 are displayed on the display 12 via the switch control circuit 32. Multi-chip module 10
Is divided into the CPU chip 20 and the peripheral control chip 30, the CPU chip 20 includes a display data RAM 21 corresponding to the display data RAM 31 of the peripheral control chip 30, and further includes the CPU chip 20 and the peripheral control chip 30. 30 are provided with serial transfer interfaces 23 and 33, respectively.

In the CPU chip 20, a display data RAM
21, a serial transfer interface 23, a CPU 24 as a bus master, and a register 25
7 are connected. In the peripheral control chip 30, a bus 37 connects the display data RAM 31, the serial transfer interface 33, the control circuit 34, the register 35, and the buffer register 36.

In the CPU chip 20, when the CPU 24 changes the contents of the display data RAM 21, the peripheral control chip 30 also changes the display data RA.
It is necessary to change the contents of M31. Peripheral control chip 3
0, the display data R
When the contents of AM31 are changed, C
In the PU chip 20, it is necessary to change the contents of the display data RAM 21. That is, the display data RAM2
The contents of 1 and 31 are mirror images of each other.

The contents of the display data RAMs 21 and 31 are made the same as follows.

When the CPU 24 writes data to the display data RAM 21, the data is transferred to the serial transfer interface 33 by the serial transfer interface 23 in parallel with the writing of the data to the display data RAM 21.
31 is written to the corresponding address.

When display data is input by operating the keyboard 11, the data is held in the buffer register 36 via the key input interface 38, and then stored in the display data RAM 31 by the control circuit 34. In parallel with this storage,
The data is transferred to the serial transfer interface 23 via the serial transfer interface 33 and the display data R
It is stored in the corresponding address of AM21.

FIG. 2 shows the serial transfer interface 23.
An example of the configuration will be described.

The address on the bus 27 is held in the address register 40, and the coincidence judgment circuit 41 judges whether the value ADDR is within a predetermined range (the address range of the display data RAM 21 or the address of the register 25 in FIG. 1). Is done. The output EQ of the match determination circuit 41 is supplied to the state circuit 42. The state circuit 42 includes states S1, S2,
A transition is made between S31 to S35 and S41 to S45 as shown in the figure, and a timing signal is generated. Initially, it is in the idle state S1.

(S1) When the coincidence signal EQ becomes '1',
Transition to the state S2.

The R / W signal on the bus 27 is held in the R / W flip-flop 43, and its output is supplied to the state circuit 42.

(S2) When the output of the R / W flip-flop 43 changes from "1" to "0" (write), the state circuit 42 changes to state S31.

An offset address OFA is set in the offset register 44 in the initialization routine. The offset address OFA is the address ADDR
Is added by the adder circuit 45, and the result is supplied to the multiplexer 46.

(S31) The state circuit 42 determines that CMND =
A write command of '0' + (header) is supplied to one data input terminal of the multiplexer 46, a selection control signal is supplied to the multiplexer 46 to select it, and a shift clock is supplied to the parallel / serial conversion circuit 47. Then, the output of the multiplexer 46 is held in the parallel / serial conversion circuit 47.

(S32) The state circuit 42 makes the multiplexer 46 select the output of the adder circuit 45, supplies the shift clock to the parallel / serial conversion circuit 47, and holds the output of the multiplexer 46 in the parallel / serial conversion circuit 47. Let it.

(S33) The state circuit 42 supplies a shift clock to the parallel / serial conversion circuit 47 to cause the parallel / serial conversion circuit 47 to transfer the write command and the address.

FIG. 3 shows a configuration example of the serial transfer interface 33 of FIG.

The header of the received serial data is detected by the header detection circuit 70, and the detection signal is supplied to the R / W control circuit 7.
1 is supplied. In response to this detection, the R / W control circuit 71 supplies the shift clock to the serial / parallel conversion circuit 69 via the state circuit 62, and the R / W flip-flop 72
And a latch pulse is supplied to the address register 73 in this order. As a result, the R / W signal and the address converted to the parallel data correspond to the R / W flip-flop 72, respectively.
And stored in the address register 73. The R / W control circuit 71 changes the output of the address register 73 and the output of the R / W flip-flop 72 from the high impedance state to the enable state in this order, and sets the display data RAM 3 of FIG.
Write control is performed halfway on 1.

(S34) In FIG. 2, the state circuit 42
Causes the data register 48 to hold the data on the bus 27 and the multiplexer 46 to
, And a shift clock is supplied to the parallel / serial conversion circuit 47 to hold the output of the multiplexer 46 in the parallel / serial conversion circuit 47.

(S35) The state circuit 42 supplies a shift clock to the parallel / serial conversion circuit 47 to transfer the data held in the parallel / serial conversion circuit 47. Next, the process returns to the idle state S1.

In FIG. 3, an R / W control circuit 71 supplies a shift clock to a serial / parallel conversion circuit 69,
A latch pulse is supplied to the data register 74. As a result, the data is converted into parallel data and held in the data register 74. The R / W control circuit 71 changes the output of the data register 74 from the high impedance state to the enabled state, and completes the write control on the display data RAM 31 in FIG.

Thus, the data written in the display data RAM 21 or the register 25 is stored in the display data RAM 21 or the register 25.
It is also written to the corresponding address or register 35 of the AM 31.

In FIG. 1, when the content of the display data RAM 31 is changed by operating the keyboard 11, the same operation as when the content of the display data RAM 21 is changed as described above is performed.
This is also written in the corresponding address of the display data RAM 21.

Components 60 to 71, 73 and 7 in FIG.
4 respectively correspond to the components 40 to 51, 53 and 54 in FIG. Serial transfer interface 33
2 to 23 are the transfer of the write address and data, there is no command transfer, and the one corresponding to the R / W flip-flop 72 does not exist in FIG.

FIG. 4 shows the state of the CPU chip 20 as described above.
When the CPU 24 writes data in the display data RAM 21, the data is automatically stored in the peripheral control chip 3.
7 is a memory map for explaining that data is also written to a display data RAM 31 of 0.

According to the first embodiment, by performing such automatic writing, it is possible to further speed up the transfer of data between chips and the corresponding processing by both chips.

In FIG. 1, for example, the control state of the control circuit 34 is stored in the register 35. When the CPU 24 executes an instruction to address the register 25 and read the contents, the contents of the register 35 are stored in the register 25 via the serial transfer interfaces 33 and 23, and the contents are stored in the CPU 2 as follows.
4 is read into the register.

When the above instruction is executed, in FIG. 2, the address on the bus 27 is held in the address register 40, and it is determined by the coincidence determination circuit 41 whether or not the value is within the predetermined range, and the affirmative determination is made. And the state is S1
To S2.

(S2) When the output of the R / W flip-flop 43 transitions from “0” to “1” (read), the state circuit 42 transitions to state S41.

(S41) The state circuit 42 determines that CMND =
The write command of “1” + (header) is supplied to the data input terminal of the multiplexer 46, and the same control as in the state S31 is performed.

In states S42 and S43, the state S3
Control similar to the control in 2 and S33 is performed.

In the state S43, in FIG. 3, the R / W control circuit 71 sets the input of the address register 60 to the high impedance state, and then sets the address register 73 and R
Enable the output of the / W flip-flop 72.
Thereby, the address of the register 35 and “1” are placed on the address bus of the bus 37 and the R / W control line, respectively.
Is supplied. The data held in the register 35 of FIG. 1 is read onto the data bus of the bus 37, and the R / W control circuit 71 causes the data register 68 to hold the data.
The R / W control circuit 71 causes the multiplexer 66 to select the output of the data register 68 via the state circuit 62, and further supplies a shift clock to the parallel / serial conversion circuit 67 to convert the data into the serial / serial data in FIG. Parallel conversion circuit 4
9 is supplied.

(S44) In preparation for writing by the write control circuit 51, the state circuit 42 supplies an interrupt signal WAIT to the CPU 24 in FIG. The shift clock is supplied to the conversion circuit 49.

(S 45) The state circuit 42 holds the parallel output data of the serial / parallel conversion circuit 49 in the data register 54 via the write control circuit 51, and further holds the data in the register 25. The WAIT for the CPU 24 is released, and the CPU 24 takes in the data on the data bus of the bus 27 into the internal register.

As described above, the CPU 24 sets the register 2
By executing the read instruction for 5, the data in the register 35 can be read and held in the register 25, and the data can be taken into the internal register.

[Second Embodiment] FIG. 5 is a block diagram schematically showing a multichip module 10A according to a second embodiment of the present invention.

In the peripheral control chip 30A, the change detection circuit 39 detects a data change in the buffer register 36 and outputs a signal. In the CPU chip 20A, the interrupt control circuit 28 makes a WAIT interrupt to the CPU 24A in response to the detection signal from the change detection circuit 39.

By changing the contents of the buffer register 36 by operating the keyboard 11, the display data RAM 3
When the data of 1 is updated, on the one hand, the address and data on the bus 37 are transferred to the 23 via the serial transfer interface 33 as described above, and on the other hand, the change detection circuit 39 sends the data and the data to the CPU 24A via the interrupt control circuit 28. An interrupt is issued, the bus right of the CPU 24A to the bus 27 is released, and this data is written from the serial transfer interface 23 to the corresponding address of the display data RAM 21 as described above.

FIG. 6 shows a state in which the CPU chip 20A has a CP.
This is a memory map for explaining that when U24A writes data to the display data RAM 21, the data is automatically written also to the display data RAM 31 of the peripheral control chip 30.

The CPU 24A has a head address register,
It has an access number register and a data register. Data is set in the data register, and the display data RAM 21
Each time a data write command is executed, the content i of the access count register is incremented, for example, and the data is written to the display data RAM 21 and the display data RAM 31 as in the first embodiment. The write address is ((head address register) + i). The address range of the display data RAM 21 is (start address register) to ((start address register) +
n), and when i = n, the next value automatically becomes the initial value 0.

The other points are the same as in the first embodiment.

FIG. 7 is a modification of FIG. 6, in which the CPU 24A of the CPU chip 20A
7 is a memory map for explaining that when data is written to the peripheral control chip 30, the data is automatically written to the display data RAM 31 of the peripheral control chip 30.

The CPU 24A has a head address register,
It has a final address register and a data register. Data is set in the data register, and the display data RAM 21
Each time a data write command is executed, the variable i is incremented, and data is written to the display data RAMs 21 and 31 as in the first embodiment. Write address is ((start address register)
+ I). When this value becomes equal to the content of the last address register, the variable i automatically becomes the initial value 0 next.

[Third Embodiment] FIG. 8 is a block diagram schematically showing a multichip module 10B according to a third embodiment of the present invention.

The multi-chip module 10B has a CPU
A chip 20B and a peripheral control chip 30B are provided, and an external battery 80 is connected to the peripheral control chip 30B.

The peripheral control chip 30B is a power control chip, and the serial transfer interface 33, the voltage regulator 81, and the low voltage detection circuit 82 are connected via the bus 37. The voltage regulator 81 boosts the input voltage from the battery 80 according to the mode.
For example, the voltage regulator 81 boosts the input voltage 3V to 5V in the normal mode and 4V in the standby mode.

Mode control circuit 83 has a register R to be addressed.

When the low voltage detection circuit 82 detects that the output voltage of the battery 80 is, for example, 3 V or less, it outputs write information to the register R of the mode control circuit 83 onto the bus 37. This information is written into the register R of the mode control circuit 83 via the serial transfer interfaces 33 and 23. In response, the mode control circuit 83 resets the CPU 24 via the interrupt control circuit 28 to execute the operation. Stop. Thereby, the CPU 2
4 is prevented.

In the normal mode, when the CPU 24 writes into the register R of the mode control circuit 83 to set the standby mode, this information is supplied to the voltage regulator 81 via the serial transfer interfaces 23 and 33. As a result, the output voltage becomes 4 V, and the mode control circuit 83
When the system clock of the chip 20B is set to a low frequency and C
The PU chip 20B shifts to the standby mode.

External data is transmitted to the mode control circuit 83 and the serial transfer interface 23 via the UART 84.
, The normal mode information is written into the register R of the mode control circuit 83, and the mode control circuit 83
Thus, the state becomes the same as when the normal mode information is written to the register in the serial transfer interface 23. As a result, this information is transferred to the voltage regulator 81 via the serial transfer interfaces 23 and 33.
, And the output voltage becomes the above 5V. Further, the system clock of the CPU chip 20B is set to a high frequency by the mode control circuit 83, and the CPU chip 20B returns to the normal mode.

[Brief description of the drawings]

FIG. 1 is a block diagram schematically showing a multichip module according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of a master side serial transfer interface 23 in FIG.

FIG. 3 is a block diagram showing a configuration example of a slave side serial transfer interface 33 in FIG. 1;

FIG. 4 is a block diagram showing the configuration of display data RA in a CPU chip;
9 is a memory map for explaining that when data is written to M, the data is automatically written also to the display data RAM of the peripheral control chip.

FIG. 5 is a block diagram schematically illustrating a multi-chip module according to a second embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of display data RA in the CPU chip.
9 is a memory map for explaining that when data is written to M, the data is automatically written also to the display data RAM of the peripheral control chip.

FIG. 7 is a modification of FIG.
9 is a memory map illustrating that when a PU writes data to a display data RAM, the data is automatically written to the display data RAM of the peripheral control chip.

FIG. 8 is a block diagram schematically showing a multichip module according to a third embodiment of the present invention.

[Explanation of symbols]

 10, 10A, 10B Multichip module 11 Keyboard 12 Display 20, 20A, 20B CPU chip 21, 31 Display data RAM 23, 33 Serial transfer interface 24, 24A CPU 25, 35, R register 27, 37 Bus 28 Interrupt control Circuits 30, 30A, 30B Peripheral control chip 32 Switch control circuit 34 Control circuit 36 Buffer register 38 Key input interface 39 Change detection circuit 40, 53, 60, 73 Address register 41, 61 Match determination circuit 42, 62 State circuit 43, 63 , 72 R / W flip-flop 44, 64 Offset register 45, 65 Addition circuit 46, 66 Multiplexer 47, 67 Parallel / serial conversion circuit 48, 54, 68, 74 Data register 49, 69 Serial / parallel conversion Road 50,70 header detecting circuit 51 write control circuit 71 R / W control circuit 80 battery 81 voltage regulator 82 low voltage detection circuit 83 mode control circuit 84 UART OFA offset address

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Yoshihiko Koike 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Yoshiaki Nagatomi 4-chome, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa No. 1 Fujitsu Limited (72) Inventor Norihiro Nakatsuhama 4-1-1 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Fujitsu Limited (72) Inventor Toshifumi Yamagami Kami-Odanaka, Nakahara-ku, Kawasaki-shi, Kanagawa 4-1-1 1-1 Inside Fujitsu Limited (72) Inventor Yoshiyuki Kubo 4-1-1 1-1 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Tetsuya Yoshida Kami-Odanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture 4-1-1, Fujitsu Limited F-term (reference) 5B045 BB02 BB29 DD03 DD06 KK07 5B060 CA17 KA03 MB09 5B077 NN02

Claims (7)

[Claims] 1. A storage unit designated and accessed by an address in a predetermined address range, a bus master connected to the storage unit by a bus, and accessing the storage unit via the bus, a bus master connected to the bus, When it is determined based on the signal on the bus that the designated address is within the predetermined address range and the access is determined to be a write, the designated address or an address obtained by modifying the designated address and the data on the bus are determined. And a data transfer interface for outputting to the outside. 2. The data transfer interface according to claim 1, further comprising: a coincidence determination circuit for determining whether or not the storage unit is addressed; and when the coincidence determination circuit determines affirmatively and determines that the access is a write operation. A state circuit for outputting a control signal for sequentially transmitting the specified address or an address modified from the specified address and data on the bus; a parallel / serial conversion circuit; 2. The semiconductor integrated circuit according to claim 1, further comprising: a selection circuit for sequentially selecting the modified address and the data and supplying the data to the parallel / serial conversion circuit. 3. The data transfer interface according to claim 2, further comprising: an offset register; and an adding circuit for adding the contents of the offset register and the specified address to perform the modification. Semiconductor integrated circuit. 4. A storage unit designated and accessed by an address in a predetermined address range, a bus master connected to the storage unit by a bus, and accessing the storage unit via the bus, a bus master connected to the bus, Based on the signal on the bus, when it is determined that the specified address is within the predetermined address range and the access is determined to be read, the specified address or an address obtained by modifying the specified address is output to the outside,
And a data transfer interface that waits for data to be transferred from the outside and supplies the transferred data to the bus. 5. The data transfer interface according to claim 1, wherein the bus master releases the bus right to the bus, and stores the data in the storage unit after the data is transferred from the outside. The semiconductor integrated circuit according to claim 4. 6. A storage unit specified and accessed by an address in a predetermined address range, and connected to the storage unit by a bus, and the storage unit is addressed by an address transferred from the outside to store the storage unit. A semiconductor integrated circuit, comprising: a data transfer interface for accessing; 7. A first semiconductor chip having a bus master, a first storage unit, and a first data transfer interface connected to each other via a bus, and a second storage unit and a second data transfer interface connected to each other via a bus. A method of synchronizing an inter-chip storage unit in a chip system having a second semiconductor chip connected thereto, wherein the first data transfer interface and the second data transfer interface are connected. 1 In response to accessing the storage unit,
A method of synchronizing an inter-chip storage unit, wherein the bus master also accesses the second storage unit via the first data transfer interface and the second data transfer interface.