JP2001159983A - Scheduling method of common subexpression recognition type instruction - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently use information of common subexpression elimination and to enhance the degree of parallelism of an instruction in an instruction scheduling processing. SOLUTION: Information about an intermediate language 32 to which common subexpression elimination 6 is performed is registered in a common information table 4, the information is applied to the scheduling processing 2 by referring to it, and a processing different from the normal processing is performed for the scheduling of the instruction has become the common subexpression. A scheduling result is registered in a schedule information table 5. In particular, in the case of target architecture in which a plurality of clusters exist, the common subexpression is arranged in different clusters as far as possible. The instruction scheduling processing 2 refers to the information of the common subexpression deleted by the common subexpression elimination and a scheduling method is selected depending on whether the common subexpression elimination has been performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compiling method for a compiler, and more particularly to a compiling method having an instruction scheduling mechanism, which enables efficient instruction scheduling to improve the processing performance of an object program. The present invention relates to a cognitive instruction scheduling method.

[0002]

2. Description of the Related Art Generally, a compiler that converts a program described in a high-level language into machine instructions generates the machine language by rearranging the generated machine language in a predetermined order. This instruction rearrangement processing is called instruction scheduling. Instruction scheduling is a static reordering of instructions at compile time, and (generally) VLIW
(Very Long Instruction Wo
This is an essential function in the case of a compiler that targets an architecture in which hardware such as rd) does not have an instruction rearranging function. In addition, RISC (Reduc
ed Instruction Set Comput
er), the compiler generally performs instruction scheduling to improve processing performance even when hardware has a function of dynamically rearranging instructions during execution.

A target architecture of a compiler sometimes has a configuration called a cluster. A cluster is a unit that has an arithmetic unit that performs operations, registers that hold data to be operated, and the like. By arranging a plurality of clusters in parallel, it aims to improve instruction parallelism and ensure scalability. Things. Each cluster is connected by a system bus or the like, and data transfer at an instruction word level is generally enabled. Since each cluster has a distributed register configuration including a unique register, data transfer between clusters is required to perform a collective process as a whole. Such a cluster configuration is often found in the VLIW architecture, and is called a cluster configuration VLIW architecture.

A compiler targeting the cluster configuration VLIW architecture needs to convert a sequential instruction sequence into an instruction sequence to be executed in a plurality of clusters at the time of instruction scheduling. The division of the sequential instruction sequence into clusters (and the insertion of an inter-cluster data transfer instruction necessary for the division) is hereinafter referred to as clustering. Clustering is a part of instruction scheduling, and in a cluster configuration VLIW compiler, it is common to perform clustering at the time of instruction scheduling. A general problem of the clustering process is an instruction division method. Since the register is unique to each cluster, data transfer between clusters may be required due to instruction division.

For example, when there is a sequential instruction sequence of a = b + c; (1) d = a + e; (2), when (1) and (2) are divided into different clusters, a. b.0 + c.0; (3) a.1 = a.0; (4) d.1 = a.1 + e.1; (5) It becomes necessary to generate an inter-data transfer instruction.

In the example of the low-level intermediate language, "."
The following shows the cluster number. That is, "a.0"
This shows data a in cluster 0, and the intermediate language (4) is
This is an instruction to transfer a of cluster 0 to a of cluster 1.
In the following, this notation will be followed. When (1) and (2) are arranged in the same cluster, the instruction as in (4) becomes unnecessary. In the above example, since the same value “a” is distributed to a plurality of clusters, the number of execution cycles increases. On the other hand, in the case of instruction sequences that do not depend on each other, since they can be executed independently, in some cases it is better to divide them.

For example, in the case of a = b * c; (6) d = a + e; (7) f = a + g; (8), it takes time to execute (6). For example, there is room to execute inter-cluster data transfer before (7) and (8) are executed, and (7) and (8) can be executed in parallel in a plurality of clusters. In this case, it is possible to perform processing at higher speed than when (6) to (8) are executed in the same cluster. In the case of executing in the same cluster, an inter-cluster transfer instruction is unnecessary, but (7) and (8) must be executed sequentially, and the processing is delayed by that much.

As shown in the above example, it is necessary to determine whether an instruction including a reference to the same data should be placed in the same cluster or divided into a plurality of clusters according to the scheduling situation. In compilers targeting, instruction scheduling (clustering) is a problem that affects processing performance. By the way, if data commonly used in a certain instruction sequence is copied to a plurality of clusters, dependence between the instruction sequences is reduced, and an improvement in instruction parallelism at the time of scheduling can be expected. If the effect of improving the degree of instruction parallelism is greater than the overhead of inserting an inter-cluster data transfer instruction, it is worth distributing the data. Generally, an argument, a stack pointer, and the like are assumed as data commonly used in all instruction sequences. Therefore, a clustering strategy of first transferring these values to all clusters is often effective.

On the other hand, as one of the optimization processes performed by the compiler, one of the processes called traditional optimization which has been performed for a long time, common expression elimination (also called common subexpression elimination,
Since there is no essential difference, there is a common expression elimination in the following). The deletion of the common expression is intended to improve the processing performance by using the first operation result when executing the same instruction (same in operand and operation). For example,
By converting the intermediate language shown in FIG. 5 as shown in FIG. 6, an improvement in processing performance can be expected. A temporary variable that stores the operation result of the common expression obtained as a result of the deletion of the common expression (hereinafter, referred to as a common expression operation result definition variable) is the data itself that is commonly used in the following instruction sequence, and is stored in multiple clusters. Promising as data to be transferred. However, deletion of the common expression is generally performed for a sequential instruction sequence that is a high-level intermediate language, and is independent of instruction scheduling that is a process for a low-level intermediate language that is aware of multiple clusters. there were.

Regarding instruction scheduling in the cluster configuration VLIW, for example, Emre Ozer, Sanjeev B
anerjia, Thomas M. Conte "Unified Assign and Sched
ule: A New Approach to Scheduling for Clustered Reg
ister File Microarchitecture ", Proceedings of the
31st Annual ACM / IEEE International Symposium onMic
Roarchitecture, pp. 308-315.

[0011]

As described above, in the prior art, in the instruction scheduling process, the information of the common expression deletion is not utilized, so that the common expression deletion may hinder the instruction scheduling effect. This hindered the improvement of processing performance. In other words, conventionally,
The data of the common-expression elimination optimization is not reflected in the instruction scheduling process, and these are performed in separate processes, so that there is a problem that the performance of the compiled program is ineffective.

An object of the present invention is to solve these conventional problems and to perform instruction scheduling using information on common expression elimination. Particularly, it is more efficient for a compiler targeting a cluster configuration architecture. An object of the present invention is to provide a common-recognition-type instruction scheduling method capable of improving the processing performance of an object program by performing efficient instruction scheduling.

[0013]

In order to achieve the above object, according to the common-expression-recognition-type instruction scheduling method of the present invention, when a common expression is deleted, information on an intermediate language related to the common expression is retained. Also, in the instruction scheduling process, the clustering process is performed by referring to the common expression deletion information as a data distribution candidate (see FIG. 3). It is also characterized in that the instruction scheduling process performs a clustering process of allocating instructions to clusters, and the selection of a scheduling method based on the common expression deletion information is a selection of a clustering method (see FIG. 15). It is also characterized in that the instruction clustering process directs instructions whose common expression has been deleted using the common expression deletion information to different cluster arrangements (see FIG. 17). It is also characterized by having common-expression operation result variable definition information for performing the same operation a plurality of times and common-expression operation result replacement information indicating a plurality of operation groups to be replaced with the common expression operation result variable (FIG. 10). , See FIG. 11). Further, the selection of the scheduling method based on the common expression deletion information is the selection of the inter-cluster data transfer method, the selection of the inter-cluster data transfer method is the selection of the destination cluster indicating the storage cluster of the instruction operation result, and In the cluster configuration having the whole area cluster transfer which is the simultaneous transfer of data to all the clusters, it is also characterized by having the whole area cluster transfer as a destination cluster selection candidate (FIG. 20,
See FIG. 21). As a result, efficient inter-cluster transfer of common data can be applied, thereby contributing to an improvement in the processing performance of an object program by improving the degree of instruction parallelism.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings. The present invention provides a compiler instruction scheduling method using common expression deletion information,
Specifically, the information on the intermediate language from which the common expression has been deleted is applied to the instruction scheduling process, and the scheduling of the instruction that has become the common expression is performed in a different manner from the usual process. In particular,
In the case of the target architecture in which a plurality of clusters exist, the degree of instruction parallelism can be improved by arranging the common expression in different clusters as much as possible. still,
In the following description, the intermediate language of the compiler is shown in the form of an equivalent instruction word. In order to clearly show the parallel execution status in a plurality of clusters, the execution instructions for each cluster are represented in a vertical format.

FIG. 1 is a configuration diagram of a computer system to which the compiling method of the present invention is applied. The computer system includes a CPU 101, a display device 102, a keyboard 103, a main storage device 104, and an external storage device 105. The keyboard 103 receives a compiler activation command from the user. Further, a compiler end message and an error message are displayed on the display device 102. The external storage device 105 stores a source program 106 and an object program 107. The main storage device 104 includes a compiler 108, which stores an intermediate language 3, a common expression information table 4, and an instruction scheduling information table 5, which are required in the compilation process. The compiling process is performed by the CPU 1
01 is controlled.

(First Embodiment) FIG. 2 is a flowchart showing an outline of a processing procedure of a compiler according to a first embodiment of the present invention. First, in the syntax analysis processing (201),
The lexical analysis is performed using the source program 106 as an input, and the intermediate language 3 is output. Next, in the common expression deletion process (6), the intermediate language 3 is input, the common expression is recognized, the common expression is deleted, and then the intermediate language 3 is output. Next, in the instruction scheduling process (2), the intermediate language 3 is input, the instruction scheduling process for arranging sequential instruction sequences in a plurality of clusters is performed, and the intermediate language 3 is output. In the next code generation process (202), the intermediate language is converted into the final object program 107 format.

FIG. 3 is a flow chart of a method of scheduling a common type recognition instruction according to the first embodiment of the present invention. Note that the flow of FIG. 3 shows the procedure of the common expression deletion processing (6) and the instruction scheduling processing (2) of FIG. 2 in more detail. First, common expression registration processing (6
According to 1), common expression information in the intermediate language 3 is extracted, and a common expression information table 4 is created. Next, common expression deletion processing (6
According to 2), common expressions in intermediate language 3 are deleted, and
The common expression information table 4 is updated to reflect the deletion result. In the common expression deleted intermediate language conversion process (62), the intermediate language nodes are classified into common expression deleted related intermediate words whose common expressions have been deleted and intermediate word nodes that have not been deleted and converted. After the common expression deletion processing step (6), the instruction scheduling processing (2) is performed.

This instruction scheduling process (2)
Step 30 for determining the existence of the unprocessed intermediate language node op
1. Step 302 for determining whether or not op is a common-expression-deletion-related intermediate language node, and an instruction arrangement position for determining the instruction arrangement position of op shown in the instruction scheduling process (2) of FIG. The processing includes a determination process (21) and a DEST cluster (destination cluster) determination process (22) for determining a storage location of an operation result when converting an op into a parallelized intermediate language node. The instruction arrangement position determination process (21) is performed by a common expression deletion recognition type instruction arrangement determination process (3031) performed in the case of a common expression deletion related node, and the conventional technology type instruction arrangement determination process (3032) in other cases.
Divided into Similarly, DEST cluster determination processing (2
2) is also divided into a common-expression-deletion-recognition-type DEST cluster determination process (3041) performed in the case of a common-expression-deletion-related node, and a conventional-type DEST cluster determination process (3042) in other cases. Each process will be described in detail with reference to FIGS.

FIG. 4 is a processing configuration diagram showing the relationship between intermediate words and tables used as inputs and outputs in the common expression recognition type instruction scheduling processing shown in FIG. However, since the intermediate language 3 is generally referred to, only the main input / output relationship is shown. The common expression deletion process (6) includes a common expression registration process (61) and a common expression deletion intermediate language conversion process (62). The common expression registration process (61) receives the common language before deleting the common expression 31 as input and generates a common expression information table 4 in which information on common expressions is collected. The common expression information table 4 includes a common expression table 41 that stores a list of common expression sets, and an instruction node table 42 that collects information on intermediate nodes corresponding to each entry. Common expression deleted intermediate language conversion processing (6
2), the intermediate language 31 before the common expression is deleted and the common expression information table 4 are input, the intermediate language 32 after the common expression is deleted is generated, and the conversion contents of the intermediate language accompanying the common expression deletion are recorded in the instruction node table 42. I do. Instruction placement position determination processing (2
1) and the instruction scheduling processing (2) including the DEST cluster determination processing (22),
2 and the common expression information table 4 as inputs, and generates an instruction-scheduled parallelized intermediate language 33 in which instructions are arranged in a plurality of clusters.

The instruction arrangement position determination processing (21) receives the common expression-removed intermediate language 32 and the common expression information table 4 as inputs,
While registering and referring to the instruction arrangement table 51 included in the schedule information table 5, the arrangement position of the intermediate language node is determined. In the next DEST cluster determination process (32), the DEST cluster of the intermediate language node is determined with reference to the instruction arrangement table 51. Next, for the purpose of explaining a specific application example, an example of an intermediate language to be processed will be described. The present embodiment is a compiler for an architecture having a plurality of clusters.
Requires a format that can represent a cluster. In the description of the present embodiment, in order to express that the instructions arranged in each cluster are executed in parallel in the same cycle, the execution cycle is set on the vertical axis, and the instructions executed in that cycle (for simplicity, per cycle) (It is possible to execute only one instruction in each cluster). Also, the intermediate language needs to be aware of the cluster in the intermediate language 33 after instruction scheduling, and in the intermediate language 3 before that.
In 1 and 32, there is no need to be particularly conscious.

FIGS. 5 and 6 show examples of the intermediate language configuration before and after the elimination of the common expression in the present invention. Here, all instructions are sequential intermediate word strings assuming sequential execution. FIG. 5 shows the intermediate language before the common expression is deleted.
The common expression “a + b” exists in lines 004, 005, and 005. Line 006 ~
There is no common expression in line 009, and instruction expressions divided into cluster 1 and cluster 2 are arranged. FIG. 6 shows an intermediate language after the common expression is deleted. The operation of the common expression “a + b” is replaced with the reference of the common expression operation result variable t, and the common expression that defines the common expression operation result variable t. An operation result variable definition instruction is inserted in line 101. Common expression elimination is shown in FIG.
This is an optimization process for converting into an intermediate language.

FIG. 7 is a diagram showing an example of an intermediate language after instruction scheduling in the present invention. This is an example of the configuration of the intermediate parallelized intermediate language after the removal of the common expression, in which each instruction is a parallelized intermediate language string arranged in a plurality of clusters. That is, an example is shown in which the intermediate words in FIG. 6 are arranged in parallel by the instruction scheduling process. For example, in line 204, the instruction “t.2 = t” in cluster 0 and the instruction “x1 =
t "respectively. A blank portion such as cluster 2 and cluster 3 in line 204 indicates that no instruction is executed (NOP). Hereinafter, in order to indicate the individual instructions arranged in these clusters, the line number and the cluster number are combined, and the arrangement position is indicated by “line number-cluster number”. For example,
The instruction “t = a + b” is arranged at the arrangement position (201, 0) in FIG.
The arrangement position (201, 1) is NOP. In the parallelized intermediate language notation, the operation result storage cluster (DEST cluster) of the instruction can be specified in the form of “.n”. For example, “t.2 = At “t”, the DEST cluster is cluster 2. In the present embodiment, all variables serving as operands of the operation on the right side of the instruction are limited to use in the cluster where the instruction is arranged. Therefore, the cluster number of the variable on the right side can be omitted. For example, “t” on the right side of “t.2 = t” at the arrangement position (204,0) in FIG. 7 is equivalent to “t.0”.

The parallel intermediate language as shown in FIG. 7 represents an execution process by a final machine instruction, and the number of lines directly corresponds to the number of execution cycles. That is, the number of lines of the parallel intermediate language indicates the processing performance of the object program.
Therefore, for simplicity, in the present embodiment, it is assumed that all operations can be executed in one cycle. Thereby, for example, in the example of FIG. 7, the number of execution cycles of all instructions is six. Hereinafter, the details of the common expression deletion processing (6) and the instruction scheduling processing (2) shown in FIG. 4 will be described. In the explanation, the intermediate language of FIG. 5 is used as an input example, and output examples of various tables are sequentially shown. Therefore,
First, a configuration example of various tables will be described, and then a processing procedure will be described. Hereinafter, a configuration example will be described in the order of the common expression information table 4 and the scheduling information table 5 shown in FIG.

FIG. 8 is a diagram showing a configuration example of the common expression set table 41 obtained for the example of FIG. The common expression set table 41 contains, for each common expression appearing in the program,
An entry is created. Each common expression is assigned a unique common expression set number, and each entry is accessible by the common expression set number. Each entry is
Common expression number column 411, arithmetic expression column 412, common expression set column 4
13, an operation result definition column 414, and an operation result variable column 415. The common expression number column 411 stores the entry number of the common expression set table, and the operation expression column 412 stores the operation expression of the corresponding common expression (the right side of the assignment). The common expression set column 413 stores information on the recognized common expression set in the form of an entry number of the instruction node table 42. The operation expression column 424 of the instruction node table entry which is each element of the common expression set is a common operation.
The operation result definition column 414 holds a common operation result definition instruction for performing the operation of the common operation in the form of an entry number of the instruction node table. The result variable name column 415 stores the name of a common expression definition variable (temporary variable) when the common expression is deleted. This common expression definition variable is given a unique name for one of the common expression sets.
Is provided to clarify the result of the common expression deletion intermediate language conversion 426 shown in FIG.

FIG. 9 is a diagram showing a configuration example of the instruction node table 42 obtained for the example of FIG. The instruction node table 42 is represented in a table format for explaining information of each node of the intermediate language 3. Each entry is
The information of each node of the intermediate language is converted into a table, and is mutually accessible. Each entry has an instruction number column 421, an appearance line number column 422, a definition variable column 42
3, an arithmetic expression column 424, a belonging common expression number column 425, and a common expression deleted intermediate language conversion column 426. Instruction number column 42
1 stores the entry number of the instruction node table 42, and the appearance line number column 422 stores the appearance position of the intermediate language node corresponding to the entry in the form of a line number. All information on the corresponding intermediate language node can be obtained from the intermediate language position in the appearance line number column 422. For example, insertion of a common expression variable definition instruction, common expression occurrence deletion conversion, and the like are also possible. In the present embodiment, as shown in FIG. 7, it is shown in the form of an intermediate language line number.

In the definition variable column 423 and the arithmetic expression column 424,
(In the case of an assignment operation) The variable on the left side (destination of the instruction) and the operation expression on the right side (the operation of the instruction and its operand) of the corresponding intermediate language node are stored.
The belonging common expression number column 425 stores the entry number of the common expression set table 41 indicating the belonging common expression set.
The common expression deleted intermediate language conversion column 426 stores intermediate language conversion contents when performing common expression deleted conversion. For example, information such as "definition insertion" is stored when a common expression definition variable is inserted, and "use replacement" is stored when a common expression is replaced with a common expression variable at a common expression usage point. Note that a blank column indicates that no common expression is deleted and no intermediate language conversion is performed.

FIGS. 10 and 11 show the common expression table 4 after performing the common expression deletion intermediate word conversion on the intermediate words shown in FIG. 5 in accordance with the common expression information tables of FIGS. 8 and 9.
1 is a diagram showing an example of an instruction node table 42. The table configuration is the same as that in FIGS. 8 and 9, only showing the state after the common expression-removed intermediate language conversion. FIG.
FIG. 5 is a diagram illustrating a configuration example of an instruction arrangement table 51 used by the instruction arrangement position determination process (21) in FIG. 4 when determining an instruction arrangement position of an intermediate language node. Each entry has a one-to-one correspondence with an instruction node, and the content of each entry represents the content when the intermediate language shown in FIG. Each entry includes an instruction number column 511, an appearance line number column 512, a definition variable column 513, an arithmetic expression column 514,
Affiliation common expression number column 515, common expression deletion intermediate language conversion column 51
6, an arrangement cluster number column 517. In columns 511 to 516, information obtained by indicating the entry numbers in FIG. 11 is provided for simplification of description. The contents are the same as the corresponding columns in FIG. The allocation cluster number column 517 stores the cluster number where the instruction node corresponding to the entry is allocated.
This concludes the description of various table configurations used in this embodiment.

Hereinafter, various processes for generating / referencing these tables will be sequentially described in accordance with the flow. FIG.
5 is a flowchart of a common-type registration process (61) in FIG. The common expression registration process (61) sequentially scans the intermediate language 3 and, if a common expression is detected, generates a common expression information table 4 in which the common expression information is collected and registered. Hereinafter, the procedure will be described. First, the common expression table entry number cei is initialized with 0 (step 1301).
Next, it is determined whether or not there is an unprocessed intermediate language node (step 1302).
Step 1303 and subsequent steps are performed. If there is an unprocessed intermediate language node N, first, the instruction node table 42
, A new entry ee is secured, and information on the intermediate language node N is stored (step 1303). Next, N common expression candidates (contents of the operation expression column 424 of = ee) are set as cce (step 1304).

Note that a plurality of common expression candidates cce can be considered for N depending on the format of the intermediate language. However, in this embodiment, they are uniquely determined (because there is no essential difference). Next, it is checked whether or not cce is already registered in the common expression table 41 (step 1305). This determination can be made based on whether or not the common expression table 41 has an entry in the arithmetic expression column 412 that matches the common expression candidate cce. If it is already registered, the corresponding entry of the common expression table is set to ce (step 1306), and ee is added to the common expression set column of ce, thereby registering ee in the common expression element set (step 1307). . On the other hand, if cce is not registered in the common expression table, it is checked whether or not cce is already registered in the instruction node table 42 (step 1308). This determination can be made based on whether or not there is an entry in the instruction node table 42 in which the operation expression column 424 matches the common expression candidate cce. If they match, the entry number cei of the common expression set table is incremented, cce is registered in the common expression table 41 (step 1309), and the process returns to step 1302 to process the next intermediate language node. If cce is not registered in the instruction node table, the process for the next intermediate language node is performed. When all the intermediate language nodes have been processed (step 1302), the processing ends.

FIGS. 8 and 9 show examples of the common expression information table 4 showing the result of performing the above processing on the intermediate language shown in FIG. For example, entry 42
71 and entry 4272 are the 002 line and the 00
Information of three rows of operations is stored. These two operations are constituent elements of the common expression set indicated by the entry 416 in FIG. 8, and are registered in the common expression set column 413 as common expressions.

FIG. 14 shows a common expression deleted intermediate language conversion process 62.
It is a flowchart of FIG. Common expression deletion intermediate language conversion processing 6
2 sequentially scans the common expression information table 4 and, for a common expression set capable of common expression deletion, converts the corresponding intermediate language instruction group from the intermediate language 31 before common expression deletion to the intermediate language 32 after common expression deletion. I do. Hereinafter, the procedure will be described. First, it is determined whether or not there is an unprocessed common expression set entry uce (step 1401), and the processing from step 1402 is performed until there is no unprocessed common expression set. Unprocessed common expression set uce
If there is, first, the common expression operation result definition instruction cer
Generate In the generation of the common expression calculation result definition instruction cer, the common expression calculation result variable t is generated (step 14).
02), a common expression calculation result definition instruction cer is generated (step 1403). Next, after calculating the definition insertion position dip, the common expression calculation result definition instruction cer is inserted into the intermediate language (step 1404). Then, the instruction node table 4
A new table entry nte of No. 2 is created with a conversion type of "definition insertion", and the node information of cer is stored (step 1405).

Next, the contents of the common expression set column of uce are expressed as CES
(Step 1406), and it is determined whether or not there is an unprocessed common expression set element uces in the CES (step 1407).
Step 140 until there are no unprocessed common expression set elements
8 and below are performed. That is, the unprocessed common expression set element
If there is uces, first, the entry of the instruction node table indicated by the common expression set element is set as ECES (step 1408). Next, the arithmetic expression of the intermediate language indicated by ECES is replaced with the use of the common expression variable t, and the ECE
The conversion type of S is set to “use replacement” and reflected in the instruction node table (step 1409). After the execution of step 1409, the process returns to step 1407 to process the next common expression set element. The definition insertion position is immediately before the instruction node to be executed first among the elements of the common expression set, and in this embodiment, immediately before the element registered in the common expression set. Further, as the common expression calculation result variable, a variable having a uniquely determined name may be arbitrarily generated.

FIGS. 10 and 11 show examples of the configuration of the common expression set table 41 and the instruction node table 42 showing the results of the above processing. For example, FIG.
0 entry 417 is the entry 4273, 4
It shows a state of common expression deletion for a common expression set represented by 274, 4275, and 4276. That is, entry 4
277 is a common expression operation result definition insertion, and entry 4273
Entry 4276 represents a common expression usage replacement. In fact, the intermediate language corresponding to entry 4277 is line 101 in FIG. 6 where the common expression operation result definition is inserted.
The common expression on line 102 has been replaced by a common expression variable t. In addition, in line 102 of FIG. 6, which is an intermediate language corresponding to the entry 4273, it can be seen that the common expression is used and replaced. In the following, the group of intermediate expressions subjected to the common expression deletion conversion will be referred to as common expression-related intermediate words. In FIGS. 10 and 11, the common expression deletion-related intermediate language is the entry 427.
3, 4274, 4275, 4276 and entry 42
77 is equivalent. This concludes the description of the common expression deletion procedure. Next, the procedure of the common type recognition type instruction scheduling will be described.

FIG. 15 is a flowchart of the common type recognition type instruction scheduling process (2) shown in FIG. The common expression recognition type instruction scheduling process (2) sequentially scans the sequential execution intermediate language 32 to generate a parallel execution intermediate language 33 corresponding to a plurality of clusters. In general, instruction scheduling does not schedule all intermediate words in order, but divides intermediate words into scheduling units according to a specific procedure, and schedules the intermediate words in the scheduling unit. The intermediate language processing unit of the instruction scheduling may be different from the intermediate language processing unit when the common expression is deleted. How the scheduling intermediate language processing unit is performed is not essential in the present invention, and is omitted in the following description, and the intermediate language is simply scanned sequentially and processed.

The procedure of the common type recognition type instruction scheduling process (2) will be described below. First, the relative instruction execution cycle number p for each schedule is initialized to 0 (step 1501). Next, it is determined whether or not there is an unprocessed intermediate language node op (step 1502), and the processing from step 1503 is repeated until all intermediate language nodes are processed. In the process of the op, first, the schedule information setting process of the op is performed (step 1503), and the schedule information of the op is set in the schedule information table 5. next,
It is determined whether or not the instruction placement of the op is possible in the current placement area (step 1504).
In step 505, the arrangement area is expanded by setting p = p + 1, and step 1
After 503, instruction placement is tried again. Step 150
4, the arrangement position determination processing (15)
Go to 06). Even if it is determined by this arrangement position determination processing (1506) that it is inappropriate, the process proceeds to step 1505, and the processing after step 1503 is continued. When the arrangement position is determined in the arrangement position determination processing (1506), the allocation cluster AC and the execution cycle position ap are determined. Next, after determining the transfer cluster of the operation result in the DEST cluster determination processing of op (1507), the instruction placement processing (150
In step 8), the instruction is arranged at the schedule position <ap, AC> (the arrangement possibility determination processing (1504) will be described in detail with reference to FIG. 16 and the arrangement position determination processing (1506) will be described in detail with reference to FIG. 17).

In the schedule processing, it is general to configure a dedicated schedule table and determine the setting of a schedule area and the possibility of arrangement on the schedule table. However, in the present invention, the details are not essential. In the description of the present invention, since the parallel intermediate language expression is sufficient, the description of the schedule situation is shown in the form of the parallel intermediate language. In the process of determining the existence of an unprocessed cluster,
It is also possible to sort the clusters by priority and select the clusters in descending order of priority. However, the setting of the cluster priorities in these prior arts is determined from information in the schedule processing such as the current scheduling status and the nature of the operand of the instruction. Although the present invention uses the common type deletion information as the cluster priority information, these prior art cluster priority information is not directly related to the present invention. These priorities may be set, and clusters may be selected in descending order of priority, but there is no essential relationship. The selection of unprocessed clusters may be performed in the order of priority or simply in the order of cluster numbers. Therefore, in this embodiment, particularly, the cluster priorities in these prior arts are not set.

FIG. 16 is a flowchart of the placement possibility determination processing shown in step 1504 of FIG. First, it is determined whether or not an unprocessed cluster C exists (step 1601), and the processes from step 1602 are performed until there is no unprocessed cluster. If there is an unprocessed cluster, it is determined whether or not the op can be arranged in the current arrangement area (step 1602). If placement is not possible, the process proceeds to step 1601 to try placement in the next cluster. If the determination in step 1602 is Yes, it is determined in step 1603 that placement is possible, and the process ends.
When the determination in step 1602 is No, placement is not possible in all clusters, so it is determined in step 1604 that placement is not possible, and the process ends.

FIG. 17 is a flowchart of the instruction arrangement position determination processing (21) shown in step 1506 of FIG. The instruction arrangement position determination process (21) determines an arrangement position of a given instruction op in a given arrangement area <p, C>. Hereinafter, the procedure will be described. First, op
Is set to E (step 17).
01). Next, it is determined whether or not op is a common expression deletion related intermediate language node (1702). This determination can be made easily from the belonging common expression number column 515 of E. If it is a common expression deletion-related intermediate language node, the common expression table entry CE is obtained from the belonging common expression column 515 of E (step 1703), and the common expression set CE is obtained from the common expression set column.
S is obtained (step 1704).

Next, it is determined whether or not there is an unprocessed set element cese in the CES (step 1705). If so, it is checked whether or not the cese has been arranged (step 170).
6). This determination as to whether or not the allocation has been completed can be easily made based on whether or not the allocation cluster number column of the instruction allocation table 51 is blank. If cese has been arranged, the arrangement cluster is set to cls (step 1707), and it is checked whether or not cls matches the arrangement determination cluster C (step 170).
8). If they match, it is determined that the arrangement on C is inappropriate,
(Step 1709), and the process ends. If the comparison of all the placed instructions with the placed clusters is completed in step 1705, C is recorded in the placed cluster column of E (step 1710), and then placed in C (step 1711). To end. If it is determined in step 1702 that the node is not a common expression deletion-related intermediate language node, the assignment cluster determination result is determined as “suitable” (step 1711), and the process ends.

FIG. 12 shows the intermediate language 3 shown in FIG.
2 and the common expression information table shown in FIGS. 10 and 11 as inputs, and is an example of the configuration of an instruction arrangement table showing the results of performing the processing from FIG. 13 to FIG. Entries 5181 to 5184 in FIG. 12 show the instruction arrangement statuses of the common expressions 4273 to 4276 in the instruction node table shown in FIG. It can be seen that the arrangement cluster number columns of these entries 5181 to 5184 are all different. FIG. 7 shows the intermediate language 32 shown in FIG.
And the common expression information table shown in FIG. 10 and FIG. 11 as input, and is an example of the intermediate language 53 showing the result of performing the processing from FIG. 13 to FIG. In this intermediate example,
It can be seen that the intermediate language nodes recognized as common expressions are all arranged in different clusters. This concludes the description of the present embodiment. Next, the effect of the embodiment of the present invention will be described first in order to compare with the conventional technique.

FIG. 18 is a flowchart showing the procedure of the conventional instruction scheduling process. FIG. 18 shows a conventional procedure of the processing of FIG. 15 according to one embodiment of the present invention. Here, steps 1501 and 1 in FIG.
Step 502 is omitted as a matter of course. Step 1503 in FIG. 15 corresponds to step 0801 in FIG. First, schedule information of the intermediate language op is set (step 1801), and it is determined whether or not there is an unprocessed cluster (step 1802). If there is an unprocessed cluster, p is incremented (step 1803), and after expanding the arrangement area, the scheduling process is continued from step 1801 onward. If there is an unprocessed cluster C in step 1802, it is determined whether or not it can be arranged in the current arrangement area (step 1804). If not, the process proceeds to step 1802 to continue the processing. If it is determined in step 1804 that the DEST cluster can be arranged (step 1805), the op-position DEST cluster is set as the arrangement cluster C (step 1806), and the process ends.

FIG. 19 is an intermediate language diagram showing the result of the instruction scheduling process in the prior art shown in FIG. Although the number of execution cycles is 9 in the instruction scheduling result, the number of execution cycles is 6 in the scheduling result of the embodiment of the present invention shown in FIG. According to the present embodiment, the parallelism of the execution instructions can be improved by the instruction scheduling using the common expression deletion information, and the processing performance of the object program can be improved.

(Second Embodiment) Next, a second embodiment of the present invention will be described. In the second embodiment, the target architecture of the compiler is slightly different from that in the first embodiment. That is, the designation of the DEST cluster designated by the instruction destination is such that the same operation result can be transferred to all clusters, and c.
Specify as a = a + b. “Ca” on the left side indicates that the operation result c of the operation “a + b” on the right side is transferred to all clusters. In general, the entire cluster area of the DEST cluster is specified for a variable that is expected to be frequently used in the entire program (hereinafter, referred to as a common variable). The common variable is generally selected based on the role of the variable, such as the argument of a function or the head address of an array. Note that most of the processing in the second embodiment, the table configuration, and the like are the same as those in the first embodiment, and therefore, only the outline will be described below.

FIG. 20 shows a second embodiment of the present invention in which all cluster targets of common expression variables are designated.
10 is a flowchart showing the procedure of DEST cluster determination processing in step 1507 of FIG. First, it is determined whether or not op is a common expression deletion related intermediate language (step 200).
1) If it is, the process proceeds to step 2002, and it is determined whether or not op is a common expression calculation result definition instruction (step 2002). This determination can be easily made by referring to the common expression deleted intermediate language conversion column 516 of the instruction arrangement table 51. If op is a common expression operation result definition instruction, the DEST cluster of op is set as the entire area cluster (step 2003), and the process ends. When No is determined in step 2002, normal DEST cluster setting processing (equivalent to the prior art) is performed in step 2004 and thereafter. That is, DES of op
The T variable is set to D (step 2004), and it is determined whether or not D is a common variable (step 2005). If D is a common variable, the DEST cluster is set to an entire cluster (step 2003). If it is not a common variable, DEST
Let the cluster be an op placement cluster (step 200
6), end the process.

FIG. 21 is a diagram showing an example of an intermediate language after instruction scheduling showing a scheduling result when all cluster targets of the common expression variables are designated according to the second embodiment of the present invention. It is assumed that b is a function argument and is a common variable. The number of processing cycles in FIG. 21 is five.

FIG. 22 is a flowchart showing a conventional instruction scheduling procedure, and shows a conventional instruction scheduling procedure in the same architecture as the second embodiment of the present invention. Note that since the processing is the same as step 2004 and subsequent steps in FIG. 20, the description of the processing procedure is omitted. FIG. 23 is a diagram showing an example of an intermediate language after instruction scheduling showing the result of instruction scheduling according to the prior art, and shows a conventional instruction scheduling procedure in the same architecture as the second embodiment of the present invention. The whole-area cluster designation of the DEST cluster is performed only for b as an argument. It can be seen that the number of execution cycles in FIG. 23 is nine, which is later than the case in FIG. In the present embodiment, the DEST cluster determination processing using the common expression deletion information can improve the degree of parallelism of the execution instructions, and can contribute to the improvement in the processing performance of the object program.

[0047]

As described above, according to the present invention,
The compiler can perform instruction scheduling using the information on common expression deletion. Since this information on common expression deletion is information useful for instruction scheduling processing, the processing performance can be improved. In particular, compilers targeting a cluster configuration architecture can contribute to improving the processing performance of object programs because more efficient instruction scheduling is possible when arranging instruction clusters and specifying destination clusters for operation results. Can be.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a computer system on which a compiler embodying the present invention operates.

FIG. 2 is a flowchart illustrating a processing procedure of a compiler that implements the present invention.

FIG. 3 is a flowchart of a compiler common expression deletion process (6) and an instruction scheduling process (2) according to the first embodiment of the present invention.

FIG. 4 is a functional configuration diagram of a common expression deletion process (6) and an instruction scheduling process (2) of the compiler according to the present invention.

FIG. 5 is a diagram showing an example of an intermediate language according to the present invention (a configuration example of the intermediate language 31 before deleting a common expression).

FIG. 6 is a diagram showing an example of an intermediate language according to the present invention (a configuration example of the intermediate language 32 after removing a common expression).

FIG. 7 is a diagram showing an example of an intermediate language (an example of an intermediate language 33 after instruction scheduling) according to the present invention.

FIG. 8 is a diagram showing a configuration example of a common expression table 41 in FIG. 4;

9 is a diagram showing a configuration example of an instruction node table 42 in FIG.

FIG. 10 is a diagram showing an example of a common expression table 41 after common expression deletion in FIG. 4;

11 is a diagram illustrating an example of an instruction node table after a common expression is deleted in FIG. 4;

FIG. 12 is a diagram showing a configuration example of an instruction arrangement table 51 in FIG. 4;

FIG. 13 is a flowchart of a common expression registration process (61) in FIG.

FIG. 14 is a diagram illustrating a common expression deleted intermediate language conversion process (6) in FIG.
It is a flowchart of 2).

FIG. 15 is a flowchart of an instruction scheduling process (2) in FIG. 4;

FIG. 16 is a flowchart of an instruction placement possibility determination process in FIG. 4;

FIG. 17 is an instruction arrangement position determination process (21) in FIG. 4;
It is a flowchart of FIG.

FIG. 18 is a flowchart of an instruction arrangement position determination process in the related art.

FIG. 19 is a diagram showing an example of an intermediate language indicating a scheduling result in the related art.

FIG. 20 is a flowchart of a DEST cluster determination process (22) showing the second embodiment of the present invention.

FIG. 21 is a diagram illustrating an intermediate language 33 indicating a scheduling result according to the second embodiment of the present invention.

FIG. 22 is a flowchart of a DEST cluster determination process of the related art.

FIG. 23 is a configuration diagram of an intermediate language 33 showing a second embodiment of the present invention.

[Explanation of symbols]

101 CPU, 102 display device, 103
Keyboard, 104 main storage device, 105 external storage device, 106 source program, 107 object program, 108 compiler, 3 intermediate language, 4 common expression information table, 5 scheduling information table, 31 common expression Intermediate language before deletion, 32: Intermediate language after common expression deletion, 33: Intermediate language after scheduling, 41: Common expression table, 42: Instruction node table, 51: Instruction arrangement table.

Claims (5)

[Claims] 1. Analyzing an arithmetic expression represented by a program,
For a common expression recognition step of recognizing a common expression when commonization is possible,
A compiling method including a common expression deleting step of replacing a first operation result with a subsequent operation expression, and an instruction scheduling step of arranging an instruction group constituting a program under an instruction arrangement constraint of a predetermined target architecture. Wherein the instruction scheduling step includes a step of referring to information of the common expression deleted by the common expression deletion step, and a step of selecting a scheduling method depending on whether or not the common expression deletion has been performed. A featured common expression recognition type instruction scheduling method. 2. A method according to claim 1, wherein said target architecture has a cluster which is a processing unit having independent operation means and storage means capable of communicating with each other. Wherein the instruction scheduling step includes a step of performing a clustering process of allocating instructions to clusters, and the selection of the scheduling method based on the common expression deletion information is the selection of a clustering method. Expression-aware instruction scheduling method. 3. The common expression recognition type instruction scheduling method according to claim 2, wherein the instruction clustering step directs instructions whose common expression has been deleted using the common expression deletion information to different cluster arrangements. A common expression recognition type instruction scheduling method, characterized in that: 4. The common-expression-recognition-type instruction scheduling method according to claim 1, wherein the common-expression deletion information includes common-expression-operation-result-variable-information that performs the same operation a plurality of times. A common expression recognition type instruction scheduling method, comprising: common expression operation result replacement information indicating a plurality of operation groups to be replaced with an expression operation result variable. 5. The common type recognition type instruction scheduling method according to claim 2, wherein the selection of the scheduling method based on the common type deletion information is a selection of an inter-cluster data transfer method, and the selection of the inter-cluster data transfer method is an instruction. Is a selection of a destination cluster indicating a storage cluster of the calculation result of the above, and a cluster configuration architecture having an entire cluster transfer that is a simultaneous transfer of data to all clusters as a means of intercommunication between clusters provided in the target architecture. A common type recognition type instruction scheduling method, characterized in that the destination cluster selection candidate includes an entire cluster transfer.