JP2001159809A - Mask pattern designing device, mask pattern designing method and computer-readable recording medium storing mask pattern design program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the yield of a semiconductor integrated circuit manufacturing process. SOLUTION: This device has a pattern matching section 111 which determines the shape of a correction pattern for suppressing the fluctuation in the shape or dimensions of a transfer pattern to be added to (deleted from) a mask pattern in accordance with the shape of the mask pattern to be designed, a correction function forming section 112 which forms a correction function indicating the relation between the distance between the mask pattern and the adjacent patterns and the dimensions of the correction pattern, and a mask data correction section 113 which determines the shape and dimensions of the correction pattern to be added to (deleted from) the mask pattern by using the information relating to the shape of the correction pattern and correction function information and corrects the mask pattern by adding (or deleting) the correction pattern to (or from) the mask pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mask pattern designing apparatus, a mask pattern designing method, and a computer readable recording medium storing a mask pattern designing program for designing a mask pattern used for manufacturing a semiconductor integrated circuit. The present invention relates to a technique for efficiently correcting a mask pattern, thereby reducing variations in the shape and dimensions of a transfer pattern generated using the mask pattern, and improving the yield of a semiconductor integrated circuit manufacturing process.

[0002]

2. Description of the Related Art In recent years, in a manufacturing process of a semiconductor integrated circuit, a process proximity effect (Process Proximit) in which the shape or size of a transfer (or drawing) pattern formed using a mask pattern is changed by the influence of a pattern in the vicinity thereof.
y Effects: PPE (hereinafter referred to as PPE) is a major problem. If the shape and dimensions of the transfer pattern change due to the influence of the PPE, it becomes difficult for the integrated circuit to operate in accordance with the design specifications, and the yield of the integrated circuit manufacturing process is reduced. It is now one of the most important issues in the integrated circuit manufacturing process.

[0003] From such a background, recently, at the stage of designing a mask pattern, a process of adding a correction to a mask pattern in anticipation of a change in a transfer pattern has been actively performed.

[0004] For mask pattern design processing in which a change in a transfer pattern due to PPE is anticipated, two systems, a rule-based system and a simulation-based system, have been proposed and used. Here, these two methods will be briefly described.

[0005] The former rule-based method is generally called a one-dimensional correction method, and the correction amount for a mask pattern is as follows.
The change amount of the transfer pattern is approximated and predicted from the correlation graph of the adjacent distance of the mask pattern and the change amount of the pattern width obtained by the experiment.
This is performed in combination with a command such as an RC (Design Rule Checker) tool.

On the other hand, the latter simulation method is generally called a two-dimensional correction method, and uses a suitable function to determine the size and shape fluctuation of a transfer pattern due to PPE during a lithography process or the like. And a correction amount for the mask pattern is calculated back and extracted from the simulation result.

As described above, at present, in the manufacturing process of a semiconductor integrated circuit, a mask pattern design process taking into account a change in a transfer pattern by PPE is one of very important processes.

[0008]

However, there are the following technical problems to be solved in the conventional mask pattern design processing in consideration of the change of the transfer pattern due to the influence of PPE.

The first problem is that it is difficult to correct a mask pattern having a complicated configuration in the conventional rule-based mask pattern design processing. That is, as described above, since the rule-based method is a method for correcting a mask pattern based on one dimension, it cannot cope with a method requiring two-dimensional correction. If complicated correction is required even if the dimension is not so high, the correction rule becomes very complicated, so the labor and time required for the mask pattern design processing become enormous, and the mask for reducing the influence of the PPE is reduced. It is difficult to generate patterns efficiently.

The second problem is that the mask pattern processing of the conventional simulation method is different from the rule-based method.
Since it is a dimensional correction method, it can cope with complicated mask pattern correction, but it is necessary to execute a simulation for a two-dimensional mask pattern every time correction processing is performed, and it is necessary for mask pattern design processing. Effort and time are enormous than the rule-based method described above,
Correction processing for a full chip is almost impossible.
Therefore, similarly to the rule-based method, it is also difficult to efficiently generate a mask pattern that reduces the influence of PPE.

As described above, the conventional mask pattern design processing in consideration of the change of the transfer pattern by the PPE
A great deal of effort and time is required to generate a mask pattern that reduces the effects of E, and it is difficult to generate a mask pattern that reduces the effects of PPE. As a result, the yield of the semiconductor integrated circuit manufacturing process increases. Had been reduced.

The present invention has been made in view of such technical problems, and an object of the present invention is to efficiently generate a mask pattern in which the influence of PPE is reduced and improve the yield of a semiconductor integrated circuit manufacturing process. Another object of the present invention is to provide a mask pattern designing apparatus for causing the mask pattern to be designed.

Another object of the present invention is to provide a mask pattern designing method for efficiently generating a mask pattern in which the influence of PPE is reduced and improving the yield of a semiconductor integrated circuit manufacturing process.

Still another object of the present invention is to provide a computer-readable recording program storing a mask pattern design program for efficiently generating a mask pattern with reduced influence of PPE and improving the yield of a semiconductor integrated circuit manufacturing process. To provide a medium.

[0015]

SUMMARY OF THE INVENTION In order to solve the above technical problems, the inventor made a library of correction pattern shapes to be applied to a mask pattern for each mask pattern shape, and designed a mask pattern. Determines a correction pattern for a mask pattern with reference to a correction function and a library indicating the relationship between the shape of the mask pattern and the dimension of the correction pattern, and adds (or deletes) the determined correction pattern to the mask pattern, thereby obtaining a PPE Has been found to be able to efficiently generate a mask pattern in which the influence of the above is reduced, and to improve the yield of the semiconductor integrated circuit manufacturing process.

A first feature of the present invention is that in a mask pattern designing apparatus for designing a mask pattern used for manufacturing a semiconductor integrated circuit, the mask pattern is corrected based on the shape of the designed mask pattern. A pattern matching unit that determines the shape of a correction pattern for correcting variations in dimensions and dimensions, a correction function generation unit that generates a correction function indicating the relationship between the distance between a mask pattern and an adjacent pattern and the dimensions of the correction pattern, A mask including a mask data correction unit that corrects a mask pattern by correcting a mask pattern by determining a shape and a dimension of a correction pattern for correcting a mask pattern using information on a shape of the mask pattern and correction function information. It is a pattern design device.

According to this configuration, it is possible to efficiently generate a mask pattern in which the influence of PPE is reduced, and to improve the yield of the semiconductor integrated circuit manufacturing process.

A second feature of the present invention is that in a mask pattern designing method for designing a mask pattern used for manufacturing a semiconductor integrated circuit, the mask pattern is corrected based on the shape of the designed mask pattern. Pattern matching step for determining the shape of a correction pattern for correcting variations in dimensions and dimensions; a correction function generating step for generating a correction function indicating the relationship between the distance between the mask pattern and the adjacent pattern and the dimensions of the correction pattern; A mask having a mask data correcting step of correcting the mask pattern by correcting the mask pattern by determining the shape and dimension of the correction pattern for correcting the mask pattern using the information on the shape of the mask pattern and the correction function information; It is a pattern design method.

According to this configuration, it is possible to efficiently generate a mask pattern in which the influence of PPE is reduced, and to improve the yield of the semiconductor integrated circuit manufacturing process.

A third feature of the present invention is that, in a computer-readable recording medium storing a mask pattern design program for designing a mask pattern used for manufacturing a semiconductor integrated circuit, a mask is designed based on the shape of the designed mask pattern. A pattern matching process for correcting a pattern, determining the shape of a correction pattern for correcting a variation in the shape and dimensions of a transfer pattern, and generating a correction function indicating a relationship between a distance between a mask pattern and an adjacent pattern and a dimension of the correction pattern. By using the correction function generation processing to perform the correction pattern information and the correction function information and the correction function information, the shape and dimensions of the correction pattern for correcting the mask pattern are determined, and the mask pattern is corrected by the correction pattern. And a mask data correction process for correcting Lies in a computer-readable recording medium which stores a mask pattern design program for executing management to the computer.

According to this configuration, it is possible to efficiently generate a mask pattern in which the influence of PPE is reduced, and to improve the yield of the semiconductor integrated circuit manufacturing process.

Here, the pattern matching process is preferably performed with reference to a library describing the relationship between the shape of the mask pattern and the shape of the correction pattern.

Thus, the shape of the correction pattern with respect to the mask pattern can be quickly determined.
A mask pattern in which the influence of PPE is reduced can be efficiently generated.

Further, it is desirable that the mask pattern is divided into a plurality of regions, and that each processing is performed on a region including the outer periphery of the mask pattern in the divided regions.

Thus, since the correction process is not performed on a mask pattern portion that does not require the correction process, an efficient mask pattern design process can be performed even on a full-chip mask pattern.

The computer readable recording medium includes a semiconductor memory, a magnetic disk, an optical disk,
It is preferable to use a magneto-optical disk, a magnetic tape, or the like.

The correction function may be obtained experimentally, or a process simulation may be used.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to FIGS. 1 to 17, a mask pattern designing apparatus according to an embodiment of the present invention will be described.
The mask pattern designing method and the computer readable recording medium storing the mask pattern designing program will be described in detail.

First, the configuration of a mask pattern designing apparatus according to an embodiment of the present invention will be described with reference to FIG.

The mask pattern designing apparatus 110 according to the embodiment of the present invention is connected to an integrated circuit manufacturing apparatus 123 for manufacturing an integrated circuit based on a generated mask pattern so as to realize an efficient integrated circuit manufacturing process. In this manner, the integrated mask manufacturing system 100 is constructed, the input mask data is divided, and a correction type (shape of a correction pattern) is assigned to each of the divided mask data by referring to the database 120. A correction function generation unit for executing a process simulation using the test data and extracting a correction function indicating a relationship between an adjacent distance of the mask pattern and a correction amount (dimension of the correction pattern) based on a result of the process simulation; Compensation assigned to each of the divided mask data A mask data correction unit 113 that corrects the mask data by determining a correction pattern for each of the divided mask data using the type information and the correction function information and adding (or deleting) the determined correction pattern to the mask data. Have.

Here, the pattern matching unit 111
A mask data dividing unit 111a for dividing the input mask data; a division for extracting coordinate values, intersection numbers, and vertex numbers of intersections between the divided mask data (hereinafter, referred to as divided figures) and the divided meshes as divided figure information The correction type determination unit 111c that determines the correction type for each divided figure with reference to the graphic information extraction unit 111b, the database 120, and the divided figure information, and determines the distance s to the adjacent pattern and the pattern width w of the divided figure itself for each divided figure. It has a distance information extracting means 111d for extracting as distance information.

The correction function generator 112 performs a process simulation on the test pattern, evaluates the shape and dimensional change of the transfer pattern, a process simulation means 112a, and calculates the values of the size of the mask pattern and the size of the transfer pattern. The variation amount extraction means 112b extracts a function (see FIG. 11A) indicating the relationship between the variation amount and the adjacent distance s, which is a difference between the test amounts, converts the relationship between the variation amount and the adjacent distance s, and corrects the correction value. There is provided a correction function determining unit 112c for determining a correction function (see FIG. 11B) indicating the relationship between d and the adjacent distance s.

Further, the mask data correction unit 113 extracts a correction value d using the correction type, distance information and correction function information, and determines a dimension of the correction type, thereby generating a correction pattern. Means 11
3a, a correction mask data generation unit 113b that adds (or deletes) the generated correction pattern to each of the divided figures and then outputs a mask pattern obtained by integrating the divided figures as correction mask data.

The processes in the pattern matching unit 111, the correction function generation unit 112, and the mask data correction unit 113 are independent of each other, and are configured to be able to execute parallel processing. Thereby, the mask pattern design processing speed can be significantly improved.

Further, the mask pattern designing apparatus 110
A database 121 storing various data and libraries related to mask pattern design, an input unit 121 for inputting various input data and control parameters related to mask pattern design processing, and outputting various output information such as correction mask data and error output. It is connected to the output unit 122.

Next, a mask pattern designing process according to the embodiment of the present invention will be described with reference to FIG.

When performing the mask pattern design processing according to the embodiment of the present invention, (1) first, mask data described in a GDS format or the like is input to the input unit 121 (mask data input step, S201). ).

(2) Next, the pattern matching unit 111
In, the input mask data is divided, and a correction type is assigned to each of the divided figures including the outer periphery of the original mask data with reference to the database 120 (pattern matching step, S202).

(3) Subsequently, a process simulation is performed for each process step using the test pattern, and a correction function indicating the relationship between the adjacent distance of the mask pattern and the correction amount is extracted based on the result of the process simulation (correction). Function generation step, S203).

(4) Next, the shape and size of the correction pattern for each of the divided figures are determined using the correction type information and the correction function information, and the correction pattern is added (or deleted) to each of the divided figures. Then, a mask pattern obtained by integrating the divided figures is output as correction mask data (mask data correction step, S204).

(5) Subsequently, the correction mask data is output to the integrated circuit manufacturing apparatus 123 (correction mask data output step, S205).

(6) Finally, in the integrated circuit manufacturing apparatus 123, an integrated circuit is manufactured using the corrected mask data (integrated circuit manufacturing step, S206).

Next, the pattern matching processing, the correction function generation processing, and the mask data correction processing will be described in detail with reference to FIGS.

The pattern matching processing according to the embodiment of the present invention is as follows: (2-1) First, the mask data dividing means 111a divides the input mask data (mask data dividing step, S301). In the mask pattern design processing according to the present embodiment, the mask pattern 71a,
As shown in FIG. 7A, a rectangular mesh (=
(Divided mesh) 70. The dividing process is not limited to the rectangular mesh, but may be performed using, for example, a triangular mesh.

It is desirable that the rectangular mesh is generated by any of the following rules or a combination of these rules. Specifically, a mesh may be generated by combining the following rules (a) and (b).

(A) The length of one side of the mesh is set within the design rule, specifically, within the SPACE rule of the target layer so that adjacent mask patterns are not mixed.

(B) As shown in FIG. 8A, the figure cut out by the rectangular mesh is made to fall within 5 to 10 types of ranges (optimal ranges). In this case, when cutting the mesh, the length of one side is gradually increased from 0, and the length of the mesh when it reaches the optimum range is defined as the length of one side of the mesh.

(C) As shown in FIG. 8B, a rectangular mesh centering on the vertex of the mask pattern is generated, and the length of one side of the rectangular mesh is within the design rule.

(D) As shown in FIG.
In addition to the rectangular mesh at the vertices generated in (b),
A rectangular mesh is also generated adjacent to a straight line location, and the length of one side of the rectangular mesh is within the design rule. In addition,
At this time, leave the area where the rectangular mesh overlaps,
The processing described below is similarly applied to the overlapping portion.

(2-2) Next, divided figure information extracting means 1
In step 11b, for each of the divided figures including the outer periphery of the mask pattern, as shown in FIG. 7B, the coordinate value of the intersection with the divided mesh, the number of intersections, and the number of vertices are extracted as divided figure information (divided figure information). Extraction step, S30
2).

(2-3) Subsequently, the correction type determining means 1
11c, the divided graphic information and the database 12
0, a correction type (correction pattern shape) for each divided figure is determined (correction type determination step,
S303). Here, in the database 120, FIG.
As shown in (1), information on a correction type to be added to or deleted from a mask pattern is registered in a library for each shape of a divided figure. Therefore, when determining the correction type, a search is performed to determine which shape of the mask pattern shown in FIG. 9 the divided figure corresponds to based on the divided figure information, and the correction type corresponding to the corresponding divided figure is output. To In the example of the correction type shown in FIG. 9, the shapes of the divided figures are (a) fringe, (b) contact,
(C) Angle (270 °), (d) Angle (90 °), (e) Axis parallel / vertical line, (f) Oblique line, (g) Oblique angle / Acute angle section However, this is only the minimum necessary, and the user can appropriately replenish it appropriately according to the shape of the mask pattern to be designed.

(2-4) Next, the distance information extracting means 111
In d, the distance s to the adjacent pattern and the pattern width w of the divided figure itself are extracted as distance information for each divided figure (distance information extraction step, S304). Here, the distance s from the adjacent pattern and the pattern width w of the divided figure itself
The definition will be described. First, the distance s to the adjacent pattern is defined as a vertical distance (s0, s1) to the adjacent pattern closest to the divided figure, as shown in FIG. 10A. Note that, when the divided figures are tangled with oblique lines, the figures may not face each other as shown in FIG. 10B. Is the distance s. If there is no adjacent pattern, the distance s
Is ∞. On the other hand, the pattern width w is basically the distance (w0, w1) between directly facing sides in the pattern as shown in FIG. As a method of measuring the distance s and the pattern width w, for example, a scanning method in which a scanning line is scanned from a pattern end to a pattern end may be used.

As the distance information, in addition to the vertical distance (s0, s1) to the adjacent pattern, a distance in an oblique direction of 45 ° may be given as shown in FIG.

Further, as shown in FIG. 11B, a 3 × 3 area is set around the rectangular mesh which has been cut.
A (or 5 × 5) mesh is generated, and the surrounding mesh is set to 1 (with an adjacent pattern) or 0 (no adjacent pattern) according to whether or not there is an adjacent pattern in the generated mesh.
And these 1 and 0 may be used for the subsequent fluctuation amount extraction processing.

(2-5) Finally, the correction type and the distance information (the distance s from the adjacent pattern and the pattern width w of the own pattern) are stored for each divided figure (save processing step, S30).
5).

Next, the correction function generation processing according to the embodiment of the present invention will be described.

The correction function generation processing according to the embodiment of the present invention is performed by the following steps.

(3-1) First, information on a test pattern is input as test data to the process simulation means 112a (test data input step, S401). Here, the test data corresponds to FIG.
As shown in FIG. 5, the pattern is configured such that adjacent patterns are arranged around the mask pattern 10 from which the variation amount of the transfer pattern is to be extracted, and a plurality of combinations of the pattern width w and the distance s are prepared. . Note that the configuration of the test pattern may be appropriately added in addition to the three types shown in FIG.

Specifically, as shown in FIG. 11A, the vertical distances (s0, s
In addition to 1), when a distance of 45 ° is given,
As shown in FIG. 13A, the distance information ((s0, s1, s2), (w0,
Data obtained by assigning each value of w1)) may be used as test data.

When a pattern (256 patterns) in which 1 or 0 of a 3 × 3 mesh is prepared as shown in FIG. 11B, the center rectangular mesh is 5 to 5.
It has 10 variations (see Fig. 8 (a))
Since there are 256 (2 8) test patterns for each of these, these test patterns may be used as test data. In the case of a 5 × 5 mesh, 16,777,216 test patterns are used as test data.

(3-2) Next, in the process simulation means 112a, a process simulation is performed on the input test data, and the shape and dimensional change of the transfer pattern are evaluated for each of the plurality of test patterns. Process simulation execution step, S402). Here, the process simulation is performed using a general process simulation technique that analyzes using various physical equations.

(3-3) Subsequently, the fluctuation amount extracting means 112
In FIG. 14B, for each test pattern, as shown in FIG. 14A, a function indicating the relationship between the amount of variation, which is the difference between the size of the mask pattern and the size of the transfer pattern, and the adjacent distance s is calculated by means such as the least square method. (Variation amount extraction step, S403).

(3-4) Finally, the correction function determining means 11
In 2c, for each test pattern, a function indicating the relationship between the amount of variation and the adjacent distance s is converted, and a correction function indicating the relationship between the correction value d and the adjacent distance s is determined as shown in FIG. Correction function determination step, S404).

Next, the mask data correction processing according to the embodiment of the present invention will be described.

The mask data correction processing according to the embodiment of the present invention is performed by the following steps.

(4-1) First, using the correction type, distance information and correction function information, a correction value d which is a parameter for determining the size of the correction type for each divided figure.
(Correction value determination step, S501). Specifically, first, a function corresponding to the divided graphic is selected from a plurality of correction functions according to the value of the pattern width w of the divided graphic, and then, the adjacent distance, which is the distance between the divided graphic and the adjacent pattern, is selected. s is inputted, and the size (correction value d) of the correction type of the divided figure is determined.

(4-2) Next, a correction pattern is generated by introducing the correction value d to the correction type of each divided figure and determining the dimensions of the correction type (correction pattern generation step, S502). Here, the size of the correction type in the direction orthogonal to the correction value d is determined so as to maintain the shape ratio (the ratio of the length of the side) of the correction type before deformation.

As shown in FIG. 8B, when a rectangular mesh centering on the vertices of the mask pattern is generated, the one-dimensional OP
C processing (bucket method or model simulation method)
To generate a correction pattern.

(4-3) Finally, the generated correction pattern is added (or deleted) to the divided figures, and then the divided figures are integrated and output as correction mask data (correction mask data generation step, S503). .

Here, a simple experimental example of the mask data correction processing according to the embodiment of the present invention will be described.

FIG. 15 shows that the divided figure has a corner (90 °) (FIG. 9).
It is a mimetic diagram for explaining mask pattern design processing in case of shape of (d)). The pattern width w of the divided figure is w0, w1, and the distance s corresponding to each pattern width w.
Are s0 and s1.

When the correction type for the divided figure is determined with reference to the database 120 (FIG. 15).
(A)), the correction functions (w0, s0), (w1, s1)
And the correction values d0 and d1 that are the magnitudes of the correction types
Is derived. Next, since the size of the correction type is determined, the correction type is deformed so as to correspond to the correction values d0 and d1, and a correction pattern is generated (FIG. 15B). The pattern 12b is output. As a result, a mask pattern in which the influence of PPE is reduced can be efficiently generated, and the yield of the semiconductor integrated circuit manufacturing process can be improved.

Here, an application example of the mask pattern design processing according to the embodiment of the present invention will be described with reference to FIG.

In this application example, first, in addition to the test pattern shown in FIG. 10, a process simulation is performed by the same method for all the mask patterns shown in FIG. After obtaining the relational expression of the adjacent distance s, a plot diagram showing the relationship between the correction pattern and the adjacent distance shown in FIG. 12A is generated (each plot in the plot diagram includes the distance s of the divided figure and the pattern width). w and information on the shape and dimensions of the correction pattern, and plot information is stored in the database 120). Subsequently, when performing the pattern matching process, the plot information registered in the database 120 is searched in the order of the shape of the divided figure, the pattern width w, and the distance s to obtain the plot corresponding to the divided figure to be corrected. To determine. That is, the divided figure to be corrected using the information on the divided figure is the divided figure shown in FIG.
Is determined (P1 in this example), and the correction pattern indicated by the plot P1 is added (or deleted) to the divided figure (see FIG. 16B) to perform the correction processing. Complete. Here, since a plot corresponding to the distance s of the divided figure does not always exist, in that case, the plot closest to the distance s is selected.

According to this application example, since the shape and size of the correction pattern for the divided figure are determined at a time,
Higher-speed and higher-accuracy mask pattern design processing in which the influence of PPE is reduced is enabled.

In the above description, the size of the correction pattern in the direction orthogonal to the correction value d is determined by the shape ratio of the correction type registered in advance, but the shape of the correction pattern falls within the mesh. In this manner, the size of the correction pattern is determined by the derived correction value.
Only the portions (d0 ', d1') indicated by arrows in (a) may be variable. That is, the appropriate magnification (k0, k1) obtained from the correction function is calculated as (d0 ′,
d1 ′) and the size of the correction pattern (d0, d1)
The size of the correction pattern in the direction orthogonal to the correction value d is made to match the mesh (see FIG. 17B). Accordingly, it is possible to prevent adjacent correction patterns from overlapping each other, and to prevent an unnecessary step from being generated at a mesh boundary.

The above is the description of the mask pattern designing apparatus and method according to the embodiment of the present invention.
Mask pattern designing apparatus 11 according to an embodiment of the present invention
0 has an appearance like the configuration shown in FIG. 6, for example.
That is, the mask pattern designing apparatus 110 according to the embodiment of the present invention is configured by incorporating each element of the mask pattern designing apparatus 110 in the computer system 60. The computer system 60 includes a floppy (registered trademark) drive 61 and an optical disk drive 63. Then, the floppy disk drive 61
By inserting a floppy disk 62 into the optical disk drive 63 and an optical disk 64 into the optical disk drive 63 and performing a predetermined read operation, the document classification program stored in these recording media can be installed in the computer system 60. Can be. Further, by connecting a predetermined drive device, for example, installation and reading / writing of data can be executed using a ROM 65 serving as a memory device and a cartridge 66 serving as a magnetic tape device.

The mask pattern designing apparatus 110 according to the embodiment of the present invention may be programmed and stored in a computer-readable recording medium. Then, when performing the planning support process, the recording medium is read into a computer system, the program is stored in a storage unit such as a memory in the computer system, and the mask pattern design program is executed by an arithmetic unit, thereby realizing the present invention. Mask pattern designing apparatus and method can be realized. Here, the recording medium includes, for example, a computer-readable recording medium capable of recording a program such as a semiconductor memory, a magnetic disk, an optical disk, a magneto-optical disk, and a magnetic tape.

Further, when a mask pattern designing process is performed at a higher speed, (1) a region where mask correction is to be performed (or a region not to be processed) in input data is locally limited, and (2) mask correction is performed. Information such as removing shapes that do not need to be corrected (for example, oblique lines) from the correction target, and (3) limiting (or removing) a pattern having a pattern width that requires (or does not need) mask correction as a correction target is input. By inputting from the unit 121, useless correction can be avoided and faster mask pattern design processing can be performed.

As described above, it is to be fully understood that the present invention includes various embodiments and the like not described herein. Therefore, the present invention must be limited only by the matters specifying the invention according to the claims that are reasonable from this disclosure.

[0081]

As described above, according to the mask pattern designing apparatus of the present invention, even for a complicated mask pattern, it is possible to efficiently perform correction in consideration of the PPE in the mask pattern at the mask pattern designing stage. Since it can be added, the yield of the semiconductor integrated circuit manufacturing process can be improved. In addition, since the correction process is not performed on a mask pattern portion that does not require the correction process,
Efficient mask pattern design processing can be performed on a full-chip mask pattern.

Further, according to the mask pattern designing method of the present invention, even in the case of a complicated mask pattern, it is possible to efficiently correct the mask pattern in consideration of the PPE at the mask pattern designing stage. It is possible to improve the yield of the integrated circuit manufacturing process. In addition, since the correction process is not performed on a mask pattern portion that does not require the correction process, an efficient mask pattern design process can be performed even on a full-chip mask pattern.

Further, according to the computer-readable recording medium storing the mask pattern design program of the present invention, even in the case of a complicated mask pattern, it is possible to efficiently correct the mask pattern in consideration of the PPE in the mask pattern designing stage. Therefore, the yield of the semiconductor integrated circuit manufacturing process can be improved. In addition, since the correction process is not performed on a mask pattern portion that does not require the correction process, an efficient mask pattern design process can be performed even on a full-chip mask pattern.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a mask pattern designing apparatus according to an embodiment of the present invention.

FIG. 2 is a flowchart illustrating a mask pattern designing method according to an embodiment of the present invention.

FIG. 3 is a flowchart illustrating a pattern matching process according to the embodiment of the present invention.

FIG. 4 is a flowchart illustrating a correction function generation process according to the embodiment of the present invention.

FIG. 5 is a flowchart illustrating a mask data correction process according to the embodiment of the present invention.

FIG. 6 is a diagram showing an overview of a mask pattern designing apparatus according to an embodiment of the present invention.

FIG. 7 is a schematic diagram for explaining mask data division processing and division graphic information extraction processing according to the embodiment of the present invention.

FIG. 8 is a schematic diagram for explaining mask data division processing according to the embodiment of the present invention.

FIG. 9 is a schematic diagram for explaining a correction type determination process according to the embodiment of the present invention.

FIG. 10 is a schematic diagram for explaining distance information extraction processing according to the embodiment of the present invention.

FIG. 11 is a schematic diagram for explaining distance information extraction processing according to the embodiment of the present invention.

FIG. 12 is a schematic diagram showing a configuration of a test pattern according to the embodiment of the present invention.

FIG. 13 is a schematic diagram showing a configuration of a test pattern according to the embodiment of the present invention.

FIG. 14 is a schematic diagram for explaining a variation extraction process and a correction function determination process according to the embodiment of the present invention.

FIG. 15 is a schematic diagram for explaining a correction pattern generation process and a correction mask data generation process according to the embodiment of the present invention.

FIG. 16 is a schematic diagram for explaining a modification of the mask pattern designing method according to the embodiment of the present invention.

FIG. 17 is a schematic diagram for explaining a modification of the mask pattern designing method according to the embodiment of the present invention.

[Explanation of symbols]

10, 12a, 12b, 13, 14 Mask pattern 15 mesh 60 Computer system 61 Floppy drive 62 Floppy disk 63 Optical disk drive 64 Optical disk 65 ROM 66 Cartridge 70, 90 Mesh 71, 71a, 71b, 91, 91a, 91b Mask pattern 100 Integration Circuit manufacturing system 110 Mask pattern design device 111 Pattern matching unit 111a Mask data division unit 111b Divided figure information extraction unit 111c Correction type determination unit 111d Distance information extraction unit 112 Correction function generation unit 112a Process simulation unit 112b Variation amount extraction unit 112c Correction function Determination means 113 Mask data correction unit 113a Correction pattern generation means 113b Correction mask data generation means Reference Signs List 120 database 121 input unit 122 output unit 123 integrated circuit manufacturing apparatus

Claims (9)

[Claims] 1. A mask pattern designing apparatus for designing a mask pattern used for manufacturing a semiconductor integrated circuit, comprising: correcting a mask pattern based on a shape of the designed mask pattern; A pattern matching unit that determines the shape of the correction pattern for correction, a correction function generation unit that generates a correction function indicating the relationship between the distance between the mask pattern and the adjacent pattern, and the size of the correction pattern, and the shape of the correction pattern. A mask data correction unit that determines the shape and dimensions of a correction pattern for correcting the mask pattern using the information and the information of the correction function, and corrects the mask pattern by correcting the mask pattern with the correction pattern. And a mask pattern designing apparatus. 2. The mask pattern designing apparatus according to claim 1, wherein the pattern matching unit performs the pattern matching by referring to a library describing a relationship between the shape of the mask pattern and the shape of the correction pattern. 3. The pattern matching section divides the mask pattern into a plurality of regions, corrects the mask pattern based on the shape of the divided mask pattern, and corrects variations in the shape and dimensions of a transfer pattern. The mask pattern designing apparatus according to claim 1, wherein the shape of the correction pattern is determined. 4. A mask pattern designing method for designing a mask pattern used for manufacturing a semiconductor integrated circuit, comprising: correcting a mask pattern based on a shape of the designed mask pattern; A pattern matching step of determining a shape of a correction pattern for generating a correction function indicating a relationship between a distance between the mask pattern and an adjacent pattern and a dimension of the correction pattern; and a shape of the correction pattern. A mask data correcting step of determining the shape and dimensions of a correction pattern for correcting the mask pattern using the information and the information of the correction function, and correcting the mask pattern by correcting the mask pattern with the correction pattern. A mask pattern comprising: Design method. 5. The method according to claim 4, wherein the pattern matching step is performed with reference to a library describing a relationship between the shape of the mask pattern and the shape of the correction pattern. 6. The method according to claim 4, wherein the mask pattern is divided into a plurality of regions, and each of the steps is performed on a region including an outer periphery of the mask pattern in the divided regions. Item 6. A mask pattern designing method according to Item 5. 7. A computer-readable recording medium storing a mask pattern design program for designing a mask pattern used for manufacturing a semiconductor integrated circuit, wherein the mask pattern is corrected based on the shape of the designed mask pattern. A pattern matching process for determining the shape of a correction pattern for correcting variations in pattern shape and dimensions, and a correction function generation for generating a correction function indicating a relationship between a distance between the mask pattern and an adjacent pattern and a dimension of the correction pattern. Processing, using the information on the shape of the correction pattern and the information on the correction function, determine the shape and size of the correction pattern for correcting the mask pattern, and correct the mask pattern with the correction pattern, Mask data correction processing to correct the mask pattern And
A computer-readable recording medium storing a mask pattern design program for causing a computer to execute these processes. 8. The computer-readable storage medium according to claim 7, wherein the pattern matching process is performed with reference to a library describing a relationship between a shape of the mask pattern and a shape of the correction pattern. A computer-readable recording medium in which is stored. 9. The method according to claim 7, wherein the mask pattern is divided into a plurality of regions, and each of the steps is performed on a region including an outer periphery of the mask pattern in the divided regions. Item 9. A computer-readable recording medium storing the mask pattern design program according to Item 8.