JP2001157735A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine wherein each control means can surely receive commands from a game control means. SOLUTION: The voltage of a +30 V power source to which a power source monitoring IC901 outputs a signal is preset to be the same as the voltage of a +30 V power source to which a power source monitoring IC931 outputs a signal and the same kind of IC is used as the power source monitoring IC901 and IC931. Therefore, when the voltage of the power source is decreasing, NMI cuts in prize ball controlling CPU371 of a prize ball controling substrate 37 at the same time as NMI cuts in CPU56 of a main substrate 31. In response to the interruption by NMI, each CPU stops its usual control, that is, CPU56 of the main substrate 31 and the prize ball controlling CPU371 shut down at the same time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a game machine such as a pachinko game machine, a coin game machine, a slot machine, etc., in which a game is played in accordance with a player's operation. A gaming machine in which a game is played in accordance with a game machine.

[0002]

2. Description of the Related Art As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium wins a winning area such as a winning opening provided in the game area, a predetermined number of prize balls are obtained. Are paid out to players.
Furthermore, a variable display unit capable of changing the display state is provided,
There is a configuration in which a predetermined game value is provided to a player when a display result of the variable display unit has a predetermined specific display mode.

[0003] The game value means that the state of the variable prize ball device provided in the game area of the gaming machine is in an advantageous state for a player who is likely to win a hit ball, or in an advantageous state for the player. Or a condition in which the conditions for paying out prize game media are easily satisfied.

In a pachinko gaming machine, when a display result of a variable display section for displaying a special symbol is a combination of a predetermined specific display mode, it is generally called a "big hit". When a big hit occurs, for example, the big winning opening is opened a predetermined number of times, and the state shifts to a big hit game state in which a hit ball is easy to win. In each open period, a predetermined number (for example, 10
) Will be closed when there is a prize in the special winning opening.
The number of opening of the special winning opening is a predetermined number (for example, 16
Round). An opening time (for example, 29.5 seconds) is determined for each opening, and if the opening time elapses even if the number of winnings does not reach a predetermined number, the winning opening is closed. Further, at the time when the special winning opening is closed, predetermined conditions (for example, winning in the V zone provided in the special winning opening)
Is not established, the big hit gaming state ends.

[0005] In addition, among the combinations of display modes other than the "big hit" combination, at a stage where some of the display results of the plurality of variable display portions have not been derived and displayed yet, the display results have already been derived and displayed. The state in which the display mode of the variable display unit that satisfies the display condition that is a combination of the specific display modes is called “reach”. If the display result of the identification information variably displayed on the variable display unit does not satisfy the condition of “reach”, the result is “out” and the variable display state ends. A player plays a game while enjoying how to generate a big hit.

The progress of the game in the gaming machine is controlled by game control means such as a microcomputer. The identification information, the character image, and the background image displayed on the variable display device are controlled by display control means operating according to display control command data from the game control means.
The identification information, the character image, and the background image displayed on the variable display device generally include a display control microcomputer and a video display processor (FIG. 1) that generates image data in accordance with instructions from the microcomputer and transfers the image data to the variable display device side. VDP), and the display control microcomputer has a large program capacity.

Therefore, the microcomputer of the game control means, which has a limited program capacity, cannot control the identification information and the like displayed on the variable display device, and is different from the microcomputer of the game control means for display control. A microcomputer (display control means) is used. Therefore, the game control means for controlling the progress of the game needs to transmit a command for display control to the display control means.

In such a gaming machine, a speaker is provided on the game board, and various sound effects are emitted from the speaker as the game progresses in order to enhance the game effect. Further, a light emitting body such as a lamp or an LED is provided on the game board, and these light emitting bodies are turned on or off as the game progresses in order to enhance the game effect. Generally, sound control for generating a sound effect and timing control of lamp lighting / extinguishing are performed by game control means for controlling the progress of the game. Therefore, it is necessary for the game control means to transmit a command to the sound control means or the lamp control means for actually generating sound or driving the lamp / LED.

In general, a player rents out a game medium via a game machine. In that case, a gaming medium lending mechanism is provided in the gaming machine. Since the progress of the game is controlled by the game control means mounted on the main board, the number of winning balls based on the winning is determined by the game control means and transmitted to the payout control board.

As described above, the gaming machine is equipped with various control means in addition to the game control means. Then, the game control means for controlling the progress of the game transmits each command indicating an operation instruction according to the game situation to each control means mounted on each control board. Hereinafter, each control means mounted on each control board other than the game control board may be referred to as an electric component control means. Further, a board other than the game control board may be called an electric component control board.

[0011]

When the power supply to the gaming machine is stopped, the drive voltage (for example, +5 V) for driving each control means gradually decreases. Each control unit generally includes a microcomputer, but the voltage at which each control unit becomes inoperable is different due to variations in elements and the like. When transmitting a command from the game control means to each control means, from the viewpoint of preventing unauthorized signal input to a game control board on which the game control means is mounted, it is configured not to take a response from each control means. I have. Then, for example, even though the game control means has transmitted the command immediately before the power supply to the gaming machine is stopped, the control means on the side receiving the command may have already become inoperable.
In this case, the game control means recognizes that the command has been transmitted, but the control means on the side receiving the command has not received the command. In that case, in general, the driving voltage is lost, the game control means and other control means do not operate, and thereafter, when the power is turned on again, the game is reset, so that there is often no problem.

However, when an unexpected power failure such as a power failure occurs, necessary data is stored in a power supply backup RAM, and the stored data is restored when the power is restored to restart the game. This is a problem when configured. For example, the payout control means stores the number of prize balls instructed by the game control means in the backup RAM, and continues the prize ball payout based on the number of prize balls stored when the power is restored after the power is turned off. If so,
It is conceivable that the payout control means did not receive the instruction even though the game control means issued a predetermined number of prize ball payout instructions immediately before the power-off. In this case, even if the payout control means resumes the prize ball payout based on the memory after the power is restored, a smaller number of prize balls are paid out than the number of prize balls to be paid out. That is, a disadvantage is given to the player.

[0013] In addition to the payout control means, a situation arises in which the other control means cannot receive the command even though the game control means has transmitted the command immediately before power-off. After power restoration, the control state may fall into an undesirable state. For example, after the power is restored, there is a possibility that a display state or an utterance state that should not appear originally may occur. Furthermore, even when the power is turned on, despite the game control means sending a command,
If other control means are not ready to receive, there is a possibility that the command may be missed.

Therefore, an object of the present invention is to provide a gaming machine in which each control means can reliably receive a command from the game control means.

[0015]

A gaming machine according to the present invention comprises:
A gaming machine capable of playing a predetermined game by a player, comprising: a game control means for controlling a progress of the game; and a payout control means for performing a payout control of a game medium used for the game, at least a game control. For the means and the payout control means, the stop condition of the game progress control and the stop condition of the payout control relating to the power state are the same.

The game control means and the payout control means perform predetermined power supply stop processing when the power supply is stopped, and provide a power supply state and payout control means for causing the game control means to start the power supply stop processing. May be configured to be the same as the power supply state for starting the power supply stop processing.

Power supply monitoring means for monitoring a predetermined potential power supply used in the gaming machine and outputting a detection signal when a detection condition is satisfied, wherein the game control means and the payout control means are adapted to detect the detection signal from the power supply monitoring means. The power supply stop processing may be performed accordingly.

The game control means and the payout control means may be configured to execute a power supply stop processing in an interruption processing when receiving a detection signal of the power supply monitoring means.

The game control board is provided with a storage means capable of retaining the contents immediately before the power supply is stopped for a predetermined time even when the power supply is cut off by the backup power supply, and the storage means is provided when the power supply is restored. It may be configured such that information necessary for restoring a gaming state is held.

The storage means capable of holding the contents immediately before the power supply is stopped may be included in the game control means. That is, the storage means is, for example, a memory (RA) built in the game control microcomputer.
M).

The dispensing control board on which the dispensing control means is mounted is provided with a storage means capable of retaining the contents immediately before the power supply is stopped for a predetermined time even when the power supply is cut off by the backup power supply, and When the power supply is restored, information necessary for restoring the payout state may be held.

The storage means capable of holding the contents immediately before the power supply is stopped may be included in the payout control means. That is, the storage means is, for example, a memory (RA) built in the payout control microcomputer.
M).

The game control board and the payout control board are provided with initial reset means for outputting a reset signal to the game control means and the payout control means, and the reset signal from the initial reset means is delayed to be transmitted to the game control means. A delay means for supplying may be provided.

The game control board and the payout control board are provided with initial reset means for outputting a reset signal to the game control means and the payout control means, and are used to generate a reset signal in the initial reset means of the game control board. The capacity of the capacitor may be larger than the capacity of the capacitor for generating the reset signal in the initial reset means of the payout control board.

The game control board and the payout control board are provided with initial reset means for outputting a reset signal to the game control means and the payout control means, and the game control means executes a predetermined program when the power-on reset is released. The initial reset means in the game control board and the initial reset means in the payout control board may have the same configuration.

[0026]

An embodiment of the present invention will be described below with reference to the drawings. First, the overall configuration of a pachinko gaming machine, which is an example of a gaming machine, will be described. 1 is a front view of the pachinko gaming machine 1 as viewed from the front, FIG. 2 is an overall rear view showing the internal structure of the pachinko gaming machine 1, and FIG. 3 is a rear view of the mechanical board of the pachinko gaming machine 1 as viewed from the back. Here, a pachinko gaming machine is shown as an example of a gaming machine, but the present invention is not limited to a pachinko gaming machine, and may be, for example, a coin gaming machine. Further, the present invention can be applied to an image-type gaming machine or a slot machine.

As shown in FIG. 1, the pachinko gaming machine 1 comprises:
It has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2, there is a hit ball supply tray 3. Below the hitting ball supply tray 3, a surplus ball receiving tray 4 for storing prize balls overflowing from the hitting ball supply tray 3 and a hitting operation handle (operation knob) 5 for firing a hitting ball are provided. Behind the glass door frame 2,
The game board 6 is detachably attached. A game area 7 is provided on the front of the game board 6.

In the vicinity of the center of the game area 7, a variable display section 9 for variably displaying a plurality of types of symbols and a 7-segment L
A variable display device 8 including a variable display 10 using an ED is provided. In this embodiment, the variable display section 9 has three symbol display areas of “left”, “middle”, and “right”. On the side of the variable display device 8, a passing gate 11 for guiding a hit ball is provided. The hit ball that has passed through the passing gate 11 is guided to the starting winning opening 14 via the ball exit 13. In a passage between the passage gate 11 and the ball outlet 13, there is a gate switch 12 for detecting a hit ball that has passed through the passage gate 11. In addition, the winning ball that entered the starting winning port 14 is
It is guided to the back of the game board 6 and is detected by the starting port switch 17. In addition, a variable winning ball device 15 that performs opening and closing operations is provided below the starting winning port 14. The variable winning ball device 15 is opened by the solenoid 16.

Below the variable winning ball device 15, there is provided an opening / closing plate 20 which is opened by a solenoid 21 in a specific game state (big hit state). In this embodiment, the opening and closing plate 20 serves as a means for opening and closing the special winning opening. The winning ball that enters one (V zone) of the winning balls guided from the opening / closing plate 20 to the back of the game board 6 is detected by the V count switch 22. The winning ball from the opening / closing plate 20 is detected by the count switch 23. Variable display device 8
A start winning prize storage display 18 having four display sections for displaying the number of winning balls entering the starting winning prize port 14 is provided below. In this example, the start winning prize storage display 18 increases the number of lit display units by one each time there is a starting prize, with the upper limit being four. Then, each time the variable display of the variable display unit 9 is started, the number of the lit display units is reduced by one.

The game board 6 is provided with a plurality of winning ports 19 and 24, and the winning of the game balls to the winning ports 19 and 24 is detected by the winning port switches 19a and 24a. At the left and right sides of the game area 7, there are provided decorative lamps 25 which are displayed blinking during the game, and at the lower part there is an out port 26 for absorbing hit balls which have not won. In addition, two speakers 27 that emit sound effects are provided at upper left and right sides outside the game area 7. A gaming effect LED 2 is provided on the outer periphery of the gaming area 7.
8a and gaming effect lamps 28b and 28c are provided.

In this example, one of the speakers 27
Is provided with a prize ball lamp 51 which is lit when a prize ball is paid out, and a ball out lamp 52 which is lit when a supply ball is out is provided near the other speaker 27. Further, FIG. 1 also shows a card unit 50 which is installed adjacent to the pachinko gaming table 1 and enables lending of a ball by inserting a prepaid card.

The card unit 50 has a usable indicator lamp 151 for indicating whether or not the card can be used. If there is a fraction (less than 100 yen) in the balance information recorded in the card, the fraction is displayed. Fraction display switch 1 for displaying on a frequency display LED provided near hit ball supply tray 3
52, a connecting stand direction indicator 15 indicating which side of the pachinko gaming machine 1 the card unit 50 corresponds to
3. Card insertion indicator 154 indicating that a card has been inserted into card unit 50, card insertion slot 155 into which a card as a recording medium is inserted, and a card reader provided on the back of card insertion slot 155 A card unit lock 156 is provided to release the card unit 50 when checking the mechanism of the writer.

The hit ball fired from the hitting ball launching device enters the game area 7 through the hitting ball rail, and thereafter, the game area 7
Come down. When a hit ball is detected by the gate switch 12 through the passage gate 11, the display number of the variable display 10 is changed continuously. Further, when a hit ball enters the starting winning opening 14 and is detected by the starting opening switch 17, the symbol in the variable display section 9 starts rotating if the symbol can be changed. If it is not possible to start changing the symbol, the start winning memory is increased by one.

The rotation of the image in the variable display section 9 stops when a certain time has elapsed. If the combination of images at the time of stop is a combination of big hit symbols, the game shifts to a big hit game state. That is, the opening / closing plate 20 is opened until a predetermined time elapses or until a predetermined number (for example, 10) of hit balls is won. Then, when a hit ball wins in the specific winning area while the opening and closing plate 20 is opened and is detected by the V count switch 22, a continuation right is generated and the opening and closing plate 20 is opened again. Generation of the continuation right is permitted a predetermined number of times (for example, 15 rounds).

If the combination of images in the variable display section 9 at the time of stoppage is a combination of big hit symbols accompanied by a probability change, the probability of the next big hit increases. That is, a high probability state, which is more advantageous for the player, is obtained. Also, when the stop symbol on the variable display 10 is a predetermined symbol (hit symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the high probability state, the probability that the stop symbol on the variable display 10 hits the symbol is increased, and the opening time and the number of times the variable winning ball device 15 is opened are increased.

Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. On the back of the variable display device 8, as shown in FIG. 2, a prize ball tank 38 is provided above the mechanism plate 36, and when the pachinko gaming machine 1 is installed on the gaming machine installation island, a prize ball is provided from above. Premium ball tank 3
8 is supplied. The prize ball in the prize ball tank 38 reaches the ball payout device through the guide gutter 39.

On the mechanism board 36, a variable display control unit 29 for controlling the variable display section 9 via the relay board 30, and a game control board (main board) covered with a board case 32 and mounted with a game control microcomputer and the like. ) 31, a relay board 33 for relaying a signal between the variable display control unit 29 and the main board 31, and a prize ball control board on which a prize ball control microcomputer for performing payout control of prize balls is mounted. A payout control board) 37 is provided. Further, below the mechanism plate 36, a hitting ball firing device 34 for shooting a hitting ball into the game area 7 using the rotating force of a motor, a game effect lamp / LEDs 28a, 28b, 28c, a prize ball lamp 51
In addition, a lamp control board 35 for sending a signal to the burnout lamp 52 is provided.

FIG. 3 is a rear view of the mechanical panel of the pachinko gaming machine 1 as viewed from the rear. The ball that passed through the induction gutter 39
As shown in FIG. 3, the ball cut detectors 187a, 187
b, and reaches the ball dispensing device 97 via the ball supply gutters 186a and 186b. The prize ball paid out from the ball payout device 97 is supplied to the hit ball supply tray 3 provided on the front surface of the pachinko gaming machine 1 through the communication port 45. On the side of the communication port 45, an excess ball passage 46 communicating with the excess ball tray 4 provided on the front of the pachinko gaming machine 1 is formed. A large number of prize balls based on the prize are paid out, and the ball supply tray 3 becomes full. Finally, after the prize balls reach the communication port 45, further prize balls are paid out. It is led to the ball tray 4. When the prize ball is further paid out, the sensing lever 47 is set to the full switch 4.
By pressing 8, the full tank switch 48 is turned on. In this state, the rotation of the stepping motor in the ball discharging device 97 stops, the operation of the ball discharging device 97 stops, and the driving of the hitting ball firing device 34 also stops as necessary.

Signals from the winning opening switches 19a and 24a, the starting opening switch 17 and the V count switch 22 are sent to the main board 31 in order to perform the prize ball payout control.
When the starting port switch 17 is turned on, the CPU 56 of the main board 31 knows that a winning corresponding to the payout of six winning balls has occurred. Further, when the count switch 23 is turned on, it is known that a winning corresponding to the payout of 15 prize balls has occurred. Then, when the winning opening switch is turned on, it is known that a winning corresponding to the payout of 10 prize balls has occurred. In this embodiment, for example, a game ball that has won the winning opening 24 is detected by the winning opening switch 24 a provided in the winning ball flow path from the winning opening 24, and the game ball that has won the winning opening 19 is detected. Is
It is detected by a winning opening switch 19a provided in a winning ball flow path from the winning opening 19.

FIG. 4 is a block diagram showing an example of a circuit configuration of the main board 31. FIG. 4 also shows the prize ball control board 37, the lamp control board 35, the sound control board 70, the emission control board 91, and the display control board 80. On the main board 31, a basic circuit 53 for controlling the pachinko gaming machine 1 according to a program, a gate switch 12,
The starting port switch 17, the V count switch 22, the count switch 23, the full switch 48, the cut-out switches 187a and 187b (hereinafter sometimes referred to as the cut-out switch 187), and the winning opening switches 19a and 2
Switch circuit 5 for applying a signal from 4a to basic circuit 53
And a solenoid 16 for opening and closing the variable winning ball device 15 and a solenoid 21 for opening and closing the opening and closing plate 20.
A solenoid circuit 59 driven in accordance with a command from 3;
The start memory display 18 is turned on and off, and 7
Variable display 10 and decorative lamp 2 by segment LED
5 is provided.

In accordance with the data supplied from the basic circuit 53, jackpot information indicating the occurrence of a jackpot, effective start information indicating the number of start winning balls used to start image display on the variable display section 9, and probability fluctuation have occurred. And an information output circuit 64 that outputs probability change information or the like indicating the fact to a host computer such as a hall management computer.

The basic circuit 53 includes a ROM 54 for storing a game control program and the like, a RAM 55 used as a work memory, a CPU 56 for performing a control operation in accordance with the control program, and an I / O port unit 57. In this embodiment, the ROM 54 and the RAM 55 are
6 is built in. That is, the CPU 56 is a one-chip microcomputer. The one-chip microcomputer only needs to include at least the RAM 55, and the ROM 54 and the I / O port unit 57 may be externally provided.

Further, the main board 31 has an initial reset circuit 65 for resetting the basic circuit 53 when the power is turned on.
And an address decode circuit 67 that decodes an address signal provided from the basic circuit 53 and outputs a signal for selecting one of the I / O ports in the I / O port unit 57. Although there is switch information input from the ball dispensing device 97 to the main board 31, FIG.
Then they are omitted.

A hit ball launching device that hits and launches a game ball is driven by a drive motor 94 controlled by a circuit on a launch control board 91. Then, the driving force of the driving motor 94 is adjusted according to the operation amount of the operation knob 5. That is, the circuit on the firing control board 91 is controlled so that the hit ball is fired at a speed corresponding to the operation amount of the operation knob 5.

FIG. 5 shows the circuit configuration in the display control board 80 by using the CRT 82 as an example of the variable display section 9 and the output ports (ports A and B) 571 and 572 of the main board 31.
FIG. 9 is a block diagram shown together with an output buffer circuit 63. The output port 571 outputs 8-bit data, and the output port 572 outputs a 1-bit strobe signal (INT signal).

The display control CPU 101 controls the control data R
It operates according to the program stored in the OM 102, and receives a display control command via the input buffer circuit 105 when a strobe signal is input from the main board 31 via the noise filter 107 and the input buffer circuit 105. As the input buffer circuit 105, for example, a general-purpose IC
74HC244 can be used. In addition,
When the display control CPU 101 does not include an I / O port, the input buffer circuit 105 and the display control CP
An I / O port is provided between U101.

Then, the display control CPU 101 controls display of a screen displayed on the CRT 82 in accordance with the received display control command. Specifically, a command corresponding to the display control command is given to the VDP 103. VDP103
Reads necessary data from the character ROM 86. The VDP 103 generates a CRT 8 according to the input data.
2 is generated, and the image data is stored in the VRAM 87. Then, the image data in the VRAM 87 is converted into R, G, B signals, converted into analog signals by the DA converter 104, and output to the CRT 82.

FIG. 5 also shows a reset circuit 83 for resetting the VDP 103, an oscillation circuit 85 for supplying an operation clock to the VDP 103, and a character ROM 86 for storing frequently used image data. The frequently used image data stored in the character ROM 86 is, for example, a person, an animal, or an image composed of characters, graphics, or symbols displayed on the CRT 82. In this embodiment, the display control C
PU 101 is a one-chip microcomputer,
At least a RAM is built-in.

The input buffer circuit 105 can pass signals only in the direction from the main board 31 to the display control board 80. Therefore, there is no room for a signal to be transmitted from the display control board 80 side to the main board 31 side. Display control board 80
Even if the internal circuits are modified illegally, the signal output by the illegal modification is not transmitted to the main board 31 side. The outputs of the output ports 571 and 572 may be output to the display control board 80 as they are. However, by providing the output buffer circuit 63 capable of transmitting a signal in only one direction, the output from the main board 31 to the display control board 80 is provided. One-way signal transmission can be further ensured. Further, for example, a three-terminal capacitor or a ferrite bead is used as the noise filter 107 that cuts off a high-frequency signal. However, even if noise is present between display control commands between substrates due to the presence of the noise filter 107, the effect is eliminated. Is done.

FIG. 6 is a block diagram showing an example of the configuration of the voice control command signal transmitting portion of the main board 31 and the voice control board 70. In this embodiment, according to the progress of the game, the voice control command for instructing the voice output of the speaker 27 provided outside the game area 7 is:
It is output from the main board 31 to the voice control board 70.

As shown in FIG. 6, the voice control command is
The data is output from output ports (output ports C and D) 573 and 574 of the I / O port unit 57 in the basic circuit 53.
8-bit data is output from the output port 573,
A 1-bit strobe signal (I
NT signal) is output. In the voice control board 70,
Each signal from the main board 31 is input to the audio control CPU 701 via the input buffer circuit 705. When the audio control CPU 701 does not include an I / O port, the input buffer circuit 705 and the audio control CPU 7
01, an I / O port is provided. In this embodiment, the voice control CPU 701 is a one-chip microcomputer and has at least a RAM.

The voice synthesizing circuit 702 using, for example, a digital signal processor is
The sound and the sound effect corresponding to the instruction 01 are generated and output to the volume switching circuit 703. The volume switching circuit 703 sets the output level of the voice control CPU 701 to a level corresponding to the set volume and outputs the output level to the volume amplification circuit 704. The volume amplification circuit 704 outputs the amplified audio signal to the speaker 27.

As the input buffer circuit 705, for example,
74HC244 which is a general-purpose CMOS-IC is used. A low level (GND level) is always applied to the enable terminal of the 74HC244. Therefore, the output level of each buffer is the input level, that is, the main board 31.
Signal level has been determined. Therefore, there is no room for a signal to be transmitted from the voice control board 70 side to the main board 31 side.
Therefore, even if the circuit in the voice control board 70 is tampered with, the signal output by the tampering is transmitted to the main board 31.
It does not reach the side. Note that the input buffer circuit 705
, A noise filter may be provided on the input side.

In the main board 31, the output port 5
A buffer circuit 67 is provided outside of 74 and 575. As the buffer circuit 67, for example, a general-purpose CMOS
-74HC244 which is IC is used. The enable terminal is always given a low level (GND level). According to such a configuration, since a signal input from the outside to the inside of the main board 31 is blocked, a signal line to which a signal may be supplied from the voice control board 70 to the main board 31 is more reliably eliminated. be able to.

FIG. 7 is a block diagram showing a signal transmitting / receiving portion in the main board 31 and the lamp control board 35.
In this embodiment, a game effect LED 28a and a game effect lamp 28b provided outside the game area 7 are provided.
A lamp control command indicating ON / OFF of 28c and ON / OFF of the award ball lamp 51 and the ball out lamp 52 is output.

As shown in FIG. 7, the lamp control command relating to the lamp control is output from the output ports (output ports E, F) 575, 5 of the I / O port unit 57 in the basic circuit 53.
76. The output port 575 outputs 8-bit data, and the output port 576 outputs a 1-bit strobe signal (INT signal). Lamp control board 35
In, the control command from the main board 31 is input to the lamp control CPU 351 via the input buffer circuit 355. When the lamp control CPU 351 does not include an I / O port, the input buffer circuit 355
An I / O port is provided between the CPU and the lamp control CPU 351. In this embodiment, the lamp control CPU 351 is a one-chip microcomputer and has at least a RAM.

On the lamp control board 35, the CPU 351 for lamp control includes a game effect LED 28a and a game effect lamp 28 defined according to each control command.
b, 28c, the game effect L
A light-on / light-off signal is output to the ED 28a and the game effect lamps 28b and 28c. The light-on / light-off signal is output from the game effect LED 28a and the game effect lamps 28b and 28c.
Is output to The light-on / light-off pattern is stored in a built-in ROM or an external ROM of the lamp control CPU 351.

On the main board 31, the CPU 56 outputs a control command for instructing lighting of a prize ball lamp at the time of a prize ball,
When a ball-out detection sensor installed on the game ball supply path on the back of the game board is turned on, a control command for instructing the ball-out lamp to be turned on is output. In the lamp control board 35, each control command is input to the lamp control CPU 351 via the input buffer circuit 355. Lamp control CPU3
51 is a prize ball lamp 5 according to those control commands.
1 and the ball out lamp 52 are turned on / off.

As the input buffer circuit 355, for example,
74HC244 which is a general-purpose CMOS-IC is used. A low level (GND level) is always applied to the enable terminal of the 74HC244. Therefore, the output level of each buffer is the input level, that is, the main board 31.
Signal level has been determined. Therefore, there is no room for a signal to be transmitted from the lamp control board 35 side to the main board 31 side. For example, even if a circuit in the lamp control board 35 is tampered with, a signal output by the tampering is not transmitted to the main board 31 side. Note that a noise filter may be provided on the input side of the input buffer circuit 355.

In the configuration shown in FIG. 7, it is possible to eliminate a signal line from which a signal may be supplied from the lamp control board 35 to the main board 31. That is, the unidirectionality of the signal from the main board 31 to the lamp control board 35 is ensured, and the possibility that the lamp control board 35 influences the game control on the main board 31 is eliminated. As a result, even if, for example, the lamp control board 35 is modified so as to give an illegal signal for causing a big hit to the basic circuit 53 of the main board 31, the illegal signal cannot be transmitted to the main board 31.

Further, on the main board 31, a buffer circuit 62 is provided outside the output ports 575, 576. As the buffer circuit 62, for example, a general-purpose CMO
74HC244 which is S-IC is used. The enable terminal is always given a low level (GND level). According to such a configuration, the main substrate 31 is externally provided.
Is prevented from being input to the main board 31, so that a signal line to which a signal may be given from the lamp control board 35 to the main board 31 can be more reliably eliminated.

In FIG. 7, the lamp control CPU 35 is used.
Signals for instructing the game effect LED 28a, the game effect lamps 28b and 28c, the prize ball lamp 51 and the ball out lamp 52 to be turned on or off are output from the internal output port 1 in practice. -A driver circuit is inserted between the LED and the LED.

FIG. 8 is a block diagram showing components related to the prize ball, such as the components of the prize ball control board 37 and the ball payout device 97. As shown in FIG. 8, the detection signal from the full tank switch 48 is transmitted to the main board 3 via the relay board 71.
1 is input to the I / O port 57. Full tank switch 4
Reference numeral 8 denotes a switch that detects whether the surplus ball tray 4 is full. The prize ball control CPU 371 mounted on the prize ball control board 37 constitutes a payout control means for performing a game ball payout control based on a winning and a game ball payout control based on a ball lending request.

The ball out switch 187 (187a, 187)
The detection signal from b) is transmitted to the relay board 72 and the relay board 7.
1 is input to the I / O port 57 of the main board 31. The out-of-ball detection switch 167 is a switch for detecting a shortage of replenishment balls in the prize ball tank 38, and the out-of-ball switch 187 is a switch for detecting the presence or absence of a prize ball in the prize ball passage.

The CPU 56 of the main board 31 determines whether the detection signal from the ball out switch 187 indicates that the ball is out.
Alternatively, when the detection signal from the full tank switch 48 indicates the full tank state, a prize ball control command for instructing ball lending prohibition is transmitted. When receiving the prize ball control command instructing the ball lending prohibition, the prize ball control CPU of the prize ball control board 37
Step 371 stops the ball lending process.

Further, a detection signal from the prize ball count switch 301A is also input to the I / O port 57 of the main board 31 via the relay board 72 and the relay board 71. A drive signal from the I / O port 57 of the main board 31 to the winning ball discharging solenoid 127 is supplied to the winning ball discharging solenoid 127 via the relay board 71. The prize ball count switch 301A is provided in the prize ball mechanism portion of the ball payout device 97, and detects an actually paid prize ball.

When a prize is won, the output ports (ports G, H) 577, 578 of the main board 31 are provided on the prize ball control board 37.
, A prize ball control command indicating the number of prize balls is input. The output port 577 outputs 8-bit data, and the output port 578 outputs a 1-bit strobe signal (INT signal). The award ball control command indicating the number of award balls is input to the I / O port 372a via the input buffer circuit 373. The CPU 371 for controlling the prize ball includes an I / O port 37.
A prize ball control command is input via 2a, and the ball payout device 97 is driven according to the prize ball control command to perform a prize ball payout. In this embodiment, the CPU 37 for controlling the prize ball
Reference numeral 1 denotes a one-chip microcomputer having at least a RAM.

Each buffer in the input buffer circuit 373 can pass a signal only in the direction from the main board 31 to the prize ball control board 37. Therefore, there is no room for a signal to be transmitted from the award ball control board 37 side to the main board 31 side. Even if the circuit in the prize ball control board 37 is tampered with, the signal output by the tampering is not transmitted to the main board 31 side. Note that a noise filter may be provided on the input side of the input buffer circuit 373.

On the main board 31, a buffer circuit 68 is provided outside the output ports 577 and 578 for outputting award ball control commands. According to such a configuration, since a signal input from the outside to the inside of the main board 31 is blocked, a signal line to which a signal may be given from the prize ball control board 37 to the main board 31 is more reliably formed. Can be eliminated.

The prize ball controlling CPU 371 outputs a ball lending number signal indicating the number of lending balls to the terminal board 160 and a buzzer driving signal to the buzzer board 75 via the output port 372g. A buzzer is mounted on the buzzer board 75. Further, an error signal is output to the error display LED 374 via the output port 372e.

Further, the input port 3 of the prize ball control board 37
The detection signal of the prize ball count switch 301A and the detection signal of the ball lending count switch 301B are input to 72b via the relay board 72. The ball lending count switch 301B detects a game ball actually lent. The drive signal from the prize ball control board 37 to the payout motor 289 is output from the payout motor 2 in the prize ball mechanism portion of the ball payout device 97 via the output port 372c and the relay board 72.
It is told to 89.

The card unit 50 is equipped with a microcomputer for controlling the card unit. Also,
The card unit 50 is provided with a fraction display switch 152, a connection board direction indicator 153, a card insertion indicator lamp 154, and a card insertion slot 155 (see FIG. 1). The balance display board 74 is connected to a frequency display LED, a ball lending switch, and a return switch provided near the hit ball supply tray 3.

From the balance display board 74 to the card unit 50
In response to the player's operation, a ball lending switch signal and a return switch signal are provided via the prize ball control board 37. In addition, the balance display board 74 is provided from the card unit 50.
, A card balance display signal indicating the balance of the prepaid card and a ball lending possible display signal are given via the prize ball control board 37. Between the card unit 50 and the prize ball control board 37, a unit operation signal (BRDY signal), a ball lending request signal (BRQ signal), a ball lending completion signal (EXS signal)
A pachinko machine operation signal (PRDY signal) is exchanged via the I / O port 372f.

When the power of the pachinko gaming machine 1 is turned on,
The prize ball control CPU 371 of the prize ball control board 37 outputs a PRDY signal to the card unit 50. When a card is accepted in the card unit 50 and the ball lending switch is operated to input a ball lending switch signal, the microcomputer for controlling the card unit outputs a BRDY signal to the prize ball control board 37. When a predetermined delay time elapses from this point, the microcomputer for controlling the card unit outputs a BRQ signal to the prize ball control board 37. The CPU 37 for controlling the prize ball on the prize ball control board 37
1 drives the payout motor 289 and pays out a predetermined number of lending balls to the player. Then, when the payout is completed, the prize ball controlling CPU 371 outputs an EXS signal to the card unit 50.

As described above, all signals from the card unit 50 are input to the prize ball control board 37. Therefore, regarding the ball lending control, the card unit 5
No signal is input from 0 to the main board 31, and there is no room for a signal to be incorrectly input from the card unit 50 side to the basic circuit 53 of the main board 31. Although the main board 31 and the prize ball control board 37 are provided with a solenoid and a driver circuit for driving a motor or a lamp, these circuits are omitted in FIG.

In this embodiment, at least the main substrate 3
At 1, a part of the RAM is backed up by a power supply. That is, even if the power supply to the gaming machine is stopped,
The data in the backup RAM area is saved. Also,
CPU 101 for display control, CPU 701 for voice control, CPU 351 for lamp control, and CPU 371 for award ball control
In this case, a part of the RAM may be configured to be backed up by a power supply.

FIG. 9 shows a main board 31, a display control board 80,
FIG. 3 is a block diagram showing a configuration around a CPU in a voice control board 70, a lamp control board 35, and a prize ball control board 37. In this example, the main board 31 and the CPU for controlling the prize ball
At 371, a part of the CPU built-in RAM is backed up by connecting a backup power supply to the backup terminal.

As shown in FIG. 9, on the main substrate 31,
The power supply monitoring IC 901 introduces a voltage of +30 V,
By monitoring the 0V voltage, the occurrence of power interruption is detected. Specifically, the voltage of +30 V is a predetermined value (for example, +22
V) When it becomes less than the above, an interrupt signal is given to the CPU 56 in order to notify that the power is cut off. CPU5
6, the interrupt is generated by a non-maskable interrupt (IN
T) terminal. The signal input to the NMI terminal is also input to an input port built in the CPU 56.

Although the predetermined value for the power supply monitoring IC 901 to detect the power-off is lower than the normal voltage, the CPU 56
Is a voltage that can operate for a while. Further, since the power supply monitoring IC 901 is configured to monitor a voltage higher than the voltage required by the CPU 56 (+5 V in this example) and immediately after conversion from AC to DC, the CPU 56 is required. It is possible to extend the monitoring range with respect to the voltage. Therefore, more precise monitoring can be performed. Further, when +30 V is used as the monitoring voltage, the voltage supplied to various switches of the gaming machine is +1.
Since it is 2 V, prevention of erroneous switch-on detection at the moment of a power interruption can be expected. That is, by monitoring the voltage of the +30 V power supply, it is possible to detect a decrease in the voltage of +12 V generated after the generation of +30 V before the voltage starts to drop. Therefore, when the voltage of the + 12V power supply decreases, the switch output comes to the on state. However, if the + 30V power supply voltage that drops faster than + 12V is monitored and the power cutoff is recognized, the power supply is turned on before the switch output turns on. It is possible to enter a state of waiting for restoration and to enter a state where the switch output is not detected.

In the prize ball control board 371, the power supply monitoring IC 931 detects the occurrence of power interruption by introducing a + 30V voltage and monitoring the + 30V voltage. Specifically, a predetermined value (for example, + 2V) in which the + 30V voltage is lower than the voltage at the time of detection of the power supply monitoring IC 901 described above.
2V) or less, an interrupt signal is given to the prize ball controlling CPU 371 in order to notify that the power is cut off. In the winning ball control CPU 371, this interrupt is input to a non-maskable interrupt (INT) terminal.
The signal input to the NMI terminal is a prize ball control CP.
It is also input to the input port built in U371.

In the configuration shown in FIG. 9, the output of the power supply monitoring IC is input to the NMI terminal of the CPU, but may be input to the maskable interrupt terminal (IRQ terminal). The output of the power monitoring IC is also input to the input port of the CPU, but may be input only to the interrupt terminal. Further, the voice control board 7
0, the lamp control board 35 and the display control board 80 also have the same power monitoring ICs 901 and 931 mounted thereon.
A configuration may be adopted in which a signal is given to each CPU when the + 30V voltage falls below a predetermined value.

In the configuration shown in FIG. 9, the voltage of the +30 V power supply at which power supply monitoring IC 901 outputs a signal is set to be the same as the voltage of the +30 V power supply at which power supply monitoring IC 931 outputs a signal. Have been. Also, as the power supply monitoring ICs 901 and 931, I
C is used. Therefore, when the power supply voltage decreases,
For the prize ball control CPU 371 of the prize ball control board 37,
An NMI interrupt is applied at the same timing as when the NMI interrupt is applied to the CPU 56 of the main board 31. As will be described later, since each CPU stops the normal control in accordance with the NMI, the game control means and the payout control means have the same game progress control stop condition and payout control stop condition related to the power state. .

Accordingly, the actual start timing of the NMI process is the same for the CPU 56 of the main board 31 and the CPU 371 for controlling the prize ball when there is no timing shift due to the variation of the power monitoring ICs 901 and 931. .
Then, the CPU 56 of the main board 31 and the CPU 3 for controlling the prize ball
At step 71, at substantially the same time, normal control processing is interrupted to start a predetermined processing when power is turned off (for example, processing for backing up the contents of the RAM).

Therefore, immediately before the power is turned off, the CP
The award ball control command sent by U56 is a CPU for award ball control.
There is no inconvenience that the message is not received at 371. For example, when the prize ball control CPU 371 interrupts the normal control process early and starts a predetermined process when the power is turned off, the prize ball control command sent by the CPU 56 of the main board 31 immediately before the power is turned off is used. It will not be received by the prize ball control CPU 371. However, such an inconvenience does not occur in this embodiment.

Further, the reset IC 6 is provided on the main board 31.
An initial reset circuit 65 including 51 is mounted. When detecting that +5 V rises when the power is turned on, the initial reset circuit 65 outputs a signal indicating reset release after a predetermined time (time determined by an external resistance value and a capacitor capacity). Further, the display control board 80, the audio control board 70, the lamp control board 35, and the prize ball control board 37
Also has a similar initial reset circuit. However, in FIG. 9, the reset IC in the prize ball control board 37 is used.
Only the initial reset circuit including 380 is shown.

In the structure shown in FIG. 9, the resistance value and the capacitance of the resistor and the capacitor in the initial reset circuit 65 of the main board 31 are the same as those of the resistor and the capacitor externally connected to the reset IC 380 of the other control board. Equal to resistance and capacitance. That is, they have the same configuration. Therefore, when the power of the gaming machine is turned on, the reset signals from the reset ICs 651 and 380 rise substantially simultaneously.

In the main board 31, the initial reset circuit 6
5 is input to the reset terminal of the CPU 56 via the delay circuit 655. Therefore, when the power is turned on, the CPU 56 of the main board 31
Get up later than U. The output of the delay circuit 655 is input to the reset terminal of the output port 570 via two gate circuits 656 and 657. The output port 570 is a port for sending a command to another board, and when the reset signal indicates a reset release state, the output port 570 enters an information output enabled state. Note that the output port 570 is
8 correspond to the output ports 571 to 578 shown in FIG.

Since the CPU 56 of the main board 31 rises later than the CPUs of all the other boards, the CPU 56 of the main board 31 waits for the completion of the startup of the CPUs of the other boards and becomes ready to receive commands. It becomes ready to send. Therefore, even if a command is sent from the game control unit to another electric component control unit immediately after the power is turned on, the command is reliably received by the other control unit.

In the configuration shown in FIG. 9, the power supply monitoring means for monitoring the power interruption is mounted on each board. For example, the power supply monitoring means is mounted on a power supply board which will be described later.
From there, a signal indicating a voltage drop may be supplied to each substrate.

FIG. 10 is a block diagram showing an example of the configuration of the power supply board 910. The power supply board 910 includes a main board 31,
The display control board 80, the voice control board 70, the lamp control board 35, and the control board such as the prize ball control board 37 are installed independently of each other, and generate voltages used by each control board and mechanical components in the gaming machine. In this example, AC24V, DC + 3
Generates 0V, + 21V DC, + 12V DC and + 5V DC. A capacitor 9 serving as a backup power supply
16 is charged from DC + 5V, that is, a power supply line for driving an IC or the like on each substrate.

The transformer 911 converts an AC voltage from an AC power supply to 24V. AC 24V voltage is applied to connector 9
15 is output. Further, the rectifier circuit 912 includes an AC24
A DC voltage of +30 V is generated from V and output to the DC-DC converter 913 and the connector 915. DC-D
The C converter 913 has + 21V, + 12V and + 5V.
V is generated and output to the connector 915. Connector 91
Reference numeral 5 is connected to, for example, a relay board, from which power of a voltage required for each control board and mechanical components is supplied.

+5 V from DC-DC converter 913
The line branches to form a backup + 5V line. A large-capacity capacitor 916 is connected between the backup + 5V line and the ground level. The capacitor 916 serves as a backup power supply for the backup RAM area in each control board when power supply to the gaming machine is cut off. Further, a diode 917 for preventing backflow is inserted between the + 5V line and the backup + 5V line.

Note that a battery that can be charged from a +5 V power supply may be used as a backup power supply. In the case of using a battery, a rechargeable battery is used which runs out of capacity when power is not supplied from a + 5V power supply for a predetermined time.

The second power supply monitoring circuit may be mounted on the main board and the electric component control board. The second power supply monitoring circuit is, for example, a first power supply monitoring circuit (power supply monitoring IC 90
1, 931) monitors a + 30V power supply voltage which is the same as the power supply voltage to be monitored, and generates a low-level voltage drop signal when the voltage value falls below a predetermined value. For example, the detection voltage of the first power supply monitoring circuit (the voltage at which a voltage drop signal is output) is set to +22 V, and the detection voltage of the second power supply monitoring circuit is set to +9 V.

Further, the voltage drop signal from the second power supply monitoring circuit is ORed with the initial reset signals from the reset ICs 651 and 380, and then inputted to the reset terminal of the CPU. Therefore, the CPU enters the reset state (non-operating state) when the initial reset signal has a low level, or when the voltage drop signal from the second power supply monitoring circuit has a low level.

In such a configuration, after the CPU performs a predetermined power supply stop process in response to the detection signal from the first power supply monitoring circuit, the CPU is reset. Therefore, the system is reset in the voltage unstable state when the power supply voltage drops, and the danger of CPU runaway or the like is avoided. And because it monitors the same voltage,
The difference between the timing at which the first voltage monitoring circuit outputs the voltage drop signal and the timing at which the second voltage monitoring circuit outputs the voltage drop signal can be reliably set to a desired predetermined period. The desired predetermined period is a period from the start of the power supply stop processing in response to the voltage drop signal from the first power supply monitoring circuit until the power supply stop processing is completely completed.

Next, the operation of the gaming machine will be described. When the power of the gaming machine is turned on, the capacitor is charged via the resistor in the initial reset circuit 65 of the main board 31 shown in FIG. Therefore, the potential of the capacitor increases. When the potential of the capacitor exceeds a predetermined value, the reset IC 651 changes the output level from a low level to a high level, as shown in FIG. The delay circuit 655 delays the output of the reset IC 651 and
It is supplied to the PU 56 as a reset signal. Therefore, CP
U56 has an initial reset circuit 6 as shown in FIG.
The reset signal at a low level is applied until a time point later than the time point when the output signal of No. 5 rises, and thereafter, the reset signal rises to a high level. That is, the CP
The reset of U56 is released.

Note that the amount of delay in the delay circuit 655 is
For example, the amount is set so that a command is not transmitted from the game control means before the CPU of each control board has completed execution of the initialization program.

In each of the electric component control boards other than the main board 31, no delay circuit is provided, so that the reset signal input to each CPU rises earlier. That is, each CPU is in an operable state earlier than the CPU 56 of the main board 31. Therefore, a situation does not occur in which the electric component control means cannot receive the command sent by the CPU 56 of the main board 31 immediately after the power of the gaming machine is turned on.

FIG. 12 shows the CPU 56 on the main board 31.
It is a flow chart which shows the game control processing of. FIG.
FIG. 1A shows a main process executed by the CPU 56, and FIG.
2 (B) shows an interruption process. When the reset at the time of power-on is released, the CPU 56 first sets a built-in clock monitor register to a clock monitor enable state in order to enable clock monitor control (step S1). Clock monitor control means that when detecting a drop or stop of an input clock signal, the CPU
This is a control for automatically generating a reset inside 56.
Next, the CPU 56 performs an initialization process (step S
2). In the initialization process, after a predetermined period (for example, 2 m
After s), the timer is set so that the timer is interrupted. Thereafter, the process of updating the display random number such as the random number for determining the type of the stop symbol is repeatedly executed (step S).
17).

The processing shown in FIG.
6 is activated by an internal timer interrupt. In the interrupt processing, the CPU 56 firstly sets a predetermined period (for example, 2 ms).
After that, a timer setting process is performed so that the timer is again interrupted (step S20).

Next, after performing processing for setting a display control command sent to the display control board 80 to a predetermined area of the RAM 55 (display control data setting processing: step S
4) A process for outputting a display control command is performed (display control data output process: step S5).

Next, processing for outputting the contents of the storage area for various output data to each output port is performed (data output processing: step S6). Further, an output data setting process for setting output data such as jackpot information, start information, and probability variation information output to the hall management computer in the storage area is performed (step S8). Further, various abnormality diagnosis processes are performed by a self-diagnosis function provided inside the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error process: step S9).

Next, a process for updating each counter indicating a random number for determination such as a random number for big hit determination used in game control is performed (step S10).

Next, the CPU 56 performs a special symbol process (step S11). In the special symbol process control, a corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to a gaming state. Then, the value of the special symbol process flag is updated during each processing according to the gaming state. Further, a normal symbol process is performed (step S12). In normal symbol processing, 7 segments L
A corresponding process is selected and executed according to a normal symbol process flag for controlling the variable display 10 by the ED in a predetermined order. Then, the value of the normal symbol process flag is updated during each process according to the gaming state.

Further, the CPU 56 includes a switch circuit 58
, The state of the gate sensor 12, the starting port sensor 17, and the count sensor 23 are input, and it is determined whether or not there is a prize for each prize port or prize device (switch processing: step S13). The CPU 56 further performs a process of updating a display random number such as a random number for determining the type of stop symbol (step S15).

The CPU 56 performs signal processing with the award ball control board 37 (step S16). That is,
When a predetermined condition is satisfied, a prize ball control command is output to the prize ball control board 37. The prize ball control CPU mounted on the prize ball control board 37 drives the ball payout device 97 according to the prize ball control command.

In this embodiment, the game control process of steps S20 and S4 to S16 is executed in the 2 ms timer interrupt process. In the timer interrupt process, only the flag set indicating that the timer interrupt has occurred is performed. Then, the flag may be monitored in the main process, and the game control process may be executed when the flag is turned on.

FIG. 13 is a flowchart showing the NMI interrupt processing of the CPU 56. As described above, when the power supply monitoring IC 901 detects a drop in the power supply voltage, the CPU 5
6 receives an NMI interrupt. In this embodiment,
The processing illustrated in FIG. 13 corresponds to the power supply stop processing.

In the NMI interrupt processing based on the drop in the power supply voltage, the CPU 56 first transfers the contents of the register to the backup RAM (step S31). Then N
The MI flag is set (step S32). The NMI flag is an internal flag indicating that an interrupt has occurred due to a drop in power supply voltage. The NMI flag is set in the backup RAM area. The CPU 56 further disables the RAM access (step S3).
3) Continue to monitor the level of the input port to which the output of the power monitoring IC 901 is introduced (step S34).
In this state, the power supply voltage further decreases, and finally,
The operation of the CPU 56 stops.

However, when the level of the input port has returned to the normal level, the CPU 56 enables the RAM access (step S35), and stores the register value stored in the backup RAM into the original register. It is returned (step S36). Then, the NMI flag is reset (step S37), and the address returns to the address where the NMI interrupt was interrupted.

As described above, upon detecting that the power supply voltage has returned to normal, the CPU 56 returns the state of the register to the original state and returns to the address at which the NMI interrupt has occurred. Therefore, control can be returned to a normal state even when noise or the like is present on the NMI line.

However, the input port monitoring process in step S34 may not be performed. In that case, the program is put into a loop state after the RAM access is prohibited, or a HALT (Halt) instruction is issued. When the input port monitoring process is not performed, it is not necessary to connect the NMI signal to the input port of the CPU in the configuration shown in FIG.

As shown in FIG. 11, the main substrate 31
When the power supply monitoring IC 901 detects a voltage drop of +30 V, the power supply monitoring IC 931
Is the same as when the voltage drop of +30 V is detected. That is, when the CPU 56 of the main board 31 starts the NMI processing, the award ball control CPU 371 also starts the NMI processing. Then, in the NMI process of the CPU 56, since a loop is performed in step S34, transmission of a new command is not started. Therefore, the CPU 37 for controlling the prize ball.
No. 1 does not fall into a situation in which a command from the main board 31 cannot be received when the power is turned off.

FIG. 14 is a flowchart showing an example of the initialization processing (step S2) in the main processing shown in FIG. When the power supply to the gaming machine is resumed,
A reset signal is input from the initial reset circuit 65 to the CPU 56. The CPU 56 starts the main process in response to the initial reset signal. In the system check process, first, the CPU 56 checks whether or not the NMI flag is set (step S42).

If the NMI flag is not set,
Clear all registers and RAM area (step S
46), necessary initial values are set (step S47).
Then, a power-on screen display command transmission request is set (step S48), the stack pointer is initialized (step S49), and the initialization processing ends.

When the power-on screen display command transmission request is set, the power-on screen display command is transmitted to the display control board 80 by, for example, the display control data output process (step S5) shown in FIG. Is done. When the display control CPU 101 of the display control board 80 receives the power-on screen display command, the display control CPU 101
Next, a screen that is determined in advance as a screen displayed when the power is turned on is displayed.

When it is confirmed in step S42 that the NMI flag is set, the CPU 56 restores the register value stored in the backup RAM to the original register (step S43). Then, the NMI flag is reset (step S44), and an error screen display command transmission request is set (step S45).

When an error screen display command transmission request is set, an error screen display command is transmitted to the display control board 80 by, for example, display control data output processing (step S5). Upon receiving the power-on screen display command, the display control CPU 101 of the display control board 80 displays a predetermined error screen on the variable display unit 9.

Then, the CPU 56 jumps to the value of the stack area indicated by the stack pointer as a jump destination. Since the stack pointer is one of the registers, the stack pointer has been restored to the value at the time of power-off by the processing in step S43. Also, in this embodiment,
The stack area is formed in the backup RAM area. That is, it is preserved even when the power is turned off. Therefore, the control state returns to the state when the power was turned off.

For example, it is assumed that the display control CPU 101 on the display control board 80 is performing symbol variation display on the variable display section 9 when the power is turned off. Then, when the power is restored, the display control CPU 101 receives the error screen display command, and displays an error screen on the variable display unit 9. On the other hand, the CPU 56 of the main board 31 returns to the state when the power is turned off, that is, the gaming state in which the special symbol is changing. Then, when the gaming state in which the special symbol is changed ends, a command indicating a symbol stop or a command indicating a big hit display is transmitted. At this stage, the display control CPU 101 can stop the error display and continue the subsequent display control.

As described above, the CPU 56 sets N
If the MI flag has been set, data recovery processing is performed, and if the NMI flag has not been set, normal initialization processing (steps S46 and S47) is performed. And
In the data restoration processing, the restoration processing of the saved register and the reset processing of the NMI flag are performed. Also,
Since the return to the return address stored in the stack area in the RAM area where the power is backed up is returned, the game control means can return to the game state when the power is turned off.

In this embodiment, when the power is turned on, whether the initialization processing or the state return processing is performed is determined depending on whether or not the NMI flag is set. The check data is calculated and stored in the RAM area where the power is backed up. When the power is turned on, if the NMI flag is on, a check based on the parity check data is performed, and if the data is correctly stored, the state restoration process is performed. It may be configured as follows.

In the above embodiment, the main substrate 31
The resistance value and the capacitance of the resistor and the capacitor in the initial reset circuit 65 are set equal to the resistance value and the capacitance of the resistor and the capacitor externally attached to the reset IC 380 in the other electric component control board. However, the capacity of the capacitor in the initial reset circuit 65 may be larger than the capacity of the capacitor in another electric component control board. In such a configuration, the rising point of the reset signal from the reset IC 651 of the initial reset circuit 65 is later than the rising point of the reset signal from the reset IC 380 in another electric component control board. Therefore, the delay circuit 6
55, the output of the initial reset circuit 65 is supplied to the CPU 56 as it is,
However, it is possible to start up later than CPUs on all other boards.

The CPU 56 of the main board 31 may be configured to execute a predetermined security check program prior to the game control program after the reset is released. If it takes a certain amount of time to execute the security check program, it is possible to use the time to quickly release the reset of each CPU in another electric component control board when the power is turned on. FIG. 15 is a block diagram showing another embodiment based on such a concept.

In this case, the delay circuit 655 is not provided on the main board 31, and the output of the initial reset circuit 65 is directly connected to the reset input terminal of the CPU 56. Then, the resistance value and the capacitance of the resistor and the capacitor in the initial reset circuit 65 of the main board 31 are set to values equal to the resistance value and the capacitance of the resistor and the capacitor externally attached to the reset IC 380 in the other electric component control boards. You. However, the CPU 56 of the main board 31
By the time the CPU in the other electrical component control board starts up and completes the execution of the initialization program before the execution of the security check program is completed, the resistance value and the capacitance of the capacitor of the other electrical component control board are: The resistance value and the capacitance of the capacitor of the main board 31 need not be equal.

Therefore, as shown in FIG.
CPU 56 of each of the other electrical component control boards
The reset is released almost simultaneously. When the reset is released, the CPU 56 first executes the security check program. While the security check program is being executed, commands for other electric component control boards are not output from the CPU 56. If it takes a long time to execute the security check program, during that time, each CPU of the other electric component control boards
The execution of the initialization program has been completed. Therefore, it is in a state of waiting for a command.

In this embodiment, as shown in FIG. 16, the time when the execution of the security check program is completed is the substantial timing of reset release of the CPU 56. Therefore, also in this embodiment, after the power of the gaming machine is turned on, the reset release timing of each CPU in each electric component control means is substantially earlier than the reset release timing of the CPU 56 in the game control means. Therefore, a situation does not occur in which a command is sent from the game control means before the execution of the initialization program in each electric component control means, and each electric component control means fails to receive command data.

As described above, in each of the above embodiments,
When the power is turned on, the CPU 56 of the main board 31 is configured to rise later than the CPUs of all the other electric component control means.
The possibility that the command from the main board 31 cannot be received can be eliminated.

When the power is turned on, the CPU of the main board 31
By providing a delay time by software before the 56 sends a command to the other electrical component control board, the CPU 56 of the main board 31 rises substantially later than each CPU of the other electrical component control means. It may be.

Also, at least when the power of the gaming machine is turned off,
Since the timing at which the CPU 56 of the main board 31 is interrupted to indicate power-off and the timing at which the prize ball control CPU 371 is interrupted to indicate power-off are made substantially the same, the command transmitted immediately before the power-off is executed. The possibility that reception on the receiving side is not possible is reduced.

Hereinafter, the processing at the time of stopping the power supply in each electric component control means other than the game control means will be described. Here, the award ball control means is taken as an example, but other control means for executing the NMI interrupt processing also perform the same processing. In this embodiment, the NMI interrupt processing corresponds to the power supply stop processing. As shown in FIG. 17, the prize ball control CPU 3
71 sets the NMI flag first (step S
801). Further, the RAM access is prohibited (step S802), and the level of the input port to which the output of the power monitoring IC 931 is introduced is continuously monitored (step S803).

When the level of the input port returns to the normal level, the award ball control CPU 371 sets the RAM access to a permitted state (step S804), and sets the NMI
The flag is reset (step S805), and the process returns to the address where the NMI interrupt has occurred.

As described above, the CPU 371 for controlling the prize ball
When it is detected that the power supply voltage has returned to normal, the state of the register is returned to the original state, and the address returns to the address where the NMI interrupt was interrupted. Therefore, control can be returned to a normal state even when noise or the like is present on the NMI line.

However, the input port monitoring processing in step S803 may not be performed. In such a case, the program may be put into a loop state after the RAM access is prohibited, or
Alternatively, a HALT (Halt) instruction is issued. When the input port monitoring process is not performed, the NMI signal is sent to the CPU for controlling the prize ball in the configuration shown in FIGS.
There is no need to connect to the 371 input port.

FIG. 18 is a flowchart showing an initialization process in the main process executed by the award ball control CPU 371. In this case, the award ball control CPU 37 first checks whether or not the NMI flag is set (step S812). If not set, the register and the RAM area are all cleared (step S81).
4), necessary initial values are set (step S815).
Then, the stack pointer is initialized (step S8).
16) End the initialization process.

When it is confirmed in step S812 that the NMI flag is set, the CPU 56 sets the NMI flag
The flag is reset (step S813), and a jump is made to the value of the stack area pointed to by the stack pointer as a jump destination. In this embodiment, it is not necessary to save the value of each general-purpose register in the backup RAM when the power is turned off, but at least the stack pointer needs to be saved. Further, since the stack area is formed in the backup RAM area, the CPU for controlling the prize ball
By detecting that the NMI flag is set when the power is turned on, the 371 can reliably return to the control state when the power is turned off.

For example, when the award ball flag is set to backup RA
If it is formed in the M area, it is detected that a flag indicating that a prize ball is being set is set, and the CPU 371 for controlling the prize ball.
Can immediately restart the prize ball payout process based on the value of each number counter stored in the backup RAM area.

Even if the flags are not set in the backup RAM area, the number counter is set to the backup RAM area.
If the area is set, the CPU 371 for controlling the prize ball
When the power is restored, the game state memory is read out,
That is, by reading the set value of each number counter, it is possible to detect whether or not there are unpaid prize balls. And
When it is detected that there is an unpaid prize ball, for example, the prize ball payout process can be restarted by setting the prize ball paying flag.

FIG. 19 is a flowchart showing another example of the NMI interrupt processing executed by the award ball control CPU 371. In this case, the CPU 371 for controlling the prize ball first
It is checked whether the number of unpaid prize balls or the number of unpaid ball lending is stored (step S821). If there is such a storage, the NMI flag is set (step S8).
22). Further, the RAM access is prohibited (step S823), and the level of the input port to which the output of the power monitoring IC 931 is introduced is continuously monitored (step S803).

When the level of the input port returns to the normal level, the award ball control CPU 371 sets the RAM access to a permitted state (step S804), and sets the NMI
The flag is reset (step S805), and the process returns to the address where the NMI interrupt has occurred.

If the number of unpaid prize balls or the number of unpaid ball lending is not stored, the RAM access is disabled (step S823), and the flow shifts to step S803.
According to such control, the preparation for the return of the control state when the power is restored is performed only when the power is cut off in the unpaid state, that is, only when necessary.

In each of the above embodiments, when the power is turned off, each electric component control means performs a process based on an NMI interrupt from the power supply monitoring IC. Power monitoring I only at
C may be configured to be mounted. In each of the above embodiments, the NMI interrupt is exemplified. However, a signal indicating a power supply voltage drop is introduced to an external interrupt (INT) terminal which is not maskable, and an interrupt based on an interrupt signal of the INT terminal is performed. Processing may be performed.

Further, similarly to the RAM in the prize ball control means, the RAM in the voice control means, the lamp control means and the display control means may have a part to be backed up.

[0145]

As described above, according to the present invention, in the gaming machine, at least the game control means and the payout control means, the stop condition of the game progress control and the stop condition of the payout control relating to the power supply state are the same. With such a configuration, there is no inconvenience that the command sent by the game control means immediately before the power is turned off is not received by the payout control means, and the payout control means reliably receives the command from the game control means. There is an effect that can be.

In the case where the power supply state for causing the game control means to start the power supply stop processing and the power supply state for causing the payout control means to start the power supply stop processing are the same, Since the power supply stop processing is started at the same time, the game control means and the payout control means can be simultaneously shut down.

Power supply monitoring means for monitoring a predetermined potential power supply and outputting a detection signal when a detection condition is satisfied, wherein the game control means and the payout control means are adapted to stop power supply according to the detection signal from the power supply monitoring means. When configured to perform the processing, the payout control means can reliably receive the command from the game control means, and the game control means and the payout control means perform processing for data storage, etc. It is possible to reliably grasp the timing at which the power supply stop processing is performed.

When the game control means and the payout control means which have received the detection signal of the power supply monitoring means are configured to execute the power supply stop processing in the interruption processing, the processing having a high priority is performed by The power-off processing is executed reliably.

If the storage means on the game control board is configured to back up the power and retain the information necessary for restoring the game state when the power of the game machine is restored, an unexpected power failure occurs. Etc.
When the power is restored, the power can be returned to the state at the time of the power failure, and there are effects such as not giving a disadvantage to the player.

If the game control means includes a storage means capable of holding the contents immediately before the power supply is stopped, the storage means is integrated with the game control means, thereby reducing the cost of the game control means. Can be reduced.

The storage means on the payout control board on which the payout control means is mounted is backed up by a power supply, and is configured to hold information necessary for restoring the payout state when the power of the gaming machine is restored. In this case, even if the power is cut off due to an unexpected power outage or the like, it is possible to return to the payout state at the time of the power cut when the power is restored, and there is an effect that the player is not disadvantaged.

When the payout control means includes a storage means capable of holding the contents immediately before the power supply is stopped, the storage means is integrated with the payout control means, thereby reducing the cost of the payout control means. Can be reduced.

In the case where a delay means for delaying the reset signal from the initial reset means and supplying it to the game control means is provided, the initial reset means of the game control board and the initial reset means of the payout control board have the same configuration. can do.

If the capacity of the capacitor for generating the reset signal in the initial reset means of the game control board is larger than the capacity of the capacitor for generating the reset signal in the initial reset means of the payout control board, the delay circuit This is advantageous in that the circuit configuration can be simplified because the above-mentioned steps are not required.

The game control means executes a predetermined program when the power-on reset is released. If the initial reset means on the game control board and the initial reset means on the payout control board have the same structure, the same design is used. Therefore, the design cost is reduced, and as a result, the gaming machine cost is reduced.

[Brief description of the drawings]

FIG. 1 is a front view of a pachinko gaming machine viewed from the front.

FIG. 2 is a front view of the gaming board of the pachinko gaming machine as viewed from the front.

FIG. 3 is a rear view of the pachinko gaming machine as viewed from the rear.

FIG. 4 is a block diagram showing a circuit configuration example of a game control board (main board).

FIG. 5 is a block diagram illustrating a circuit configuration example of a display control board.

FIG. 6 is a block diagram illustrating a circuit configuration example of an audio control board.

FIG. 7 is a block diagram illustrating a circuit configuration example of a lamp control board.

FIG. 8 is a block diagram showing a circuit configuration example of a winning ball control board.

FIG. 9 is a block diagram illustrating a configuration around a CPU in each control board.

FIG. 10 is a block diagram illustrating a configuration example of a power supply board.

FIG. 11 is a timing chart showing signal examples when power is turned on and when power is turned off.

FIG. 12 is a flowchart showing the operation of the basic circuit on the main board.

FIG. 13 is a flowchart showing an interrupt process of the CPU of the main board.

FIG. 14 is a flowchart illustrating an initialization process in a main process.

FIG. 15 is a block diagram showing another configuration around the CPU in each control board.

FIG. 16 is a timing chart showing another example of signals when power is turned on and when power is turned off.

FIG. 17 is a flowchart showing an NMI process executed by the winning ball control CPU.

FIG. 18 is a flowchart showing an initialization process executed by the winning ball control CPU.

FIG. 19 is a flowchart showing another example of the NMI process executed by the winning ball control CPU.

[Explanation of symbols]

 1 Pachinko Machine 31 Main Board 35 Lamp Control Board 37 Prize Ball Control Board 53 Basic Circuit 56 CPU 65 Initial Reset Circuit 70 Voice Control Board 80 Display Control Board 101 Display Control CPU 351 Lamp Control CPU 371 Prize Ball Control CPU 701 Voice control CPU 901, 931 Power supply monitoring IC 910 Power supply board 916 Capacitor

Claims (11)

[Claims] 1. A game machine in which a player can play a predetermined game, comprising: a game control means for controlling the progress of the game; and a payout control means for performing a payout control of a game medium used for the game. A gaming machine, characterized in that at least the game control means and the payout control means have the same stop condition of the game progress control and the stop condition of the payout control with respect to the power supply state. 2. The game control means and the payout control means perform a predetermined power supply stop processing when the power supply is stopped, and a power supply state for causing the game control means to start the power supply stop processing. The gaming machine according to claim 1, wherein a power supply state for causing the payout control means to start a power supply stop process is the same. 3. The game machine further comprises a power supply monitoring means for monitoring a predetermined potential power supply used in the game machine and outputting a detection signal when a detection condition is satisfied, wherein the game control means and the payout control means 3. The gaming machine according to claim 2, wherein the power supply stop processing is performed in response to a detection signal from the power supply monitoring unit. 4. The gaming machine according to claim 3, wherein the game control means and the payout control means execute a power supply stop process in an interruption process when receiving a detection signal of the power supply monitoring device. 5. The game control board is provided with a storage means capable of holding the contents immediately before the power supply is stopped by the backup power supply for at least a predetermined time even when the power supply is stopped, and the storage means is provided when the power supply is restored. 5. The gaming machine according to claim 1, wherein information necessary for restoring a gaming state is stored in the gaming machine. 6. The gaming machine according to claim 5, wherein the storage means capable of holding the contents immediately before the stop of the power supply is included in at least the game control means. 7. A dispensing control board on which dispensing control means is mounted is provided with a storage means capable of holding the contents immediately before the power supply is stopped by the backup power source for at least a predetermined time even when the power is stopped. 7. The gaming machine according to claim 1, wherein information necessary for restoring a payout state when power supply is restored is held. 8. The gaming machine according to claim 7, wherein the storage means capable of holding the contents immediately before the stop of the power supply is included in at least the payout control means. 9. The game control board and the payout control board include:
2. An initial reset means for outputting a reset signal to the game control means and the payout control means, and a delay means for delaying a reset signal from the initial reset means and supplying the reset signal to the game control means.
A gaming machine according to claim 8. 10. The game control board and the payout control board are provided with initial reset means for outputting a reset signal to the game control means and the payout control means, and generate a reset signal in the initial reset means of the game control board. 9. The gaming machine according to claim 1, wherein the capacity of the capacitor for performing the resetting is larger than the capacity of the capacitor for generating a reset signal in the initial reset means of the payout control board. 11. The game control board and the payout control board are provided with initial reset means for outputting a reset signal to the game control means and the payout control means. The gaming machine according to claim 1, wherein a program is executed, and the initial reset means in the game control board and the initial reset means in the payout control board have the same configuration.