JP2001154859A - Digital processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To quicken the responding speed at the generation of interruption and at the request for memory access of a microcomputer in a hierarchical storage system equipped with a real time OS. SOLUTION: This microcomputer in a hierarchical storage system equipped with a real time OS is provided with a function for executing a task which is highly likely to be executed afterwards in an idle time without any task to be executed, that is, the processing of steps ST3-ST4 for transferring an interruption handler from a main storage device to a cache memory or preparation processing related with a prescribed task, that is, the processing of steps ST5-ST6 for transferring dirty data in the cache memory to the main storage device in advance.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital processing apparatus, and more particularly to a technique which is particularly effective for use in increasing the response speed to an interrupt or the like of a microcomputer employing a hierarchical storage system.

[0002]

2. Description of the Related Art There is a digital processing device such as a microcomputer employing a stored program system, and an operating system which controls the execution of application programs and the like as basic software of such a digital processing device. As one means for improving the processing capability of a microcomputer or the like, a so-called hierarchical storage system in which a cache memory having a higher operation speed than a main storage device is provided in the same chip as a central processing unit (CPU) is known. .

[0003]

Prior to the present invention, the present inventors were involved in the development of an operating system for a microcomputer and noticed the following problems. That is, this microcomputer adopts the above-mentioned hierarchical storage method, and includes a cache memory having a relatively high operation speed and a main storage device having a relatively low operation speed.

An operating system as basic software of the microcomputer, that is, a central processing unit (CPU) as its substantial execution means, for example, as shown in FIG. 6, confirms that there is no task to be executed in step ST21. It becomes idle at the time of judgment,
At step ST23, for example, when it is determined that an interrupt has occurred, the CPU leaves the idle state. After determining in step ST24 whether an interrupt handler for interrupt analysis processing is in the cache memory, if this is not in the cache memory and a mishit occurs, the interrupt handler is read from the main storage device in step ST25. Is transferred to the cache memory. Thereafter, an interrupt analysis process in step ST26 is performed, and a process related to, for example, the task D corresponding to the interrupt factor is started.

On the other hand, when the processing of task D in step ST27 is started and, for example, there is a memory access request from the central processing unit, in step ST28 the dirty data in the cache memory, that is, the central processing unit, etc. It is determined whether there is data whose corresponding address in the main storage device has not been rewritten. As a result, if there is no dirty data in the cache memory, the memory access is performed in step ST30. If there is dirty data, the corresponding address in the main storage device is rewritten in step ST29, and then the memory access is performed in step ST30. Is performed.

That is, this operating system,
That is, as shown in FIG. 7, the central processing unit, which is the substantial execution means, completely stops the control operation in the idle state where there is no task to be executed, and sets the cache memory necessary for the interrupt analysis processing IP. Transfer processing IH to the interrupt handler and dirty data transfer processing DT to the main storage device are performed each time an interrupt request or a memory access request occurs. Therefore, a relatively long time is required until the interrupt analysis processing IP is started or the memory access is started, and the response speed of the microcomputer and its operating system is reduced.

An object of the present invention is to provide, for example, a real-time O
An object of the present invention is to increase the response speed when an interruption occurs in a microcomputer or the like that employs a hierarchical storage system and has a memory access request.

[0008] The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0009]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, in a microcomputer having a real-time OS and employing a hierarchical storage method,
When there is no task to be executed at the time of idle, a task having a high probability of being executed thereafter, for example, a process of transferring an interrupt handler for interrupt analysis from the main storage device to the cache memory, or a preparation process for a predetermined task, that is, for example, a cache It has a function of executing in advance the process of transferring dirty data in the memory to the main storage device.

According to the above means, for example, when an interrupt occurs, the interrupt analysis process can be started immediately without reading the interrupt handler into the cache memory, and when a memory access request occurs, the dirty data is transferred to the main storage device. Without starting, the memory access can be started immediately. As a result, it is possible to reduce the response time when an interrupt occurs in the real-time OS, and in addition, when a microcomputer or the like including the real-time OS and a memory access request occurs.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an explanatory diagram of one embodiment for explaining a control system including a real-time OS (operating system) of a microcomputer (digital processing device) to which the present invention is applied. FIG. 2 is an explanatory diagram of an embodiment for explaining the storage hierarchy. First, an outline of a control system and a storage hierarchy of the microcomputer of this embodiment will be described with reference to these drawings.

In FIG. 1, the microcomputer of this embodiment adopts a stored program system, and has a basic structure of a hardware 1 including a central processing unit CPU as a center of a control system and a storage device (not shown).
The software includes an operating system 2 serving as basic software, n tasks including various control programs or application programs, that is, tasks 31 to 3n, and an interrupt handler 4 for interrupt analysis. . Of these, the operating system 2 includes a kernel as its core, and the execution of the tasks 31 to 3n is controlled and controlled by the kernel.

Although not particularly limited, during normal operation, the interrupt handler 4 is read directly into the cache memory by the central processing unit CPU of the hardware 1 that has received the interrupt request and executed, but is not described later. Sometimes, the instruction is read into the cache memory in response to an instruction from the kernel of the operating system 2. Needless to say, whether or not the interrupt handler 4 exists in the cache memory and reading from the main storage device to the cache memory are performed by a cache memory control unit (not shown) of the hardware 1.

The microcomputer of this embodiment employs a so-called hierarchical storage system, and its storage device 1
2 is, for example, as shown in FIG.
A cache memory 121 composed of a memory having a relatively high operation speed such as an AM (random access memory) and a dynamic RAM, an EEPROM (electrically erased /
It includes a main storage device 122 composed of a memory having a relatively low operation speed such as a rewritable ROM) or a mask ROM (read only memory), and a large-capacity auxiliary storage device 123 composed of, for example, a magnetic disk or an optical disk.

As described above, the hardware 1 of the microcomputer includes the cache memory control unit. The cache memory control unit receives the memory access request, and first receives a program or a program corresponding to the memory address requested to be accessed. It is determined whether data or the like is left in the cache memory. As a result, when a so-called hit is found in the cache memory, the designated program or data is directly transferred to the central processing unit CPU.
If the corresponding program or data does not exist in the cache memory and a so-called mishit occurs, it is read in a predetermined unit in the main storage device 1.
After reading from the cache memory 121 and transferring it to the cache memory 121, a corresponding process is started.

On the other hand, a new memory access request by the central processing unit CPU may involve rewriting of the cache memory 121 as described above. If the cache memory 121 receives dirty data, ie, rewrite in the cache memory, If there is data for which the rewriting of the corresponding address in the main storage device 122 has not been completed yet, there is a risk that these data are erroneously erased and the latest information is not retained. For this reason, the cache memory control unit determines in advance whether or not dirty data exists based on a predetermined flag in the cache memory at the time of receiving the memory access request. It also has a function of transferring data to a corresponding address in the storage device 122.

FIG. 3 is a flow chart showing an operation of the microcomputer shown in FIG. 1 at the time of idling according to an embodiment. FIG. 4 is a flowchart showing the operation of the microcomputer at the time of idling. A timing chart of one embodiment is shown. FIG. 5 is a partial explanatory diagram of one embodiment for describing a description format in C language of the operating system of the microcomputer in FIG. With reference to these figures, an outline of the processing procedure and operation of the microcomputer of this embodiment and its real-time OS at the time of idling and the features thereof will be described.

Note that the idle state refers to a state in which the central processing unit CPU of the microcomputer, that is, the operating system, that is, the kernel has no tasks to execute or to control the execution, but in the description of this specification, The period during which the interrupt handler reads the cache memory and writes the dirty data to the main storage device is also included in the idle state. Hereinafter, a specific description will be given from the viewpoint of the kernel of the operating system.

In FIG. 3, the kernel of the operating system determines in step ST1 whether there is a task to be executed, and if there is a task to be executed, controls to execute this task in step ST2. However, when it is determined in step ST1 that there is no task to be executed, an idle state is set.

In this embodiment, the kernel of the operating system in the idle state does not immediately stop the control operation. First, in step ST3, the cache memory control unit is activated, and the interrupt handler is previously stored in the cache memory. Is read and it is determined whether or not it has been saved. As a result, if an interrupt handler remains in the cache memory and a hit occurs, step S
The process proceeds to T5. If there is no interrupt handler in the cache memory and a miss occurs, the process proceeds to step ST4.
Reads the interrupt handler in the main memory,
After the transfer to the cache memory, the process proceeds to step ST5.

The operating system of the microcomputer of this embodiment is described using, for example, the C language, and the process of transferring the interrupt handler and the like to the cache memory when the kernel is idle is performed, for example, as shown in FIG.
It is described in a format as shown in FIG. The structure of the table used at this time is described, for example, in a format as shown in FIG. In the embodiment shown in FIG. TBL) consists of ten regions.

The kernel, which has shifted the processing to step ST5, activates the cache memory control unit again and determines whether dirty data is left in the cache memory based on a predetermined flag of the cache memory. As a result, if no dirty data is left in the cache memory, the process proceeds to step ST6, and the control enters an original idle state in which no control operation is performed. However, if dirty data is left in the cache memory, After the dirty data is written to the corresponding address in the main storage device in step ST6, the device enters the original idle state.

The process for transferring the dirty data in the cache memory to the main storage device is described in C language in a format similar to that of FIG. 5A or 5B. Needless to say.

In step ST7, the kernel that has originally entered the idle state, that is, the central processing unit CPU, determines whether or not an interrupt request has been generated by an interrupt request flag (not shown), and maintains the idle state until some interrupt request occurs. Then, when the interrupt request is generated, the CPU leaves the idle state. However, since the interrupt handler has already been read into the cache memory in step ST3, the cache memory control unit determines the cache memory hit and immediately The interrupt analysis processing in step ST8 is started.

On the other hand, upon receiving the result of the interrupt analysis in step ST8, the kernel starts processing relating to, for example, task D corresponding to the interrupt factor. If a memory access request is received from the central processing unit CPU or the like during that time, the kernel instructs the cache memory control unit to perform dirty data transfer processing. However, since the dirty data in the cache memory has already been transferred to the corresponding address in the main storage device in step ST6, the cache memory control unit determines that there is no dirty data, and immediately proceeds to the memory access in step ST10. Execute Further, upon completion of the task D process in step ST11, the kernel executes the next process or shifts to an idle state.

The control procedure when the microcomputer operating system kernel is idle is as follows:
Further, a description will be given in chronological order based on FIG.

In FIG. 4, the central processing unit CPU, that is, the kernel of the operating system first performs, for example, a preparation process for executing the task A by the kernel process K11 and then starts the task A process TA1. In response to the termination, the kernel process K12 terminates the task A process TA1 and terminates the task B process.
After performing the preparation process for executing the task B, the task B process T
Start B. Further, in response to the end of the task B process TB, the kernel process K13 prepares the task C, and then starts the task C process TC.

When the kernel receives the end of the task C processing TC, the kernel determines that there is no other task to be executed, and enters an idle state. After performing a preparation process for reading the interrupt handler into the cache memory, the cache memory control unit activates the interrupt handler transfer process IH. At this time, as described above, the cache memory control unit determines whether or not the previously read interrupt handler is left in the cache memory, and if not, reads it from the main storage device, and Transfer to memory. When the reading of the interrupt handler into the cache memory is completed, the fact is reported to the kernel.

Upon completion of the interrupt handler transfer processing IH, the kernel performs the termination processing by the kernel processing K15, performs the preparation processing for transferring the dirty data to the main storage device, and then again executes the cache memory control unit. To start the dirty data transfer process DT. Then, dirty data transfer processing D to the main storage device
At the end of T, after the termination process is performed by the kernel process K16, all control operations are stopped, and a transition is made to the original idle state.

Next, the central processing unit CPU in the idle state receives the interrupt request, leaves the idle state, and attempts to start the interrupt analysis processing by the interrupt handler. The cache memory control unit receives an instruction from the central processing unit CPU and determines whether or not an interrupt handler is left in the cache memory. Since the handler has been read, the central processing unit CPU is immediately notified of the hit, and the central processing unit CPU starts the interrupt analysis processing IP. This interrupt handler transfer processing I
H and the interrupt analysis processing IP are started without intervention of the kernel of the operating system, but the end is reported to the kernel, and in response to this, the termination processing by the kernel processing K17 and the task D corresponding to the interrupt cause are performed. Preparation processing for processing TD is performed.

When a memory access request is issued by the central processing unit CPU or the like while the task D process TD is being executed, the cache memory control unit stores dirty data in the cache memory based on a predetermined flag. Determine if any are left. However, since the dirty data in the cache memory has already been transferred to the main storage device by the dirty data transfer process DT at the time of idling, a predetermined memory access is immediately started. The kernel that has received the end of the task D process TD performs the termination process and the preparation process for the next task A process TA2 by the kernel process K18,
A similar control operation is repeated.

As described above, the microcomputer and its operating system according to the present embodiment precede the cache memory with a program relating to a task having a high probability of being executed, that is, an interrupt handler, for example, when there is no task to be executed. It has a function of transferring predetermined data in the cache memory, that is, dirty data, for example, prior to the main storage device. For this reason, even if the CPU leaves the idle state due to some interrupt request or receives a memory access request immediately after that, the interrupt handler necessary for interrupt analysis is already in the cache memory, and is stored in the cache memory prior to the memory access. There is no dirty data to be transferred to the main memory. As a result, since the interrupt analysis process can be started immediately or the memory access can be executed immediately, the response speed to the interrupt request or the memory access request as the microcomputer and its operating system is increased.

The functions and effects obtained from the above embodiment are as follows. (1) In a microcomputer equipped with an operating system such as a real-time OS or the like and adopting a hierarchical storage system, when there is no task to be executed, a task with a high probability of being executed thereafter, for example, an interrupt for interrupt analysis A function to precede the process of transferring the handler from the main storage device to the cache memory or the preparation process for a predetermined task, that is, the process of transferring dirty data in the cache memory to the main storage device in advance, for example. Thus, for example, when an interrupt occurs, the interrupt analysis process can be started immediately without loading the interrupt handler into the cache memory, and when a memory access request occurs, the memory access is immediately performed without transferring the dirty data to the main storage device. Start The effect that it can be obtained is obtained.

(2) According to the above item (1), an effect is obtained that the response time when an interruption of a microcomputer or the like and its operating system occurs and a memory access request occurs can be shortened.

As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the invention is not limited to the above embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say, there is. For example, in FIG. 1, the control system including the software of the microcomputer can take various embodiments without being restricted by the present embodiment. In FIG. 2, the storage hierarchy of the microcomputer can be variously conceived, for example, by providing a cache memory of a plurality of stages, and the type of the memory constituting each storage device can be arbitrarily selected. The cache memory is not necessarily required to be formed on the same chip as the central processing unit CPU.

In FIG. 3, for example, the transfer processing of the interrupt handler in steps ST3 and ST4 and the transfer processing of the dirty data in steps ST5 and ST6 are as follows.
The order may be changed. Further, the program transferred to the cache memory at idle is not limited to the interrupt handler, and the same applies to data transferred from the cache memory to the main storage device. The illustrated processing flows of the microcomputer and its operating system are merely examples, and various embodiments can be taken. In FIG. 4, the specific time relationship between the processes does not restrict the gist of the present invention at all, and the processing order and the processing time of each task and the combination thereof are not restricted by this embodiment. In FIG.
The operating system is not necessarily required to be described in the C language, and its description method and specific contents are not limited by this embodiment.

In the above description, the invention made mainly by the present inventor has been described as applied to a microcomputer and its real-time OS, which are the fields of use as the background, but the invention is not limited to this. The present invention can also be applied to a workstation or a microcontroller having a similar real-time OS, or to a storage medium or the like in which various operating systems are stored. INDUSTRIAL APPLICABILITY The present invention is widely applicable to at least a digital processing device using a stored program method and its operating system.

[0038]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a microcomputer having a real-time OS and adopting a hierarchical storage system, when there is no task to be executed, the task having a high probability of being executed thereafter, for example, an interrupt handler for interrupt analysis is cached from the main storage device. A function is provided for executing processing for transferring data to a memory and preparation processing for a predetermined task, that is, processing for transferring dirty data in a cache memory to a main storage device in advance.

Thus, for example, when an interrupt occurs, the interrupt analysis process can be started immediately without reading the interrupt handler into the cache memory. For example, when a memory access request occurs, dirty data can be transferred to the main storage device. And the memory access can be started immediately. As a result, it is possible to reduce the response time when an interrupt occurs in the real-time OS, and in addition, when a microcomputer or the like including the real-time OS and a memory access request occurs.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing an embodiment for explaining a microcomputer to which the present invention is applied and a control system of an operating system thereof.

FIG. 2 is an explanatory diagram showing one embodiment for explaining a storage hierarchy of the microcomputer of FIG. 1;

FIG. 3 is a processing flowchart showing an embodiment for explaining a processing procedure at the time of idling of the microcomputer in FIG. 1;

FIG. 4 is a timing chart showing an embodiment for explaining the operation of the microcomputer of FIG. 1 at the time of idling;

FIG. 5 is a partial explanatory diagram showing one embodiment for describing a description format in C language of the operating system of the microcomputer in FIG. 1;

FIG. 6 is a processing flowchart showing an example for explaining a processing procedure at the time of idling of a microcomputer and its operating system developed by the present inventors prior to the present invention;

7 is a timing chart showing an example for explaining an operation of the microcomputer in FIG. 6 at the time of idling;

[Explanation of symbols]

1. Hardware 2. Operating system 31 to 3n Task 4. Interrupt handler 1
1 CPU (central processing unit), 12 storage device, 121 cache memory, 122 main storage device, 123 auxiliary storage device. ST1 to ST11, ST
21 to ST31 Processing steps. K11 to K18, K
21 to K26: Kernel processing, IH: Interrupt handler transfer processing, IP: Interrupt processing, DT: Dirty data transfer processing, TA1 to TA2: Task A processing, T
B1 to TB2: Task B processing, TC: Task C processing, TD: Task D processing

Claims (1)

[Claims] 1. A digital process comprising an operating system capable of executing a task with a high probability of being executed or a preparation process related thereto in an idle state when there is no task to be executed. apparatus.