JP2001127615A - Division level logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a division level logic circuit that is operated at a power supply voltage over the breakdown voltage of an element and outputs output signals with respect to input signals at a variable level. SOLUTION: Two clamp transistors(TRs) MP3, MN4 are connected in series between operating TRs MP1 (PMOS) and MN2 (NMOS) being components of a CMOS inverter circuit. A clamp voltage VBp is applied to a gate of the clamp TR MP3 and a clamp voltage VBn is applied to a gate of the clamp TR MN4. An input signal Vin-P whose amplitude is VDD (power supply voltage)-VBp is given to the operating TR MP1 and an input signal Vin-N whose amplitude is VBb-GND (ground level) in the same as above is given to the operating TR MP2. An inverter output terminal Vout is extracted from a connecting point between the MP3 and the MN4, a PMOS output terminal YP is extracted from a connecting point between the MP1 and the MN3, and an NMOS output terminal YN is extracted from a connecting point between the MN4 and the MN2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a basic logic circuit in a semiconductor integrated circuit, and more particularly to a complementary logic circuit using a p-type field effect transistor (hereinafter abbreviated as PMOS) and an n-type field effect transistor (hereinafter abbreviated as NMOS). Field-effect transistor (hereinafter abbreviated as CMOS) logic circuit.

[0002]

2. Description of the Related Art FIG. 10 shows a circuit diagram of the most basic and general CMOS inverter circuit (NOT gate) among conventional CMOS logic circuits.

In FIG. 10, MP1 is a PMOS and MN2 is an NMOS. The input terminal Vin is connected to the gates of MP1 and MN2, and the power supply VDD is connected to the drain of MP1. The source of MN2 is grounded (GND). MP1 and MN2 are connected in series, and the intermediate connection point is connected to the output terminal Vout. Here, when the potential of Vin is at a high level,
Since MP1 is non-conductive and MN2 is conductive, Vou
The ground level (low level) is output to t. Vin
Is low, MP1 is conductive and MN2 is nonconductive, so that VDD potential (high level) is output to Vout.

This circuit does not require a clock, and has a high load driving capability and low power consumption, so that it is widely and generally used as a basic logic circuit. In addition, there are several types of basic logic circuits.
MOSs are connected in series or in parallel, and an output signal corresponding to an input signal is output as a power supply voltage or a ground potential.

[0005]

The problem of the conventional CMOS logic circuit will be described with reference to FIG. 10 using a CMOS inverter circuit as an example of the conventional logic circuit.

First, the potential Vin of the input signal, the power supply voltage VDD, or the potential difference between the input signal and the power supply voltage is limited to the range of the source / drain breakdown voltage and the gate oxide film breakdown voltage of the transistor. In a device having a low withstand voltage, there are restrictions on the potential amplitude of the input signal and the power supply voltage. For this reason, SOI (Silicon On Ins)
In order to constitute a circuit with a device having a low withstand voltage represented by an ullator element, it is necessary to operate at a low power supply voltage, and a mechanism for lowering the power supply voltage is additionally required. Inconsistency with the conventional parts, causing a problem in mixing with conventional parts.

Second, for example, the power supply voltage VDD is reduced by a regulator or the like to VDDL, and in the circuit A used as the power supply of the logic circuit, the output level is always lower than VDDL.
Therefore, when the output of the circuit A is input to the circuit B that operates using VDD as a power supply voltage, a problem such as insufficient amplitude occurs.

That is, in the prior art, there is no logic circuit that uses a power supply voltage higher than the withstand voltage of the element as it is.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a divided level logic circuit which operates at a power supply voltage higher than the withstand voltage of an element to be used and can output a plurality of output signals corresponding to a plurality of input signals at variable levels.

[0010]

In order to solve the above-mentioned problems, a split-level logic circuit according to the present invention comprises a CMOS logic circuit using MOS transistors, wherein one or more CMOS logic circuits operate by receiving predetermined signals. A first operating transistor comprising a PMOS transistor and one or more NMOs;
A third and a fourth clamp transistor are added in series between a second operating transistor composed of an S transistor, and an output terminal is connected to a connection point of the third and / or the fourth clamp transistor. It is characterized by having.

Alternatively, in the above-described division level logic circuit, the predetermined signal input to each of the pair of the first operation transistor and the second transistor is the same as that of the first operation transistor and the second transistor while maintaining the phase of the input signal. The input signal is divided into two different signals by the clamp voltage of the third and fourth clamp transistors.

Alternatively, in the above-mentioned divided level logic circuit, an output terminal YP is connected to a connection point between a first operating transistor and a third clamp transistor as the output terminal.
Is characterized in that an output terminal YN is provided at a connection point between the second operation transistor and the fourth clamp transistor.

Alternatively, in the above-mentioned division level logic circuit, different signals obtained by dividing one input signal for each pair of the first operation transistor and the second operation transistor are input to the third and fourth clamp transistors, respectively. By applying the same clamp voltage VB to the gates of the above, a signal that swings between the power supply voltage and VB is output to the output terminal YP, and a signal that swings between VB and ground potential is output to the output terminal YN. It is characterized by.

Alternatively, in the above-described division level logic circuit, different signals obtained by dividing one input signal for each pair of the first operation transistor and the second operation transistor are input to the gate of the third clamp transistor. By providing circuits for adjusting the applied clamp voltage VBn and the clamp voltage VBp applied to the gate of the fourth clamp transistor, the potential amplitudes of the output terminals YP and YN are adjusted.

The division level logic circuit of the present invention (hereinafter referred to as SLL)
[Abbreviated as [Separated LevelLogic]) divides an input terminal to a PMOS and an NMOS constituting a conventional CMOS logic circuit into two, adds two clamp transistors therebetween, and connects the gates of these clamp transistors to the gates of these clamp transistors. The input of the same voltage VB or the output level adjustment voltages VBp and VBn is different from the conventional logic circuit. Therefore, in the conventional logic circuit,
While only the input / output voltage that oscillates the power supply voltage and the ground potential is obtained, the present invention additionally provides VB or VB
An input / output signal having a plurality of potential amplitudes obtained by dividing the power supply potential and the ground potential by p and VBn is obtained. By adjusting VBp and VBn, an optimal input / output voltage according to the power supply voltage can be set.

For this reason, compared to the conventional device, the source
Even for devices with low drain withstand voltage and gate oxide film withstand voltage, operation with a voltage amplitude within the withstand voltage range of the device can be realized without changing the power supply voltage, so long-term reliability can be achieved without compromising compliance with existing standards. The secured circuit design becomes possible.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings.

The configuration of the first embodiment of the present invention will be described with reference to FIG. In the present embodiment, the most basic inverter circuit (NOT gate) is exemplified. MP1 and M
P3 is a P-channel MOS transistor having a threshold voltage Vthp, and MN4 and MN2 are N-channel MOS transistors having a threshold voltage Vthn. V for MP1
An input signal Vin_P having an amplitude of DD (power supply voltage) −VBp (PMOS clamp voltage) is input, and a signal having an amplitude of VBn (NMOS clamp voltage) −GND (ground potential) having the same phase as the input signal Vin_P is input to MN2. Vin_
Enter N. These two operating transistors MP1 and M
Between N2, two clamp transistors MP3 and MN
4 in series. An intermediate connection point between MP3 and MN4 is an inverter output terminal Vout, an intermediate connection point between MP1 and MP3 is a PMOS output terminal YP, and MN4 and MN4 are
The intermediate connection point of N2 is the NMOS output terminal YN.

In the above, the input signals Vin_P and Vin_N to the operation transistor are input to the input signal Vi by a waveform shaping circuit such as a level shifter, a clipper, and a clamper.
n. The output terminals YP and YN are
The output level Vout is used when connecting the divided level logic circuits in multiple stages, and the output terminal Vout is used when connecting to a conventional logic circuit or other general circuits. Therefore, output terminals that are not used depending on the purpose may be omitted. MP3, MN
4 is supplied from the outside or, for example, a circuit as shown in FIG. 2, that is, the PMOS transistors MP5, MP6 and NMO are connected between the power supply voltage VDD and the ground potential.
The S transistors MN7 are connected in series, and are supplied using a circuit that obtains a bias voltage from a connection point of each transistor. This bias voltage can be adjusted by changing the transistor size (eg, gate width, source-drain length, etc.) and adjusting the on-resistance. For simplicity, a resistance dividing circuit can be used.

In FIG. 1, high level signals (VDD and V) are supplied to operating transistors MP1 and MN2, respectively.
Bn) is input. Since the operation transistor MN2 and the clamp transistor MN4 are turned on, V
The GND level is output to the out terminal and the YN terminal.
On the other hand, the potential of the YP terminal does not decrease below VBp because the operation transistor MP1 is off and the clamp transistor MP3 maintains the threshold state.
| Vthp | is output.

Next, it is assumed that low-level signals (VBp and GND) are input to the operating transistors MP1 and MN2, respectively. Since the operation transistor MP1 and the clamp transistor MP3 are turned on, the VDD level is output to the Vout terminal and the YP terminal. On the other hand, since the operating transistor MN2 is off and the clamp transistor MN4 maintains the threshold state,
The potential does not increase above VBn, and VBn− | Vthn |
Is output.

As described above, the inverted signals of the input signals to MP1 and MN2 are output to the YP terminal and the YN terminal, respectively, and the inverted signals having the amplitude of the power supply voltage and the ground potential are output to the Vout terminal. Therefore, no potential difference between any terminal of any transistor is equal to or less than the difference between the power supply voltage and the clamp voltage, or equal to or less than the clamp voltage and the ground potential.

FIG. 3 shows that VDD = 3.3 V and VBp = 1.0 in the first embodiment of the present invention shown in FIG.
The circuit simulation results when V and VBn = 2.0 V are shown. In the simulation, four stages of the inverter circuits shown in FIG. 1 are connected in parallel, and the result shows each output of the third stage inverter. Frequency is 200MHz
The duty ratio, that is, the ratio of the ON (high level) time in one pulse period was set to 50%. In FIG. 3, the output signals of the output terminals YP, YN, and Vout are represented as VYP, VYN, and Vout.

As shown in FIG. 3, the power supply voltage is 3.3 V
, The YP terminal outputs a voltage amplitude of 1V to 3.3V, and the YN terminal outputs an amplitude of 0V to 2V. Further, when the YP and YN terminals are at a high level,
The Vout terminal also outputs 3.3V, which is at a high level, and when the YP and YN terminals are at a low level, the Vout terminal also outputs 0V, which is at a low level. That is, Vout
From the terminal, as in the conventional inverter circuit, VDD
And a signal having the amplitude of GND can be obtained.

As described above, the potential difference between the terminals of each transistor does not exceed VDD-VBp in MP1, and
P3 does not exceed VDD-VBp or VBp-GND. Similarly, a potential difference exceeding VBn-GND in MN2 and VBn-GND or VDD-VBn in MN4 is not applied between the terminals. V according to the withstand voltage of the device
If the values of Bp and VBn are selected, the upper limit of the power supply voltage can be increased as compared with the conventional technique, as long as the maximum potential difference does not exceed the breakdown voltage.

The structure of the second embodiment of the present invention will be described with reference to FIG. Although the first embodiment requires two different clamp voltages, VBp = VBn (= V
When B) can be selected, one clamp terminal can be used as shown in FIG.

A third embodiment of the present invention will be described with reference to FIG. FIG. 5 shows N which is one of the most basic logic circuits.
FIG. 3 is a circuit diagram in the case where an AND gate is configured using the division level logic circuit of the present invention.

In this embodiment, the operating transistors MP1-1 and MP1-2 (PMOS) connected in parallel,
Operating transistors MN2-2 and MN2 connected in series
-1 (NMOS) between the clamp transistor MP
3 (PMOS) and MN4 (NMOS) are connected in series.

Operating transistors MP1-1 and MP1-2
Input terminals are denoted by AP1 and AP2, respectively, and input signals are denoted by VP1 and VP2, respectively. Similarly, input terminals and input signals to the operation transistors MN2-1 and MN2-2 are supplied to AN1, AN2 and VN1, V, respectively.
N2. Operating transistors MP1-1 and MP1
The output terminal YP is drawn from the connection point of the operating transistor MN2-2 and the clamp transistor MN4, and the output terminal Vout is drawn from the connection point of the clamp transistors MP3 and MN4. , Each output signal is VY
P, VYN and Vout. The correspondence between each terminal and the voltage (signal) in the circuit of FIG. 5 is as shown in FIG.

Operation The input / output signals to the PMOS transistors, ie, VP1, VP2, and VYP, have the high-level potential as the power supply voltage VDD and the low-level potential as the clamp voltage VBp input to the clamp transistor MP3. The input / output signals to the operation NMOS transistors, that is, VN1, VN2, and VYN are such that the high-level potential is the clamp voltage VBn input to the MN4 and the low-level potential is the ground potential (0 V). AP1, AN1, AP2
And AN2 are paired to form two inputs of a NAND gate. Input signals of the same level are divided and input to the transistors of each pair by a clamp voltage.

The means for dividing the input signal, the means for generating the clamp voltage, and the use of the output terminal and the omission thereof are as described in the first embodiment.

FIG. 6 shows a truth table of the circuit of FIG. This circuit outputs a low level (L) at both the YP and YN terminals when all the input signals are at a high level (H), but outputs a high level (H) in other combinations and outputs the NAND logic. Functions as a circuit.

According to the same principle as that of the first embodiment, the low level (L) of the YP terminal is obtained by the operation of the clamp transistor.
Is not lower than VBp, and the high-level (H) potential of the YN terminal is not higher than VBn. By appropriately selecting the clamp voltages VBp and VBn, the potential difference between the terminals of each element can be reduced. The device can be operated within a range not exceeding the withstand voltage of the element.

A fourth embodiment of the present invention will be described with reference to FIG. FIG. 7 shows N which is one of the most basic logic circuits.
FIG. 3 is a circuit diagram in the case where an OR gate is configured using the division level logic circuit of the present invention.

In this embodiment, operating transistors MP1-1 and MP1-2 (PMOS) connected in series
Operation transistors MN2-2 and MN2 connected in parallel
-1 (NMOS) between the clamp transistor MP
3 (PMOS) and MN4 (NMOS) are connected in series.

Operating transistors MP1-1 and MP1-2
Input terminals are denoted by AP1 and AP2, respectively, and input signals are denoted by VP1 and VP2, respectively. Similarly, input terminals and input signals to the operation transistors MN2-1 and MN2-2 are supplied to AN1, AN2 and VN1, V, respectively.
N2. The output terminal YP is connected from the connection point between the operation transistors MP1-2 and the clamp transistor MP3, the output terminal YN is connected from the connection point between the operation transistors MN2-1 and MN2-2, and the connection point between the clamp transistors MP3 and MN4. Output terminal Vo
ut respectively, and output signals VYP, V
YN and Vout. The correspondence between each terminal and the voltage (signal) in the circuit of FIG. 7 is as shown in FIG.

Operation The input / output signals to the PMOS transistors, ie, VP1, VP2, and VYP, have the high-level potential as the power supply voltage VDD and the low-level potential as the clamp voltage VBp input to the clamp transistor MP3. The input / output signals to the operation NMOS transistors, that is, VN1, VN2, and VYN are such that the high-level potential is the clamp voltage VBn input to the MN4 and the low-level potential is the ground potential (0 V). AP1, AN1, AP2
And AN2 are paired to form two inputs of a NOR gate. Input signals of the same level are input to the transistors of each pair after being divided by the clamp voltage.

The means for dividing the input signal, the means for generating the clamp voltage, and the use of the output terminal and the omission thereof are as described in the first embodiment.

FIG. 8 shows a truth table of the circuit of FIG. This circuit outputs a high level (H) at both the YP and YN terminals when all the input signals are at a low level (L), but the other combination, that is, one or both of the paired input terminals are output. In the case of a high level (H), a low level (L) is output and functions as a NOR logic circuit.

According to the same principle as in the first embodiment, the low level (L) of the YP terminal is obtained by the operation of the clamp transistor.
Is not lower than VBp, and the high-level (H) potential of the YN terminal is not higher than VBn. By appropriately selecting the clamp voltages VBp and VBn, the potential difference between the terminals of each element can be reduced. The device can be operated within a range not exceeding the withstand voltage of the element.

As described above, by connecting two clamp transistors between one or more PMOS transistors and one or more NMOS transistors that perform switching operation, the NOT, NAND, NOR shown in the above embodiment can be obtained.
The same effect can be achieved for all other logic gates. The logic circuit of the present invention is digital,
The present invention can be applied to both analog circuits and the same effect can be realized in a digital / analog mixed circuit.

[0042]

As described above, according to the present invention, even when a power supply voltage exceeding the breakdown voltage of an element is used, the logic circuit can be operated with a potential difference within the breakdown voltage range without stepping down the power supply voltage by a regulator or the like. it can. Also, since no external step-down circuit or booster circuit is required, it is possible to avoid an increase in cost,
System volume can be reduced. In the present invention, for example, SOI
In circuits using elements such as elements that can be easily miniaturized and highly integrated, have high-speed operation and low power consumption characteristics, but have low withstand voltage between the source and drain and do not have sufficient performance at high power supply voltages. Also, a conventional power supply voltage such as 5 V or 3.3 V can be applied as it is. Furthermore, like a lithium ion battery, it has a high power density but an initial voltage of 4.1.
Since a battery having a high output voltage of V can be used as a power source as it is, a low-voltage element can be used in a portable environment. As described above, by using the division level logic circuit of the present invention, it is possible to exhibit high performance such as an SOI element while maintaining the consistency with the conventional element.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention,
The division level logic circuit of the present invention is connected to an inverter circuit (NO
FIG. 9 is a circuit diagram when applied to a (T gate).

FIG. 2 is a diagram illustrating an example of a bias voltage generation circuit according to the embodiment.

FIGS. 3A, 3B, 3C, and 3D are diagrams illustrating simulation analysis results of the circuit illustrated in FIG. 1;

FIG. 4 is a diagram showing a second embodiment of the present invention,
FIG. 2 is a circuit diagram when the clamp voltages in the circuit shown in FIG. 1 are integrated into one.

FIG. 5 is a view showing a third embodiment of the present invention,
FIG. 3 is a circuit diagram when the division level logic circuit of the present invention is applied to a NAND gate.

FIG. 6 is a diagram showing a truth table of FIG. 5;

FIG. 7 is a diagram showing a fourth embodiment of the present invention,
FIG. 3 is a circuit diagram in a case where the division level logic circuit of the present invention is applied to a NOR gate.

FIG. 8 is a diagram showing a truth table of FIG. 7;

FIG. 9 is a diagram showing the correspondence between each terminal and a voltage (signal) in FIGS. 5 and 7;

FIG. 10 is a diagram illustrating a conventional inverter circuit (NOT gate).

[Explanation of symbols]

MP1, MP1-1, MP1-2: operation transistor (PMOS) MN2, MN2-1, MN2-2: operation transistor (NMOS) MP3: clamp transistor (PMOS) MN4: clamp transistor (NMOS)

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J055 AX33 AX34 AX52 AX64 BX16 CX24 DX22 DX56 DX72 DX83 EX07 EX21 EY21 EZ07 EZ16 FX12 FX17 FX35 GX01 GX04 5J056 AA03 AA11 BB46 CC12 DD13 DD29 EE11

Claims (5)

[Claims] In a CMOS logic circuit using MOS transistors, one or more P-type logic circuits, each of which operates by receiving a predetermined signal, are provided.
A third operating transistor having a configuration in which third and fourth clamp transistors are added in series between a first operating transistor including a MOS transistor and a second operating transistor including one or more NMOS transistors; Wherein the output terminal is provided at a connection point of one or both of the clamp transistors. 2. The division level logic circuit according to claim 1, wherein said predetermined signal input to each of a pair of a first operation transistor and a second transistor maintains a phase of an input signal. A divided level logic circuit comprising two different signals obtained by dividing the amplitude of the input signal by the clamp voltages of the third and fourth clamp transistors. 3. The divided level logic circuit according to claim 1, wherein an output terminal YP is connected to a connection point between the first operating transistor and the third clamp transistor as the output terminal.
And an output terminal YN at a connection point between the operating transistor and the fourth clamp transistor. 4. The divided level logic circuit according to claim 3, wherein different signals obtained by dividing one input signal for each pair of the first operation transistor and the second operation transistor are inputted, respectively, By applying the same clamp voltage VB to the gate of the clamp transistor of
A split-level logic circuit, wherein a signal that swings between a power supply voltage and VB is output to P, and a signal that swings between VB and ground potential is output to the output terminal YN. 5. The divided level logic circuit according to claim 3, wherein different signals obtained by dividing one input signal for each pair of the first operation transistor and the second operation transistor are input, respectively, and a third clamp transistor is provided. The circuit for adjusting the clamp voltage VBn applied to the gate of the fourth clamp transistor and the clamp voltage VBp applied to the gate of the fourth clamp transistor is provided, whereby the output terminal YP and the output terminal YN are provided.
A divided level logic circuit, wherein a potential amplitude of the divided level logic circuit is adjusted.