JP2001125694A - Bridge device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bridge device which actualizes adequate ordering control through a serial transmission line without providing a signal line for ordering. SOLUTION: A PCI-PCI bridge 300 makes a cable connection between a PCI bus (primary) 2 on the side of a computer main body 100 and a PCI bus (secondary) 3 on the side of an extension unit 200 for function extension and is divided physically into two controllers (P-PCI bridge 300a and S-PCI bridge 300b) for the cable connection. Each of these two controllers processes, for example, posted memory write preferentially to all other transactions and operates so that adequate ordering control is performed as a logically single PCI-PCI bridge 300 irrelevantly to the state of the PCI bus connected to the other controller.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bridge device for connecting two buses constituted by parallel transmission lines having a plurality of bit widths via a serial transmission line, and more particularly to a bridge device having a signal line for ordering. The present invention relates to a bridge device that realizes appropriate ordering control via a serial transmission path without using a bridge device.

[0002]

2. Description of the Related Art In recent years, various notebook personal computers which are easy to carry and can be operated by a battery have been developed. Some of these types of personal computers are configured so that they can be attached to an expansion unit as needed to expand their functions. In order for the resources of the expansion unit to be effectively used from the computer main unit, it is necessary to connect a bus in the computer main unit to a bus in the expansion unit. With this bus connection, devices on the bus in the expansion unit can be handled in the same way as devices in the computer main body.

In recent personal computers, PCs
I (Peripheral Component In)
A terconnect bus is often used. Therefore, the bus connection between the computer main body and the expansion unit is performed by providing docking connectors having a number of pins corresponding to the number of signal lines of the PCI bus on the computer main body side and the expansion unit side, respectively. This is usually done by physically connecting both PCI buses via a connector.

FIG. 7 is a diagram for explaining a state of bus connection between a computer main unit and an expansion unit in a conventional computer system.

As shown in FIG. 7, in the conventional computer system, the PCI bus (primary) 2 is electrically led out of the docking connector only when the expansion unit 200 is mounted on the computer main body 100 side. Switch 15 is provided for one of the extension units 2
On the 00 side, a PCI bus for connecting the PCI bus (primary) 2 and the PCI bus (secondary) 3 in two directions is provided.
By providing the PCI bridge 16, a device on the PCI bus (primary) 2 accesses a device on the PCI bus (secondary) 3, and
A device on the I bus (secondary) 3 can access a device on the PCI bus (primary) 2.

However, in such a configuration, since a large area is required for mounting the docking connector, miniaturization and thinning of the computer main body are hindered. Since the connector mounting position must be matched, the physical housing structure has been restricted.

For these reasons, recently, a bridge device (PCI-PCI bridge) for connecting between two PCI buses in order to connect a computer main body and an extension unit with a cable having a small number of signal lines. Is divided into two physically different controllers connected to two PCI buses, respectively, and the two controllers are connected by a serial transmission line. That is, a logically single controller is physically divided into two controllers.

By the way, the ordering of a bridge device for interconnecting the two PCI buses is defined as a PCI bus standard as shown in FIG.
-To-PCI Bridge Architect
re Specification Rev .. 1.
1). Since the conventional bridge device is physically a single controller, the status of the two PCI buses can be grasped in real time, and this ordering control is easy. However, in a bridge device physically divided into two controllers, the ordering control is very difficult because the state of the PCI bus connected to the other controller cannot be grasped in real time. Further, if a signal line for ordering is provided between the two controllers, the intended purpose of connecting the computer main unit and the extension unit with a cable having a small number of signal lines cannot be achieved. .

[0009]

As described above, in a bridge device physically divided into two controllers, the status of a PCI bus connected to the other controller cannot be grasped in real time. Is very difficult, and if the signal line for ordering is provided between the two controllers, the intended purpose of connecting the computer and the expansion unit with a cable with few signal lines is achieved. There was a problem that it became impossible to do.

[0010] The present invention has been made in view of such circumstances, and provides a bridge device that realizes appropriate ordering control via a serial transmission line without having a signal line for ordering. With the goal.

[0011]

In order to achieve the above-mentioned object, a bridge device according to the present invention comprises a PCI device in which two controllers are connected to each other.
Regardless of the state of the bus, it operates so that appropriate ordering control is performed as a whole, that is, as a logically single bridge device. Connected to the configured first and second buses, respectively, and
A first physically different device that communicates transactions with each other via a serial transmission path so that devices on one bus of the other bus can access devices on the other bus.
And a second controller, wherein each of the first and second controllers processes a write transaction that ends without receiving a write completion notification from a final write destination with priority over all other transactions. It is characterized by having ordering control means for controlling the transfer of the transaction.

The write transaction referred to here is:
For example, Posted Memory Write.

Further, in the bridge device according to the present invention, the ordering control means may be configured such that the ordering control means gives priority to sending delayed read completion or delayed write completion for responding to a request from the other controller. The transmission of the transaction is controlled to process the transmission of the posted memory write.

Further, in the bridge device according to the present invention, the ordering control means may be configured such that the ordering control means gives priority to sending delayed read completion or delayed write completion for responding to a request from the other controller. The transmission of the transaction is controlled to process the transmission of the delayed read request or the delayed write request.

Further, in the bridge device according to the present invention, the ordering control means may be arranged so that the ordering control means responds to a request from the other controller prior to transmission of its own delayed read request or delayed write request. The transmission of the transaction is controlled to process the transmission of the read completion or the delayed write completion.

In the bridge device according to the present invention, it is not necessary to have a signal line for ordering control, so that the number of signal lines on the serial transmission line can be reduced to a minimum.

Further, in the bridge device according to the present invention, the ordering control means may be configured to perform a single delayed read operation prior to the burst delayed read completion.
Preferably, the transmission of transactions is controlled to handle read completions.

In the bridge device according to the present invention, the transfer performance between the two buses can be improved.

Further, in the bridge device according to the present invention, the ordering control means has an operation mode for controlling transmission of a transaction by rotation priority instead of a predetermined priority order. Regardless of the above, it is preferable to have an operation mode for controlling transmission of a transaction.

In the bridge device according to the present invention, it is possible to prevent unexpected deadlock.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a configuration of a computer system according to one embodiment of the present invention.

This computer system is a notebook type personal computer, and includes a computer main body 100 and an expansion unit 200 for function expansion which can be used by connecting to the computer main body 100 via a cable.
And a PCI-PCI bridge 3 in which a single logical controller is physically divided into two controllers (P-PCI bridge 300a and S-PCI bridge 300b) in order to perform this cable connection.
00 is provided. These two controllers (P-PC
I bridge 300a, S-PCI bridge 300b)
Are connected by a bus having a protocol different from that of the PCI bus, and are viewed as one PCI bridge device in terms of software.

In the computer main body 100, a processor bus 1 and a PCI bus (primary) 2 are laid, and a CPU 11, a host-PCI bridge 12, a main memory 13, various PCI devices 14, and a PCI-P
The P-PCI bridge 300a of the CI bridge 300 is mounted.

The CPU 11 is connected to the computer main body 10.
0 controls the entire operation of the main memory 1
3 to execute various application programs including an operating system, a system BIOS, and a utility. The host-PCI bridge 12 is a bridge device that bidirectionally connects the processor bus 1 and the PCI bus (primary) 2, and has a built-in memory control logic for controlling access to the main memory 13. The host-PCI bridge 12 is connected to a PCI bus (primary) 2.
Can function as the upper bus master. The main memory 13 stores an operating system and a system BIO.
S or various application programs including utilities and various user data.

The P-PCI bridge 300a is provided with an S-PCI bridge 300b provided in the extension unit 200.
And a logically single PCI-PCI bridge 30
0. The PCI-PCI bridge 300 is used to bidirectionally connect a PCI bus (primary) 2 in the computer main body 100 and a PCI bus (secondary) 3 in the expansion unit 200, and provides a PCI bus (primary). PCI device 1 on 2)
4 is a PCI device 1 on a PCI bus (secondary) 3
7 and allow the PCI device 17 on the PCI bus (secondary) 3 to access the PCI device 14 on the PCI bus (primary) 2. In this embodiment, a PC connecting the PCI bus (primary) 2 and the PCI bus (secondary) 3
The I-PCI bridge 300 is connected to two physically different controllers (P-PCI bridge 300a, S-PCI
A PCI serial interface is realized by dividing the bridge into bridges 300b) and connecting them with a serial transmission line. Then, the PCI-P of this embodiment
The CI bridge 300 uses the two controllers (P-
PCI bridge 300a, S-PCI bridge 300
b) PCs each connected to the other controller
Regardless of the state of the I bus, by operating to perform appropriate ordering control as a whole, that is, as a single logically single PCI-PCI bridge 300, without having a signal line for ordering, It is characterized by realizing appropriate ordering control via a serial transmission line. Hereinafter, this point will be described in detail.

FIG. 2 shows an internal block of the P-PCI bridge 300a. The P-PCI bridge 300a
And the S-PCI bridge 300b have basically the same structure.

The PCI bus control block 301
Is a PCI bus master and target
It is for controlling the bus interface and has a master latency timer (MLT).

PCI bus arbitration block 3
An arbiter 02 performs arbitration of a PCI bus master on the PCI bus (secondary) 3.

The cycle decode block 303 includes a PC
At the time of I bus target operation, a PCI cycle type and an address are decoded to determine hit. The cycle decode block 303 includes a cycle start signal for the transaction buffer & control block 305 and a PCI bus control block 3.
01 is generated.

Configuration register block 3
04 is a so-called PCI configuration register. The transaction buffer & control block 305 is a buffer for managing a PCI bus cycle as a transaction, and includes a block transfer buffer block 307 and a PCI bus control block 30.
1 is controlled.

Block & word buffer block 306
Is a block in which two blocks of a block transfer buffer block 307 and a word buffer block 308 are combined into one for convenience.
Reference numeral 07 denotes a buffer for temporarily storing data exchanged with the transaction buffer & control block 305 or the word buffer block 308. Also, a buffer for post-write (OE
B / IEB), and independently for transactions other than post-write (OBB / IBB). OE in the figure
B / OBB is a transmission buffer, and IEB / IBB is a reception buffer. Note that this post-write is performed without the request source receiving a write completion notification from the write destination.
This is a write transaction that ends when a response is received from a bridge device that intervenes with the write destination. The transmission and reception buffers operate with asynchronous transmission and reception clocks generated by the PLL in the bit layer block 309, respectively. Since the PCI clock is not used, the block is not synchronized with the block in the layer higher than the block transfer buffer block 307.
The block & word buffer block 306
Performs checksum generation, error checking on the serial bus, and control of retransmission processing.

On the other hand, the word buffer block 308
This is a buffer for temporarily storing fixed-length data from the block transfer buffer block 307 so as to be transferred one by one with the bit layer block 309. In the figure, OWB denotes a transmission buffer, and IWB denotes a reception buffer.
It operates with asynchronous transmission and reception clocks generated by the PLLs within.

The bit layer block 309 divides the fixed-length data from the word buffer block 308 into two parts and performs serial communication as two systems of serial data. The transmitting side performs parallel-to-serial conversion. The receiving side performs serial-to-parallel conversion. Also,
This bit layer block 309 has PLLs for transmission and reception, respectively.
It operates based on the input (multiplied by 9), and the receiving PLL
It operates based on DC_I (LVDS serial reception clock) input. Note that the output of LVDC_O (LVDS serial transmission clock) has the same frequency as the input of PLCLK.

The Misc information update block 310 is a PC
Miss interrupt signal (INT [A: D] #) of I bus
This is a block for processing as c information. The serial interrupt synchronization block 311 is a block for processing an Intel serial interrupt and a legacy interrupt signal.

Next, the control flow will be briefly described with reference to FIGS.

First, a memory write cycle (PM) from the computer main body 100 to the extension unit 200 side is performed.
The case W) will be described.

(1) The memory write cycle issued from the CPU 11 appears on the PCI bus (primary) 2 via the host-PCI bridge 12.

(2) In the P-PCI bridge 300a,
The cycle is decoded by the cycle decode block 303, and the PCI bus control block 301 and the transaction buffer & control block 3
05 is notified that the cycle is to be responded to.

(3) PCI bus control block 3
01 is DEVSEL on the PCI bus (primary) 2
Assert # and respond to this cycle.

(4) The transaction buffer & control block 305 executes the memory write cycle (PM
At the stage when W) is latched, a cycle end (TRDY # assert) request is issued to the PCI bus control block 301.

(5) PCI bus control block 3
01 asserts the TRDY # signal on the PCI bus (primary) 2 to end the cycle.

(6) The PMW request latched in the transaction buffer & control block 305 is transmitted from OEB → O in the block & word buffer block 306.
WB → Sent to the P / S circuit in the bit layer block 309, and sent to the S-PCI bridge 300b via the LVDS buffer.

(7) The PMW request arriving at the S-PCI bridge 300b is sent to the S / P circuit in the bit layer block 309 → the block & word buffer block 306.
Is sent to the transaction buffer & control block 305 via IWB → IEB.

(8) The transaction buffer & control block 305 requests the PCI bus control block 301 to issue a memory write cycle as a PCI master.

(9) PCI bus control block 3
01 asserts REQ # to the PCI bus (secondary) 3 and executes a memory write cycle as a PCI master when GNT # is received.

Next, a case of a single memory read cycle (DRR / DRC) from the computer main body 100 to the extension unit 200 will be described.

(1) The memory read cycle issued from the CPU 11 appears on the PCI bus (primary) 2 via the host-PCI bridge 12.

(2) In the P-PCI bridge 300a,
The cycle is decoded by the cycle decode block 303, and the PCI bus control block 301 and the transaction buffer & control block 3
05 is notified that the cycle is to be responded to.

(3) PCI bus control block 3
01 is DEVSEL on the PCI bus (primary) 2
Assert # and respond to this cycle.

(4) The transaction buffer & control block 305 executes the memory read cycle (DR
At the same time as R) is latched, preparation for data transfer to the block & word buffer block 306 is started.

(5) If there is no return data (or end status) for this memory read cycle from the block & word buffer block 306 after waiting for a certain time, a retry request is issued to the PCI bus control block 301.

(6) PCI bus control block 3
01 asserts the STOP # signal on the PCI bus (primary) 2 to retry the cycle.

(7) The DRR request latched by the transaction buffer & control block 305 is changed from OBB → O in the block & word buffer block 306.
WB → Sent to the P / S circuit in the bit layer block 309, and sent to the S-PCI bridge 300b via the LVDS buffer.

(8) The DRR request arriving at the S-PCI bridge 300b is sent to the S / P circuit in the bit layer block 309 → the block & word buffer block 306.
Is sent to the transaction buffer & control block 305 via IWB → IBB.

(9) The transaction buffer & control block 305 requests the PCI bus control block 301 to issue a memory read cycle as a PCI master.

(10) The PCI bus control block 301 sends REQ # to the PCI bus (secondary) 3.
Is asserted, and a memory read cycle is executed as a PCI master when GNT # is received.

(11) When TRDY # is asserted from the PCI device 17 which is the target of this cycle, the PCI bus control block 301
End the cycle as master.

(12) The transaction buffer & control block 305 latches the data at this time and simultaneously changes the internal flag from DRR to DR.
Change to C, block & word buffer block 30
Preparations for data transfer to 6 begin.

(13) The read data (DRC) latched by the transaction buffer & control block 305 is stored in the block & word buffer block 30.
6 OBB → OWB → bit layer block 309
And is sent to the P-PCI bridge 300a via the LVDS buffer.

(14) The read data (DRC) arriving at the P-PCI bridge 300a is transferred to the transaction buffer via the S / P circuit in the bit layer block 309 → IWB in the block & word buffer block 306 → IBB. & Control block 305.

(15) If the flag inside the transaction buffer & control block 305 is DRR →
The state changes to DRC, and a response to the memory read cycle retried in (6) is ready.

(16) The memory read cycle subjected to the retry in (6) is reissued.

(17) In the P-PCI bridge 300a, the cycle is decoded by the cycle decode block 303, and the PCI bus control block 301
Then, the transaction buffer & control block 305 is notified that the cycle is to be responded.

(18) The PCI bus control block 301 transmits the DEVSE on the PCI bus (primary) 2.
Assert L # and respond to this cycle.

(19) The transaction buffer & control block 305 determines whether or not this cycle is the cycle in which the retry was performed in (6). If it is determined that the cycle is the same as the cycle (6), the transaction buffer & control block 305 issues a data transfer request to the PCI bus control block 301.

(20) The PCI bus control block 301 asserts TRDY # and ends the cycle.

Before the state (15) is reached, (6)
When the same cycle as the cycle (1) is issued, a retry is performed after waiting for a predetermined time.

Next, the case of a write cycle (DWR / DWC) other than memory write from the computer main body 100 to the expansion unit 200 side is used in the case of the single memory read cycle described above. The control is almost the same except that the flags are different.

FIG. 3 shows an internal block of the transaction buffer & control block 305.

The configuration access (target) control block 312 performs control as a PCI target when the chip is in the test mode. Single read buffer (target) control block 313
Controls a single read cycle as a PCI target.

The single write buffer (target) control block 314 controls a single write cycle other than a memory write as a PCI target. The prefetch burst read buffer (target) control block 315 controls a memory read burst cycle as a PCI target.

The memory post-burst buffer (target) control block 316 has a PCI target
The memory write (single / burst) cycle is controlled. The single read buffer (master) control block 317 controls a single read cycle as a PCI master.

The single write buffer (master) control block 318 controls a single write cycle other than memory write as a PCI master. Prefetch burst read buffer (master) control block 31
Reference numeral 9 controls a (prefetch) memory read burst cycle as a PCI master.

Memory post burst buffer (master)
The control block 320 controls a memory write (single / burst) cycle as a PCI master. Synchronization block (OBB buffer / TBC block) 32
1 synchronizes data at the time of asynchronous data transfer between the OBB buffer and itself (TBC block).

Synchronization block (IBB buffer / TBC)
The block 322 synchronizes data at the time of asynchronous data transfer between the IBB buffer and itself (TBC block). The PCI target latency timer block 323 counts the latency when responding as a PCI target.

OBB buffer access arbitration block 3
24 arbitrates an access request to the OBB buffer.
The configuration register block access arbitration block 325 arbitrates an access request to the configuration register block. Then, the PCI master access arbitration block 326 arbitrates an access request as a PCI master.

FIG. 4 shows connection of ordering-related signals in the transaction buffer & control block 305.

Ordering is performed in four places: the OBB buffer access arbitration block 324, the PCI master access arbitration block 326, the single read buffer (target) control block 313, and the prefetch burst read buffer (target) control block 315.

(1) OBB Buffer Access Arbitration Block 324 The OBB buffer access arbitration block 324 arbitrates requests from the following six blocks and permits access to the OBB buffer.

Prefetch burst read buffer (target) control block 315 = burst DRR, single read buffer (target) control block 313
= Single DRR, single write buffer (target) control block 314 = DWR, prefetch burst read buffer (master) control block 319 = burst DRC, single read buffer (master) control block 317 = single DRC, single write buffer (master) control Block 318 = DWC.

Note that a read request is handled as an independent request because control is divided into a single cycle and a burst cycle. The burst DRR is a burst memory read request, the single DRR is a single memory read / IO read / configuration read request, the DWR is an IO write / configuration write request, the burst DRC is return data and a cycle end flag for the burst DRR, the single DRC
Is return data and an end flag for a single DRR, and DWC is an end flag for a DWR.

The priority in arbitration is single DRC>
Single DWC> Burst DRC> Single DRR> Single DWR> Burst DRR. However, PMW
Memory post burst buffer (target) control block 316 to prioritize (post memory write)
If there is data in the file (MPBT_BUSY = “1”), the access permission to the OBB buffer is not issued (the PMW has the highest priority). Note that OBODR_D
By setting the S signal to "1", this priority can be given to the rotation priority.

(2) PCI Master Access Arbitration Block 326 The PCI master access arbitration block 326
It arbitrates requests from the two blocks and grants access as a PCI mask.

Prefetch burst read buffer (master) control block 319 = burst DRR, single read buffer (master) control block 317 = single DRR, single write buffer (master) control block 318 = DWR, memory post burst buffer (master) control Block 320 = PMW.

The priorities at the time of arbitration are: PMW> single DRR>DWR> burst DRR.

Note that, by setting the PMODR_DS signal to “1”, this priority can be given to rotation priority.

(3) Single Read Buffer (Target) Control Block 313 Single Read Buffer (Target) Control Block 3
In step 13, when responding as a PCI target, control (retry is returned) so as not to end the single read (takeover of single DRC) cycle until the PMW in the reverse direction ends (until MPBM_DIN = "0"). Do.

Note that by setting PTODR_DS to "1", the single read cycle can be terminated regardless of the PMW factor.

(4) Prefetch Burst Read Buffer (Target) Control Block 315 When responding as a PCI target, the prefetch burst read buffer (target) control block 315 waits until the PMW in the reverse direction ends (MPBM_DI).
Until N = "0"), control (retry is returned) so as not to end the burst memory read (burst DRC takeover) cycle.

Note that by setting PTODR_DS to "1", the burst memory read cycle can be terminated regardless of the PMW factor.

FIG. 5 shows an internal block of the block & word buffer block 306.

The transmission express buffer 327 includes a transaction buffer & control block 305.
Is a buffer for temporarily storing and transmitting a PMW request (& data) from the server.

The transmission block buffer 328 is a buffer for temporarily storing and transmitting DRR, DRC, DWR, and DWC requests and data from the transaction buffer & control block 305.

Serial interrupt synchronization & transmission block 3
Reference numeral 29 denotes a block for transmitting serial interrupt information. Misc information synchronization & transmission block 330
Is a block for transmitting Misc information (such as a PCI interrupt).

[0095] The NOP information transmission block 331 is a block for transmitting a specific code (NOP) when there is no transmission data. ACK information transmission block 33
Reference numeral 2 denotes a block for transmitting a code (ACK or NACK) indicating whether or not the received data (or code) has been normally received.

The transmission word buffer 333 includes the six blocks (the transmission express buffer 327, the transmission block buffer 328, the serial interrupt synchronization & transmission block 329, the Misc information synchronization & transmission block 330, and the NOP information transmission block). 331, a buffer for temporarily storing and transmitting the transmission data from the ACK information transmission block 332).

The transmission word buffer arbiter 334 is
The six blocks (express buffer for transmission 3)
27, transmission block buffer 328, serial interrupt synchronization & transmission block 329, Misc information synchronization &
Transmission block 330, NOP information transmission block 331,
The request for using the transmission word buffer 333 from the ACK information transmission block 332) is arbitrated, and use permission is given to any one of them.

The receiving express buffer 335 is a transaction buffer & control block 305.
Buffer for receiving and temporarily storing a PMW request (& data) to the server.

The receiving block buffer 336 is a buffer for receiving the DRR, DRC, DWR, and DWC requests and data to the transaction buffer & control block 305 and temporarily storing the data.

Serial interrupt information receiving block 337
Is a block for receiving serial interrupt information. The Misc information receiving block 338 is a block for receiving Misc information (such as a PCI interrupt).

The NOP information receiving block 339 determines whether the NOP
It is a block for receiving information. The ACK information receiving block 340 is a block for receiving ACK or NACK information.

The receiving word buffer 341 includes the six blocks (the receiving side express buffer 335, the receiving side block buffer 336, the serial interrupt information receiving block 337, the Misc information receiving block 338, N
It is a buffer for receiving the data received to the OP information receiving block 339 and the ACK information receiving block 340) and temporarily storing the data.

The ACK arbiter 342 receives ACKs (data has been received) from three blocks on the receiving side (reception express buffer 335, reception block buffer 336, serial interrupt information reception block 337).
Arbitrate the NACK (data not received) transmission request and select one of them to send an ACK information transmission block 332.
Tell

The ACK flag 343 indicates the information (ACK or N) received by the ACK information reception block 340.
ACK), and express buffer 32 for transmission
7. Transmit to the transmission block buffer 328 or the serial interrupt synchronization & transmission block 329.

This block & word buffer block 3
The ordering at 06 is performed by the transmission word buffer arbiter 334 and the reception block buffer 336.
It takes place in several places. The transmission word buffer arbiter 334 performs the ordering on the transmission side, and the reception block buffer 336 performs the ordering on the reception side.

(1) Transmission Word Buffer Arbiter 33
4. The transmission word buffer arbiter 334 arbitrates requests from the following six blocks and permits access to the OWB buffer.

Transmission express buffer 327 = PM
W, transmission block buffer 328 = single DRR,
Burst DRR, DWR, Single DRC, Burst D
RC, DWC, serial interrupt synchronization & transmission block 329 = serial interrupt information, Misc information synchronization &
Transmission block 330 = Misc information, NOP information transmission block 331 = NOP code, ACK information transmission block 332 = ACK / NACK.

The priority in arbitration is as follows: Misc information synchronization & transmission block 330> ACK information transmission block 33
2> serial interrupt synchronization & transmission block 329> transmission express buffer 327> transmission block buffer 328> NOP information transmission block 331. P
Express buffer 3 for transmission to give priority to MW
27> The transmission block buffer 328 is provided.

By setting the ROT_PRI signal to “1”, the arbitration of the transmission express buffer 327 and the transmission block buffer 328 can be given priority to rotation.

When the RVS_PRI signal is set to "1", the priority of the transmission express buffer 327 and the transmission block buffer 328 can be set such that the transmission express buffer 327 <the transmission block buffer 328.

Neither signal affects the arbitration circuits other than the transmission express buffer 327 and the transmission block buffer 328.

(2) Reception block buffer 336 In the reception block buffer 336, the transaction buffer & control is performed until the IEB_EMPTY signal indicating that there is no PMW request (or data) in the reception express buffer 335 becomes "1". Control is performed so as not to issue a data collection request to the block 305. This is how the PMW is converted to DRR / DRC / DWR
This is for giving priority to / DWC.

By setting the ODR_DIS signal to “1”, the DRR / DRC / DWR in the receiving block buffer 336 can be set regardless of the IEB_EMPTY signal.
/ DWC to the transaction buffer & control block 305.

As described above, the ordering control circuit shown in FIG. 4 and FIG.
Since each of the CI bridges 300b has this PCI-PCI bridge 300, the P-PCI bridge 300a and the S-PC
The ordering shown in FIG. 6 is realized without having between the I-bridges 300b. More specifically, the following rules 1 to 10 are satisfied.

Rule 1: (no1) Only one set of transaction buffers is implemented for each type. Therefore, competition between buffers of the same type does not occur. The result is automatically No due to the hardware structure.

Rule 2: Yes2 When the right to use the bus for the chip is obtained, the PMW can use the bus with the highest priority. DRR and DWR are postponed even if they arrive earlier.

Rule 3: Yes3 DR waiting for pickup
Even if C and DWC are present, it does not prevent the PMW from coming out.

Rule 4: No. 4 When the right to use the bus for the chip is obtained, the PMW can use the bus with the highest priority. A DRR or DWR arriving later cannot be overtaken by a PMW arriving earlier. In the mode with arbitration, even if the PMW uses the bus and the cycle has been retried, the DRR or DWR is not allowed to use the bus when the next bus right is given to the chip. Until PMW disappears, DRR or DW
R is not allowed to use the bus. This is the same even if the DRR or DWR uses the bus once before the arrival of the PMW and the cycle ends with a retry (when the bus has been debuted). In the non-arbitration mode, the answer is Yes. A method different from the arbitration mode is used for the distribution of the bus use right given to the chip. A bus use opportunity is equally given for the three factors of PMW, DRR, and DWR. This does not mean that the order of arrival is kept. In addition, even if the bus is used once and the cycle is completed by retry (the bus debuts) (any of PMW, DRR and DWR), the bus use opportunity is again provided fairly.

Rule 5: No5 The DRC must not be taken over until the discharge of the PMW is completed (the retry is completed). In non-arbitration mode, Y
es. Even if the discharge of the PMW is not completed, the DRC may be taken over. Rev .. 02 Rule 6: Yes6 Even if the discharge of the PMW is not completed,
DWC pick-up may be accepted.

Rule 7: Yes7, No7 The priority of bus use is DRR (s), DWR, DRR
The order is as shown in (b). In arbitration mode, for example, D
When the WR uses the bus first and the cycle ends retry (when the bus has been debuted), the next time the chip is given the bus use right, the DRR (b) that arrives later Alternatively, DRR (s) is not allowed to use the bus. DRR (b) or DRR (s) is not allowed to use the bus until DWR is complete and becomes DWC. That is, the right to use the bus is fixed at the time of first debut on the bus, and does not change until the request is completed. Do not allow other requests to debut on the bus. The decision of the bus user at the time of debuting on the bus for the first time is to perform arbitration according to the above-mentioned fixed priority between requests at that time. In non-arbitration mode, for all matrix conditions, Y
es. A method different from the arbitration mode is used for the distribution of the bus use right given to the chip. DRR
(S), DWR, DRR (b), so that the bus use opportunity is equally given. This does not mean that the order of arrival is kept. In addition, the bus was used once and the cycle was completed by retry (the bus debuted)
In the case of any of them (either DRR (s) DWR or DRR (b)), the opportunity to use the bus is provided fairly again.

Rule 8: Yes8 DR waiting for pickup
The presence of C and DWC does not prevent the DRR and DWR from leaving.

Rule 9: Yes9 Even if there is DRR and DWR, it does not prevent DRC and DWC from being taken over.

Rule 10: Yes10 DRC, DWC
There is no ordering for mutual pick-up. Complete promptly from those that can be completed.

As described above, the PCI-PC of this embodiment
The I-bridge 300 is configured such that the P-PCI bridge 300a and the S-PCI bridge 300b are each independent of the state of the PCI bus connected to the other controller.
By operating to perform appropriate ordering control as a logically single PCI-PCI bridge 300, appropriate ordering control via a serial transmission line is realized without having a signal line for ordering.

[0125]

As described in detail above, according to the bridge device of the present invention, each of the two controllers is logically a single bridge regardless of the state of the PCI bus connected to the other controller. Since the apparatus operates so as to perform appropriate ordering control, it is not necessary to have a signal line for ordering control, so that the number of signal lines in the serial transmission line can be reduced to a minimum.

Further, in order to control the transmission of a transaction so as to process a single delayed read completion prior to a burst delayed read completion, the transfer performance between two buses may be improved. It becomes possible.

Further, there is provided an operation mode for controlling the transfer of transactions by rotation priority instead of the predetermined priority order, or an operation mode for controlling the transfer of transactions regardless of the predetermined priority order. Therefore, unexpected deadlock can be prevented.

[Brief description of the drawings]

FIG. 1 is an exemplary view showing the configuration of a computer system according to an embodiment of the present invention.

FIG. 2 is an exemplary view showing an internal block of the P-PCI bridge of the embodiment.

FIG. 3 is an exemplary view showing internal blocks of a transaction buffer & control block according to the embodiment;

FIG. 4 is an exemplary view showing connection of ordering related signals in the transaction buffer & control block according to the embodiment;

FIG. 5 is an exemplary view showing an internal block of a block & word buffer block according to the embodiment;

FIG. 6 is an exemplary view showing ordering realized by the PCI-PCI bridge of the embodiment.

FIG. 7 is a view for explaining a state of bus connection between a computer main body and an expansion unit in a conventional computer system.

FIG. 8 is a diagram showing ordering of a bridge device defined as a PCI bus standard.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Processor bus 2 ... PCI bus (primary) 3 ... PCI bus (secondary) 11 ... CPU 12 ... Host-PCI bridge 13 ... Main memory 14 ... PCI device (computer main body side) 15 ... Switch 16 ... Conventional type PCI-PCI Bridge 17 PCI device (expansion unit side) 100 Computer body 200 Expansion unit 300 PCI-PCI bridge 300a P-PCI bridge 300b S-PCI bridge 301 PCI bus control block 302 PCI bus arbitration block 303 Cycle decode block 304 Configuration register block 305 Transaction buffer & control block 306 Block & word buffer block 307 Block Transfer buffer block 308 ... word buffer block 309 ... bit layer block 310 ... Misc information update block 311 ... serial interrupt synchronization block 312 ... Configuration Access (target)
Control block 313: Single read buffer (target) control block 314: Single write buffer (target) control block 315: Prefetch burst read buffer (target) control block 316: Memory post burst buffer (target)
Control block 317: Single read buffer (master) control block 318: Single write buffer (master) control block 319: Prefetch burst read buffer (master) control block 320: Memory post burst buffer (master) control block 321 ... Synchronization block ( IBB buffer / TBC block 322 Synchronization block (IBB buffer / TBC block) 323 PCI target latency timer block 324 OBB buffer access arbitration block 325 Configuration register block access arbitration block 326 PCI master access arbitration block 327 … Transmission express buffer 328… Transmission block buffer 328 329… Serial interrupt synchronization & transmission block C 330 Misc information synchronization & transmission block 331 NOP information transmission block 332 ACK information transmission block 333 Transmission word buffer 334 Transmission word buffer arbiter 335 Reception express buffer 336 Reception block buffer 337 Serial Interrupt information receiving block 338 Misc information receiving block 339 NOP information receiving block 340 ACK information receiving block 341 Receive word buffer 342 ACK arbiter 343 ACK flag

Claims (8)

[Claims] 1. A device on one of the first and second buses is connected to first and second buses each constituted by a parallel transmission line having a plurality of bit widths. And a physically different first and second controller for transmitting a transaction to each other via a serial transmission path so that the first controller and the second controller can write data from a final write destination. A bridge device comprising ordering control means for controlling transmission of a transaction so that a write transaction that ends without receiving a completion notification is processed with priority over all other transactions. 2. The bridge device according to claim 1, wherein the write transaction is a posted memory write. 3. The ordering control means transmits its own posted memory write prior to transmission of a delayed read completion or delayed write completion for responding to a request from the other controller. 3. The bridge device according to claim 2, wherein the transmission of the transaction is controlled so as to process the transaction. 4. The ordering control means has its own delayed read request or delayed write completion prior to transmission of a delayed read completion or delayed write completion for responding to a request from the other controller. 3. The bridge device according to claim 2, wherein the transmission of the transaction is controlled to process the transmission of the write request. 5. The apparatus according to claim 1, wherein said ordering control means responds to a request from the other controller prior to transmission of its own delayed read request or delayed write request. 3. The bridge device according to claim 2, wherein the transmission of the transaction is controlled to process the transmission of the write completion. 6. The system according to claim 2, wherein said ordering control means controls transmission of a transaction so as to process a single delayed read completion prior to a burst delayed read completion. Bridge device. 7. The bridge apparatus according to claim 1, wherein said ordering control means has an operation mode for controlling transmission of a transaction by rotation priority instead of a predetermined priority order. 8. The system according to claim 1, wherein said ordering control means has an operation mode for controlling transmission of a transaction irrespective of a predetermined priority order.
The bridge device as described.