JP2001125659A - Information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processor which does not increase in the time needed for hibernation processing even if the storage capacity of a main storage part increases and can suppress an increase in its size and a rise in its cost. SOLUTION: The information processor has a main control part 1 which controls the transfer of at least storage contents, a main storage part 2 which is composed of a nonvolatile storage element, and two or more storage parts 3 and 8 which are composed of nonvolatile storage elements or nonvolatile storage devices; and the main control part 1 divides the storage contents stored in the main storage part 2 into two ore more storage contents and transfers the storage contents to the nonvolatile storage parts 3 and 8 corresponding to the divided storage contents at the time of hibernation processing when the power source is turned off, and transfers the storage contents stored in the nonvolatile storage parts 3 and 8 to the main storage part 2 when the power source is turned on again.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus capable of performing a hibernation process when power is cut off.

[0002]

2. Description of the Related Art When a hibernation process is executed when the power of a conventional information processing apparatus is turned off, the hibernation process is stored in a main storage unit composed of a volatile storage element (usually a random access memory: RAM). The stored content is transferred to a non-volatile storage unit including a non-volatile storage element or a non-volatile storage device, and thereafter, the power is turned off. Further, in the conventional information processing apparatus, when the power is turned on again after the hibernation process, the stored contents are transferred from the nonvolatile storage unit to the main storage unit. By the hibernation process, the information processing apparatus can easily reproduce the environment before the power is turned off after the power is turned on again. For example, in a general notebook personal computer or the like, the hibernation process is performed so that the power stored in the battery is not consumed when no input is performed for a certain period of time or the like. That is, after the power is cut off by performing the hibernation process, the power for refreshing the RAM of the main storage unit,
Since power for driving a main control unit such as a U (central processing unit) and a power for driving a hard disk drive and the like are not required, it is possible to prevent consumption of a battery built in a notebook personal computer. When the power is turned on again after the power is turned off after the hibernation process, the operating system is started up, the application software is executed, and the necessary files are opened as in the case of normal power-on. Even if no operation is performed, it is possible to immediately return to the operating environment before the power was turned off. In addition, desktop personal computers and the like that are capable of hibernation processing are increasing in response to recent energy saving policies.

[0003]

In recent years, however, personal computers have increased the RAM capacity of a main storage unit. For example, an 8 Mbyte or 16 Mbyte RAM is used as a main storage unit.
Capacity is not enough, 32 Mbytes, 64 Mbytes, etc. RA
M capacity is required as a standard main storage capacity. Therefore, the process of transferring the storage content from the main storage unit to the nonvolatile storage unit, which is necessary for the hibernation process,
Or, conversely, the time required for the process of transferring the stored content from the nonvolatile storage unit to the main storage unit has become longer. In particular, when the nonvolatile storage unit is a storage device such as a hard disk in which the writing speed / reading speed is much slower than a storage element such as a RAM, an increase in the time required for the hibernation process is caused by power-off. In addition, the time from when the power is turned on to when the operating environment is restored is lengthened, so that the work efficiency of the operator is deteriorated. In order to solve this problem, for example, as described in JP-A-9-44418 and JP-A-9-319667, the effective area and the invalid area in the volatile main storage unit are managed, and only the effective area is managed. Has been proposed to save the time required for the hibernation process by storing the data in a non-volatile auxiliary storage device.
Further, as described in Japanese Patent Application Laid-Open No. Hei 9-31901, by storing the contents stored in the main storage device in a dedicated flash memory connected to the same bus as the bus to which the main storage device is connected, A method for shortening the time required for the hibernation process has been proposed.

However, in the means described in JP-A-9-44418 and JP-A-9-319667, only the effective area in the main storage unit is stored in a nonvolatile auxiliary storage device. When recent operation systems, application software, and data used by application software are used for information processing devices, their capacities tend to increase. The main storage unit may be used, and almost all of the storage contents in the main storage unit may become valid (in use). Therefore, it is necessary to prepare a nonvolatile auxiliary storage device having a storage capacity equivalent to that of the main storage unit. Also, in the method described in Japanese Patent Application Laid-Open No. Hei 9-31901, in order to store a large-capacity main storage device in recent years in a flash memory, it is necessary to prepare a flash memory in the same manner as a large-capacity main storage device. There is. Therefore, in the above-described means or method, it is necessary to provide a nonvolatile auxiliary storage device or flash memory having the same capacity as the main storage device in the information processing device. However, there is a problem that the mounting area of the information processing device becomes large, the information processing apparatus becomes large, and the cost increases. The present invention has been made to solve the conventional problems as described above,
It is an object of the present invention to provide an information processing apparatus in which the time required for the hibernation process does not increase much even if the storage capacity of the main storage unit increases, and the size and cost of the apparatus can be reduced.

[0005]

According to a first aspect of the present invention, there is provided an information processing apparatus comprising at least a main control unit for controlling transfer of stored contents and a volatile storage element. An information processing device, comprising: a main storage unit; and two or more nonvolatile storage units including a nonvolatile storage element or a nonvolatile storage device, wherein each of the units is connected by a bus. The main control unit divides the storage contents stored in the main storage unit into two or more storage contents during the hibernation process when the power is turned off, and divides each of the divided storage contents into the non-volatile storage unit. The stored contents are transferred to the main storage unit when the power is turned on again, and the stored contents stored in the nonvolatile storage units are transferred to the main storage unit. The present invention of claim 2 is the invention of claim 1
3. The information processing device according to claim 1, wherein the non-volatile storage unit includes at least one relatively low-speed storage unit and at least one relatively high-speed storage unit. DMA transfer or bus master transfer is used for transfer of each storage content between the main memory and the main storage unit. According to a third aspect of the present invention, in the information processing apparatus according to the first or second aspect, when each storage content is transferred between the relatively high-speed storage unit and the main storage unit, the compression and decompression of each storage content are performed. Is performed.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described based on illustrated embodiments. FIG. 1 is a block diagram illustrating a configuration of the information processing apparatus according to the first embodiment of this invention. As shown in FIG. 1, an information processing apparatus 200 according to the present embodiment includes a CPU
(Central processing unit), etc., which controls the entire apparatus, controls the transfer of stored contents during hibernation processing and power-on, and a volatile high-speed storage element such as a RAM. A main storage unit 2 serving as storage means for temporarily storing a file being processed by the main control unit while operating system, application software or files are resident, and storage contents such as a hard disk drive device A non-volatile low-speed storage unit 3 that requires an order of magnitude more time than a RAM to write and read data, a display unit 4 that can display and output the input and output contents of an operator like a display device, A display control unit 5 for controlling display contents of the unit 4,
For example, another control unit 6 that performs input / output control or communication control of a connected device and an R that stores software or commands for calling an operation system, for example.
A read-only storage unit 7 composed of an OM or the like, a nonvolatile high-speed storage unit 8 composed of a storage element capable of writing and reading the storage contents at a high speed, such as a flash ROM, and a memory for connecting the above units A bus 9 that enables transmission and reception of signals such as contents. In addition, as the nonvolatile high-speed storage unit 8, for example, an empty area such as a flash ROM in which a BIOS is stored can be used. By using the empty area of the flash ROM or the like as the nonvolatile high-speed storage unit 8, it is possible to increase the number of components or to increase the mounting area of the printed wiring board or the like, thereby increasing the size and cost of the apparatus. In addition, even when the storage capacity of the main storage unit increases, the increase in the time required for the hibernation process can be reduced.

FIG. 2 is a diagram showing a correspondence relationship in which the storage contents stored in the respective storage units in FIG. 1 are transferred in the first embodiment. In the present embodiment, the storage contents stored in the storage area 21 in the main storage unit 2 are A section, B section, C section,
It is divided into a D part and four parts. The storage areas for storing each part of the storage contents are stored in the storage areas 21A, 21B, 21 respectively.
C and 21D. A non-volatile storage unit corresponding to the storage content A is referred to as a first storage unit 11, and a storage area for storing the storage content A in the storage unit 11 is referred to as a storage area 101A.
The non-volatile storage unit corresponding to the storage content B is the second storage unit 12, and the storage area in the storage unit 12 where the storage content B is stored is the storage area 101B. A non-volatile storage unit corresponding to the storage content C is a third storage unit 13, and a storage area for storing the storage content C in the storage unit 13 is a storage area 1.
01C. A non-volatile storage unit corresponding to the storage content D unit is a fourth storage unit 14, and the storage content D is stored in the storage unit 14.
The storage area for storing the unit is a storage area 101D. The storage units 11 to 14 are either the nonvolatile low-speed storage unit 3 or the nonvolatile high-speed storage unit 8 shown in FIG. The operation at the time of the hibernation process according to the present embodiment is performed by the main control unit 1 in which each storage area 21A in the storage area 21 in the main storage unit 2
The storage contents A to D stored in the storage contents A to D are stored in a first storage unit, which is a nonvolatile storage unit corresponding to each storage content.
To the fourth storage units 11 to 14, and
The storage contents A to D transferred to the storage areas 101A to 101D in the storage areas 101 to 101 are respectively stored. Thereafter, the main control unit 1 shuts off a power supply (not shown). The operation when the power is turned on again according to the present embodiment is as follows.
The storage contents A to D stored in the storage areas 21 to 14 are stored in the respective storage areas 21 in the main storage unit 2 corresponding to the respective storage contents.
A to 21D, and store the transferred contents A to D in the respective storage areas 21A to 21D. As described above, in the present embodiment, at the time of the hibernation process, the storage contents stored in the storage area 21 of the main storage unit 2 are transferred from the A section to the D section.
Divided into non-volatile storage units 11 to 1 corresponding to each unit.
4 and store it, and when the power is turned on again, the storage contents A to D stored in the nonvolatile storage units 11 to 14 are transferred to the storage area 21 in the main storage unit 2 and stored. Therefore, even when the storage capacity of the main storage unit 1 increases, an increase in the time required for transfer can be reduced.

FIG. 3 is a diagram showing a correspondence relation in which the storage contents stored in the main storage unit of FIG. 1 are transferred to the nonvolatile storage unit during the hibernation process in the second embodiment of the present invention. At the time of the hibernation process according to the second embodiment of the present invention, the storage content stored in the storage area 21 in the main storage unit 2 is divided into two parts, an A part and a B part. The storage areas for storing each part of the storage contents are referred to as storage areas 21A and 21B, respectively. The non-volatile storage unit corresponding to the storage content A unit is the non-volatile low-speed storage unit 3 shown in FIG. 1, and a storage area for storing the storage content A unit in the non-volatile low-speed storage unit 3 is a storage area. 31. The nonvolatile storage unit corresponding to the storage content B is the nonvolatile high-speed storage unit 8 shown in FIG. 1, and the storage area for storing the storage content B in the nonvolatile high-speed storage unit 8 is a storage area. 81
And At the time of the hibernation processing of the present embodiment, when transferring the storage content A from the storage area 21A of the main storage 2 to the storage area 31 in the nonvolatile low-speed storage 3,
Using MA transfer or bus master transfer, transfer is performed at a higher speed than normal transfer. In addition, during the hibernation process, when the storage content B is transferred from the storage area 21B of the main storage unit 2 to the storage area 81 in the nonvolatile high-speed storage unit 8, the content is stored in the nonvolatile high-speed storage unit 8. Since the storing process is much faster than the storing process in the nonvolatile low-speed storage unit 3, the main control unit 1 performs a compression transfer for compressing the stored content, and performs the non-volatile high-speed storage. The capacity of storage contents that can be stored in the unit 8 is increased.

FIG. 4A is a flowchart showing the operation during the hibernation process of the second embodiment. FIG. 4B shows the operation of the interrupt process executed during the process of FIG. 4A. It is a flowchart shown. As shown in FIG. 4A, at the time of the hibernation process of the present embodiment, the main control unit 1 stores the storage content A stored in the storage area 21A in the main storage 2 in a nonvolatile low-speed mode. The transfer is started to the storage unit 3 using DMA transfer or bus master transfer (step S1). Next, the main control unit 1 starts compressing and transferring the storage contents B stored in the storage area 21B in the main storage unit 2 to the nonvolatile high-speed storage unit 8 (step S2). After that, the main controller 1 stores the stored content B
It is determined whether the compression transfer to the non-volatile high-speed storage unit 8 has been completed (step S3). If the compression transfer of the storage content B has not been completed (step S3: No), Returning to step S2, if the compressed transfer of the stored content B has been completed (step S3: Yes), the process proceeds to step S4. In step S4, the main control unit 1 determines whether or not the transfer end flag of the stored content A has been set, thereby completing the transfer of the stored content A to the nonvolatile low-speed storage unit 3. It is determined whether or not this is the case (step S4). If the transfer of the stored content A has not been completed (step S4: No), step S4 is repeated again, and if the transfer of the stored content A has been completed (step S4: Yes), the processing is performed. finish. Step S1
When the transfer of the stored content A is completed during the processing from step S4 to step S4, the processing of setting the transfer end flag to indicate the transfer end by the interrupt processing is the processing of the flowchart shown in FIG. It is. When the transfer of the stored content A is completed, the main control unit 1 determines whether or not the transfer of the stored content A of the main storage unit 1 is completed (step S11). If the transfer has been completed (Step S11: Yes), the process proceeds to Step S13, and if the transfer of the stored content A has not been completed (Step S1).
1: No), the process proceeds to step S12. Step S1
In 2, the main control unit 1 starts transferring the next area in the storage content A of the main storage unit 1. In step S13, the main control unit 1 sets a transfer end flag indicating that the transfer of the stored content A has been completed, and ends the process. Thereafter, the main control unit 1 shuts off a power supply (not shown).

FIG. 5 shows a correspondence relationship in the second embodiment of the present invention in which the contents stored in the non-volatile storage unit in FIG. 1 are transferred to the main storage unit when the power is turned on again after the hibernation process. FIG. When the power is turned on again after the hibernation process according to the second embodiment of the present invention, the main control unit 1 stores the storage contents A stored in the storage area 31 in the nonvolatile low-speed storage unit 3 in the main storage. Storage area 2 of unit 2
When transferring to 1A, the transfer is performed at a higher speed than the normal transfer using DMA transfer or bus master transfer. Also,
When transferring the compressed storage contents B stored in the storage area 81 in the nonvolatile high-speed storage unit 8 to the storage area 21B of the main storage unit 2, the main control unit 1 Perform restoration transfer to perform restoration processing. FIG. 6A is a flowchart illustrating an operation when the power is turned on again after the hibernation process according to the second embodiment, and FIG. 6B is a flowchart illustrating the operation.
5 is a flowchart showing an operation of an interrupt process executed during the processing of FIG. As shown in FIG. 6A, when the power is turned on again after the hibernation process according to the present embodiment, the main control unit 1 stores the storage area 31 in the nonvolatile low-speed storage unit 3.
The transfer of the storage content A stored in the storage area 21A to the storage area 21A of the main storage 2 is started using DMA transfer or bus master transfer (step S21). Next, the main control unit 1
Stores the storage contents B stored in the storage area 81 in the nonvolatile high-speed storage unit 8 in the storage area 21 of the main storage unit 2.
The restoration transfer to B starts (step S22). afterwards,
The main control unit 1 stores the storage area 2 of the main storage unit 2 of the storage content B unit.
It is determined whether or not the restoration transfer to 1B has been completed (step S23). If the restoration transfer of the stored content B has not been completed (step S23: No), the process returns to step S22, and the stored content B portion is returned. If the restoration transfer has been completed (step S23: Yes), the process proceeds to step S24. In step S24, the main control unit 1 determines whether or not the transfer end flag of the storage content A has been set, thereby completing the transfer of the storage content A to the storage area 21A of the main storage unit 2. It is determined whether or not (step S24).
When the transfer of the stored content A has not been completed (step S
24: No), the step S24 is repeated again, and the transfer of the stored content A has been completed (step S2).
4: Yes), the process ends.

If the transfer of the stored content A is completed during the processing from step S21 to step S24, the processing of setting a transfer end flag to indicate the transfer end in the interrupt processing is shown in FIG. This is the processing of the flowchart shown. When the transfer of the stored content A has been completed, the main control unit 1 determines whether the transfer of the stored content A of the nonvolatile low-speed storage unit 3 has been completed (step S3).
1) When the transfer of the stored content A is completed (step S
31: Yes), the process proceeds to step S33, and if the transfer of the stored content A has not been completed (step S31: N)
In o), the process proceeds to step S32. In step S32, the main control unit 1 starts transferring the next area in the storage content A of the nonvolatile low-speed storage unit 3. Step S33
Then, the main controller 1 sets a transfer end flag indicating that the transfer of the stored content A has been completed, and ends the process.
Further, in the present embodiment, when the storage content stored in the storage area 21 in the main storage unit 2 is divided into the A unit and the B unit, the A unit and the B unit in the main storage unit 2 are fixed. Not long
The DMA transfer or the bus master transfer of the section A can be performed from a higher address in the storage area 21, and the compressed transfer of the section B can be performed from a lower address in the storage area 21. At this time, when the storage area 81 of the nonvolatile high-speed storage unit 8 is full of the storage contents B, the compression transfer processing of the part B ends and the remaining storage in the main storage unit 2 is completed. The DMA transfer or the bus master transfer is continued by regarding the stored contents as the part A. When the storage area 31 of the nonvolatile low-speed storage unit 3 is full of the storage contents A, the DMA transfer or the bus master transfer processing of the unit A ends, and the remaining storage contents in the main storage unit 2 are terminated. Is regarded as part B, and the compression transfer is continued. When both the storage area 81 of the non-volatile high-speed storage unit 8 and the storage area 31 of the non-volatile low-speed storage unit 3 are full of storage contents, the hibernation process ends. D of part A performed from the highest address in the storage area 21
The hibernation process is also ended when the MA transfer or the bus master transfer and the compressed transfer of the B section performed from the lower address in the storage area 21 reach the same part in the storage area 21. The above processing is enabled by monitoring the address of each storage unit instead of monitoring the transfer end flag of the unit A.

As described above, in the present embodiment, at the time of the hibernation process, the storage content stored in the storage area 21 of the main storage unit 2 is divided into the A part and the B part, and the A part is a nonvolatile low-speed storage part. DMA transfer or bus master transfer to the storage unit 3 and store the compressed and transferred data in the nonvolatile high-speed storage unit 8, and when the power is turned on again, the unit B is stored in the nonvolatile low-speed storage unit 3. The storage content A is stored in the storage area 21A in the main storage unit 2 by DMA transfer or bus master transfer, and the storage content B stored in the nonvolatile high-speed storage unit 8 is stored in the main storage unit 2. The data is restored and transferred to the area 21B and stored. For this reason, in the present embodiment,
From the storage contents in the main storage unit 2, the nonvolatile high-speed storage unit 8
As many memory contents as possible. Further, in the present embodiment, the storage contents transferred to the non-volatile low-speed storage unit 3 are DMA-transferred or bus-master-transferred so as to be faster than normal transfer. Therefore, even when the storage capacity of the main storage unit 1 increases, the increase in the time required for the transfer can be further reduced as compared with the first embodiment. Further, in the present embodiment, two nonvolatile storage devices, the nonvolatile low-speed storage unit 3 and the nonvolatile high-speed storage unit 8, are used, but three or more nonvolatile storage devices can be used. If, the individual transfer process is executed as an interrupt process. For example, when executing a process of DMA transfer or bus master transfer of the unit A to the nonvolatile low-speed storage unit 3 and storing it in a plurality of nonvolatile low-speed storage units 3, This can be handled by setting the process of transferring and storing the data to the low-speed storage unit 3 as an interrupt process.

[0013]

As described above, according to the first aspect of the present invention, the storage contents of the main storage are divided and transferred to the non-volatile storage, so that the hibernation process is performed even if the storage capacity of the main storage increases. The increase in the time required for the device is small, and the increase in the size and cost of the device can be suppressed. According to the present invention, since the DMA transfer or the bus master transfer is used to transfer each storage content between the relatively low-speed storage unit and the main storage unit, the time required for the hibernation process is further reduced. be able to. According to the third aspect of the present invention, when each storage content is transferred between the storage unit and the main storage unit at relatively high speed, each storage content is compressed and decompressed, so that the time required for the hibernation process is further increased. Can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an information processing apparatus according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a correspondence relationship in which storage contents stored in each storage unit of FIG. 1 are transferred in the first embodiment.

FIG. 3 is a diagram illustrating a correspondence relationship in which storage contents stored in a main storage unit in FIG. 1 are transferred to a nonvolatile storage unit during a hibernation process in a second embodiment of the present invention.

FIG. 4A is a flowchart illustrating an operation during a hibernation process according to a second embodiment, and FIG. 4B is a flowchart illustrating an interrupt process performed during the process of FIG.

FIG. 5 is a diagram showing a correspondence relationship in which storage contents stored in a nonvolatile storage unit in FIG. 1 are transferred to a main storage unit when power is turned on again after a hibernation process in the second embodiment of the present invention. .

FIG. 6A is a flowchart illustrating an operation when the power is turned on again after a hibernation process according to the second embodiment, and FIG. 6B illustrates an interrupt process performed during the process of FIG. It is a flowchart shown.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Main control part, 2 ... Main storage part, 3 ... Non-volatile low-speed storage part, 4 ... Display part, 5 ... Display control part, 6 ... Other control Unit, 7: read-only storage unit, 8: nonvolatile high-speed storage unit, 9: bus, 21, 21A to 21D, 31, 81, 101A to 1
01D storage area, 11 first storage unit, 12
... 2nd storage unit, 13 ... 3rd storage unit, 14
..Fourth storage unit, 200... Information processing apparatus

Claims (3)

[Claims] 1. A main control unit for controlling transfer of at least storage contents, a main storage unit including a volatile storage element, and two or more nonvolatile storage units including a nonvolatile storage element or a nonvolatile storage device. And an information processing device, wherein each of the units is connected by a bus, wherein the main control unit performs a hibernation process when shutting down a power supply, and stores a storage content stored in the main storage unit. Each storage content is divided into two or more storage contents, and each of the divided storage contents is transferred to each of the nonvolatile storage units. When the power is turned on again, each of the storage contents stored in each of the nonvolatile storage units is transferred. An information processing apparatus for transferring contents to the main storage unit. 2. The non-volatile storage unit comprises at least one
A relatively low-speed storage unit and at least one relatively high-speed storage unit. The transfer of each storage content between the relatively low-speed storage unit and the main storage unit includes a DMA transfer. 2. The information processing apparatus according to claim 1, wherein a bus master transfer is used. 3. The information according to claim 1, wherein each storage content is compressed and decompressed when transferring each storage content between the relatively high-speed storage unit and the main storage unit. Processing equipment.