JP2001119377A - Transport stream generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a transport stream generator capable of generating a right transport stream. SOLUTION: This device is obtained by improving a transport stream generator having a transmission clock generator for generating a transmission clock, digital information storage part for storing transport stream data, FIFO memory for outputting the transport stream data on the basis of the transmission clock of the transmission clock generator and CPU for reading the transport stream data out of the digital information storage part and writing them in the FIFO memory corresponding to a write signal. This device is provided with a FIFO controller for controlling the amount of stored data in the FIFO memory by controlling the write/read of the FIFO memory on the basis of the write signal of the CPU and the transmission clock of the transmission clock generator.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transport stream generator capable of outputting a correct transport stream.

[0002]

2. Description of the Related Art MPEG (Moving Picture Coding Exposure) is an international standard for compression encoding and multiplexing of digital broadcasting.
(rts Group) 2 standard is used. There is a transport stream generator as a test device of the digital broadcast receiving equipment of the MPEG2 standard. Such an apparatus is described in, for example, Japanese Patent Application Laid-Open No. 10-257487. This transport stream generator is shown and described in FIG.

In FIG. 1, a hard disk 10 stores transport stream data. FIFO (Fi
(rst In First Out) The memory 11 inputs and outputs the transport stream data of the hard disk 10 based on the write signal and the read signal. The CPU 12
In response to the permission signal, the transport stream data of the hard disk 10 is read, and the transport stream data and the write signal are given to the FIFO memory 11. The transmission clock generator 13 generates a transmission clock (fixed frequency) that is a system clock of the transport stream, and supplies the transmission clock to the FIFO memory 11 as a read signal. The FIFO controller 14 adds “1” to the count value according to the write signal from the CPU 12 and subtracts “1” from the count value according to the transmission clock from the transmission clock generator 13 so that the count value becomes a predetermined value. When:
A permission signal for permitting writing is given to the CPU 12.

[0004] The buffer 15 temporarily holds the transport stream data from the FIFO memory 11. The main memory 16 stores the transport stream data from the buffer 15. The selector 17 is a FIF
The transport stream data from the O memory 11 and the transport stream data from the main memory 16 are selected and output. The main memory controller 18
The transmission clock of the transmission clock generator 13 is input, input / output control of the main memory 16 is performed, and
Is switched. The driver 19 outputs the transport stream data from the selector 17.

The operation of such a device will be described below.
When receiving the permission signal from the FIFO controller 14, the CPU 12 reads the transport stream data from the hard disk 10 and provides the transport stream data and the write signal to the FIFO memory 11.
The transport stream data is written to the IFO memory 11. Such an operation is performed from the beginning to the end of the transport stream data stored on the hard disk 10. At this time, the FIFO controller 14
The write signal of U12 is input, and "1" is added to the count value.

[0006] A transmission clock generator 13 outputs a transmission clock. Using this transmission clock as a read signal, the FIFO memory 11 reads the transport stream data and supplies it to the buffer 15 and the selector 17. Then, the buffer 15 temporarily holds the transport stream data. At this time, the FIFO controller 14 receives the transmission clock of the transmission clock generator 13 and subtracts “1” from the count value.

[0007] The FIFO controller 14 controls the CPU 1
The count value is incremented or decremented by the write signal of No. 2 and the transmission clock of the transmission clock generator 13. If the count value is equal to or less than a predetermined value, a permission signal is given to the CPU 12. When the counter value exceeds a predetermined value, permission is not given to the CPU 12 and C
The PU 12 is prohibited from writing to the FIFO memory 11.

First, the main memory controller 18 causes the selector 17 to select the transport stream data from the FIFO memory 11. The main memory controller 18 changes the address in accordance with the transmission clock of the transmission clock generator 13, changes the address, and writes the transport stream data in the buffer 15 to the main memory 16. Then, the transmission clock of the transmission clock generator 13 is input and counting is performed. Based on this count, the main memory controller 18 detects one round of the transport stream data, and
7 causes the transport stream data from the main memory 16 to be selected. Then, the main memory controller 18
Changes the address according to the transmission clock of the transmission clock generator 13 and supplies the address to the main memory 16. The main memory 16 outputs the transport stream data to the selector 17.

The driver 19 inputs the transport stream data selected by the selector 17 and outputs a transport stream.

As described above, the transport stream data is output from the hard disk 10 and stored in the main memory 16 until the transport stream makes one round, and the transport stream data is output from the main memory 16 after one round. Therefore, a transport stream can be output immediately. Also,
Since it is only necessary to access the hard disk 10 up to one round, reliability can be improved.

[0011]

However, when a part of the hard disk 10 is lost, data is written to another sector called an alternate sector. As a result, a seek time occurs, and it takes more time to read and write data on the hard disk 10 than usual. If this happens accidentally and continuously, there is a problem that the data cannot be absorbed by the FIFO memory 11 and erroneous data is output from the FIFO memory 11.

An object of the present invention is to realize a transport stream generator capable of generating a correct transport stream.

[0013]

The present invention provides a transmission clock generator for generating a transmission clock, a digital information storage unit for storing transport stream data, and a transformer based on the transmission clock of the transmission clock generator. A FIFO memory for outputting port stream data;
A transport stream generator having a CPU that reads the transport stream data of the digital information storage unit and writes the data to a FIFO memory by a write signal, based on a write signal of the CPU and a transmission clock of the transmission clock generator; It is characterized in that a FIFO controller for controlling writing and reading of the FIFO memory and adjusting the amount of data stored in the FIFO memory is provided.

Also, a transmission clock generator for generating a transmission clock, a digital information storage unit for storing transport stream data, and the transport stream data of the digital information storage unit are input, and the transmission clock generator A transport stream generator having a FIFO memory for outputting transport stream data based on a clock, wherein the transport stream data in the digital information storage section has a predetermined identification number. Data is written to the FIFO memory, and if not a predetermined identification number, null data is written to the FIFO memory.
Null means for writing to the O memory is provided.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram showing one embodiment of the present invention. Here, the same components as those in FIG. 3 are denoted by the same reference numerals, and description thereof is omitted.

In FIG. 1, a CPU 12 includes a null means 1.
21 are provided. The null means 121 is generally software, and the CPU 12 determines the ID (identification number) of the transport stream packet of the transport stream data of the hard disk 10. Then, in the case of the data to be transmitted, the null means 121 causes the CPU 12 to
The transport stream data is read from the hard disk 10 and written to the FIFO memory 11.
In the case of data not to be transmitted, the null means 121
2, null data is written to the FIFO memory 11.

The FIFO controller 20 gives a write enable signal to the CPU 12 and a read signal to the FIFO memory 11 based on the write signal from the CPU 12 and the transmission clock from the transmission clock generator 13.
Outputs a read inhibit signal. The FIFO controller 20 includes a counter 21, digital comparators 22 and 2,
3. An AND (logical sum) gate 24.

The counter 21 performs addition by a write signal from the CPU 12 and performs subtraction by a read signal of the FIFO memory 11.

The digital comparator 22 has a counter 2
The count value of 1 is compared with the stop value, and when the count value becomes equal to or smaller than the stop value, a low level and a read inhibition signal are output. The stop value is determined by a value that does not empty the data in the FIFO memory 11 and the remaining data storage number.

The digital comparator 23 has a counter 2
The count value of 1 is compared with the full value, and when the count value is less than the full value, a permission signal is given to the CPU 12. Full value is FIF
It is determined by the data storage limit of the O memory 11.

The AND gate 24 receives the output of the digital comparator 22 and the transmission clock of the transmission clock generator 13 and outputs the signal to the FIFO memory 11 as a read signal.

The main memory controller 30 controls the transmission clock of the transmission clock generator 13 and the digital comparator 22
And the input / output control of the main memory 16 based on the output (read inhibit signal). The driver 40 includes the transmission clock generator 13
The transport stream data from the selector 17 is output as a transport stream for each transmission clock.

The operation of such a device will be described below.
FIG. 2 is a diagram illustrating the data structure of a transport stream. As shown in FIG. 2, the transport stream has 184 bytes of data in a 4-byte header.
The transport stream packet is composed of a total of 188 bytes. The 4-byte header indicates the ID and the like of the transport stream packet.
In general, a transport stream is obtained by multiplexing data of a plurality of channels. In FIG. 2, each of the three channels has one video and one audio data. In satellite broadcasting or the like, about 6 to 8 channels are multiplexed, and one channel has a transmission rate of about 6 Mbps including video and audio. As described above, since a plurality of channels are multiplexed, the transmission rate (transmission clock) is increased, and writing from the hard disk 10 to the FIFO memory 11 cannot keep up with the transmission rate.

Therefore, the CPU 12 controls the FIFO controller 2
If the permission signal is received from 0, the ID of the header of the transport stream data is read from the hard disk 10. The ID of the header is obtained by the null means 121
Is a transport stream packet to be transmitted. When transmitting, the null means 121 causes the CPU 1
2 reads the transport stream data and the hard disk 10, gives the write signal to the FIFO memory 11, and writes the transport stream data to the FIFO memory 11. If not sending, null means 1
At 21, null data and a write signal are given to the FIFO memory 11, and null data is written to the FIFO memory 11. Such an operation is performed from the beginning to the end of the transport stream data stored on the hard disk 10.

That is, the transport stream for the test does not need all the channels, but only the channel to be tested. Therefore, the null means 121
However, instead of transferring data other than the necessary channels from the hard disk 10 to the FIFO memory 11 by the ID of the header, the CPU 12
The transfer time is reduced by transferring the null data to the memory. For example, in order to transfer data from the hard disk 10 to the FIFO memory 11, a 10 MB / sec.
12 MB to the FIFO memory 11, 400 MB
/ Sec. As a result, it is possible to prevent data errors due to data not being written to the FIFO memory 11.

At this time, the counter 21 inputs the write signal from the CPU 12, performs addition, and inputs the transmission clock of the transmission clock generator 13 as a read signal of the FIFO memory 11 via the AND gate 24. Perform subtraction. This counter value is stored in digital comparator 2
2 and 23 are input and compared with the stop value and the full value, respectively.

The digital comparator 22 outputs a high level if the counter value is larger than the stop value, and outputs a low level if the counter value is equal to or smaller than the stop value. The AND gate 24 receives the output of the digital comparator 22, passes or not passes the transmission clock of the transmission clock generator 13 based on the output of the digital comparator 22, and supplies the read clock to the FIFO memory 11. Upon receiving the read signal, the FIFO memory 11 stores the transport stream data in the buffer 1.
5. Output to selector 17.

The digital comparator 23 outputs a permission signal to the CPU 12 if the count value is less than the full value, and does not output a permission signal if the count value is larger than the full value. With this permission signal, the CPU 12
Writing to the O memory 11 is prohibited.

First, the main memory controller 30 causes the selector 17 to select the transport stream data from the FIFO memory 11. Further, the main memory controller 30 changes the address according to the transmission clock of the transmission clock generator 13, gives the address to the main memory 16, and writes the transport stream data of the buffer 15 in the main memory 16. Then, the transmission clock of the transmission clock generator 13 is input and counting is performed. At this time, when a low level is input from the digital comparator 22, the main memory controller 30 interrupts the above operation. That is, the writing operation to the main memory 16 and the counting operation are interrupted. Again, digital comparator 2
When a high level is input from 2, the above operation is started.

Based on the above count, the main memory controller 30 detects one cycle of the transport stream data and causes the selector 17 to select the transport stream data from the main memory 16. Then, the main memory controller 30 changes the address according to the transmission clock of the transmission clock generator 13 and gives the address to the main memory 16. The main memory 16 outputs the transport stream data to the selector 17.

The driver 40 receives the transport stream data selected by the selector 17 and outputs a transport stream for each transmission clock of the transmission clock generator 13.

As described above, the counter 21 counts the difference between the writing and reading of the FIFO memory 11, and the digital comparators 22 and 23
Perform a comparison, and prohibit writing or reading. Therefore, it is possible to prevent erroneous data from being output from the FIFO memory 11. There is no real harm even if the same data is transmitted.

If the correct transport stream data from the FIFO memory 11 is stored in the main memory 16 in the first round of the transport stream, the main memory 16 is selected by the selector 17 and the correct transport You can output a stream.

It should be noted that the present invention is not limited to this. In the first cycle, the transport stream data is stored in the main memory 16 and thereafter the transport stream data is output from the main memory 16. Are the buffer 15, the main memory 16, the selector 1
7. The configuration may be such that the main memory controller 30 is not provided. That is, the transport stream data may be continuously output from the FIFO memory 11.

Although the hard disk 10 is shown as the digital information storage unit, a CD-ROM or the like may be used.

The stop value and the full value do not need to be determined by the remaining data storage limit and the limit of the data storage limit.
It may be configured to have a margin.

[0037]

According to the present invention, the FIFO controller controls writing and reading of the FIFO memory based on the write signal of the CPU and the transmission clock of the transmission clock generator, and stores the data stored in the FIFO memory. Adjust the volume. Therefore, erroneous data can be prevented from being output from the FIFO memory.

According to the second aspect, when the correct transport stream data from the FIFO memory is stored in the main memory in the first round of the transport stream, the main memory is selected by the selector, and thereafter, the correct transport stream data is stored. A port stream can be output.

According to the fourth aspect, the null means does not transfer data other than the necessary channel from the digital information storage unit to the FIFO memory by the transport stream data, but transfers the null data from the null means to the FIFO memory. The transfer reduces the transfer time. As a result, it is possible to prevent data errors due to data not being written to the FIFO memory.
That is, a correct transport stream can be output.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention.

FIG. 2 is a diagram showing a data structure of a transport stream.

FIG. 3 is a diagram showing a configuration of a conventional transport stream generator.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Hard disk 11 FIFO memory 12 CPU 13 Transmission clock generator 16 Main memory 17 Selector 20 FIFO controller 30 Main memory controller 21 Counter 22, 23 Digital comparator 24 AND gate 121 Null means

Claims (4)

[Claims] A transmission clock generator for generating a transmission clock; a digital information storage unit for storing transport stream data; and a FIFO memory for outputting transport stream data based on the transmission clock of the transmission clock generator. A transport stream generator having a CPU that reads the transport stream data from the digital information storage unit and writes the data to a FIFO memory with a write signal, based on a write signal from the CPU and a transmission clock from the transmission clock generator. And a FIFO controller for controlling writing and reading of the FIFO memory and adjusting the amount of data stored in the FIFO memory. 2. A main memory for storing transport stream data from the FIFO memory, and until the transport stream data is stored in the main memory, the transport stream data in the FIFO memory is selected and stored. 2. The transport stream generator according to claim 1, further comprising a selector for selecting and outputting transport stream data in a memory. 3. A FIFO controller, comprising: a counter for counting a difference between writing and reading of a FIFO memory; a count value of the counter and a stop value for determining a remaining data storage number of the FIFO memory; A first digital comparator for inhibiting the transmission of the transmission clock to the FIFO memory; a second digital comparator for comparing the count value of the counter with a full value determined by the data storage limit of the FIFO memory; 3. The transport stream generator according to claim 1, further comprising a digital comparator. 4. A transmission clock generator for generating a transmission clock, a digital information storage unit for storing transport stream data, and transport stream data from the digital information storage unit, A transport stream generator having a FIFO memory for outputting transport stream data based on a clock, wherein the transport stream data in the digital information storage unit has a predetermined identification number. A transport stream generator comprising null means for writing data to the FIFO memory and for writing null data to the FIFO memory if the identification number is not a predetermined identification number.