JP2001119308A - Mil pattern generation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an MIL pattern generation circuit whose integration degree is high and whose circuit scale is small. SOLUTION: An MIL pattern generation circuit provided with plural counters has a first counter outputting a counted value as a first count value and clearing counting when the first count value reaches a maximum count value and a second counter to which the first count value is inputted, which counts the pulse of the first count value in accordance with the clearance of the first count value, outputs the counted value as a second count value and clears counting when the second count value reaches the maximum count value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention particularly relates to an MIL pattern generation circuit for generating an MIL pattern indicating the order of data rearrangement in interleave processing.

[0002]

2. Description of the Related Art In mobile communications, data transmission errors often occur due to the effects of fading or the like during wireless transmission. Therefore, error correction methods such as convolutional coding and Viterbi coding are used. However, although these error correction methods are effective for random errors, error correction is difficult for burst errors in which data transmission errors occur continuously. For this reason, an interleaving process is used in which data is transmitted after rearranging codes and rearranging received signals upon reception. By using the interleave processing, even if a burst error occurs during transmission, the transmission error becomes a random error during error correction performed by the receiving side,
The error can be corrected.

The MIL pattern is one of patterns indicating the order of data rearrangement in such interleaving processing. For example, when patterns 0, 3, 1, 4, 2, and 5 are used in the interleave processing, A,
The data in the order of B, C, D, E, F are A, D, B,
Rearrange in the order of E, C, F. More specifically, for example, 1
The 2 [4 × 3] interleave processing will be described.
0, 1, 2,. . . , 11 as inputs, the data is written in a 4 × 3 grid in the horizontal direction from the upper left to the lower right, and read in the vertical direction, as shown in FIG. By this processing, 0, 3, 6,
A sequence (pattern) of 9, 1, 4, 7, 10, 2, 5, 8, 11 is obtained. The rearrangement of this sequence is 12 [4 ×
3] interleaving. As described above, the MIL pattern is a pattern obtained by performing the interleaving process in multiple stages.

Conventionally, such an MIL pattern is generally obtained in advance and stored in a ROM, and read out and used as needed.

[0005]

However, the prior art has a problem that the use of the ROM reduces the degree of integration of the entire circuit during layout.

The present invention has been made in view of such a problem, and an object of the present invention is to provide an MIL pattern generation circuit having a high degree of integration and a small circuit scale.

[0007]

Means for Solving the Problems In order to solve the above problems, the present invention has the following constitution. The gist of the invention according to claim 1 is an MIL pattern generation circuit including a plurality of counters, wherein the MIL pattern generation circuit counts pulses of an input clock, outputs the counted value as a first count value, and outputs the first count value. A first counter that clears the count when the maximum count value is reached, and a pulse of the first count value is input in response to the input of the first count value and the clearing of the first count value. Counting, outputting the counted value as a second count value,
And a second counter that clears the count when the count value of
It exists in the IL pattern generation circuit. The gist of the invention according to claim 2 is that the output from the first counter circuit and the second
And a first adding circuit for adding the output from the counter circuit of (1). The gist of claim 3 is as follows.
3. The semiconductor device according to claim 2, further comprising: a first arithmetic circuit interposed between the first counter circuit and the first adder circuit, the first arithmetic circuit being configured to multiply an output from the first counter circuit by a constant.
In the described MIL pattern generation circuit. The gist of the invention according to claim 4 is that the second count value is input, and the second count value is cleared in response to the second count value being cleared.
Counts the pulses of the count value, outputs the counted value as a third count value, and clears the count when the third count value reaches the maximum count value.
The MIL pattern generation circuit according to any one of claims 1 to 3, further comprising: The gist of the invention according to claim 5 is characterized by comprising a second addition circuit for adding an output from the first addition circuit and an output from the third counter circuit. In the MIL pattern generation circuit. The gist of the invention according to claim 6 is that a second arithmetic circuit interposed between the first addition circuit and the second addition circuit and configured to multiply an output from the first addition circuit by a constant is provided. The MIL pattern generation circuit according to claim 5, wherein The gist of the invention according to claim 7 is that the pulse of the third count value is counted in response to the third count value being input and the third count value being cleared, and the counted value to be counted. 5. A fourth counter which outputs a fourth count value and clears the count when the fourth count value reaches a maximum count value.
6. The MIL pattern generation circuit according to any one of 1. to 6., The gist of the invention according to claim 8 includes a third addition circuit that adds an output from the second addition circuit and an output from the fourth counter circuit. In the MIL pattern generation circuit. Claim 9
The gist of the present invention is to provide a third arithmetic circuit interposed between the second addition circuit and the third addition circuit and configured to multiply an output from the second addition circuit by a constant. An MIL pattern generation circuit according to claim 8 is provided.
The gist of the invention according to claim 10 is that a signal which is connected to a subsequent stage of a counter whose maximum count value is variable, selects a signal representing the maximum count value from among the count values of the counter, and outputs the signal to another counter connected to the subsequent stage. The MIL pattern generation circuit according to any one of claims 1 to 9, further comprising a selector (A) for transmitting a count clear signal. 12. The gist of the invention according to claim 11, wherein the third counter has a variable maximum count value, is connected to a stage subsequent to the third counter, and represents a maximum count value among the third count values. 10. The MIL pattern generation circuit according to claim 1, further comprising: a selector A for selecting a signal as a clear signal of a count to the fourth counter connected to a subsequent stage. The gist of the invention according to claim 12 is characterized in that a selector B is provided for selecting either one of the output of the counter in the preceding stage and the output of the counter in the preceding stage of the counter, and outputting it to another counter in the subsequent stage. The MIL pattern generation circuit according to any one of claims 4 to 11. The gist of the invention according to claim 13 is that the third counter is connected to a stage preceding the third counter, and switches the input of the third counter to either the output of the first counter or the output of the second counter. The MIL pattern generation circuit according to any one of claims 4 to 11, further comprising a selector (B). The gist of the invention according to claim 14 is as follows.
13. A transmitter comprising the MIL pattern generation circuit according to any one of 13. The gist of the invention according to claim 15 resides in a receiver including the MIL pattern generation circuit according to any one of claims 1 to 13. The gist of the invention according to claim 16 resides in a transmission / reception device including the MIL pattern generation circuit according to any one of claims 1 to 13. The gist of the invention described in claim 17 resides in a mobile communication device including the MIL pattern generation circuit according to any one of claims 1 to 13. The gist of the invention described in claim 18 resides in a mobile phone provided with the MIL pattern generation circuit according to any one of claims 1 to 13. The gist of the invention described in claim 19 resides in a recording apparatus including the MIL pattern generation circuit according to any one of claims 1 to 13. The gist of the present invention resides in a magnetic recording apparatus including the MIL pattern generation circuit according to any one of claims 1 to 13.

[0008]

Embodiments of the present invention will be described below in detail with reference to the drawings. -First Embodiment- As shown in FIG. 1, an MIL pattern generation circuit according to a first embodiment has an L [M1 [N1 × N2] × M2 [N3
× N4]]. However, N1,
N2, N3 and N4 are the counters 101 and 1 shown in FIG.
02, 103, and 104 are represented.
L = M1 × M2, M1 = N1 × N2, M2 = N3 × N4
And

The MIL pattern generation circuit of the first embodiment shown in FIG. 1 has four counters 101, 102, 1
03, 104 and three adders 301, 302, 303, respectively.
And arithmetic units 201, 202, and 203 of constant times. In FIG. 1, counters 101, 102, 10
(Nn) in each of the blocks 3 and 104 indicates that each counter is a counter that counts from 0 to n-1, and the arithmetic units 201, 202 and 203
“× Nn” in each block indicates that each of the arithmetic units is an Nn-times arithmetic unit.

The counters 101, 102, 103, 104
Are supplied to the adders 301, 302, 303 connected to each other or the arithmetic unit 201 for multiplying by a constant, and the arithmetic operation is performed. According to the calculation result, L [M1 [N1 × N2] × M2 [N3 × N
4]] is obtained.

Hereinafter, L [M1 [N1.times.N] shown in FIG.
2] × M2 [N3 × N4]], an operation of the MIL pattern generation circuit for generating the MIL pattern according to the first embodiment will be described with reference to a timing chart of FIG.

The count value C1, the count value C2, the count value C3, and the count value C4 correspond to the counter 101,
102, 103, and 104. The initial value of each counter is 0. The count value C1 is incremented in synchronization with the input clock clk, and becomes 0 after N1-1.
After that, repeat this. The count value C2 is incremented when the count value C1 changes from N1-1 to 0, and N
Next to 2-1 is 0. After that, repeat this. This operation corresponds to the most significant bit MSB (Mos) of the count value C1.
This can be realized by using the falling edge of t Significant Bit) as the clock of the counter 102. The relationship between the count value C3 and the count value C2 and the relationship between the count value C4 and the count value C3 are the same as the relationship between the count value C2 and the count value C1 described above. The count values C1, C2, C3, and C4 are N1-1 and N2-
In the case of 1, N3-1, and N4-1, each counter becomes the initial value of 0 at the next clock, and thereafter, the operation described above is repeated.

An arithmetic unit 20 multiplied by a constant from the value of each counter
1, 202, 203 and adders 301, 302, 303
((C1 × N2 + C2) × N3 + C3) × N4
+ C4 is obtained. This output is L [M1 [N1 × N2]
The MIL pattern of × M2 [N3 × N4] is continuously and repeatedly output.

In the first embodiment shown in FIG. 1, an MIL pattern generation circuit for generating an MIL pattern of L [M1 [N1 × N2] × M2 [N3 × N4]] has been described. More or less MIL
Even when a pattern is generated, an MIL pattern generation circuit can be similarly realized by using a counter for each minimum unit.

Since the MIL pattern generation circuit according to the present embodiment is configured as described above, the following effects can be obtained. In the present invention, an MIL pattern is created by a plurality of stages of counters and adders / arithmetic units. For this reason, since it is not necessary to obtain and hold the MIL pattern in advance, the circuit scale can be reduced as compared with the general method of the related art.

In particular, when Nn (n> 1) is a power of 2, an arithmetic unit having a constant multiple of Nn and subsequent addition processing can be realized only by bit combination, so that the circuit scale can be further reduced. As a specific example, when N4 is a power of 2 in FIG. 1, the output of the count value C4 is bit-coupled as the lower bit and the output of the adder 302 is bit-coupled to form a constant multiple arithmetic unit 203. The function of the adder 303 can be realized.

As another embodiment of the present invention, the basic configuration is as described above, but a configuration in which MIL patterns that can be created have versatility is further devised. That is, in these other embodiments, N1, N2, N
3 and N4 are each variable.
It is possible to create by switching the L pattern. It is also possible to switch between different levels of MIL patterns and create them.

Second Embodiment FIG. 3 shows that N1, N2, N3 and N4 are each variable,
9 shows an MIL pattern generation circuit according to a second embodiment, which can switch and create MIL patterns with different numbers of stages. The configuration of the second embodiment shown in FIG.
1, N2, N3, and N4 are each variable, and the others are in accordance with the first embodiment shown in FIG. Further, a selector 401 and a selector 402 are added in order to provide versatility from the first embodiment.

The selector 401 selects the signal used as the clock of the counter 104 from the count value C3 because the bit position of the most significant bit MSB of the bits whose value changes in the count value C3 changes by making N3 variable. This is a selector for performing The selector for this purpose is referred to as selector A.

The selector 402 is a selector for changing the number of stages of the MIL pattern to be created. Specifically, the use or non-use of the counter 102 is switched. That is, L
MIL of [M1 [N1 × N2] × M2 [N3 × N4]]
Based on the pattern generation circuit, L ′ [N1 × M2 [N3 × N
4]] is created. However, L '= N1
× M2. M of L '[N1 × M2 [N3 × N4]]
When creating an IL pattern, the count value C2 is always 0
And the arithmetic unit 201 is set to 1 time. The selector for this purpose is referred to as a selector B.

In the second embodiment shown in FIG. 3, one selector A and one selector B are used. However, all points where the falling edge of the most significant bit MSB of the counter is used as the clock of the next counter are used. The selector A and the selector B can be used respectively, and the selector A and the selector B can be used in combination.

In the prior art, general versatility cannot be provided, and when a plurality of MIL patterns are switched and created, the circuit scale is greatly increased. According to the present invention, the versatility can be imparted to the MIL pattern created as in the present embodiment, so that there is an effect that the increase in the circuit scale when switching a plurality of MIL patterns is relatively small.

Third Embodiment In the first and second embodiments described above, when there is no skip, that is, in the first embodiment, L = M1
The MIL pattern generation circuit in the case of × M2, M1 = N1 × N2, and M2 = N3 × N4 has been described.

The MIL pattern generation circuit in the case where there is a skip will be described below as a third embodiment and a fourth embodiment. Here, L [M1 [N1 × N2] ×
M1 in the MIL pattern of M2 [N3 × N4]
If there is a skip at [N1 × N2], ie, M1
Although an example of <N1 × N2 is shown, the present invention can also be applied to a case where there is a skip in another place or an MIL pattern having a different number of stages from the example shown here. Further, it is possible to give versatility to the MIL pattern created as in the second embodiment.

FIG. 4 (third embodiment) and FIG. 5 (fourth embodiment) show an MIL pattern generation circuit in the case where there is a skip at M1 [N1 × N2].
There is a configuration shown in FIG.

In the configuration of the third embodiment of the MIL pattern generation circuit shown in FIG. 4, M1 [N1 × N2] is created using the counter 105 and the conversion circuit 501, and the other circuits are the same as those of the first embodiment. According to. The counter 105 increments in synchronization with the input clock clk, and becomes 0 after M1-1. The conversion circuit 501 has M1 [N1 × N
2] is a circuit that obtains the MIL pattern and converts the MIL pattern so as to output the MIL pattern corresponding to the value 0 to M1-1 of the count value C5. However, the count value C5 is the value of the counter 105. In the configuration of the third embodiment shown in FIG. 4, there is no restriction on the MIL pattern that can be created as in the configuration of the fourth embodiment (FIG. 5) described later.

Fourth Embodiment FIG. 5 shows a fourth embodiment of the present invention. The configuration of the present embodiment is obtained by adding a skip condition determination circuit 601 and control based on the determination result to the configuration of the first embodiment shown in FIG. The operation of the fourth embodiment will be described with reference to the timing chart shown in FIG. The skip condition determination circuit 601 checks the skip condition in advance and sets the skip condition determination result S1 to 1 one clock before the skip timing from the count value C1 and the count value C2. When the skip condition determination result S1 is 1, the count value C1 is set to 0 at the next clock.
As a result, the value to be skipped is skipped.

In the example shown in FIG. 6, when the count value C2 = a and (N1-1) .times.N2 + a> M1-1, the skip condition determination result S1 is determined by the count value C1 = N1-2 and the count value C2 = a. 1 and the count value C1 = N1-1,
Skip the count value C2 = a. However, M1 [N1
× N2], the value of the most significant bit MSB of the count value C1 is 0 when the skip condition determination result S1 is 1.
In such a case, the configuration of the fourth embodiment cannot be used, and the configuration of the third embodiment must be used. That is, if N1 × N2-M1 <N2, N
If 1-1 is not a power of 2, the configuration of the fourth embodiment can be used. If N1 × N2-M1 ≧ N2, N
N2 ′ that satisfies 1 × N2′−M1 <N2 ′ exists, and M
The MIL pattern of 1 [N1 × N2] is M1 [N1 × N
2 ′].

The circuit configuration of the fourth embodiment has fewer changes from the circuit configuration of the first embodiment compared to the circuit configuration of the third embodiment, and N1 and N2 are common and M1 is different. The MIL pattern generation circuit has many common components. That is, in the case where the MIL pattern generation circuits having the same N1 and N2 and different M1 are used in common and switched and used, the configuration of the fourth embodiment particularly reduces the circuit scale as compared with the configuration of the third embodiment. There are advantages that can be done.

Note that, in the present embodiment, the present invention is not limited to this, and can be applied to a mode suitable for applying the present invention.

Further, the number, position, shape, etc. of the above-mentioned constituent members are not limited to the above-mentioned embodiment, but can be set to a suitable number, position, shape, etc. for carrying out the present invention.

In each of the drawings, the same components are denoted by the same reference numerals.

[0033]

Since the present invention is configured as described above, it is possible to provide an MIL pattern generation circuit having a high degree of integration and a small circuit scale.

[Brief description of the drawings]

FIG. 1 shows a first example of an MIL pattern generation circuit according to the present invention.
It is a block diagram showing the structure of 1st Embodiment.

FIG. 2 is a time chart showing the operation of the first embodiment shown in FIG.

FIG. 3 shows a second example of the MIL pattern generation circuit according to the present invention.
It is a block diagram showing the structure of 1st Embodiment.

FIG. 4 shows a third example of the MIL pattern generation circuit according to the present invention.
It is a block diagram showing the structure of 1st Embodiment.

FIG. 5 shows a fourth example of the MIL pattern generation circuit according to the present invention.
It is a block diagram showing the structure of 1st Embodiment.

FIG. 6 is a time chart showing the operation of the fourth embodiment shown in FIG.

FIG. 7 is a diagram illustrating a MIL pattern generation method in 12 [4 × 3] interleaving processing.

[Explanation of symbols]

 101, 102, 103, 104, 105 ... Counters 201, 202, 203 ... Calculators 301, 302, 303 ... Adders 401, 402 ... Selector 501 ... Conversion circuit 601 ... Skip condition judgment circuit C1, C2, C3, C4 C5: Count value clk: Input clock MSB: Most significant bit S1: Skip condition determination result

Claims (20)

[Claims] 1. An MIL pattern generation circuit including a plurality of counters, which counts pulses of an input clock, and outputs the counted value as a first count value;
A first counter that clears a count when the first count value reaches a maximum count value; and a first counter that receives the first count value and clears the first count value when the first count value is cleared. A second counter that counts pulses having a count value of, outputs the counted value as a second count value, and clears the count when the second count value reaches a maximum count value. MIL pattern generation circuit. 2. The MI according to claim 1, further comprising a first adding circuit for adding an output from the first counter circuit and an output from the second counter circuit.
L pattern generation circuit. And a first arithmetic circuit interposed between the first counter circuit and the first adder circuit for multiplying an output from the first counter circuit by a constant. The MIL pattern generation circuit according to claim 2. 4. A pulse of the second count value is counted in response to the input of the second count value and the second count value is cleared, and the counted value is counted as a third count value. The MIL pattern generation circuit according to any one of claims 1 to 3, further comprising: a third counter that outputs a count value and clears the count when the third count value reaches a maximum count value. 5. The MIL pattern generation circuit according to claim 4, further comprising a second addition circuit for adding an output from said first addition circuit and an output from said third counter circuit. . 6. A second arithmetic circuit interposed between the first addition circuit and the second addition circuit and configured to multiply an output from the first addition circuit by a constant. The MIL pattern generation circuit according to claim 5. 7. The pulse of the third count value is counted according to the input of the third count value and the third count value is cleared, and the counted value is counted as a fourth count value. 7. The MIL pattern generation circuit according to claim 4, further comprising: a fourth counter that outputs the count value and clears the count when the fourth count value reaches a maximum count value. 8. 8. The MIL pattern generation circuit according to claim 7, further comprising a third addition circuit for adding an output from said second addition circuit and an output from said fourth counter circuit. . 9. A semiconductor device comprising: a third arithmetic circuit interposed between the second adder circuit and the third adder circuit for multiplying an output from the second adder circuit by a constant. The MIL pattern generation circuit according to claim 8, wherein 10. A signal which is connected to a subsequent stage of a counter whose maximum count value is variable, selects a signal indicating the maximum count value from among the count values of the counter, and sends the selected signal to another counter connected to the latter stage as a count clear signal. 10. The MIL pattern generation circuit according to claim 1, further comprising a selector A for transmitting. 11. The third counter, the maximum count value of which is variable, is connected to the subsequent stage of the third counter, and selects a signal representing the maximum count value from the third count value, 10. The M according to claim 1, further comprising a selector A for transmitting a count clear signal to the fourth counter connected to the fourth counter.
IL pattern generation circuit. 12. The selector according to claim 4, further comprising a selector B for selecting one of the output of the counter of the preceding stage and the output of the counter of the preceding stage, and outputting the selected output to another counter of the subsequent stage. 12. The MIL pattern generation circuit according to any one of claims 11 to 11. 13. A selector B connected to a stage preceding the third counter and switching the input of the third counter to one of the output of the first counter and the output of the second counter. 4-1.
2. The MIL pattern generation circuit according to claim 1. 14. M according to claim 1, wherein
A transmitter including an IL pattern generation circuit. 15. The M according to claim 1, wherein
A receiver including an IL pattern generation circuit. 16. M according to claim 1, wherein
A transmission / reception device including an IL pattern generation circuit. 17. The M according to claim 1, wherein
A mobile communication device including an IL pattern generation circuit. 18. The M according to claim 1, wherein
A mobile phone equipped with an IL pattern generation circuit. 19. The M according to claim 1, wherein
A recording device including an IL pattern generation circuit. 20. The M according to claim 1, wherein
A magnetic recording device including an IL pattern generation circuit.