JP2001119293A - Clock generation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock generation circuit where an error between an ideal clock signal and a clock signal, which is generated by further frequency division of a clock signal of which the frequency is divided by a non-integer obtained by combining plural frequency division numbers, is small. SOLUTION: A first frequency division circuit 5 combines frequency divisions by plural frequency division numbers (integral frequency division numbers) to divide the frequency of an original clock signal to generate an intermediate frequency clock signal. A trigger circuit 11 sends a trigger signal for start of frequency division to a counter circuit 10 when a phase signal outputted from a frequency division number setting circuit 9 reaches an externally inputted specific phase value. Frequency division in a second frequency division circuit is performed when the counter circuit 10 receives the trigger signal to start frequency division of the intermediate frequency clock signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a clock generation circuit for generating a low-frequency clock signal by dividing an original clock signal in an electronic device.

[0002]

2. Description of the Related Art Conventionally, when generating a low-frequency clock signal required for signal processing by dividing the frequency of an original clock signal, the oscillation frequency of the original oscillator is generally adjusted so that the frequency division number becomes an integer. , The processing clock frequency in the signal processing unit. On the other hand, in an electric circuit having a built-in RF device, the frequency of the clock signal used in the RF part is different from the frequency of the clock signal used in the signal processing unit.
When these clock signals are generated from one original clock, for example, a clock signal to be supplied to the signal processing unit may need to be generated by non-integer frequency division. In general, non-integer frequency division may be performed when a plurality of clock signals having different frequencies must be generated in one device. This non-integer frequency division is performed by combining a plurality of integer frequency divisions.

FIG. 7 is a block diagram showing an example of a conventional frequency dividing circuit. In the figure, 1 is an oscillator for generating an original clock, 2 is a frequency divider that can change the setting of the frequency division number, and 3 is a control circuit that sets the frequency division number to the frequency divider 2. A frequency divider 4 divides the clock signal output from the frequency divider 2 by an integer. Next, the operation of the conventional frequency dividing circuit will be described. This frequency dividing circuit performs frequency division with a non-integer frequency, for example, so as to generate and output a 72 kHz clock signal from a 13 MHz clock signal. Divider 1 converts high frequency 13 MHz to intermediate frequency 576
Frequency division to kHz, intermediate frequency 576 kHz by frequency divider 2
When dividing from z to a low frequency of 72 kHz,
The frequency division by the frequency divider 1 is not an integer. Since the frequency division number in the frequency divider 1 is 13 MHz / 576 kHz = 22.57, frequency division is performed by combining frequency division 22 and frequency division 23. As described above, the intermediate clock signal generated by combining the frequency divisions with different frequency division numbers has a long or short clock pulse interval. If the intermediate clock signal is further divided, a deviation from the ideal clock signal occurs in the divided low-frequency clock signal due to the length of the pulse interval. The magnitude of the root-mean-square value of the error from the ideal clock signal included in the low-frequency clock signal depends on which phase of one cycle of the frequency division number used to generate the intermediate frequency clock signal starts frequency division. Occurs.

[0004]

In the case of the prior art, since the frequency divider 2 does not specify which phase of one cycle of frequency division in which a plurality of frequency division numbers are combined to start frequency division, it is not specified. In addition, there is a problem that the root mean square value of the error between the low-frequency clock signal and the ideal clock signal increases depending on the start position of the frequency division.

The present invention has been made in order to solve such a problem, and a clock signal generated by further dividing a non-integer frequency-divided clock signal by combining a plurality of frequency division numbers is provided. It is an object of the present invention to obtain a clock generation circuit having a small error from an ideal clock signal.

[0006]

According to a first aspect of the present invention, there is provided a clock generation circuit which generates an oscillator by repeating an oscillator for generating an original clock signal and a frequency dividing cycle in which a plurality of frequency dividing numbers are combined. A first frequency divider for dividing the frequency of the original clock signal to generate an intermediate frequency clock signal; and a frequency divider for starting frequency division from a specific phase in the frequency division cycle, and converting the intermediate frequency clock signal to a low frequency clock signal. And a second frequency dividing circuit that generates

According to a second aspect of the present invention, there is provided a clock generation circuit for dividing an original clock signal and outputting two low-frequency clock signals, comprising: an oscillator for generating an original clock signal; A first frequency dividing circuit that divides the frequency by repeating a frequency dividing cycle in which the frequency dividing number is combined and generates an intermediate frequency clock signal from the original clock signal; and a frequency dividing circuit that divides the frequency from a specific phase in the frequency dividing cycle. Starting, comprising a second frequency dividing circuit for generating a low frequency clock signal from the intermediate frequency clock signal, and a third frequency dividing circuit for dividing the original clock signal by an integer frequency division number. The low frequency clock signal generated by the second frequency dividing circuit and the low frequency clock signal generated by the third frequency dividing circuit are output.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 First Embodiment A clock generation circuit according to a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram of the clock generation circuit according to the first embodiment, FIG. 2 is a signal timing diagram of the clock generation circuit according to the first embodiment, and FIG. 3 is an intermediate frequency clock signal of the clock generation circuit according to the first embodiment. FIG. 4 is a characteristic diagram showing a combination of phases of an intermediate frequency clock signal of the clock generation circuit according to the first embodiment, and FIG. 5 is a low frequency clock of the clock generation circuit according to the first embodiment. FIG. 4 is a characteristic diagram illustrating a root-mean-square error occurring in a signal.

First, a block diagram of the clock generation circuit shown in FIG. 1 will be described. In FIG. 1, reference numeral 5 denotes a first frequency divider, 6 denotes a second frequency divider, and 7 denotes an oscillator. The first frequency dividing circuit 5 divides the frequency of the original clock signal from the oscillator 7 by combining frequency division by a plurality of frequency division numbers (all of them are integer frequency division numbers). In the first frequency dividing circuit 5, 8 is a counter circuit, and 9 is a frequency dividing number setting circuit. The second frequency divider 6 divides the intermediate frequency clock signal output from the first frequency divider 5 by an integer to generate a low frequency clock signal. In the second frequency dividing circuit 6, reference numeral 10 denotes a counter circuit, and reference numeral 11 denotes a trigger circuit. The counter circuit 8 divides the frequency of the original clock signal generated by the oscillator 7 by the frequency division number set by the frequency division number setting circuit 9. When the counting for 22 pulses of the signal is completed, a count-up signal is output to the frequency division number setting circuit 9. The division number setting circuit 9 stores a combination of a plurality of division numbers in advance, and every time the count-up signal is input from the counter circuit 8, the division number setting circuit 9 divides the division number into the counter circuit 8 in order. Command a change in the number of laps. A combination frequency division cycle is formed by a combination of a plurality of frequency division numbers stored in the frequency division number setting circuit 9, and a division number change command to the counter circuit 8 repeats this combination frequency division one cycle. It is done by doing. That is, when one cycle is completed, the division number setting circuit 9 returns to the first division number in this cycle and issues a division number change command. Further, the frequency division number setting circuit 9
Is calculated by a count-up signal from the counter circuit 9.
The number of divisions in one cycle of the combination frequency division (which is referred to as a phase in one cycle of the combination frequency division or simply a phase) is counted and output to the trigger circuit 11 as a phase signal. As for this phase, for example, if one cycle of combination frequency division is formed by ten frequency division numbers, there are 10 phases. The counter circuit 10 frequency-divides the intermediate frequency clock signal output from the first frequency dividing circuit 5 by an integer frequency division number. In the present invention, frequency division in the counter circuit 10 is started by a trigger signal from the trigger circuit 11. When the phase signal from the frequency division number setting circuit 9 becomes a phase specific value input from the outside, the trigger circuit 11
Supplies a trigger signal for starting frequency division to the counter circuit 10.
Output to

Next, the operation of the clock generation circuit according to the first embodiment will be described. The original clock signal generated by the original oscillator 7 is divided by the counter circuit 8. The frequency division number of the counter circuit 8 is set by the frequency division number setting circuit 9.
The division number setting circuit 9 stores a combination of a plurality of division numbers in advance. For example, in the first frequency dividing circuit 5, 13
When a 576 kHz intermediate frequency clock signal is generated from the original clock signal of MHz and the low frequency clock signal of 72 kHz is generated in the second frequency dividing circuit 6 from the intermediate frequency clock signal, the frequency division from 13 MHz to 576 kHz is performed. Since the frequency is not an integer, frequency division is performed by combining a plurality of frequency division numbers as described above. The combination at this time is performed by dividing the frequency of 23, 22, 23, 22, 23, 22, and 23 (4 times of frequency division and 3 times of frequency division of 22 times) into 10 sets, and performs 10 frequency divisions. If the frequency division by 22 is performed, the original clock 13MH can be obtained in one cycle of the combination frequency division.
The number of z count pulses is 1625 pulses in total, and the number of pulses after frequency division is 72 pulses.
Hz. However, dividing by 22 and 23
Due to the combination of frequency division, the clock signal after frequency division has a longer or shorter pulse interval. FIG. 2 shows the signal timing in this frequency divider circuit. In FIG. 2, 13 MHz
A pulse of φ0 is generated on the 576 kHz clock signal line for 23 pulses of the clock signal, and a pulse of φ1 is generated for the next 22 pulses. The frequency dividing number setting circuit 9 sets the frequency dividing number 23 in the counter circuit 8, and when the counter circuit 8 counts 23 pulses of the 13 MHz clock signal, a count-up signal is output to the frequency dividing number setting circuit 9. Upon receiving the count-up signal, the frequency division number setting circuit 9 sets the frequency division number 22 which is the next frequency division number in one cycle of the combination frequency division in the counter circuit 8. When a clock signal is frequency-divided by combining different frequency-dividing numbers in this way, a 16 MHz pulse of 13 MHz
72 pulses from φ0 to φ71 are generated on the 576 kHz clock signal line. These pulses correspond to one cycle of the above-described combination frequency division, and during this one cycle, phases φ0 to φ71 corresponding to pulses φ0 to φ71 are generated. The positions of the phases φ0 to φ71 on the time axis have an error with respect to the ideal pulse position of the 576 kHz clock, and this error is expressed as a percentage as shown in FIG. Note that the error is between the phase φ0 and φ71.
Is calculated by dividing the difference between the position of the ideal clock and the corresponding time of the ideal clock by the pulse interval of the ideal clock of 576 kHz.

The second frequency dividing circuit 6 has the phase φ as described above.
The 576 kHz clock signal having 0 to φ71 is divided by 8 to generate a 72 kHz clock signal. The frequency of the frequency division performed by the counter circuit 10 has eight combinations shown in FIG. 4 depending on the position of the phase within one cycle of the combination frequency division. In FIG. 4, for example, when the second frequency dividing circuit 9 starts frequency division from the phase φ0, then the φ8, φ16, φ2
In the phase of 4,..., Φ56, φ64, 72 kHz
A pulse is generated on the z clock signal line. Also, when frequency division is started in the phases φ1, φ2, φ3,..., Φ7, pulses are generated in the phase shown in FIG. Trigger circuit 11 in FIG.
Outputs a trigger signal for the counter circuit 10 to start frequency division. The phase counted by the frequency division number setting circuit 9 is input to the trigger circuit 11, and when the input phase signal becomes a specific phase value input from the outside, the trigger circuit 11 outputs the trigger signal. Output to the counter circuit 10. This trigger signal causes the counter circuit 1
0 starts frequency division.

The specific phase value set in the trigger circuit 11 is determined in advance so that the error between the output of the second frequency divider 6 and the ideal 72 kHz clock is reduced. The error generated in the output 72 kHz low frequency clock signal corresponding to the combination of the phases in one cycle of the combination frequency division shown in FIG. 4 is as shown in FIG. In this case, since the error between the 72 kHz clock signal and the ideal clock is minimized in the combination of phases including φ6, φ6 is adopted as the specific phase value and is set in the trigger circuit 11 by an external input or the like.

As described above, the error of the intermediate frequency clock signal output from the first frequency dividing circuit 5 is obtained, and the error of the low frequency clock signal output from the second frequency dividing circuit 6 is numerically calculated. , The error occurring in the low-frequency clock signal corresponding to the phase in one cycle of the combination frequency division in the first frequency dividing circuit can be calculated, and the phase in which the error occurring in the low-frequency clock signal is small can be specified. Therefore, this is set in the trigger circuit 11 as a phase specific value.

Embodiment 2 FIG. In the first embodiment,
A clock generator that divides the original clock signal generated by the oscillator by a non-integer number and further divides it by an integer to generate one low-frequency clock signal has been described. However, as shown in FIG. A third frequency divider may be added to form a clock generation circuit that outputs two low-frequency clock signals.

FIG. 6 shows a configuration of a portable telephone as an example of an electronic device in which the clock generation circuit is incorporated. This portable telephone has a plurality of signal processing circuits required to support a plurality of communication systems such as a satellite mobile communication system and a terrestrial cellular communication system. In a mobile communication system, a communicable area is determined in each communication system, and communication may be performed with a plurality of communication systems in order to expand a use range of a mobile communication terminal. . Since the data transmission format, the audio processing method, and the like are different depending on the communication system, it is necessary to provide a plurality of hardware and software for each of these differences in accordance with these differences. In particular, an electronic circuit for performing data transmission control and voice processing is often configured by an integrated circuit housed in one package in order to reduce the size. These integrated circuits are designed for communication systems specific to communication systems,
The frequency of the supplied clock signal is specified in accordance with this design, and in a mobile phone using a plurality of communication systems, it is necessary to generate a plurality of clock signals in accordance with these individual electronic circuits. .

In FIG. 6, reference numeral 12 denotes an antenna for transmitting / receiving a communication radio wave, 13 denotes a first signal processing circuit system for processing a communication signal, and 14 denotes a second signal processing for processing a communication signal of another mobile communication system. A circuit system, 15 is a clock generation circuit, and 16 is a user I / F. In the first signal processing circuit system 13 and the second signal processing circuit system 14, reference numerals 17 and 18 denote RF circuits composed of low-noise amplifiers and high-output amplifiers, and reference numerals 19 and 20 denote frequency conversions from IF signals to RF signals. , And a frequency converter that performs frequency conversion from an RF signal to an IF signal, 21 and 22 are modems that perform modulation and demodulation, 23 and 24 are transmission control circuits that perform frame processing of communication signals, and 25 and 26 are signal processing of an upper layer. Is an upper layer processing circuit that performs the following. In the clock generation circuit 15, 27 is an oscillator, 28 is a first frequency divider for dividing a frequency by a non-integer, 29 is a second frequency divider for supplying a clock signal to a first signal processing circuit, and 30 is This is a third frequency divider that supplies a clock signal to the second signal processing circuit.

Next, the operation of the portable telephone shown in FIG. 6 will be described. The mobile phone as shown in FIG. 6 has two signal processing circuits, that is, a first signal processing circuit system 13 and a second signal processing circuit system 14, in order to support a plurality of mobile communications. The configuration is such that a clock generation circuit that supplies clock signals of different frequencies to respective circuit systems is shared. In a general electronic device, when a plurality of signal processing circuit systems need to supply clock signals of different frequencies, this configuration is directly extended to a configuration in which a clock generation circuit that generates these clock signals is shared. be able to. The antenna 12 transmits and receives communication radio waves of a plurality of mobile communication systems. The first signal processing circuit system 13 or the second signal processing circuit system 1 according to the communication system to receive.
One of the four becomes the transmission / reception state. Antenna 1
2 is received by the RF circuit 17 and the RF circuit 17.
The circuit 18 amplifies the noise with low noise, and the frequency converter 19 and the frequency converter 20 convert the frequency from the RF signal to the IF signal. The modem 21 and the modem 22 demodulate the communication signal superimposed on the IF signal, perform frame synchronization in the transmission control unit 23 and the transmission control unit 24 in accordance with the communication method, deframe the communication signal, Read out call signals, data string signals, etc. The signal read in this way is further decoded by the upper layer processing circuit 25 and the upper layer processing circuit 26. For example, the decoded control signal is used for control in a signal processing circuit, and the decoded call signal is further converted to a voice signal in the user I / F 16. The data signal is transmitted as data from the user I / F 16 and used for the information terminal device. When the communication signal is transmitted from the mobile phone, the communication signal from the user I / F 16 is coded in the upper layer processing circuits 25 and 26 by following the reverse order, and the transmission control circuit 23 and the transmission control circuit 24 are coded.
And the modem 21 and the modem 22 superimpose and modulate the IF carrier on the IF carrier. Modulated IF
The communication signal that has become a signal is further frequency-converted into an RF signal by converters 19 and 20, amplified by RF circuits 17 and 18,
Send from.

As described above, in the first signal processing circuit system 13 and the second signal processing circuit system 14, signals from high frequency to low frequency, from RF signals to IF signals, and further to audio signals and data signals. The processing is performed, and the clock signal necessary for performing these processings is required to be from high frequency to low frequency. In many cases, the modem 21 and the transmission control circuit 23 are packaged using a digital signal processor, and the clock frequency to be supplied differs depending on the speed and the amount of multiplexing processing and frame processing determined in each communication system. , The clock generation circuit 15 needs to generate a plurality of clock signals.

Next, the operation of the clock generation circuit 15 will be described. The original clock from the oscillator 27 is input to the first frequency dividing circuit 28 and the third frequency dividing circuit 30. The first frequency dividing circuit 28 is equivalent to the first frequency dividing circuit 5 in FIG. 1, performs non-integer frequency division by a combination of a plurality of frequency division numbers, and performs first frequency division from the original clock signal. Signal processing circuit 1
3 to generate an intermediate frequency clock signal for generating a clock signal to be used. The third frequency dividing circuit 30 supplies the clock signal to the second signal processing circuit system 14 by dividing the original clock signal from the oscillator 27 by an integer, and the error of the supplied clock signal with respect to the ideal clock signal is small. . As described above, since the first frequency divider 28 performs non-integer frequency division, an error has already occurred in the intermediate frequency clock signal itself output from the first frequency divider 28. The second frequency dividing circuit 29 is equivalent to the second frequency dividing circuit 6 in FIG. 1 and starts frequency division from a specific phase of the clock signal output from the first frequency dividing circuit 28. And an error from the ideal clock signal is reduced. The clock generation circuit 29 supplies a plurality of clock signals to the frequency converter 19, the modem 21, the transmission control circuit 23, and the upper layer processing circuit 25. If there is no problem in signal processing even if a large error occurs in the clock signal, a part of these clock signals may be configured to divide the frequency from an arbitrary phase.
Further, FIG. 6 shows a configuration in which the original clock signal from the oscillator 27 is divided by the first frequency dividing circuit 28 by a non-integer number. It is also possible to adopt a configuration in which the frequency is divided by the first frequency dividing circuit 28 that performs integral frequency division, and the frequency is further divided by the second frequency dividing circuit 29. Further, the frequency converter 19 and the modem 2
1. For the transmission control circuit 23 and the upper layer processing circuit 25, depending on the clock frequency used, not the clock signal output from the first frequency divider 28 but the oscillator 27
May be input to the second frequency dividing circuit 29 to supply a clock signal obtained by directly dividing the frequency.

[0020]

According to the present invention, a low-frequency clock signal is generated by starting frequency division from a specific phase of a non-integer frequency-divided intermediate frequency clock signal. The error can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a clock generation circuit according to a first embodiment of the present invention.

FIG. 2 is a signal timing chart of the clock generation circuit according to the first embodiment of the present invention.

FIG. 3 is a characteristic diagram showing an error generated in the intermediate frequency clock signal of the clock generation circuit according to the first embodiment of the present invention.

FIG. 4 is a characteristic diagram showing a combination of phases of an intermediate frequency clock signal of the clock generation circuit according to the first embodiment of the present invention.

FIG. 5 is a characteristic diagram illustrating a root-mean-square error generated in a low-frequency clock signal of the clock generation circuit according to the first embodiment of the present invention;

FIG. 6 is a block diagram of a clock generation circuit according to a second embodiment of the present invention.

FIG. 7 is a block diagram illustrating a configuration of a conventional clock generation circuit.

[Explanation of symbols]

 5, 28 First frequency divider 6, 29 Second frequency divider 7, 27 Oscillator 30 Third frequency divider

Claims (2)

[Claims] An oscillator for generating an original clock signal;
A first frequency dividing circuit for dividing an original clock signal generated by the oscillator by repeating a frequency dividing cycle in which a plurality of frequency dividing numbers are combined to generate an intermediate frequency clock signal; Starts the frequency division from the phase of the second clock signal and generates a low frequency clock signal from the intermediate frequency clock signal.
And a frequency dividing circuit. 2. A clock generation circuit that divides an original clock signal and outputs two low-frequency clock signals.
An oscillator for generating an original clock signal, and a frequency dividing cycle in which a plurality of frequency dividing numbers are combined to divide the frequency, thereby generating an intermediate frequency clock signal from the original clock signal.
A second frequency divider circuit that starts frequency division from a specific phase in the frequency division cycle and generates a low frequency clock signal from the intermediate frequency clock signal; A third frequency dividing circuit that divides the frequency by a frequency dividing number; a low frequency clock signal generated by the second frequency dividing circuit; and a low frequency clock signal generated by the third frequency dividing circuit. A clock generation circuit for outputting a clock signal.