JP2001110918A - Non-volatile semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the types of multi-valued data written in a non-volatile semiconductor memory device where data are written in a storage nitride film in the shape of hot electrons. SOLUTION: Tunnel oxide films and storage nitride films are alternately deposited for the formation of a laminated gate structure, and multi-valued data are stored by the use of storage nitride films.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a semiconductor device, and more particularly to a nonvolatile semiconductor device for storing information in the form of electric charges in an insulating film.

[0002]

2. Description of the Related Art FIG. 1 shows a configuration of a memory cell transistor used in a conventional so-called MONOS type nonvolatile semiconductor memory device. Referring to FIG. 1, a memory cell transistor is formed on a Si substrate 11, and a SiO ₂ tunnel insulating film 12A covering a channel region formed between the diffusion regions 11A and 11B formed in the Si substrate 11; A storage nitride film 12B on the insulating film 12A, an SiO ₂ film 13 on the storage nitride film 12B, and a polysilicon control gate electrode 13 formed on the SiO ₂ film 13
The insulating films 12A to 12C are made of so-called O
The NO structure 12 is formed.

In such a memory cell transistor, information is written by generating hot electrons in the channel region and applying a positive voltage to the control gate electrode 13. That is, by applying a positive voltage to the control gate electrode 13, hot electrons generated in the channel region are injected into the storage nitride film 12B via the tunnel insulating film 12A and are stably trapped.
At this time, a positive voltage is applied to the diffusion region 11B to generate hot electrons in the diffusion region 1B of the channel region.
When the hot electrons are generated near 1B, the generated hot electrons are injected into a portion of the storage nitride film 12B near the diffusion region 11B. In contrast,
When the hot electrons are generated in the vicinity of the diffusion region 11A in the channel region by applying a positive voltage to the diffusion region 11A, the hot electrons are generated in the storage nitride film 12B. It is implanted into a portion near the diffusion region 11B.

FIGS. 2A and 2B show the storage nitride film 1.
2 shows a read operation of the memory cell transistor of FIG. 1 in a state where no electric charge is written in 2B. FIG. 2 (A)
, First, +5 is applied to the control gate electrode 13.
A read gate voltage of V is applied, the diffusion region 11A is grounded, and a +1 V drain voltage is applied to the diffusion region 11B. In this state, since no charge is held in the storage nitride film 12B, the memory cell transistor has an original threshold voltage, and carriers flow through the channel region. However, the carrier is the diffusion region 11A.
Has a cross-sectional area profile 11a that expands in the vicinity of and spreads out in the vicinity of the diffusion region 11B.

In FIG. 2B, a +5 V read gate voltage of the control gate electrode 13 is applied as in FIG. 2 A, the diffusion region 11 B is grounded, and a +1 V drain voltage is applied to the diffusion region 11 A. Show the case. Also in this case, carriers flow through the channel region because the memory cell transistor has an original threshold voltage.
The carrier spreads in the vicinity of the diffusion region 11B and narrows in the vicinity of the diffusion region 11A.
Having. In the following description, a read mode in which a positive voltage is applied to the diffusion region 11B and the diffusion region 11A is grounded as shown in FIG. 2A is referred to as a “forward read mode”, and a diffusion region shown in FIG. A read mode in which a positive voltage is applied to 11A and the diffusion region 11B is grounded is referred to as a “reverse read mode”.

FIG. 3A shows a forward read mode in which charges are trapped in a portion of the storage nitride film 12B near the diffusion region 11B. Referring to FIG. 3A, a carrier profile 11c cut off in the vicinity of the diffusion region 11B is formed in the channel region corresponding to the charge trap region, and this portion is formed in the storage nitride film 12B. Even when no charge is trapped in the diffusion region 11B, a depletion layer extends from the diffusion region 11B when a positive voltage is applied to the diffusion region 11B in the forward read mode. Not affected. That is, the control gate electrode 13
The channel region can be made conductive without changing the gate voltage applied to the channel region from the case of FIGS. 2A and 2B.

On the other hand, FIG. 3B shows the storage nitride film 1.
2B shows a case where information is read in a reverse read mode in a state where a charge trapping region similar to the case of FIG. 3A is formed. FIG.
Referring to (B), in this case, a carrier profile 11d having a shape that expands near the diffusion region 11B and narrows near the diffusion region 11A is formed. However, due to the influence of charges trapped near the diffusion region 11B, The carrier profile 11d corresponds to the diffusion region 1.
It is cut off near 1B. Since no positive voltage is applied to the diffusion region 11B in the reverse read mode in the region near the diffusion region 11B, the depletion layer does not protrude. Therefore, when the charge trap region is not formed, Indicates that the carrier profile 11d should continuously protrude from the diffusion region 11B. However, in the state of FIG. 3B, the presence of the charge trap region blocks the carrier profile 11d. In other words, in the state of FIG. 3B, the channel region cannot be made conductive unless the value of the gate voltage applied to the control gate electrode 13 is increased.

FIGS. 4A and 2B and FIGS.
In each of the read modes (A) and (B), the threshold voltage indicated by the memory cell transistor is shown. However, in FIG. 4, the horizontal axis indicates the threshold voltage, and the vertical axis indicates the frequency. In FIG. 4, A-1, A-2, and B-1 indicate the threshold voltages in the states of FIGS. 2A, 2B, and 3A, respectively. FIG. 3 shows -2.
The threshold voltage in the state (B) is shown.

Referring to FIG. 4, in the read state of FIGS. 2A, 2B and 3A, the memory cell transistor shows a threshold voltage V1, but the read state of FIG. In the state, the memory cell transistor exhibits a threshold voltage V2 higher than the threshold voltage V1. FIGS. 5A to 5D show possible data write states in the memory cell transistor of FIG.

Referring to FIG. 5A, this state corresponds to FIGS. 3A and 3B, and electric charges are trapped in a portion of the storage nitride film 12B near the diffusion region 11B. Have been. On the other hand, FIG. 5B shows a state in which charges are trapped in a portion near the diffusion region 11A in the storage nitride film 12B, and FIG. 5C shows a state in which charges are trapped in the storage nitride film 12B. This shows a state where charges are trapped in both the portion near the diffusion region 11A and the portion near the diffusion region 11B. Further, FIG.
Is the storage nitride film 1 corresponding to FIGS. 2A and 2B.
2B shows a state in which no charge is trapped in 2B.

As described above, the conventional MONOS type nonvolatile semiconductor device shown in FIG. 1 can hold four data in the four states of the binary values shown in FIGS. 5 (A) to 5 (D). is there. Table 1 shows examples of write conditions, read conditions, and erase conditions in the memory cell transistor of FIG.

[0012]

[Table 1]

Referring to Table 1, in the write mode, "forward write mode" and "reverse
In the forward write mode, a + 5V write voltage is applied to the diffusion region 11B.
A write gate voltage of +10 V is applied to the control gate electrode 13. On the other hand, the diffusion region 11A is grounded. On the other hand, in the reverse write mode, a write voltage of +5 V is applied to the diffusion region 11A, a write gate voltage of +10 V is applied to the control gate electrode 13, and the diffusion region 11B is grounded.

The read modes in Table 1 are the forward read mode and the reverses mode described above.
This is the same as the e read mode. Further, as shown in Table 1, the erase mode includes a “forward erase mode” and a “reverse erase mode”.
In the rd erase mode, an erase voltage of +5 V is applied to the diffusion region 11 </ b> B, and an erase gate voltage of −5 V is applied to the control gate electrode 13. As a result, the storage nitride film 1
In 2B, holes are injected into the charge trapping region shown in FIG. 5A from the channel region, and the trapped charges are neutralized. Similarly, in the reverse erase mode, an erase voltage of +5 V is applied to the diffusion j region 11A, and an erase gate voltage of -5 V is applied to the control gate electrode 13. As a result, holes are injected from the channel region into the charge trapping region shown in FIG. 5B in the storage nitride film 12B, and the trapped charges are neutralized.

Further, as shown in Table 1, the nonvolatile semiconductor memory device shown in FIG. 2 has a batch erase mode. In this case, an erase voltage of +5 V is applied to both the diffusion regions 11A and 11B. On the other hand, FIG. 6 shows another conventional M
1 shows a configuration of a memory cell transistor used in an ONOS nonvolatile semiconductor memory device.

Referring to FIG. 6, the memory cell transistor has an S region having a diffusion region 21A and a diffusion region 21B.
The diffusion regions 21A and 21B formed on the i-substrate 21
Oxide film 2 formed so as to cover the channel region between
2A and the storage nitride film 2 formed on the oxide film 22A.
2B, another oxide film 22C formed on the storage nitride film 22B, another storage nitride film 22D formed on the other oxide film 22C, and formed on the other nitride film 22D. A control gate electrode 23 made of polysilicon is formed on another oxide film 22E.

In the memory cell transistor of FIG. 6, information is transferred from the channel region in the Si substrate 21 to the storage nitride film 22.
B or the storage nitride film 22D is written in the form of a Fowler-Nordheim type tunnel current crossing the SiO ₂ film 22A or 22C. Since hot electrons accelerated in the vicinity of the diffusion region are not used, FIG.
No distinction is made between "forward" and "reverse" as in the MONOS type nonvolatile semiconductor memory device described above.

FIGS. 7 (A), 7 (B) and 8 (C)
7 illustrates writing and reading of information in the conventional memory cell transistor of FIG. 6. Referring to FIG. 7A,
In this state, no charge is injected into the storage nitride films 22B and 22D, and therefore, the memory cell transistor has an original threshold voltage.
By applying a voltage of V, grounding the diffusion region 21A, and applying a readout gate voltage of +5 V to the control gate electrode 23, carriers flow through the channel region. However, the carrier is the diffusion region 2
It has a cross-sectional area profile 21a that expands near 1A and narrows near the diffusion region 21B.

Next, FIG. 7B shows the storage nitride film 22B.
Shows the reading of information in a state where charges are stored in the storage nitride film 22D and no charge is stored in the storage nitride film 22D.
As described above, in the conventional nonvolatile semiconductor memory device shown in FIG. 6, the electric charge is not stored in the storage nitride film 22B but in the Fowler-Nordheim tunnel instead of the hot electrons generated in the vicinity of the diffusion region 21A or 21B. Since the current is injected as a current,
B is retained throughout.

In this state, the diffusion regions 21A, 2A
1B is grounded and a voltage of +1 V is applied to the other, the threshold voltage of the memory cell transistor changes due to the influence of the charge in the storage nitride film 22B. When the read gate voltage applied to the electrode 23 becomes +7 V, the memory cell transistor becomes conductive.

FIG. 8C shows the state of the storage nitride film 22.
The reading of information in a state where charges are accumulated in B and 22D is shown. Referring to FIG. 8C, in this case, with one of the diffusion regions 21A and 21B grounded and a voltage of +1 V applied to the other, the read gate voltage applied to the control gate electrode 23 is reduced. When the voltage is increased, the memory cell transistor becomes conductive when the voltage reaches + 9V.

FIG. 9 shows the relationship between the threshold voltage of such a memory cell transistor and the charge in the storage nitride films 22B and 22D. Note that in FIG. 9, (A) corresponds to the state of FIG. 7A, and the memory cell transistor has the threshold value V1. 7B corresponds to the state of FIG. 7B, and the memory cell transistor has the threshold value V2. 8C corresponds to the state of FIG. 8C, and the memory cell transistor has a threshold value V3.

As described above, in the nonvolatile semiconductor memory device shown in FIG. 6, it is possible to hold ternary information corresponding to the states shown in FIGS. 7A, 7B and 8C.

[0024]

As described above, in the conventional MONOS type nonvolatile semiconductor memory device shown in FIG. 2, it is possible to write and read four pieces of information in two values. Multi-level writing is not possible. Further, in the nonvolatile semiconductor memory device shown in FIG. 6, multi-level writing and reading of three or more values cannot be performed.

As described above, in the conventional nonvolatile semiconductor memory device shown in FIG. 2 or FIG. 6, in order to increase the amount of information that can be stored, there is a method other than advancing miniaturization using a higher resolution exposure process. However, in a nonvolatile semiconductor memory device that needs to apply a high voltage for such writing or erasing, there is naturally a limit to miniaturization.

Therefore, the present invention has solved the above problems,
It is a general object to provide a new and useful nonvolatile semiconductor memory device. A more specific object of the present invention is to provide a nonvolatile semiconductor memory device that can hold multi-valued information exceeding three values and four or more pieces of multi-information.

[0027]

The present invention has, for example, the following means for solving the above-mentioned problems. A substrate on which first and second diffusion regions are formed, and the first substrate on the substrate;
A stacked gate structure formed so as to cover a channel region between the diffusion region and the second diffusion region; and a control electrode formed on the stacked gate structure. And a stacked structure in which a second dielectric film is sequentially stacked, wherein hot electrons are generated in the channel region in at least one of the first and second diffusion regions. A non-volatile semiconductor memory device comprising a write voltage generation circuit for applying an appropriate write voltage.

Further, the following means may be used. First
A stacked gate structure formed on the substrate to cover a channel region between the first diffusion region and the second diffusion region; and a stacked gate structure formed on the substrate so as to cover a channel region between the first diffusion region and the second diffusion region. A non-volatile semiconductor memory device comprising a control electrode formed on a gate structure, wherein the stacked gate structure is formed by repeatedly stacking a stacked structure in which first and second dielectric films are sequentially stacked. A first read mode in which a first read voltage is applied to the first diffusion region and a second read voltage is applied to the second diffusion region; and a second read mode in which the second read voltage is applied to the first diffusion region.
And the first diffusion region is supplied to the first diffusion region.
And a second read mode in which a read voltage of
Different threshold voltages, wherein in each of the first read mode and the second read mode, the threshold voltage is a value selected from a plurality of different threshold values. A nonvolatile semiconductor memory device comprising:

[Operation] According to the present invention, charges are transferred in the form of hot electrons to the first or second dielectric film in a stacked gate structure formed by repeatedly stacking the stacked structure of the first and second dielectric films. By injecting the second diffusion region while applying various write voltages, electric charges are held in a plurality of layers in the stacked gate structure. Due to these different states, the non-volatile semiconductor memory device of the present invention can realize multi-level writing that exceeds the conventional non-volatile semiconductor memory device. At this time, the electric charge is transferred to the portion near the first diffusion region or the second diffusion region in each layer.
The multi-level write data can be read while being distinguished from each other by performing reading from the first diffusion region side and the second diffusion region side. Become.

[0030]

FIG. 10 shows a configuration of a memory cell transistor in a nonvolatile semiconductor memory device according to a first embodiment of the present invention. Referring to FIG. 10, the memory cell transistor is formed on a p-type Si substrate 41 on which n-type diffusion regions 41A and 41B are formed.
A thermal oxide film (tunnel oxide film) 42A having a thickness of 1 to 5 nm and a CVD-film having a thickness of 5 to 15 nm are formed on the substrate 1 so as to cover a channel region between the diffusion regions 41A and 41B.
The stacked gate structure 42 is formed by repeatedly stacking the SiN film (storage nitride film) 42B. Further, a polysilicon control gate electrode 43 is formed on the stacked gate structure 42.

FIGS. 11A and 11B are diagrams for explaining reading of the memory cell transistor in a state where no electric charge is captured in the stacked gate structure 42. FIG. Referring to FIG. 11A, a read gate voltage of +5 V is applied to the control gate electrode 43, the diffusion region 41A is grounded, and a read voltage of +1 V is applied to the diffusion region 41B. Such reading by carriers flowing from the diffusion regions 41A to 41B in the channel region will be referred to as "forward reading" hereinafter.

In this state, since no charge is held in the stacked gate structure 42, the memory cell transistor exhibits an original threshold voltage, and carriers (electrons) flow through the channel region in the diffusion region 41A. To the diffusion region 41B. As a result, the diffusion region 41B spreads in the channel region on the side of the diffusion region 41A.
A channel 41a having a profile of a cross-sectional shape narrowing on the side of is formed.

FIG. 11B shows the diffusion regions 41A, 4A.
1B shows a state where the read voltage applied to 1B is replaced, the diffusion region 41B is grounded, and a voltage of +1 V is applied to the diffusion region 41A. Such reading by carriers flowing from the diffusion regions 41B to 41A in the channel region will be hereinafter referred to as "reverse reading".

Referring to FIG. 11B, even in this state, no charge is held in the stacked gate structure 42, so that the memory cell transistor has the same threshold voltage as that of FIG. A channel 41b in which electrons flow from the diffusion region 41B to the diffusion region 41A is formed in the channel region. The channel 41b has a cross-sectional profile that expands on the diffusion region 41B side and narrows on the diffusion region 41A side.

On the other hand, FIGS. 12C and 12D show a state where charges are trapped in a portion near the diffusion region 41 B in the lowermost storage nitride film 42 B in the laminated gate structure 42. Show. The injection of the charge into the portion near the diffusion region 41B is performed in the channel region in the diffusion region 4B.
This is performed by generating hot electrons in a portion near 1B, simultaneously applying a predetermined write gate voltage to the control gate electrode 43, and injecting the generated hot electrons through the tunnel oxide film 42A.

Referring to FIG. 12C, in this state, a gate voltage of +5 V is applied to the control gate electrode 43, a read voltage of +1 V is applied to the diffusion region 41B, and the diffusion region 41A is grounded. In this case, the charge trapped in the storage nitride film 42B is located at a position corresponding to the depletion layer protruding from the diffusion region 41B, so that the threshold characteristic of the memory cell transistor is hardly affected. Accordingly, in the channel region, the channel 4 having a carrier distribution profile almost the same as the profile 41a is provided.
1c is formed.

On the other hand, as shown in FIG. 12D, a gate voltage of +5 V is applied to the control gate electrode 43, a read voltage of +1 V is applied to the diffusion region 41A, and the diffusion region 41B is grounded. In this case, the depletion layer overhangs from the diffusion region 41A, so that the charges trapped in the storage nitride film 42B are transferred from the diffusion region 41B to the diffusion region 41A in the channel region.
Actually cuts off the carriers flowing through the channel 41d and correspondingly forms a channel 41d formed in the channel region.
Is also blocked in the vicinity of the diffusion region 41B. In such a state, the threshold voltage of the memory cell transistor increases, and a higher gate voltage is required to make the channel region conductive.

FIGS. 13E and 13F show that electric charges are trapped in a portion near the diffusion region 41B in the lowermost storage nitride film 42B and the upper storage nitride film 42D in the stacked gate structure 42. It shows the state that it was. The charge injection into the portion near the diffusion region 41B is performed in the portion near the diffusion region 41B in the channel region as shown in FIG.
By generating hot electrons with higher energy than in the cases of (C) and (D) and applying a higher write gate voltage to the control gate electrode 43 than in the case of FIGS. 12 (C) and (D), This is performed by injecting the hot electrons into the lower and upper storage nitride films 42B and 42C.

Referring to FIG. 13E, in this state, a gate voltage of +5 V is applied to the control gate electrode 43, a read voltage of +1 V is applied to the diffusion region 41B, and the diffusion region 41A is grounded. In this case, the charge trapped in the storage nitride film 42B is located at a position corresponding to the depletion layer protruding from the diffusion region 41B, so that the threshold characteristic of the memory cell transistor is hardly affected. Accordingly, in the channel region, the channel 4 having a carrier distribution profile almost the same as the profile 41a is provided.
1e is formed.

On the other hand, as shown in FIG. 13F, a gate voltage of +5 V is applied to the control gate electrode 43, a read voltage of +1 V is applied to the diffusion region 41A, and the diffusion region 41B is grounded. In this case, since the depletion layer overhangs from the diffusion region 41A, the charges trapped in the storage nitride films 42B and 42D actually cause carriers flowing from the diffusion region 41B to the diffusion region 41A in the channel region. And shut off
It can be seen that the channel 41f formed in the channel region is also cut off in the vicinity of the diffusion region 41B. In such a state, the threshold voltage of the memory cell transistor is further increased than in the case of FIG. 12D, and a higher gate voltage is required to make the channel region conductive.

FIG. 14 shows the threshold value of the memory cell transistor in each of the states shown in FIGS. 11 (A) to 13 (F). Referring to FIG. 14, FIG.
(B) and the states of FIGS. 12 (C) and 13 (E),
The threshold voltage of the memory cell transistor is approximately V1
On the other hand, in the state of FIG. 12D, the threshold voltage has increased to V2. Further, in the state shown in FIG. 13F, the threshold voltage has increased to V3, which is even higher.

By forming a plurality of storage nitride films in the stacked gate structure 42 in this manner, the nonvolatile semiconductor memory device according to the present invention can hold multi-value data more than the conventional one. Become. FIG.
FIGS. 16H and 16I show possible states of the memory cell transistor of FIG. Among them, FIG.
(I) corresponds to the states of FIGS. 11 (A) and (B), while FIG. 15 (A) corresponds to the states of FIGS. 12 (C) and (D), and FIG. 15 (B) corresponds to FIG. ) And (F).
The remaining states (C) to (H) are combinations of these states.

Table 2 below shows examples of write conditions for the states shown in FIGS. 15A to 15H.

[0044]

[Table 2]

For example, to write the state shown in FIG. 15A, condition 1 in Table 2 is used. On the other hand, the condition 3 in Table 2 is used to write the state of FIG. Further, FIG.
To write the state of (C), condition 2 in Table 2 is used,
To write the state of FIG. 15D, condition 4 in Table 2 is used. To write the state shown in FIG.
Conditions 2 and 3 are used, and conditions 1 and 4 in Table 2 are used to write the state of FIG. To write the state shown in FIG. 15G, the conditions 1 and 2 in Table 2 are used. To write the state shown in FIG.
Conditions 3 and 4 in Table 2 are used.

Referring to Table 2, under condition 1, a write gate voltage of +10 V is applied to the control gate electrode 43, the diffusion region 41A is grounded and the diffusion region
A write voltage of +5 V is applied to 1B. This allows
Hot electrons are generated in the vicinity of the diffusion region 41B, and “forward writing” is performed on a portion near the diffusion region 41B in the first-layer storage nitride film 42B. On the other hand, under the condition 2, the write gate voltage applied to the control gate electrode 43 is +10 V
However, the write voltage applied to the diffusion regions 41A and 41B is switched, and as a result, "reverse writing" is performed on the portion near the diffusion region 41A in the first-layer storage nitride film 42B.

Further, under condition 3, a higher write gate voltage of +12 V is applied to the control gate electrode 43, the diffusion region 41A is grounded and the diffusion region 41A is grounded.
B applies a higher write voltage of + 7V. As a result, hot electrons having higher energy are generated in the vicinity of the diffusion region 41B, so that not only the first storage nitride film 42B but also the second storage nitride film 42D near the diffusion region 41B. "Forward
d writing "is performed. On the other hand, under the condition 4, the write gate voltage applied to the control gate electrode 43 remains +12 V, but the diffusion regions 41A, 41B
The write voltage applied to the first and second storage nitride films 42B and 42D is closer to the diffusion region 41A.
Verse writing "is performed.

Further, Table 2 shows that the above conditions f and
The conditions of the backward read and the reverse read are shown. Conditions 5 and 6 are as shown in FIG.
This is the same as described in (A) to 13 (F). Under the above conditions 1 to 6, the substrate 41 itself is grounded. Table 2 also shows conditions for erasing information stored in the stacked gate structure 42, that is, charges.

Referring to Table 2, the conditions 1 or 3
In order to erase information written in the forward write mode, an erasing voltage of +7 V is applied to the diffusion region 41B as shown in a condition 7, and an erasing gate voltage of -7 V is applied to the control gate electrode 43. As a result, holes are injected into a portion of the storage nitride film 42B or 42D near the diffusion region 41B. At this time, the diffusion region 11A is in a floating state, and the Si substrate 41 itself is grounded. In order to erase the information written in the reverse write mode of the condition 2 or 4, as shown in the condition 8, an erasing voltage of +7 V is applied to the diffusion region 41A, and the negative voltage is applied to the control gate electrode 43. By applying an erase gate voltage of 7 V, holes are injected into a portion of the storage nitride film 42B or 42D near the diffusion region 41B. At this time, the diffusion region 4
1B is in a floating state, and the Si substrate 41 is grounded.

Further, as shown in condition 9, the collective erasing can be performed by applying an erasing voltage of +7 V to the diffusion regions 41A and 41B. Condition 7
It can be seen that the Si substrate 41 is grounded also in the erasing modes of Nos. To 9. FIG. 17 (A) to FIG. 18 (G)
9 shows a manufacturing process of the nonvolatile semiconductor memory device of the present invention.

Referring to FIG. 17A, the thermal oxide film 42A is formed on the Si substrate 41 by a thermal oxidation process.
The thermal oxide film 42A is formed to a thickness of 5 nm.
An SiN film is formed to a thickness of 5 to 15 nm as the storage nitride film 42B by the CVD method. FIG.
In the step (B), the surface of the storage nitride film 42B is thermally oxidized so that the thermal oxide film 42C has a thickness of 1 to 5n.
m, and an SiN film is roughly formed on the thermal oxide film 42C by the CVD method.
D is formed to a thickness of 5 to 15 nm.

Further, in the step of FIG. 17C, the thermal oxide film 42E is formed to a thickness of 1 to 5 nm on the surface of the storage nitride film 42D by thermal oxidation. 17D, a resist pattern is formed on the thermal oxide film 42E, and the dielectric films 42E to 42A are sequentially dry-etched by the RIE method using the resist pattern as a mask. To form

Next, in the step of FIG.
In the i-substrate 41, As ⁺
Is performed to form the diffusion regions 41A and 41B adjacent to the stacked gate structure. In the step of FIG. 18F, the structure of FIG. 18E is covered with a thermal oxide film 42I by a thermal oxidation step.
In this step, a polysilicon film is deposited so as to cover the structure shown in FIG. 18F, and the polysilicon film is patterned to form the control gate electrode 43.
The control gate electrode 43 extends left and right in FIG. 18F, and forms a word line WL of the nonvolatile semiconductor memory device. On the other hand, the diffusion regions 41A and 41B
8 (F) in the direction perpendicular to the plane of the drawing, and the bit line BL
To form [Second Embodiment] FIGS. 19 and 20 are a plan view and a sectional view showing a structure of a nonvolatile semiconductor memory device having a so-called embedded bit line according to a second embodiment of the present invention. 19 and 20 are denoted by the same reference numerals and description thereof is omitted.

Referring to FIGS. 19 and 20, an Si substrate 41 is formed.
A plurality of strip-shaped element isolation insulating films 41f are formed on the surface.
Extend in parallel with each other, and in the Si substrate 41, along the surface of the element isolation insulating film 41f, a diffusion region 41A,
41B extends like a strip like the element isolation insulating film 41f. The diffusion regions 41A and 41B form bit lines BL embedded in the Si substrate 41.

Further, an element isolation insulating film 41f adjacent to one element isolation insulating film 41f is formed on the surface of the Si substrate 41.
In between, a stacked gate structure 42 including the plurality of storage nitride films 42B and 42D is formed. Further, the polysilicon control gate electrode 4 is formed on the Si substrate 41 in a direction perpendicular to the direction in which the element isolation insulating film 41f extends.
3 extend as a word line WL. That is, FIG.
The memory cell array in the nonvolatile semiconductor memory device shown in FIGS. 9 and 20 has an equivalent circuit diagram shown in FIG.

FIG. 22 is a block diagram showing a configuration of a nonvolatile semiconductor memory device using the memory cell transistors of FIGS. Referring to FIG. 22, the nonvolatile semiconductor memory device includes a memory cell array 101 shown in the equivalent circuit diagram of FIG. 21, and a desired word is stored in the memory cell array based on address data held in an address latch circuit 102. X decoder 103 for selecting line WL
And a Y decoder 104 that selects a desired bit line BL via a Y gate 101A cooperates.

Further, the nonvolatile semiconductor memory device includes an input / output buffer circuit 105 and a data latch circuit 106 cooperating therewith, and the data latch circuit 106 is supplied via the input / output buffer circuit 105. The write voltage control circuit 107 is controlled by the binary write data. More specifically, the binary write data held in the data latch circuit 106 is multi-value data written in the storage nitride films 42B and 42D,
For example, a binary-multi-level conversion circuit 1 is added to the nine data in FIG.
06A, while the write voltage control circuit 107 supplies the boosted voltage Vp via the power switch 108.
p is supplied, and a write voltage to be applied to the diffusion region 41A or 41B is generated according to the multi-value data formed by the conversion circuit 106A. The write voltage generated by the write voltage control circuit 107 is supplied to the Y gate 1 via the Y decoder 104.
01A and supplied to the selected bit line pair BL from the Y gate 101A. A well-known shift register can be used as the binary-multivalue conversion circuit 106A. The write voltage control circuit 107 includes a polarity inversion circuit 107A that inverts the polarity of the write voltage applied to the bit line pair BL in the forward write mode and the reverse write mode according to the value of the multi-value data.

Further, the nonvolatile semiconductor memory device is
Write enable signal WE and chip enable signal CE
And a control circuit 109 to which the control circuit 109 is supplied.
And a word line voltage control circuit 110 that is activated by the word line voltage control circuit 110. In the write mode of the nonvolatile semiconductor memory device, the word line voltage control circuit 110 controls a predetermined write gate voltage under the control of the control circuit 109. This is supplied to the selected word line WL in the memory cell array 101 via the address latch circuit 102 and the X decoder 103.

Further, the nonvolatile semiconductor memory device is
The bit line pair BL selected by the Y gate 101A
, A sense amplifier 111 for determining conduction of a selected memory cell transistor, and the sense amplifier 11
1, a multi-level output signal indicating the state of the selected memory cell transistor output from the state determination circuit 112 is output from a well-known shift register. Multi-value-
After being converted into a binary signal by the binary conversion circuit 106B,
The data is supplied to the data latch circuit 106. The state determination circuit 112 is activated by the control circuit 109 in the read mode.

The state determination circuit 112 further outputs a word line voltage selection signal, and controls the word line voltage control circuit 110 according to the word line voltage selection signal. That is, in the read mode, the word line voltage control circuit 110 selectively outputs one of a plurality of word line voltages according to the word line voltage selection signal. 22 further includes an input / output controller 113 to which a chip enable signal CE and an input / output control signal OE are supplied. The data latch circuit 106 and the input / output buffer 105 are connected to the input / output controller 105. Under the control of 113, the data held in the data latch circuit 106 is output.

By using the nonvolatile semiconductor memory device shown in FIG. 22, multi-valued data exceeding conventional four-valued data is written into the selected memory cell transistor in the memory cell array 101, and the written multi-valued data is stored in the selected memory cell transistor. It becomes possible to read. In summary, the present invention provides: (1) A substrate on which first and second diffusion regions are formed, and a stacked gate formed on the substrate so as to cover a channel region between the first diffusion region and the second diffusion region And a control electrode formed on the stacked gate structure, wherein the stacked gate structure has a first dielectric film that is less likely to charge and a second dielectric film that is easier to charge. In a non-volatile semiconductor memory device in which a layered structure is sequentially laminated, a write voltage that generates hot electrons in the channel region is applied to at least one of the first and second diffusion regions. A nonvolatile semiconductor memory device comprising a write voltage generation circuit.

(2) The write voltage generating circuit includes a first write voltage that does not cause the injection of the hot electrons into the stacked gate structure, and a first write voltage included in the first layer of the stacked structure. The second writing in which the hot electrons are injected into the second dielectric film, but the hot electrons are not injected into the second dielectric film included in the second layered structure. Voltage and said second
Selectively generating one of a plurality of write voltages including a third write voltage at which the hot electrons are injected into the second dielectric film included in the layered structure of the layer (1) The nonvolatile semiconductor memory device according to (1).

(3) A write control circuit for applying a write gate voltage to the control gate electrode, wherein the write control circuit selectively generates one of a plurality of write gate voltages. (1)
Or the nonvolatile semiconductor memory device according to (2). (4) Further, an erase voltage generating circuit for applying an erase voltage for generating a hot hole in the channel region is provided to at least one of the first and second diffusion regions. A first erase voltage that does not cause injection of the hot hole into the stacked gate structure, and the hot hole is injected into the second dielectric film included in the first layer of the stacked structure. However, in the second dielectric film included in the second layered structure, a second erase voltage at which the hot holes are not injected is included in the second dielectric film, and the second erasing voltage is included in the second layered structure. And (3) selectively generating one of a plurality of erasing voltages including a third erasing voltage at which the hot holes are injected into the second dielectric film. If (3) is not described in any one of Volatile semiconductor storage device.

(5) The first dielectric film is formed of a silicon oxide film, and the second dielectric film is formed of a silicon nitride film. A nonvolatile semiconductor device according to claim 1. (6) A substrate on which first and second diffusion regions are formed, and a laminated gate formed on the substrate so as to cover a channel region between the first diffusion region and the second diffusion region. And a control electrode formed on the stacked gate structure. The stacked gate structure is a non-volatile semiconductor storage device formed by repeatedly stacking a stacked structure in which first and second dielectric films are sequentially stacked. The nonvolatile semiconductor device, wherein a first read mode in which a first read voltage is applied to the first diffusion region and a second read voltage is applied to the second diffusion region; A threshold voltage different from that in the second read mode in which the second read voltage is applied to the region and the second read mode in which the first read voltage is applied to the first diffusion region;
Wherein the threshold voltage has one value selected from a plurality of different threshold values in both the read mode and the second read mode. .

Although the present invention has been described with reference to preferred embodiments, the present invention is not limited to these embodiments, and various modifications and changes can be made within the scope of the claims.

[0066]

According to the first to fifth aspects of the present invention, electric charges are stored in a stacked gate structure formed by repeatedly stacking the first and second dielectric films. In the form described above, the charge is retained over a plurality of layers in the stacked gate structure by injecting while applying various write voltages to the first or second diffusion region. Due to these different states, the non-volatile semiconductor memory device of the present invention can realize multi-level writing that exceeds the conventional non-volatile semiconductor memory device. At this time, the charge is held in a portion near the first diffusion region or a portion near the second diffusion region in each layer,
Therefore, by performing reading from the first diffusion region side and the second diffusion region side, the multi-valued write data can be read while being distinguished from each other.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a memory cell transistor of a conventional MONOS type nonvolatile semiconductor memory device.

FIGS. 2A and 2B are diagrams illustrating a multi-value storage operation of the MONOS type nonvolatile semiconductor memory device of FIG. 1 (part 1);

FIGS. 3C and 3D are diagrams (part 2) illustrating a multi-value storage operation of the MONOS type nonvolatile semiconductor memory device of FIG. 1;

FIG. 4 is a diagram showing a distribution state of threshold values of the MONOS type nonvolatile semiconductor memory device of FIG. 1;

5A to 5D are diagrams collectively showing multi-value storage of information in the MONOS-type nonvolatile semiconductor memory device in FIG. 1;

FIG. 6 is a diagram showing a configuration of another conventional nonvolatile semiconductor memory device.

FIGS. 7A and 7B are diagrams (part 1) for explaining holding of multi-level data in the nonvolatile semiconductor memory device of FIG. 6;

FIG. 8C is a diagram (part 2) illustrating holding of multi-value data in the nonvolatile semiconductor memory device in FIG. 6;

9 is a diagram showing a distribution state of threshold values of the nonvolatile semiconductor memory device of FIG. 6;

FIG. 10 is a diagram showing a configuration of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIGS. 11A and 11B are diagrams (part 1) illustrating holding of multi-value data in the nonvolatile semiconductor memory device of FIG. 10;

FIGS. 12C and 12D are diagrams (part 2) for explaining holding of multi-value data in the nonvolatile semiconductor memory device of FIG. 10;

FIGS. 13E and 13F are diagrams (part 3) illustrating holding of multi-value data in the nonvolatile semiconductor memory device of FIG. 10;

14 is a diagram showing a distribution state of threshold values of the nonvolatile semiconductor memory device of FIG. 10;

15A to 15H are diagrams (part 1) collectively showing multi-value storage of information in the nonvolatile semiconductor memory device in FIG. 10;

16A is a diagram (part 2) collectively showing multi-value storage of information in the nonvolatile semiconductor memory device in FIG. 10;

17A to 17D are diagrams (part 1) illustrating a process of manufacturing the nonvolatile semiconductor memory device in FIG. 10;

18 (E) to 18 (G) are views (No. 2) showing the steps of manufacturing the nonvolatile semiconductor memory device of FIG.

FIG. 19 is a plan view showing a configuration of a nonvolatile semiconductor memory device according to a second embodiment of the present invention.

20 is a cross-sectional view showing a configuration of the nonvolatile semiconductor memory device of FIG.

21 is an equivalent circuit diagram of a memory cell array in the nonvolatile semiconductor memory device of FIG.

FIG. 22 is a block diagram showing a configuration of the nonvolatile semiconductor memory device of FIG.

[Explanation of symbols]

11, 21, 41 substrates 11A, 11B, 21A, 21B, 41A, 41B Diffusion regions 11a to 11d. 21a-21c, 41a-41f Channel 12,42 Stacked gate structure 12A, 12C, 22E, 42A, 42C, 42E Thermal oxide film 12B, 22B, 22D, 42B, 42D Storage nitride film 13,23,43 Control gate electrode 42f Element Isolation insulating film 42I CVD insulating film 101 Memory cell array 101A Y gate 102 Address latch circuit 103 X decoder 104 Y decoder 105 Input / output buffer 106 Data latch circuit 106A Binary-to-multilevel conversion circuit 106B Multilevel-to-binary conversion circuit 107 Write voltage Control circuit 108 Power switch 109 Control circuit 110 Word line voltage control circuit 111 Sense amplifier 112 State determination circuit 113 Input / output control circuit

 ──────────────────────────────────────────────────続 き Continuing on the front page F term (reference) 5B025 AA04 AB02 AC01 5F001 AA14 AB02 AC06 AD15 AD62 AE02 AE08 AF20 AG21 5F083 EP18 EP65 EP70 EP77 ER02 ER05 ER06 ER09 ER11 ER21 ER30 GA30 JA04 KA01 LA12 LA16 NA11 Z05 BB11 BD37 BE05 BE07 BF05 BH02

Claims (5)

[Claims] A substrate on which first and second diffusion regions are formed; and a substrate formed on the substrate so as to cover a channel region between the first diffusion region and the second diffusion region. A stacked gate structure, and a control electrode formed on the stacked gate structure, wherein the stacked gate structure is a non-volatile structure obtained by repeatedly stacking a stacked structure in which first and second dielectric films are sequentially stacked. In a semiconductor memory device, a non-volatile semiconductor device comprising a write voltage generation circuit for applying a write voltage for generating hot electrons in the channel region to at least one of the first and second diffusion regions. Storage device. 2. The write voltage generation circuit includes: a first write voltage that does not cause injection of the hot electrons into the stacked gate structure; and a second write voltage included in the first stacked structure. The second write voltage is such that the hot electrons are injected into the dielectric film, but the hot electrons are not injected into the second dielectric film included in the second layered structure. One of a plurality of write voltages, including a third write voltage at which the hot electrons are injected into the second dielectric film included in the second layered structure. 2. The non-volatile semiconductor storage device according to claim 1, wherein the non-volatile semiconductor storage device is generated in a random manner. 3. A write control circuit for applying a write gate voltage to the control gate electrode, wherein the write control circuit selectively generates one of a plurality of write gate voltages. Claim 1
Or the nonvolatile semiconductor memory device according to 2. 4. An erasing voltage generating circuit for applying an erasing voltage for generating a hot hole in the channel region to at least one of the first and second diffusion regions, wherein the erasing voltage generating circuit is A first erasing voltage such that the hot holes are not injected into the stacked gate structure, and the hot holes in the second dielectric film included in the first stacked structure. A second erase voltage that is injected but does not cause the hot holes to be injected into the second dielectric film included in the second layered structure; And selectively generating one of a plurality of erasing voltages including a third erasing voltage in which the hot holes are injected into the second dielectric film included in the second dielectric film. Any one of 1-3 is described Nonvolatile semiconductor memory device. 5. A substrate on which first and second diffusion regions are formed, and formed on the substrate to cover a channel region between the first diffusion region and the second diffusion region. A stacked gate structure; and a control electrode formed on the stacked gate structure. The stacked gate structure is a nonvolatile semiconductor formed by repeatedly stacking a stacked structure in which first and second dielectric films are sequentially stacked. In the storage device, the nonvolatile semiconductor device may include a first read mode in which a first read voltage is applied to the first diffusion region, and a second read voltage in which a second read voltage is applied to the second diffusion region;
The second read voltage to the diffusion region of
In the second read mode in which the first read voltage is applied to the diffusion region, a different threshold voltage is shown. In both the first read mode and the second read mode, the threshold voltage is different. A non-volatile semiconductor memory device, wherein the threshold voltage has one value selected from a plurality of different thresholds.