JP2001101004A - Electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To rewrite a flash ROM not via the CPU of an extended board. SOLUTION: When a flash ROM down-load mode from a host CPU 2 to a PCI bus bridge 29 of an extended board 12 is set, a bus release request signal from a CPU bus release request signal generating part 34 of the extended board 12 to a CPU 21 is asserted so that the CPU 21 can release a bus 20, and the bus of a flash ROM 22 can drive a PCI bus bridge 29. The host CPU 2 executes a rewriting algorithm to the flash ROM 22 so that writing in all address regions can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a PCI (Peripera)
The present invention relates to an electronic device that stores a program of a CPU on an expansion board connected to a (Component Interconnect) bus in a flash ROM.

[0002]

2. Description of the Related Art A PCI bus has been proposed to be independent of a specific CPU when connecting an expansion board.
A bridge circuit is inserted between the CPU and the local bus expansion board. As a conventional example of this kind, for example,
In Japanese Patent Application Laid-Open No. 9-048164, in an extended multifunction system based on a printer, an application program is downloaded to a personal computer module in order to extend the function by connecting to a PCI bus, and the personal computer module installs another extension module. Controllable systems have been proposed.

[0003]

When there is a CPU mounted on an expansion board connected to the PCI bus and controlling the expansion board, an operation program is naturally required. Therefore, a flash ROM is mounted on the extension board. In order to download a program from the host CPU of the PCI bus to the flash ROM, the CPU on the expansion board must write the ROM code data transferred from the host CPU into the flash ROM by itself. For this reason, a program for rewriting must be stored in advance in the flash ROM, and if rewriting fails due to power cutoff during rewriting, the worst case is that the CPU of the expansion board does not start up. 1).

When the host CPU directly controls the flash ROM on the extension board to perform writing, if the flash ROM writing algorithm is different depending on the ROM manufacturer, or if a plurality of flash ROMs are used,
The host CPU cannot perform control (second problem). When the host CPU directly controls the flash ROM on the expansion board to perform writing, the host C
There is a trouble that the PU transfers the ROM code data to the PCI bridge on the expansion board every time one-word writing is completed while confirming the write completion status (third problem).

SUMMARY OF THE INVENTION In view of the first problem, it is a first object of the present invention to provide an electronic device capable of rewriting a flash ROM without the intervention of a CPU of an expansion board.

The present invention has also been made in view of the second problem,
The PCI bridge on the expansion board executes the write algorithm of the flash ROM, and the host CPU
It is a second object of the present invention to provide an electronic device which only needs to transfer ROM code data.

The present invention has also been made in view of the above third problem,
The PCI bridge on the expansion board becomes the bus master of the PCI bus, and reads the ROM code data each time the writing is completed and writes the data to the flash ROM, so that the host C
A third object is to provide an electronic device capable of rewriting a flash ROM without intervening PU processing.

[0008]

In order to achieve the first object, a first means is to provide a PCI bus bridge, a CPU for controlling the expansion board, a CPU and a CPU on an expansion board connected to a PCI bus. In an electronic device in which a flash ROM storing the operation program of the expansion board is mounted and the host CPU of the PCI bus controls the expansion board via the PCI bus, a PROM on the expansion board
Means for the CI bus bridge to request the CPU on the expansion board to release the bus; and controlling the bus to the flash ROM in response to access from the PCI bus so that the host CPU can directly rewrite the flash ROM. And means for performing the operation.

In order to achieve the second object, the second means includes a PCI bus on an expansion board connected to a PCI bus.
Bus bridge, CPU and C controlling the expansion board
In an electronic device in which a flash ROM in which an operation program of a PU is stored is mounted and a host CPU of the PCI bus controls the expansion board via the PCI bus, a PCI bus bridge of the expansion board is connected to the flash ROM. Means for executing a write algorithm, means for latching write data from the PCI bus, and means for notifying the PCI bus of a flash ROM write status, wherein the host CPU checks the status to the PCI bus bridge. Only the ROM code data is written, and the PCI bus bridge writes the latched data to a flash ROM.

[0010] A third means is to provide a PCI bus on an expansion board connected to a PCI bus in order to achieve the third object.
Bus bridge, CPU and C controlling the expansion board
In an electronic device in which a flash ROM storing an operation program of a PU is stored and a host CPU of the PCI bus controls the expansion board via the PCI bus, a PCI bus bridge of the expansion board is connected to a PCI bus. It has a bus master function and means for latching master read data, and every time writing to the flash ROM is completed, a device in a memory space of the PCI bus becomes a bus master to read data and write a program to the flash ROM. I do.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS <First Embodiment> An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a digital multifunction peripheral as one embodiment of an electronic apparatus according to the present invention, FIG. 2 is a block diagram showing a detailed configuration of a facsimile board as an example of an expansion board in FIG. 1, and FIG. FIG. 4 is a block diagram showing the configuration of the bus bridge in detail, and FIG. 4 is a flowchart for explaining flash ROM writing processing.

In FIG. 1, a system bus 1 has a host CPU 2, a flash ROM 3, a memory card 4, a host memory 5, a display operation unit 6, a scanner 7, a plotter 8,
The DMA controller 9 and the host PCI bridge 10 are connected, and the host PCI bridge 10
Are connected to the expansion boards 12-1 to 12-3. In this example, the host CPU 2 is a processor that controls the entire digital multifunction peripheral. That is, the host CPU 2
And the host memory 5 are connected by a system bus 1, and the system bus 1 is connected to a PC via a host PCI bridge 10.
Connected to I bus 11. An expansion board 12 is connected to the PCI bus 11 to perform function expansion. In this case, the host CPU 2 can control the expansion board 12 via the PCI bus 11.

FIG. 2 shows a facsimile board as an example of the extension board 12. Internal bus (local bus)
Reference numeral 20 denotes a CPU 21, a flash ROM 22, a RAM 2
3, the image memory 24, the DMA control unit 25, the encoding / decoding unit 26, the communication control unit 27, the DPRAM 28, and the PCI bus bridge 29 are connected. The PCI bus bridge 29 is also connected to the PCI bus 11 shown in FIG. You. The control of the board 12 is performed by the CPU 21 on the board 12, and the operation program is stored in the flash ROM 22.
The host CPU 2 is a DPRAM (Dual Port RAM) 28
Is communicated through the host CPU 2 and the expansion board 1
2 is accessed via the PCI bus 11.

FIG. 3 shows the PCI bus bridge 29 on the expansion board 12 in detail. The internal bus 30 includes a local bus controller 31, a flash ROM rewrite controller 32, a data request generator 33, and a CPU bus release request signal generator 3.
4, a PCI bus control unit 35, a configuration control unit 36, an initiator control unit 37, and a target control unit 38 are connected. The local bus control unit 31 is connected to the local bus (the internal bus 20 shown in FIG. 2), and is connected to the PCI bus control unit 35 and the PCI bus 11 shown in FIG.

In such a configuration, the PCI bus control unit 35 interfaces the PCI bus 11.
The configuration control unit 36 controls a configuration register and the like for complying with the PCI bus standard. The initiator control unit 37 determines that the expansion board 12 is connected to the PCI bus 11
And performs read / write access to devices in the PCI bus memory space. The target control unit 38 responds to an access by another bus master. The local bus control unit 31 controls input / output of the local bus.

The CPU bus release request signal generator 34 is a PC
The host CPU 2 performs target access from the I bus 11 and generates a bus release request signal to the CPU 21 on the expansion board 12. The flash ROM rewriting control unit 32 executes a rewriting algorithm of the flash ROM 22 mounted on the extension board 12 to perform rewriting, and also transmits status information of a write completed state to the host C.
The target is accessed from PU2 and notified. The data request generation unit 33 requests the master control unit (the initiator control unit 37) to read the flash ROM rewrite data from the PCI bus 11.

Next, a flash ROM writing process according to the first embodiment will be described with reference to FIG. First, a flash ROM (FROM) download mode is set from the host CPU 2 to the PCI bus bridge 29 of the expansion board 12 (step S1). Then, the CPU bus release request signal generator 34 of the extension board 12
The bus release request signal to the CPU 21 is asserted and the CPU 21
Releases the bus 20 and the bus of the flash ROM 22 becomes P
The CI bus bridge 29 can be driven. That is, the access from the host CPU 2 controls the flash ROM 22 as it is.

The host CPU 2 is a flash ROM
22 to execute a rewrite algorithm and write to all address areas (steps S2 and S2).
3). The ROM code data for rewriting is read from the memory card 4 or the like connected to the host CPU bus 1. When the rewriting is completed, the extension board 12 is reset and restarted (steps S4 and S5).

<Second Embodiment> Next, a write process according to a second embodiment will be described with reference to FIG. First,
The flash ROM download mode is set as in the case shown in FIG.
Enable the bridge 29 to drive (step S
11). Next, different from the first embodiment, the flash ROM rewrite control unit 32 controls the flash ROM 22. The flash ROM rewrite control unit 32 erases and writes the flash ROM 22, and the host CPU 2 accesses the flash ROM rewrite control unit 32 with target access to the write data.

However, if the transfer interval from the host CPU 2 is short, writing to the flash ROM 22 cannot be performed correctly.
Data is transferred one word at a time while reading the write completion status information from No. 2 and confirming completion. The flash ROM rewriting control unit 32 stores the data transferred from the host CPU 2 word by word while automatically incrementing the address.
(Steps S12 and S13). When the rewriting is completed, the extension board 12 is reset and restarted (steps S14 and S15).

<Third Embodiment> Next, a write process according to a third embodiment will be described with reference to FIG. First,
The flash ROM download mode is set as in the second embodiment (step S21), and the flash ROM
The bus 22 is driven by the PCI bus bridge 29, and the flash ROM rewriting control unit 32
2 is controlled. However, unlike the second embodiment, the write data in the flash ROM 22 is read from the memory card 4 by the PCI bus bridge 29 acting as a bus master.

The host CPU 2 has a PCI bus bridge 29
The target access is made to the data request generation unit 33 of the above-described manner, and an address in the PCI bus memory space of the memory card 4 is set. The data request generator 33 monitors the write completion status signal of the flash ROM rewrite controller 32,
When writing is completed, the master control unit (initiator control unit 37) is notified of the address of the memory card 4 and requests the next write data. The master controller 37 executes the bus master mode of the PCI bus 11, outputs the address of the memory card 4, and reads data from the memory card 4 (steps S22 and S23). When the rewriting is completed, the extension board is reset and restarted (step S2
4, S25).

[0023]

As described above, according to the first aspect of the present invention, when downloading a program to the flash ROM on the expansion board, the program is downloaded without the intervention of the CPU on the expansion board. It is no longer necessary to store a program for the operation in advance. Also, even if a failure occurs on the way, the system will not stop starting up.

According to the second aspect of the present invention, the PCI bus bridge on the expansion board executes the rewriting algorithm of the flash ROM, so that the host CPU can rewrite only by transferring the ROM code data.

According to the third aspect of the present invention, the PCI bus bridge on the expansion board becomes a bus master of the PCI bus and reads ROM code data to read the flash ROM.
In this case, rewriting can be performed without the intervention of the host CPU.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a digital multifunction peripheral as an embodiment of an electronic apparatus according to the invention.

FIG. 2 is a block diagram showing a detailed configuration of a facsimile board as an example of the extension board of FIG. 1;

FIG. 3 is a block diagram showing a configuration of a PCI bus bridge of FIG. 3 in detail.

FIG. 4 is a flowchart illustrating a flash ROM writing process.

FIG. 5 is a flowchart illustrating a flash ROM writing process according to a second embodiment.

FIG. 6 is a flowchart illustrating a flash ROM writing process according to a third embodiment.

[Explanation of symbols]

 2 Host CPU 10 Host PCI bridge 11 PCI bus 12 Expansion board 21 CPU 22 Flash ROM 29 PCI bus bridge 31 Local bus controller 32 Flash ROM rewrite controller 33 Data request generator 34 CPU bus release request signal generator 35 PCI bus control Unit 36 Config control unit 37 Initiator control unit 38 Target control unit

Claims (3)

[Claims] A PCI bus bridge, a CPU for controlling the expansion board, and a flash ROM for storing an operation program of the CPU are mounted on an expansion board connected to the PCI bus. In an electronic device in which a host CPU controls the expansion board via the PCI bus, a PCI bus bridge on the expansion board requests a CPU on the expansion board to release the bus, and the host CPU controls the flash. Means for controlling a bus to said flash ROM in accordance with an access from said PCI bus so that said ROM can be directly rewritten. 2. An expansion board connected to a PCI bus, on which a PCI bus bridge, a CPU for controlling the expansion board, and a flash ROM for storing an operation program of the CPU are mounted. An electronic device in which a host CPU controls the expansion board via the PCI bus, wherein a PCI bus bridge of the expansion board
Means for executing the OM write algorithm, means for latching write data from the PCI bus, and means for notifying the PCI bus of the flash ROM write status, and the host CPU confirms the status to the PCI bus bridge An electronic device that writes only ROM code data while the PCI bus bridge writes the latched data to a flash ROM. 3. A PCI bus bridge, a CPU controlling the expansion board, and a flash ROM storing an operation program of the CPU are mounted on an expansion board connected to the PCI bus. In an electronic device in which a host CPU controls the expansion board via the PCI bus, a PCI bus bridge of the expansion board has a bus master function of a PCI bus and a unit for latching master read data, and writes data to a flash ROM. PC every time completed
An electronic apparatus wherein a device in a memory space of an I bus serves as a bus master to read data and write a program to a flash ROM.