JP2001100707A - Driving method of electrooptical device, driving circuit, electrooptical device and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To conduct a high quality gradation displaying by binarizing the signals being applied to data lines and to increase the number of gradation regardless of data transfer interval. SOLUTION: In the driving method, data signals, which instruct applications of the voltages that turn on or off each pixel, are successively generated in accordance with gradation data and written into the memory of each pixel in each of plural subfields that are made by dividing one field. At least a data transfer interval is passed, the voltages are applied to each of the pixels in accordance with the data signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a driving method, a driving circuit, an electro-optical device, and an electronic apparatus for an electro-optical device for performing gradation display control by pulse width modulation.

[0002]

2. Description of the Related Art An electro-optical device, for example, a liquid crystal display device using liquid crystal as an electro-optical material is a cathode ray tube (CRT).
It is widely used in display units of various information processing devices, liquid crystal televisions, and the like.

Here, a conventional electro-optical device is, for example,
It is configured as follows. That is, the conventional electro-optical device includes a pixel electrode arranged in a matrix, an element substrate provided with a switching element such as a TFT (Thin Film Transistor) connected to the pixel electrode, and a pixel electrode. It comprises an opposing substrate on which opposing opposing electrodes are formed, and a liquid crystal as an electro-optical material filled between the two substrates. In such a configuration, when a scanning signal is applied to a switching element via a scanning line, the switching element is turned on. In this conductive state, when an image signal of a voltage corresponding to the gradation is applied to the pixel electrode via the data line, a charge corresponding to the voltage of the image signal is applied to the liquid crystal layer between the pixel electrode and the counter electrode. Stored. After the charge storage, even if the switching element is turned off, the charge storage in the liquid crystal layer is maintained by the capacitance of the liquid crystal layer itself, the storage capacitance, and the like. As described above, when the switching elements are driven and the amount of charge to be stored is controlled according to the gradation, the alignment state of the liquid crystal changes for each pixel, so that the density changes for each pixel. Therefore, it is possible to perform gradation display.

[0004] At this time, it is sufficient to accumulate electric charges in the liquid crystal layer of each pixel during a part of the period. First, each scanning line is sequentially selected by a scanning line driving circuit, and secondly,
In the scanning line selection period, the data lines are sequentially selected by the data line driving circuit, and thirdly, the selected data lines are sampled with an image signal of a voltage corresponding to a gray scale. Time-division multiplex driving in which a line is shared by a plurality of pixels becomes possible.

[0005]

However, the image signal applied to the data line is a voltage corresponding to the gradation, that is, an analog signal. For this reason, a peripheral circuit of the electro-optical device requires a D / A conversion circuit, an operational amplifier, and the like, thereby increasing the cost of the entire device. Furthermore, display unevenness occurs due to the characteristics of the D / A conversion circuit and the operational amplifier, and the non-uniformity of various wiring resistances, so that high-quality display is extremely difficult.
This problem is particularly noticeable when performing high-definition display.

The present invention has been made in view of the above circumstances, and has as its object to provide an electro-optical device capable of high-quality and high-definition gradation display, a driving method thereof, a driving circuit thereof, Another object of the present invention is to provide an electronic device using the electro-optical device.

[0007]

In order to achieve the above object, a first aspect of the present invention is to receive grayscale data of each pixel for one screen for each field, and according to the grayscale data,
A driving method of an electro-optical device that performs on / off driving of a plurality of pixels each including a memory, and in each of a plurality of subfields obtained by dividing one field, application of a voltage for turning on or off a pixel. Are sequentially generated in accordance with the grayscale data and written into the memory of each pixel, and at least after a data transfer period, which is a period during which the writing of the data signal is performed to the memories of all the pixels, is performed. And a method for driving an electro-optical device, wherein a voltage corresponding to the data signal is applied to each pixel.

According to the present invention, in one field, the application time of the voltage for turning on (or off) the pixel is pulse width modulated in accordance with the gradation of the pixel.
The gradation display by the effective value control is performed. At this time, in each subfield, it is only necessary to instruct ON or OFF of the pixel. Therefore, a binary signal (that is, a digital signal which can take only H level or L level) is used as the instruction signal to the pixel. Can be. Therefore, in the present invention, since the signal applied to the pixel is a digital signal, display unevenness due to non-uniformity such as element characteristics and wiring resistance is suppressed, and high-quality and high-definition gradation display is possible. Become.

In the present invention, one field is used to mean a period required to form one raster image by performing horizontal scanning and vertical scanning in synchronization with a horizontal scanning signal and a vertical scanning signal. ing.

According to the present invention, at least after a data transfer period has elapsed, either a voltage for turning on the pixel or a voltage for turning off the pixel in accordance with the data signal written to the memory in the pixel Is applied to each pixel. Therefore, the period during which the pixels are turned on and off in accordance with the data signal can be set irrespective of the length of the data transfer period, and a high-gradation image can be displayed.

In the present invention, a data transfer period is defined as a period from the start of writing of the data signal to any pixel to the writing of each data signal to the memory of all pixels for one screen. Means the period.

In one embodiment of the first invention, during the data transfer period in each subfield, the voltage for turning on the pixel or the turning off of the pixel is performed independently of the data signal written in the memory of each pixel. Is applied to each pixel.

According to a second aspect of the present invention, gradation data of each pixel for one screen is received for each field, and according to the gradation data, the gradation data is arranged corresponding to each intersection of a plurality of data lines and a plurality of scanning lines. A driving circuit of an electro-optical device for driving a plurality of pixels each having a memory, wherein scanning is performed to enable application of a voltage from a data line to a pixel in each of a plurality of subfields obtained by dividing one field. A scanning line driving circuit for sequentially supplying a signal to each of the scanning lines; and a data signal for instructing application of a voltage for turning on or off a pixel in each of the plurality of subfields. A data line driving circuit that supplies the data signal to each data line so as to write the data signal to a memory in each pixel while the scanning signal is supplied; In each field, at least,
After a data transfer period, which is a period during which the data signal is written to the memories of all the pixels, each pixel is turned on and off in accordance with the data signal written to the memory of each of the pixels. And a voltage control circuit for controlling a voltage applied to the pixel.

The second invention embodies the first invention as a drive circuit for an electro-optical device, and has the same effects as the first invention.

In one embodiment of the second invention, during the data transfer period in each subfield, the voltage control circuit turns the pixel on or off irrespective of the data signal written in the memory of each pixel. Thus, the voltage applied to each pixel is controlled.

According to a third aspect of the invention, there is provided an electro-optical device having a plurality of pixels provided at respective intersections of a plurality of scanning lines and a plurality of data lines and each including a memory. In each of the divided subfields,
A scanning line driving circuit for sequentially supplying a scanning signal enabling voltage application from a data line to a pixel to each of the scanning lines; and a voltage for turning on or off a pixel in each of the plurality of subfields A data line for sequentially generating a data signal instructing the application of a voltage in accordance with the grayscale data and supplying the data signal to each data line so as to write the data signal to a memory in each pixel while the scanning signal is supplied A driving circuit and, in each of the subfields, at least a data signal written to the memory of each pixel after a lapse of a data transfer period during which the data signal is written to the memory of all pixels. And a voltage control circuit that controls a voltage applied to each pixel so that the pixel is driven on and off in response to the electro-optical device. It is.

The third aspect of the present invention embodies the first aspect of the invention as an electro-optical device, and has the same effects as the first aspect of the invention.

In one embodiment of the third invention, during the data transfer period in each subfield, the voltage control circuit turns the pixel on or off regardless of the data signal written in the memory of each pixel. Thus, the voltage applied to each pixel is controlled.

According to a fourth aspect of the invention, there is provided an electro-optical device having a plurality of pixels which are provided corresponding to respective intersections of a plurality of scanning lines and a plurality of data lines and each have a memory. In each of the divided subfields,
A scanning line driving circuit for sequentially supplying a scanning signal enabling voltage application from a data line to a pixel to each of the scanning lines; and a voltage for turning on or off a pixel in each of the plurality of subfields A data line driving circuit for sequentially generating a data signal instructing the application of a voltage in accordance with the grayscale data, and supplying the data signal to each data line while the scanning signal is supplied; The pixel includes a pixel electrode, a counter electrode facing the pixel electrode,
An electro-optic material sandwiched between the pixel electrode and the counter electrode; a memory for storing a data signal supplied through the data line when a scan signal is supplied through the scan line; and the plurality of sub-fields. In each of the above, at least after a lapse of a data transfer period during which the data signal is written to the memory of all the pixels, one of two types of voltages is applied according to the data signal written to the memory. And a selection circuit for selecting and applying the selected pixel electrode to the pixel electrode.

The fourth invention also embodies the first invention as an electro-optical device, and has the same effects as the first invention.

In one embodiment of the fourth invention, during the data transfer period in each subfield, the pixel selection circuit applies one of two types of voltages irrespective of a data signal written in the memory. Selected and applied to the pixel electrode.

The present invention can be embodied by manufacturing or manufacturing the above-described electro-optical device itself, or by manufacturing or selling the electro-optical device as an electric device provided as a display device.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

<Driving Method of Electro-Optical Device According to the Present Embodiment> First, a driving method of the electro-optical device according to the present embodiment will be described to facilitate understanding of the device according to the present embodiment.

In general, in a liquid crystal device using a liquid crystal as an electro-optical material, the relationship between the effective voltage value applied to the liquid crystal and the relative transmittance (or reflectance) is such that a normally black display is performed when no voltage is applied. Taking the black mode as an example, the relationship is as shown in FIG. Here, the relative transmittance is a value obtained by normalizing the minimum value and the maximum value of the transmitted light amount as 0% and 100%, respectively. As shown in FIG. 6, the transmittance of the liquid crystal is 0% when the applied voltage to the liquid crystal layer is smaller than the threshold value VTH1, but when the applied voltage is not less than the threshold value VTH1 and not more than the saturation voltage VTH2. Increases nonlinearly with applied voltage. The applied voltage is the saturation voltage VTH2
In this case, the transmittance of the liquid crystal maintains a constant value regardless of the applied voltage.

Now, in order to make the transmittance of the liquid crystal intermediate between 0% and 100%, the voltage / voltage shown in FIG.
In the transmittance characteristics, it is necessary to apply an effective voltage to the liquid crystal layer corresponding to the transmittance between the voltage VTH1 and the voltage VTH2. Under the conventional technology, a voltage for obtaining such an intermediate gradation is generated by an analog circuit such as a D / A conversion circuit or an operational amplifier and applied to a pixel electrode.

However, the voltage applied to the pixel electrode by such a driving method is easily affected by variations in analog circuit characteristics, various wiring resistances, and the like. It has been difficult to display high-quality and high-definition gradations.

Therefore, in the electro-optical device according to the present embodiment, the pixels are driven by the following method. In this specification, one field is a time required to form one raster image by performing horizontal scanning and vertical scanning in synchronization with a horizontal scanning signal and a vertical scanning signal.

First, one field is divided into six subfields, and a voltage is applied to the liquid crystal layer in each subfield. In each subfield, the liquid crystal layer
The voltage corresponding to the transmittance of 0% (for example, the voltage V in FIG. 6)
L (= 0 V) or a voltage corresponding to the transmittance of 100% (for example, the voltage VH in FIG. 6) is applied.

At this time, the voltage VH within one field
The sub-field for applying the voltage VH and the sub-field for applying the voltage VL are set so that the ratio between the time during which the voltage is applied and the time when the voltage VL is applied is a ratio corresponding to the gradation data. Determined according to. By doing so, an effective voltage corresponding to the gradation data is applied to the liquid crystal layer, and display with an intermediate gradation between 0% transmittance and 100% transmittance becomes possible.

A: First Embodiment <Electrical Configuration> FIG. 1 is a block diagram showing an electrical configuration of an electro-optical device according to a first embodiment of the present invention. This electro-optical device is a liquid crystal device using liquid crystal as an electro-optical material, in which an element substrate and a counter substrate are adhered with a certain gap therebetween, and a liquid crystal as an electro-optical material is sandwiched in this gap. Has become. In this electro-optical device, a semiconductor substrate is used as an element substrate,
Along with transistors that drive pixels on this element substrate,
A peripheral drive circuit and the like are formed. FIG. 1 shows a configuration of a circuit formed on the element substrate.

As shown in FIG. 1, in the display area 101a on the element substrate, a plurality of scanning lines 112 are arranged in X (row).
The plurality of data lines 114a and 114b are formed to extend in the Y (column) direction. One end of each data line 114b is connected to one adjacent data line 114a via the pixel 110 by the inverter 1
The data lines 114a and 114b are connected to each other via a pair 14c.
The pixels 110 are provided corresponding to the intersections of the scanning lines 112 and the pair of data lines 114a and 114b, and are arranged in a matrix. In this embodiment,
For convenience of explanation, the total number of the scanning lines 112 is m, and the total number of the data lines 114a and 114b is n (m and n are integers of 2 or more), and a matrix-type display of m rows × n columns Although described as an apparatus, the present invention is not limited to this.

In FIG. 1, a timing signal generation circuit 2
00 denotes a vertical scanning signal Vs, a horizontal scanning signal Hs, and a dot clock signal DC supplied from a higher-level device (not shown).
This is a device that generates various timing signals and clock signals according to the LK. The main signals among the signals generated by the timing signal generation circuit 200 are as follows. a. Alternating drive signal LCOM This alternating drive signal LCOM is applied to the opposite electrode 1 of the opposite substrate.
08. In the present embodiment, the AC drive signal LCOM changes from VH to VL (= 0 V) and VL (= 0
From V) to VH, level inversion is repeated for each field. Here, the voltage VH is as described in FIG. For convenience of explanation, the level of the AC drive signal LCOM is simply expressed as VH
In some cases, the VL is simply called an L level. b. Start pulse DY This start pulse is a pulse signal output at the beginning of each subfield obtained by dividing one field into six. c. Clock Signal CLY This clock signal CLY is a signal that defines a horizontal scanning period on the scanning side (Y side). d. Latch Pulse LP The latch pulse LP is a pulse signal output at the beginning of the horizontal scanning period, and is output when the level of the clock signal CLY changes (that is, rises and falls). e. Clock signal CLX This clock signal CLX is a signal defined by a so-called dot clock.

The above is the outline of the main signals generated by the timing signal generation circuit 200.

In FIG. 1, the scanning line driving circuit 130
A so-called Y shift register transfers a start pulse DY supplied at the beginning of a subfield in accordance with a clock signal CLY, and sequentially and exclusively supplies each of the scanning lines 112 with scanning signals G1, G2, G3,. Is to be supplied to

The data line drive circuit 140 sequentially latches n binary signals Ds corresponding to the number of the data lines 114a in a certain horizontal scanning period, and then uses the latched n binary signals Ds in the next horizontal scanning. During the period, the data signals d1, d2, d3,.
.., Dn are supplied all at once. The specific configuration of the data line driving circuit 140 is as shown in FIG.

As shown in FIG. 2, the data line driving circuit 140 includes an X shift register 1410, a first latch circuit 1420, and a second latch circuit 1430. The X shift register 1410 transfers the latch pulse LP supplied at the beginning of the horizontal scanning period in accordance with the clock signal CLX, and outputs the latch signals S1, S2, S3,
.., Sn are sequentially and exclusively supplied. First
Latch circuit 1420 converts the binary signal Ds to the latch signal S
1, S2, S3,..., Sn are sequentially latched at the falling edge. The second latch circuit 1430 outputs the binary signal D latched by the first latch circuit 1420.
s are simultaneously latched at the falling edge of the latch pulse LP, and are supplied to the data lines 114a as data signals d1, d2, d3,..., dn. On the other hand, each data line 114b is connected to the inverter 114
is connected to each data line 114a via the
The data signals d1, d2,
A signal whose level is inverted from d3,..., dn is supplied.

Here, in this specification, from the start of writing of a data signal to any pixel in one subfield to the end of writing of a data signal to all pixels. Is referred to as a “data transfer period”. Specifically, after the output of the first scanning signal G1 (the scanning signal to the scanning line 112 located at the uppermost stage in FIG. 1) from the scanning line driving circuit 130 is started, the last scanning signal Gm (the lowermost stage) is output. The period until the output of the scanning signal (the scanning signal to the located scanning line 112) ends is a period corresponding to the data transfer period. As shown in FIG. 7 (details will be described later), actually, the start time of each subfield (that is, the rising time of the start pulse DY)
And the time when the output of the first scanning signal G1 is started is shifted in time, but for convenience of description, the following description will be given on the assumption that the start point of the data transfer period is the rising point of the start pulse DY.

In the present embodiment, as described above,
One field is divided into six subfields Sf0 to Sf5, and on / off driving of pixels corresponding to 5-bit gradation data is performed in each of these subfields. Here, the time length of each subfield is the sum of the time length of the data transfer period and the time length enough to give an effective voltage having a predetermined weight to the pixel. Hereinafter, a specific time length of each subfield will be described (see FIG. 8). a. The subfield Sf0 is a time length obtained by adding the time length of the data transfer period and the time length capable of applying an effective voltage equivalent to the voltage VTH1 in FIG. 6 to the liquid crystal layer. b. The subfield Sf1 has a time length obtained by adding a time length of the data transfer period and a time length capable of giving an effective voltage corresponding to the weight “1” to the pixel. c. The subfield Sf2 has a time length obtained by adding a time length of the data transfer period and a time length capable of giving an effective voltage corresponding to the weight “2” to the pixel. d. The subfield Sf3 has a time length obtained by adding the time length of the data transfer period and the time length enough to give an effective voltage corresponding to the weight “4” to the pixel. e. The subfield Sf4 has a time length obtained by adding the time length of the data transfer period and the time length capable of giving an effective voltage corresponding to the weight “8” to the pixel. f. The subfield Sf5 has a time length obtained by adding a time length of the data transfer period and a time length capable of giving an effective voltage corresponding to the weight “16” to the pixel.

The time length of each of the subfields Sf0 to Sf5 is selected as described above, and the ratio of the time during which the voltage VH is applied to the time during which the voltage VL is applied within one field depends on the gradation data. The subfield to which the voltage VH is applied and the subfield to which the voltage VL is applied are determined in accordance with the grayscale data so that the above ratio is obtained. Thus, it is possible to display an image of 32 gradations according to the gradation data.

Next, a specific configuration of the pixel 110 will be described with reference to FIG.

The pixel 110 in this embodiment has a memory for storing a 1-bit digital signal in the pixel itself, and a voltage Vo in accordance with the digital signal stored in the memory.
a circuit for selecting n or Voff and applying it to the pixel electrode.

Referring to FIG. 3, inverters 121 and 1
Reference numeral 22 has one output terminal connected to the other input terminal, and forms a 1-bit memory as a whole. Transistors 116a and 116b are switching transistors that are turned on when data is written to the one-bit memory, each drain is connected to each output terminal of inverters 121 and 122, and each gate is scanned. It is connected to the scanning line 112 that supplies the signal Gi. The data line 114a is connected to the source of the transistor 116a, and the data line 114b is connected to the source of the transistor 116b. Here, the signal dj (j = 1 to n) is supplied as it is from the data line driving circuit 140 to the data line 114a, while a signal obtained by inverting the level of the signal dj is supplied to the data line 114b. . The signals on each of these data lines are applied to a memory composed of inverters 121 and 122 via transistors 116a and 116b, and are written into this memory.

The transmission gate 123 has an input terminal connected to a wiring for supplying the voltage Von, and an output terminal connected to the pixel electrode 118. The transmission gate 124 has an input terminal connected to a wiring for supplying the voltage Voff, and an output terminal connected to the pixel electrode 118.
It is connected to the. Each of these transmission gates 123 and 124 is a gate which is turned on when an H level gate signal is applied thereto, and includes inverters 121 and 12 in the above memory.
2 are supplied as gate signals.

Here, the operation of this pixel will be described.

First, an H-level scanning signal Gi is output to the scanning line 112, and the transistors 116a and 116b
Is turned on, an H-level data signal dj is output to the data line 114a, and an L-level signal / dj is output to the data line 114b. In this case, since the output signal of inverter 121 is at H level and the output signal of inverter 122 is at L level, only transmission gate 123 is turned on, and voltage Von is applied to pixel electrode 118 via transmission gate 123. .

Next, the scanning signal Gi for the scanning line 112
Goes low, transistors 116a and 11a
6b is turned off, and inverters 121 and 122 are turned off.
Maintains the previous output signal level. During this time, since only the output signal of the inverter 121 is at the H level, the voltage V
on will be continuously applied to the pixel electrode 118.

Thereafter, the scanning signal G for the scanning line 112
When i becomes H level again and transistors 116a and 116b are turned on, L level data signal dj is applied to data line 114a to generate H level signal /.
Assume that dj is output to the data line 114b.
In this case, since the output signal of inverter 121 is at L level and the output signal of inverter 122 is at H level, only transmission gate 124 is turned on, and voltage Vof is transmitted through transmission gate 124.
f is applied to the pixel electrode 118.

Then, the scanning signal G for the scanning line 112
When i becomes the L level, as described above, the inverter 1
21 and 122 maintain the previous output level as they are, and apply the voltage V
off is continuously applied to the pixel electrode 118.
Thus, since the pixel 110 has a built-in memory,
There is an advantage that a situation in which the voltage applied to the pixel electrode volatilizes due to leakage does not occur.

In the following, for convenience, the data lines 11
4a, the H level data signal is applied to the data line 114.
The state in which the output signal of the inverter 121 is maintained at the H level and the output signal of the inverter 122 is maintained at the L level as a result of the supply of the L level signal ". On the other hand, as a result of the L level data signal being supplied to the data line 114a and the H level signal being supplied to the data line 114b,
When the output signal of inverter 121 is at L level and inverter 1
The state where the output signal of No. 22 is held at the H level is referred to as “the state where the signal of the L level is written in the memory”. That is, when an H-level data signal is output from the data line driving circuit 140, the H-level signal is written in the memory, and the voltage Von is applied to the pixel electrode 118. On the other hand, when an L-level data signal is output from the data line driving circuit 140, the L-level signal is written to the memory, and the voltage Voff is applied to the pixel electrode 118.

In this embodiment, the voltages Von and V applied to the pixel electrode 118 of each pixel are described.
The off level is VL (= 0 V) under a predetermined condition.
And VH. In FIG. 1, the voltage control circuit 160 controls these voltages Vo
This is for controlling the levels of n and Voff. Specifically, the voltage control circuit 160 receives the voltages VH and VL, the data transfer signal DT indicating the data transfer period, and the AC drive signal LCOM, and outputs H according to each of these signals. Voltage Von set to level (= VH) or L level (= VL = 0V)
And Voff are output. Here, the data transfer signal DT is a signal indicating whether or not it is a data transfer period and is generated by the timing signal generation circuit 200. Specifically, for example, the start pulse DY
Rise at the same time as the rise of the scanning signal G
This is a pulse signal that falls simultaneously with the fall of m (see FIG. 4).

Hereinafter, referring to FIG.
How the levels of voltages Von and Voff change as a result of the control by 0 will be described. In the following, a description will be given of a change in a data transfer period in a subfield and a level in a period after the data transfer period has elapsed (hereinafter, referred to as a “non-transfer period”).
In the following, for convenience of description, the voltages Von and Vo
Regarding the level of ff, VH is simply called H level,
VL may be simply referred to as L level. a. During the data transfer period During the data transfer period, the voltage control circuit 160
Regardless of the signal written to the memory in the pixel, the voltages Von and V
The level of off is switched. Specifically, during the data transfer period in the field where the AC drive signal LCOM is at the H level, both the voltages Von and Voff are at the H level, while the data transfer in the field where the AC drive signal LCOM is at the L level. During the period, the voltage Vo
Both n and Voff are at the L level. That is, regardless of which of the voltages Von and Voff is applied to the pixel electrode 118 according to the signal written in the memory,
Since the level difference between the AC drive signal LCOM and the voltage applied to the pixel electrode 118 is 0 V, the pixel is turned off. b. Within the non-transfer period After the elapse of the data transfer period, that is, within the non-transfer period, a voltage for driving the pixel on and off is applied to the pixel in accordance with the signal written to the memory in the pixel during the immediately preceding data transfer period. Voltage Von and Vo
The level of ff is determined. Specifically, in a field where the AC drive signal LCOM is at the H level, Vo
While n is set to L level and Voff is set to H level, Von is set to H level and Voff is set to L level in a field where the AC drive signal LCOM is at L level.
As a result, the signal written to the memory in the pixel 110 becomes H
Level (that is, the voltage V
When “on” is applied, a voltage for turning on the pixel 110 is applied, and when the signal written to the memory in the pixel 110 is at the L level (ie, the voltage Voff is applied to the pixel electrode 118). In this case, a voltage for turning off the pixel is applied.

As described above, in the present embodiment, the pixels are always turned off during the data transfer period irrespective of the signal written in the memory, and after the data transfer period, the pixels are turned off during the data transfer period. The pixel is driven to be turned on and off by a signal corresponding to the signal written in the memory.

Next, the data conversion circuit 300 shown in FIG.
Is for generating a binary signal Ds for instructing on / off driving of the pixel from the 5-bit grayscale data corresponding to each pixel in each subfield. FIG. 5 shows the relationship between the subfield number and gradation data and the binary signal Ds. The data conversion circuit 300 holds a table as shown in the figure in an internal memory, and this memory is provided with a subfield number and gradation data as an address. As a result, the data conversion circuit 300 outputs a binary signal Ds corresponding to the subfield number and the gradation data.

Here, the subfield number is the number of each subfield in one field, and is "0".
To any one of values up to “5”. There are various methods for generating the subfield number. For example, a counter is provided which counts the start pulse DY and resets the counting result by a level transition (rising and falling) of the AC drive signal LCOM. The count value obtained from this counter may be used as a subfield number. Data conversion circuit 30
0 indicates that the on / off data corresponding to the combination of the subfield number and the gradation data thus obtained is 2
It is output as a value signal Ds.

Here, the H-level binary signal Ds has the effect of applying the voltage Von to the pixel electrode 118 in the pixel, and the L-level binary signal Ds has the effect of applying the voltage Von to the pixel electrode 11 in the pixel.
8 has the effect of applying the voltage Voff. For example, an H-level signal Ds is output from the data conversion circuit 300, and as a result, any of the data lines 114
If an H-level data signal is output to a, the H-level signal is written to the memory, and the pixel electrode 11
8, the voltage Von is applied. As illustrated in FIG. 5, when the gradation data is 00000, the L-level binary signal Ds is output in all the subfields. As a result, the voltage Voff is applied to the pixel electrode 118 of the pixel in all subfields. When the gradation data is 00001, the H-level binary signal Ds is output in the subfields Sf0 and Sf1, while the L-level binary signal Ds is output in the other subfields. As a result, the pixel electrode 118 of the pixel
In subfields Sf0 and Sf1, voltage Von
Is applied, while the voltage Voff is applied in the subfields Sf2 to Sf5.

As shown in FIG. 5, in the subfield Sf0, when the gradation data is equal to or more than 00001, the H-level binary signal Ds is output regardless of the gradation data. This is because, as described above, in order to apply an effective voltage equivalent to the voltage VTH1 in FIG.
0 is output.

Since the binary signal Ds generated in the data conversion circuit 300 needs to be output in synchronization with the operation of the scanning line driving circuit 130 and the data line driving circuit 140, as shown in FIG. The circuit 300 is supplied with a start pulse DY, a clock signal CLY synchronized with horizontal scanning, a latch pulse LP defining the beginning of a horizontal scanning period, and a clock signal CLX corresponding to a dot clock signal. Has become.

<Operation> Next, the operation of the electro-optical device according to the above-described embodiment will be described. FIG. 7 is a timing chart showing the operation of the electro-optical device.

First, the AC drive signal LCOM is inverted for each field (1f) and applied to the counter electrode 108. On the other hand, the start pulse DY is output from the timing signal generation circuit 200 at the start timing of each subfield.

Here, in one field in which the AC drive signal LCOM becomes H level, the subfield Sf0
Is supplied, the start pulse DY defining the start of
By the transfer according to the clock signal CLY in the scanning line driving circuit 130 (see FIG. 1), the scanning signals G1, G2,
, Gm are sequentially and exclusively output. FIG.
As shown in (1), the data transfer period is set to a period shorter than the shortest subfield.

Now, the scanning signals G1, G2, G3,.
m has a pulse width corresponding to a half cycle of the clock signal CLY, and the first scanning line 1 counted from the top.
The scanning signal G1 corresponding to 12 is output with a delay of at least a half cycle of the clock signal CLY after the clock signal CLY first rises after the start pulse DY is supplied. Therefore, one shot (G) of the latch pulse LP is supplied after the start pulse DY is supplied at the beginning of the subfield and before the scanning signal G1 is output.
0) is supplied to the data line drive circuit 140.

The case where one shot (G0) of the latch pulse LP is supplied will be examined. First, when one shot (G0) of the latch pulse LP is supplied to the data line driving circuit 140, the data line driving circuit 140 (see FIG. 2) transfers the latch signals S1, S2, S3, ..., S
n are sequentially and exclusively output during the horizontal scanning period (1H).
Each of the latch signals S1, S2, S3,..., Sn has a pulse width corresponding to a half cycle of the clock signal CLX.

At this time, the first latch circuit 1 shown in FIG.
420 latches the binary signal Ds to the pixel 110 corresponding to the intersection of the first scanning line 112 counted from the top and the first data line 114a counted from the left at the falling of the latch signal S1. Next, at the falling of the latch signal S2, the first scanning line 112 counted from the top
, The binary signal Ds to the pixel 110 corresponding to the intersection with the second data line 114a counted from the left is latched. Similarly, the first scanning line 112 counted from the top and the left are counted from the left. Then, the binary signal Ds to each pixel 110 corresponding to each intersection with the nth data line 114a is sequentially latched.

As a result, first, in FIG.
2 for one row of pixels corresponding to the intersection with the actual scan line 112
The value signal Ds is latched point-sequentially by the first latch circuit 1420. The data conversion circuit 3
00 indicates that the grayscale data of each pixel is converted into a binary signal Ds in accordance with the timing of latching by the first latch circuit 1420.
And output. This conversion is performed according to the truth table shown in FIG.

Next, when the clock signal CLY falls and the scanning signal G1 is output, the first scanning line 112 counted from the top in FIG. All the transistors 116 of the corresponding pixel 110 are turned on. On the other hand, the falling edge of the clock signal CLY outputs the latch pulse LP. Then, at the falling timing of the latch pulse LP, the second latch circuit 1430 performs dot-sequential latching by the first latch circuit 1420 in a dot-sequential manner.
The value signal Ds is simultaneously supplied to each of the corresponding data lines 114a as data signals d1, d2, d3,..., Dn. At this time, a signal obtained by level inverting the data signal is supplied to each of the data lines 114b. By this operation,
Writing of each data signal to the memory in each pixel 110 in the first row counted from the top is performed simultaneously.

In parallel with this writing, a binary signal Ds for one row of pixels corresponding to the intersection with the second scanning line 112 from the top in FIG. Is done.

On the other hand, the voltage control circuit 160 controls the voltage values of the voltages Von and Voff as illustrated in FIG. Here, since it is assumed that the AC drive signal LCOM is at the H level, both Von and Voff are set to the H level during the data transfer period, and Von is set to the L level during the non-transfer period.
Voff is set to the H level.

Thereafter, a similar operation is performed for the m-th scanning line 112.
Is repeated until the scanning signal Gm corresponding to the is output. That is, during one horizontal scanning period (1H) in which a certain scanning signal Gi (i is an integer satisfying 1 ≦ i ≦ m) is output, data for one row of pixels 110 corresponding to the i-th scanning line 112 is provided. Writing the signals d1 to dn and (i
+1) Point-sequential latching of the binary signal Ds for one row of the pixels 110 corresponding to the first scanning line 112 is performed in parallel. The data signal written in the memory in the pixel 110 is held until a new data signal is written in the next subfield.

Further, even when the field is switched and the AC drive signal LCOM is inverted to L level, the same operation is repeated in each subfield. However, as shown in FIG. 4, the voltage control circuit 160 controls the voltages Von and Vof during the data transfer period.
Both f are set to L level, and in the non-transfer period, switching is performed so that the voltage Von is set to H level and Voff is set to L level.

Next, as a result of such an operation, a voltage applied to the liquid crystal layer in the pixel 110 will be examined. FIG. 8 is a timing chart showing the gradation data and the waveform applied to the pixel electrode 118 in the pixel 110.

As shown in FIG. 8, during the data transfer period in each subfield (the hatched section in FIG. 8), a data signal of any level is written to the memory in each pixel. Voltage is applied to turn off the pixel. For example, during a data transfer period in a field where the AC drive signal LCOM is at the H level, the voltage control circuit 160 controls the voltage Von.
And Voff are both set to H level. Therefore, in this period, no matter what level of signal is written to the memory in the pixel (that is, whether any of the voltages Von and Voff is applied to the pixel). ), The pixel is turned off.
On the other hand, during the non-transfer period, the voltage control circuit 16
By 0, the voltage Von is set to the L level and Voff is set to the H level. Therefore, when an H-level signal is stored in the memory in the pixel 110 (that is, when the voltage Von is applied to the pixel electrode 118), the pixel is turned on, while the L-level is stored in the memory in the pixel. Is stored (that is, when the voltage Voff is applied to the pixel electrode 118), the pixel is turned off.

For example, when the AC drive signal LCOM is at the H level and the gradation data of a certain pixel is 00000, as a result of following the table shown in FIG. 5, all the subfields Sf0 are stored in the memory in the pixel. An L level signal is written over Sf5. In this case, the voltage Voff (VH) is applied to the pixel electrode 118 in all the subfields, not only during the data transfer period but also during the non-transfer period during the non-transfer period. As a result, the effective value of the voltage applied to the liquid crystal layer in one field is 0V. Therefore, the transmittance of the pixel is 0% corresponding to the gradation data 00000.

When the gradation data of a certain pixel is 00001,
, The result in accordance with the table shown in FIG. 5 indicates that the subfields Sf0 and Sf1 are stored in the memory in the pixel.
, An H level signal is written, while an L level signal is written in other subfields. As a result, the voltage Von is applied to the pixel electrode 118 in the subfields Sf0 and Sf1 (data transfer period and non-transfer period). However, during the data transfer period, the level difference between the AC drive signal LCOM and the voltage Von applied to the pixel electrode 118 is 0 V
, The pixel is turned off. On the other hand, in the non-transfer period, since the level of the voltage Von is inverted (becomes L level), a voltage for turning on the pixel is applied to the pixel electrode 118. In the subfields Sf2 to Sf5, a voltage for turning off the pixels is applied in both the data transfer period and the non-transfer period. As a result, the gradation data 0
An effective voltage corresponding to 0001 is applied to the pixel, and a transmittance corresponding to the gradation data is obtained.

Further, the gradation data of a certain pixel is 0001
When it is 0, as a result according to the table shown in FIG. 5, the subfields Sf0 and Sf2 are stored in the memory in the pixel.
, An H level signal is written, while an L level signal is written in other subfields. As a result, in the subfields Sf0 and Sf2, the voltage Von is applied to the pixel electrode 118. For the same reason as described above, the pixel is turned off during the data transfer period, while being turned off during the non-transfer period. Turns on the pixel. In the subfields Sf1 and Sf3 to Sf5, a voltage for turning off the pixel is applied. As a result, an effective voltage corresponding to the gradation data 00010 is applied to the pixel, and a transmittance corresponding to the gradation data is obtained.

The same applies to the case where another gradation data is given. As a result, the pixels are turned on during the non-transfer period in the number of subfields corresponding to the gradation data, and as a result, the transmittance corresponding to the gradation data is obtained. Is obtained.

Next, when the AC drive signal LCOM becomes L level, a voltage obtained by inverting the voltage applied in the case of H level is applied to the pixel electrode 118. For this reason, the voltage applied to each liquid crystal layer when the AC drive signal LCOM is at the H level has a polarity inverted from the applied voltage when the AC drive signal LCOM is at the L level, and Their absolute values are equal. Therefore, a situation in which a DC component is applied to the liquid crystal layer is avoided, so that deterioration of the liquid crystal is prevented.

According to the electro-optical device according to this embodiment, one field includes a plurality of subfields Sf0.
~ Sf5, and the H
The level or the L level is written, and the effective voltage value in one field is controlled. Therefore, the data line 114
Since the data signals supplied to a and 114b are only at H level or L level and are binary, a peripheral circuit such as a driving circuit may use a high-precision D / A conversion circuit or an operational amplifier. Further, a circuit for processing an analog signal becomes unnecessary. Therefore, the circuit configuration is greatly simplified, and the cost of the entire device can be reduced.

Further, data lines 114a and 114b
Since the data signals (dj and / dj) supplied to are binary, display unevenness due to non-uniformity such as element characteristics and wiring resistance does not occur in principle. Therefore, according to the electro-optical device according to the present embodiment, high-quality and high-definition gradation display can be performed.

In this embodiment, in each of the plurality of subfields, a voltage corresponding to a signal written to the memory after the elapse of the data transfer period is applied to the pixel electrode 1.
18. For this reason, in each sub-field, immediately after a data signal is supplied to each pixel, a voltage corresponding to the data signal is applied to each pixel without distinction between a data transfer period and a non-transfer period with respect to application of a voltage to each pixel. Is applied to the pixel electrode (hereinafter, referred to as a driving method).
There are the following advantages as compared with "another driving method").

FIG. 9A is a timing chart showing the relationship between each subfield, the data transfer period, and the voltage application period when the above-mentioned other driving method is used. In the other driving method, when a data signal dj is supplied to a certain pixel, a voltage corresponding to the data signal dj is immediately applied to the pixel electrode as shown as a “voltage application period” in FIG. This voltage is maintained until a new data signal dj + 1 is supplied in the next subfield. Note that in FIG. 9A, immediately after the start pulse DY is output (that is,
Since a pixel to which a data signal is supplied immediately after the start of the data transfer period) is shown as an example, a voltage is applied immediately after the start of the subfield. Of course, for example, in the pixel to which the data signal is supplied at the end of one screen (that is, the pixel to which the data signal is supplied at the end of the data transfer period), the voltage application period starts from the end of the data transfer period. Becomes

Here, the case where the number of displayable gradations is increased in such a method will be examined.

In order to increase the number of displayable gradations,
It is necessary to increase the types (number) of effective voltage values that can be applied to pixels. For this purpose, a subfield that can provide a smaller effective voltage to the pixel must be provided. In other words, it is necessary to provide a subfield in which the voltage is applied to the pixel for a shorter time (= which can give a small effective value of the voltage).

However, in the case of the method shown in FIG.
The time length of each subfield cannot be shorter than the time length of the data transfer period. In other words, the time length of the voltage application period cannot be shorter than the data transfer period. As a result, the time length of one subfield is reduced, and an effective voltage smaller than the effective voltage that can be applied when the time length of the voltage application time is equal to the time length of the data transfer period is applied to the pixel. Can not do it. Here, if the data transfer period can be shortened, the voltage application period in one subfield can be further shortened, so that the number of gradations can be increased. There is a limit to shortening the period. After all, in the other driving methods described above, there is a limit to the multi-gradation of the image display.

On the other hand, in the present embodiment, FIG.
As shown in (b), the pixels are turned on or off in accordance with a signal written in the memory after the elapse of the data transfer period. Note that in FIG. 9B, the “voltage application period” is a period in which a voltage for turning on or off a pixel is applied in accordance with a signal written in the memory.
This is a period corresponding to the “non-transfer period” in the above embodiment.

As described above, in order to increase the number of gradations, a subfield that can give a smaller effective voltage value to a pixel, that is, a subfield in which a voltage is applied to a pixel for a shorter time, is provided. There is a need. Here, in the other methods described above, there is a restriction that the time length of the voltage application period cannot be shorter than the time length of the data transfer period. However, according to the method according to the present embodiment, the time length of the voltage application time is reduced. Can be freely set regardless of the time length of the data transfer period. That is, it is possible to provide a subfield capable of giving a very small effective voltage.

As described above, according to the method according to the present embodiment, regardless of the time length of the data transfer period, the non-transfer period, that is, the period during which a voltage corresponding to the data signal is applied to each pixel. Can be set arbitrarily.
As a result, by shortening the voltage application period (non-transfer period), there is an advantage that it is possible to realize multiple gradations of image display. In other words, even when performing multi-gradation display, a high-performance drive circuit with a short data transfer period is not required.

B: Second Embodiment Next, a second embodiment of the present invention will be described. In addition,
The overall configuration of the present embodiment is the same as the configuration of the first embodiment shown in FIG. 1 described above, and a description thereof will be omitted.

In the first embodiment, the voltage control circuit 160 for switching the levels of the voltages Von and Voff between the data transfer period and the non-transfer period is provided.
In the data transfer period, a voltage for turning off the pixel is applied regardless of which signal is written to the memory. On the other hand, in the present embodiment, this function is realized by a circuit provided in the pixel.

FIG. 10 is a diagram showing a configuration of the pixel 110 in the electro-optical device according to the present embodiment. FIG.
At 0, the same reference numerals as in FIG. 3 denote the same parts as those in FIG. 3, and a detailed description thereof will be omitted.

As shown in FIG. 10, the pixel 110 in this embodiment is provided with a NAND gate 125. One input terminal of the NAND gate 125 is connected to the output terminal of the inverter 121, and receives the signal written in the memory. The NAND gate 12
A signal / DT obtained by inverting the level of the data transfer signal DT is input to the other input terminal of the input terminal 5. NA
A transmission gate 124 and an inverter 126 are connected in parallel to an output terminal of the ND gate 125, and a transmission gate 123 is connected to an output terminal of the inverter 126.

These transmission gates 123
And 124 are gates which are turned on when an H level gate signal is applied. Specifically, the transmission gate 124 has the NAN
An output signal of the D gate 125 is supplied as a gate signal, and a signal obtained by inverting the output signal of the NAND gate 125 via an inverter 126 is supplied to the transmission gate 123 as a gate signal.

In the first embodiment, the voltage control circuit 160 switches the levels of the voltages Von and Voff in accordance with the switching between the data transfer period and the non-transfer period in each subfield. On the other hand, in the present embodiment, as shown in FIG.
The voltage control circuit 160 operates so that the voltage Voff is at the same level as the AC drive signal LCOM, while the voltage Von is a level signal obtained by inverting the AC drive signal LCOM.

Next, a voltage applied to the pixel electrode 118 in the pixel 110 will be described with reference to FIGS. In the following, a description will be given separately for a data transfer period and a non-transfer period. a. Data Transfer Period During the data transfer period, the data transfer signal DT goes high, so that the signal / DT input to one input terminal of the NAND gate 125 goes low (see FIG. 11). As a result, the H level signal is output from the NAND gate 125 regardless of which level signal is input to the other input terminal (that is, the input terminal connected to the inverter 121). Therefore, only the transmission gate 124 is turned on, so that the voltage Voff is applied to the pixel electrode 118. Here, FIG.
As shown in FIG. 1, in this embodiment, the voltage Voff
Are at the same level as the AC drive signal LCOM, the pixel is turned off during the data transfer period regardless of which level signal is being written to the memory. b. Non-Transfer Period In the non-transfer period, that is, in the hatched section in FIG. 11, the pixel electrode 1 is turned on in accordance with the signal written in the memory.
A voltage Von or Voff is applied to the pixel 18 to drive the pixel on and off. The details are as follows.

In the non-transfer period, the data transfer signal D
Since T goes low, the signal / DT input to one input terminal of the NAND gate 125 goes high (see FIG. 11). As a result, a signal obtained by inverting the output signal of the inverter 121 is output from the NAND gate 125. Specifically, in the data transfer period immediately before the non-transfer period, when an H-level signal is written to the memory (that is, the output signal of the inverter 121 is at the H level and the output signal of the inverter 122 is at the L level). If the signal is held), an L-level signal is output from the NAND gate 125. As a result, only the transmission gate 123 is turned on, so that the voltage Von is applied to the pixel electrode 118. Here, as shown in FIG. 11, the voltage Von is at a level opposite to that of the AC drive signal LCOM, so that the pixel is turned on.

On the other hand, when an L-level signal is written in the memory (ie, when the output signal of inverter 121 is at the L level and the output signal of inverter 122 is at the H level), NAND gate 125 outputs An H level signal is output. As a result, only the transmission gate 124 is turned on, so that the voltage Voff is applied to the pixel electrode 118. As described above, since the voltage Voff is equal to the level of the AC drive voltage LCOM, the pixel is turned off.

As described above, in this embodiment, the pixels are always turned off during the data transfer period,
The pixels are turned on / off according to the signal written to the memory after the elapse of the data transfer period. As a result, the relationship between the gradation data and the voltage applied to the pixel electrode 118 when the gradation data is given is the same as that illustrated in FIG. 8 illustrated in the first embodiment.

As described above, according to the present embodiment, the same effects as those of the first embodiment can be obtained. Further, in the above embodiment, the voltage V is repeatedly set within one field in synchronization with the switching between the data transfer period and the non-transfer period.
Although it is necessary to switch the levels of on and Voff, according to the present embodiment, it is not necessary to switch the levels of the voltages Von and Voff within one field, so that the power consumption is suppressed to be lower than in the above embodiment. There is an advantage that can be.

C: Modifications Although the embodiment of the present invention has been described above, the above embodiment is merely an example, and various modifications may be made to the above embodiment without departing from the spirit of the present invention. Can be. For example, the following modifications can be considered.

<Modification 1> (1) First Mode In the first embodiment, the pixels are always turned off during the data transfer period. However, the pixels are always turned on during the data transfer period. You may. Less than,
Referring to FIG. 12, voltages Von and Vof in this case are shown.
The change of f will be described. Note that the voltage Von in this embodiment is
The state of the level change of Voff and Voff is shown in part (a) of FIG. a. During the data transfer period During the data transfer period, the voltage control circuit 160
Regardless of the signal written to the memory in the pixel, the voltages Von and V
The level of off is switched. Specifically, in a field where the AC drive signal LCOM is at the H level, both the voltages Von and Voff are set to the L level, while in a field where the AC drive signal LCOM is at the L level, both the voltages Von and Voff are set to the H level. Level. As a result, in the data transfer period, the pixel is turned on regardless of which of the voltages Von and Voff is applied to the pixel electrode 118 in accordance with the signal written in the memory. b. Within the non-transfer period During the non-transfer period, the voltage control circuit 160 switches the voltages Von and Voff such that a voltage for driving the pixel on and off is applied to the pixel in accordance with the signal written in the memory. . Specifically, the AC drive signal LC
In the field where OM is at the H level, the voltage Von
To the L level and the voltage Voff to the H level, while in the field where the AC drive signal LCOM is the L level, the voltage Von is set to the H level and the voltage Voff is set to the L level. As a result, the pixel is turned on and off in accordance with the signal written to the memory in the pixel.

In this embodiment, since the pixels are forcibly turned on during the data transfer period, the effective voltage value in each data transfer period in one field is equal to or lower than the voltage VTH1 shown in FIG. It is necessary to select the length of the data transfer period and the like so that the data transfer time is also reduced. Here, when the effective voltage value in the data transfer period in one field is set to be equal to the voltage VTH1, the subfield Sf in the first embodiment is set.
It is not necessary to provide 0 (a subfield set to a time length long enough to apply an effective voltage corresponding to the voltage VTH1 to the pixel). On the other hand, when the effective voltage value in the data transfer period within one field is set to be smaller than the voltage VTH1, the voltage corresponding to the difference between the voltage VTH1 and the effective voltage value is set in the subfield Sf0 in the pixel. Since it only needs to be given to the electrodes, the subfield S
The time length of f0 can be further reduced.

(2) Second Mode In the first embodiment, the pixels are always turned off during the data transfer period. In the first mode, the pixels are always turned on during the data transfer period. However, the pixels may be turned on or off for each data transfer period in each subfield. That is, for example, in one field, the subfield S
The pixels may be turned on during the data transfer period in f0 to Sf2, and may be turned off during the data transfer period in subfields Sf3 to Sf5. FIG. 12B shows how the levels of the voltages Von and Voff change in this case.

When the AC drive signal LCOM is at the H level, as shown in FIG.
2 during the data transfer period, the voltages Von, Vof
Both f are set to L level. Therefore, during the data transfer period in the subfields Sf0 to Sf2, the pixel is turned on regardless of the level of the signal written in the memory in the pixel. Similarly, when the AC drive signal LCOM is at the H level, the sub-field Sf3
During the data transfer period within Sf5 to Sf5, the voltages Von,
Both Voff are set to the H level. Therefore, during the data transfer period in the subfields Sf3 to Sf5, the pixel is turned off regardless of the level of the signal written to the memory in the pixel. On the other hand, when the AC drive signal LCOM is switched to the L level, both the voltages Von and Voff are set to the H level during the data transfer period in the subfields Sf0 to Sf2. On the other hand, in the data transfer period in the subfields Sf3 to Sf5, since the voltages Von and Voff are both set to the L level, the pixel is turned off in that period. It is to be noted that the pixels are turned on and off in response to the signal written to the memory during the non-transfer period, as in the above embodiments.

According to this aspect, for example, by appropriately selecting a subfield for turning off the pixel in the data transfer period and a subfield for turning on the pixel in the data transfer period, At the voltage VTH1 described above.
The value can be adjusted so as to be equal to (or close to). In such a case, subfield Sf0 for providing an effective voltage corresponding to voltage VTH1 is provided.
Need not be included in one field. In addition,
In the example described above, the continuous subfield Sf0
To Sf2 and subfields Sf3 to Sf5,
Although the pixels are turned on or off during the data transfer period, the present invention is not limited to this. For example, the subfield Sf
The pixel is turned on or off during the data transfer period, such as turning on the pixel during the data transfer period within 0, Sf2 and Sf4, and turning off the pixel during the data transfer period within the subfields Sf1, Sf3 and Sf5. It goes without saying that the subfields to be turned off may not be continuous.

(3) Third Aspect If the configuration of the pixel in the second embodiment is changed to that shown in FIG. 13, the pixel is always turned on during the data transfer period as in the first aspect. It can be. In addition, in the respective units illustrated in FIG. 13, the same units as those in FIG. 10 illustrated in the second embodiment are denoted by the same reference numerals, and description thereof is omitted.

As shown in the figure, the pixel 110 in this modification is different from the pixel 110 shown in FIG.
The way of connecting the NAND gate 125 and the inverter 126 is different. Specifically, one input terminal of the NAND gate 125 is connected to the output terminal of the inverter 122, and receives the signal written in the memory. Also,
A signal / DT obtained by inverting the level of the data transfer signal DT is input to the other input terminal of the NAND gate 125. On the other hand, the output terminal of the NAND gate 125 is connected to the transmission gate 123 and the inverter 126. The output terminal of the inverter 126 is connected to the transmission gate 124.

Next, a specific change in each signal in this embodiment will be described. a. Data Transfer Period During the data transfer period, the data transfer signal DT goes high, so that the signal / DT input to one input terminal of the NAND gate 125 goes low. As a result,
Regardless of which level signal is input to the other input terminal (that is, the input terminal connected to the inverter 122), the H level signal is output from the NAND gate 125. As a result, only the transmission gate 123 is turned on, so that the voltage V
on is applied. Here, since the voltage Von is obtained by inverting the level of the AC drive signal LCOM, during the data transfer period, the pixel is turned on irrespective of the signal of which level is written in the memory. Become. b. Non-Transfer Period During the non-transfer period, since the data transfer signal DT is at L level, the signal / DT input to one input terminal of the NAND gate 125 is at H level. As a result, N
The output signal from the AND gate 125 is
2 is a signal obtained by inverting the level of the output signal. Specifically, in the data transfer period immediately before the non-transfer period,
When an H-level signal is written to the memory (ie,
The output signal of the inverter 121 is at the H level,
22 is held at L level), N
An H-level signal is output from AND gate 125. As a result, only the transmission gate 123 is turned on, so that the voltage Von is applied to the pixel electrode 118. Here, as shown in FIG. 11, the voltage Von is at a level obtained by inverting the AC drive signal LCOM, so that the pixel is turned on. On the other hand, L
When a level signal is written (that is, when the output signal of inverter 121 is held at the L level and the output signal of inverter 122 is held at the H level), a signal at the L level is output from NAND gate 125. . As a result, only the transmission gate 124 to which the H-level signal is supplied via the inverter 126 is turned on, so that the voltage Voff is applied to the pixel electrode 118. Since the voltage Voff is at the same level as the AC drive signal LCOM, the pixel is turned off.

As described above, in this embodiment, the pixels are always turned on during the data transfer period, and are turned on / off according to the signal written to the memory during the non-transfer period. Become. The effective voltage value during the data transfer period in one field is:
What is necessary is just to set under conditions similar to the conditions shown in the said 1st aspect.

As described in each of the above embodiments and this modification, the pixels may be turned on or off during the data transfer period. In short, in one subfield, pixels are turned on and off during the data transfer period irrespective of the signal written to the memory, but are written to the memory during the data transfer period only after the elapse of the data transfer period. If the voltage corresponding to the input signal is applied to the pixel, the first
The effects shown in the embodiment can be obtained.

<Modification 2> In each of the above embodiments,
Since the effective voltage applied to the pixel in each subfield is differently weighted, the time length of each subfield is different, but the time length of each subfield is not limited to this. For example, one field is divided into 32 subfields Sf0 to Sf31, and the time lengths of the subfields Sf1 to Sf31 other than the subfield Sf0 (subfield for applying a voltage effective value corresponding to the voltage VTH1) are made the same. Is also good. FIG. 14 is a table exemplifying the relationship between the subfield number and gradation data and the binary signal Ds in this case. The data conversion circuit 300 outputs a binary signal Ds corresponding to the gradation data according to the table shown in FIG. 3, and the data line driving circuit 140 supplies the binary signal as a data signal to each pixel. Then, in each subfield, the pixel is turned off during the data transfer period (the pixel may be turned on as described in the first modification), and the pixel is driven on and off according to a signal written in the memory after the elapse of the data transfer period. What should I do? Even if you do this,
The same effects as in the above embodiments can be obtained.

<Overall Configuration of Liquid Crystal Device> Next, with respect to the structure of the electro-optical device according to the above-described embodiment and application,
This will be described with reference to FIGS. Here, FIG.
5 is a plan view showing the configuration of the electro-optical device 100,
FIG. 16 is a sectional view taken along line AA ′ in FIG.

As shown in these figures, the electro-optical device 100 includes an element substrate 101 on which a pixel electrode 118 and the like are formed, and a counter substrate 1 on which a counter electrode 108 and the like are formed.
02 are bonded to each other with a certain gap therebetween by a sealant 104, and a liquid crystal 105 as an electro-optical material is sandwiched in this gap. Actually, the sealing material 104 has a cutout portion, and after the liquid crystal 105 is sealed through the cutout portion, it is sealed with a sealing material, but is omitted in these drawings.

The element substrate 101 is opaque because it is a semiconductor substrate as described above. Therefore, the pixel electrode 118 is formed of a reflective metal such as aluminum, and the electro-optical device 100 is used as a reflective type. On the other hand, the counter substrate 102 is transparent because it is made of glass or the like.

On the element substrate 101, a light-shielding film 106 is provided inside the sealant 104 and outside the display area 101a. In the region where the light-shielding film 106 is formed, the scanning line driving circuit 130 is formed in the region 130a, and the data line driving circuit 140 is formed in the region 140a. That is, the light shielding film 10
Numeral 6 prevents light from entering a drive circuit formed in this region. This light-shielding film 106 has a counter electrode 10
8 together with the AC drive signal LCOM. For this reason, in the region where the light-shielding film 106 is formed, the voltage applied to the liquid crystal layer becomes substantially zero, and the display state is the same as the state where no voltage is applied to the pixel electrode 118.

In the element substrate 101, a plurality of connection terminals are formed outside the region 140a where the data line driving circuit 140 is formed and separated from the sealing material 104 by external control. It is configured to input signals and power.

On the other hand, the counter electrode 108 of the counter substrate 102
Is electrically connected to the light-shielding film 106 and the connection terminals of the element substrate 101 by a conductive material (not shown) provided in at least one of the four corners of the substrate bonding portion. That is, the AC drive signal LCOM is applied to the light-shielding film 106 via the connection terminal provided on the element substrate 101 and further to the counter electrode 108 via the conductive material.

In addition, depending on the use of the electro-optical device 100, for example, first, in the case of a direct-view type, first, color filters arranged in a stripe shape, a mosaic shape, a triangle shape, or the like are provided on the counter substrate 102. Second, a light-shielding film (black matrix) made of, for example, a metal material or a resin is provided. In the case of color light modulation, for example, when used as a light valve of a projector described later, no color filter is formed. In the case of a direct-view type, a front light for irradiating the electro-optical device 100 with light from the counter substrate 102 side is provided as necessary. In addition, the element substrate 101 and the counter substrate 1
On the electrode forming surface 02, an alignment film (not shown) rubbed in a predetermined direction is provided to define the alignment direction of the liquid crystal molecules when no voltage is applied. Is provided with a polarizer (not shown) according to the orientation direction. However, when a polymer-dispersed liquid crystal in which fine particles are dispersed in a polymer is used as the liquid crystal 105, the above-described alignment film and polarizer are not required, and the light use efficiency is increased. This is advantageous in terms of low power consumption and the like.

<Others> In the embodiment, the element substrate 101 constituting the electro-optical device is a semiconductor substrate, and the transistor 116 connected to the pixel electrode 118 and the components of the driving circuit are MOS transistors. Type FET
However, the present invention is not limited to this. For example,
The element substrate 101 may be an amorphous substrate such as glass or quartz, and a semiconductor thin film may be deposited thereon to form a TFT. When a TFT is used in this manner, a transparent substrate can be used as the element substrate 101.

Further, as an electro-optical material, in addition to a liquid crystal, an electroluminescent element (EL) or the like can be used, and the present invention can be applied to a device for performing display by the electro-optical effect. In other words, the present invention provides an electro-optical device having a configuration similar to the above-described configuration, particularly, an on-off device or an on-off device.
The present invention can be applied to all electro-optical devices that perform gradation display using pixels that perform a value display. When a liquid crystal is used as the electro-optical material as described in each of the above embodiments, the level of the AC drive signal LCOM is inverted every field to avoid a situation in which a DC component is applied to the liquid crystal layer. However, when the above-described electroluminescent element is used as the electro-optical material, it is not necessary to perform the AC driving.

<Electronic Equipment> Next, some examples in which the above-described liquid crystal device is used in specific electronic equipment will be described.

<Part 1: Projector> First, a projector using the electro-optical device according to the embodiment as a light valve will be described. FIG. 17 is a plan view showing the configuration of this projector. As shown in this figure,
Inside the projector 1100, a polarized light illumination device 1110 is provided.
Are arranged along the system optical axis PL. In the polarized light illuminating device 1110, the light emitted from the lamp 1112 becomes a substantially parallel light beam due to reflection by the reflector 1114, and enters the first integrator lens 1120. As a result, the light emitted from the lamp 1112 is split into a plurality of intermediate light beams. This split intermediate beam is
The polarization conversion element 1130 having the second integrator lens on the light incident side converts the light into one type of polarized light beam (s-polarized light beam) having a substantially uniform polarization direction, and emits it from the polarized light illuminating device 1110.

Now, the s-polarized light beam emitted from the polarized light illuminator 1110 is reflected by the s-polarized light beam reflecting surface 1141 of the polarizing beam splitter 1140. Of this reflected light beam, the light beam of blue light (B) is reflected by the blue light reflecting layer of the dichroic mirror 1151, and is modulated by the reflection-type electro-optical device 100B. Further, among the light beams transmitted through the blue light reflecting layer of the dichroic mirror 1151, the light beam of red light (R) is
The light is reflected by the red light reflection layer 52 and is modulated by the reflection type liquid electro-optical device 100R. On the other hand, among the light beams transmitted through the blue light reflecting layer of the dichroic mirror 1151, the light beam of green light (G) is
The light passes through the 52 red light reflecting layer and is modulated by the reflection-type electro-optical device 100G.

Thus, the electro-optical device 100R,
The red, green, and blue lights, each of which has been color-modulated by 100G and 100B, are output to a dichroic mirror 115.
2, 1151, and are sequentially synthesized by the polarizing beam splitter 1140, and then projected on the screen 1170 by the projection optical system 1160. Note that the electro-optical devices 100R, 100B, and 100G are provided with dichroic mirrors 1151 and 1152 for R, G,
Since a light beam corresponding to each primary color of B enters, no color filter is required.

<Part 2: Mobile Computer> Next, an example in which the electro-optical device is applied to a mobile personal computer will be described. FIG. 18 is a perspective view showing the configuration of this personal computer.
In the figure, a computer 1200 includes a keyboard 12
02, a display unit 1206,
It is composed of This display unit 1206 is
It is configured by adding a front light to the front surface of the electro-optical device 100 described above.

In this configuration, the electro-optical device 100
Is used as a reflection direct-view type, so that the pixel electrode 1
At 18, the reflected light is scattered in various directions,
A configuration in which unevenness is formed is desirable.

<Part 3: Mobile phone> Further, an example in which the above-described electro-optical device is applied to a mobile phone will be described. FIG. 19 is a perspective view showing the configuration of the mobile phone. In the figure, a mobile phone 1300 includes a plurality of operation buttons 1302, an earpiece 1304, and a mouthpiece 1306.
In addition, an electro-optical device 100 is provided. The electro-optical device 100 is also provided with a front light on its front surface as needed. Also in this configuration, since the electro-optical device 100 is used as a reflection direct-view type, a configuration in which the pixel electrode 118 has unevenness is desirable.

FIGS. 17 to 19 show the electronic devices.
In addition to those described with reference to the above, a liquid crystal television, a viewfinder type, a video tape recorder of a monitor direct-view type, a car navigation device, a pager, an electronic organizer, a calculator, a word processor, a workstation, a videophone, a PO
An S terminal, a device equipped with a touch panel, and the like are included. Needless to say, the electro-optical device according to the embodiment or the applied form can be applied to these various electronic devices.

[0128]

As described above, according to the present invention,
Since the signals applied to the data lines are binarized, high-quality gradation display is possible. Further, after the data transfer period has elapsed, a voltage for turning on or off the pixel is applied in accordance with a signal written to the memory in the pixel, so that regardless of the data transfer period, The voltage application period can be set arbitrarily. Therefore, there is an advantage that it is possible to easily realize multi-gradation of a display image.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an electrical configuration of an electro-optical device according to an embodiment of the invention.

FIG. 2 is a block diagram illustrating a configuration of a data line driving circuit in the same electro-optical device.

FIG. 3 is a block diagram illustrating a configuration of a pixel in the electro-optical device.

FIG. 4 shows voltages Von and V in the electro-optical device.
It is a figure which shows the level of off.

FIG. 5 is a truth table showing functions of a data conversion circuit in the electro-optical device.

FIG. 6 is a diagram showing voltage-transmittance characteristics in the same electro-optical device.

FIG. 7 is a timing chart showing an operation of the electro-optical device.

FIG. 8 is a timing chart showing a voltage applied to a counter substrate and a voltage applied to a pixel electrode in the same electro-optical device in field units.

FIG. 9 is a diagram for describing an effect in the electro-optical device.

FIG. 10 is a block diagram showing a configuration of a pixel in an electro-optical device according to another embodiment of the present invention.

FIG. 11 is a timing chart for explaining changes in levels of voltages Von and Voff in the same electro-optical device.

FIG. 12 is a timing chart for explaining changes in levels of voltages Von and Voff in a modification of the present invention.

FIG. 13 is a block diagram showing a configuration of a pixel according to a modification of the present invention.

FIG. 14 is a truth table showing functions of a data conversion circuit according to a modification of the present invention.

FIG. 15 is a plan view showing the structure of the electro-optical device.

FIG. 16 is a sectional view showing the structure of the electro-optical device.

FIG. 17 is a cross-sectional view illustrating a configuration of a projector as an example of an electronic apparatus to which the electro-optical device is applied.

FIG. 18 is a perspective view illustrating a configuration of a personal computer as an example of an electronic apparatus to which the electro-optical device is applied.

FIG. 19 is a perspective view illustrating a configuration of a mobile phone as an example of an electronic apparatus to which the electro-optical device is applied.

[Explanation of symbols]

 100 electro-optical device 101 element substrate 101 a display area 102 counter substrate 105 liquid crystal (electro-optical material) 108 counter electrode 112 scanning lines 114 a and 114 b data lines 116 a and 116 b ... Transistor 118 Pixel electrode 130 Scan line drive circuit 140 Data line drive circuit 1410 X shift register 1420 First latch circuit 1430 Second latch circuit 160 Voltage control circuit 200 timing signal generation circuit 300 data conversion circuit

Continued on the front page F term (reference) 2H093 NA16 NA31 NA55 NA56 NC22 NC31 NC34 NC40 NC49 ND06 ND15 ND39 NG01 NG02 5C006 AA01 AA02 AA03 AA22 AB05 AC02 AC24 AC28 AF44 AF51 BB16 BC03 BC06 BC12 BF03 BF04 EC27 EC05 AA10 BB05 CC01 CC03 DD30 EE29 FF09 GG05 GG08 GG12 JJ01 JJ02 JJ03 JJ04 JJ05 JJ06 KK02 KK07 KK43

Claims (9)

[Claims] 1. A driving method for an electro-optical device which receives gradation data of each pixel for one screen for each field, and performs on / off driving of a plurality of pixels each including a memory according to the gradation data. In each of a plurality of subfields obtained by dividing one field, a data signal instructing application of a voltage for turning on or off a pixel is sequentially generated in accordance with the grayscale data, and is stored in a memory of each pixel. In writing, at least after a data transfer period, which is a period during which the data signal is written to the memories of all the pixels, a voltage corresponding to the data signal is applied to each pixel. A driving method of the electro-optical device. 2. During a data transfer period in each subfield, regardless of a data signal written in a memory of each pixel, a voltage for turning on the pixel or a voltage for turning off the pixel is applied to each pixel. The method of driving an electro-optical device according to claim 1, wherein the voltage is applied to the device. 3. Receiving gradation data of each pixel for one screen for each field, and corresponding to each intersection of a plurality of data lines and a plurality of scanning lines in accordance with the gradation data, A driving circuit of an electro-optical device that drives a plurality of pixels including a memory, wherein in each of a plurality of subfields obtained by dividing one field, a scanning signal that enables voltage application from a data line to a pixel is provided. A scanning line driving circuit for sequentially supplying each of the scanning lines; and a data signal for instructing application of a voltage for turning on a pixel or a voltage for turning off a pixel in each of the plurality of sub-fields in accordance with the gradation data. A data line driving circuit for generating and supplying the data signal to each data line so as to write the data signal to a memory in each pixel while the scanning signal is supplied; and each of the plurality of sub-fields. , At least after a lapse of a data transfer period during which the data signal is written to the memories of all the pixels, the pixels are driven on and off in accordance with the data signals written to the memories of the respective pixels And a voltage control circuit for controlling a voltage applied to each pixel. 4. The voltage control circuit applies a voltage to each pixel such that the pixel is turned on or off regardless of a data signal written in a memory of the pixel during a data transfer period in each subfield. 4. The driving circuit according to claim 3, wherein the applied voltage is controlled. 5. An electro-optical device having a plurality of pixels provided at respective intersections of a plurality of scanning lines and a plurality of data lines and each including a memory, the plurality of pixels being divided into one field. In each of the sub-fields, a scanning line driving circuit that sequentially supplies a scanning signal enabling voltage application from a data line to a pixel to each of the scanning lines; and turning on a pixel in each of the plurality of sub-fields. A data signal for instructing the application of a voltage to turn on or off is sequentially generated according to the grayscale data, and while the scanning signal is supplied, each data signal is written to a memory in each pixel. A data line driving circuit for supplying data to a line; and a data transfer period in each of the subfields, at least a period during which the data signal is written to memories of all pixels. And a voltage control circuit for controlling a voltage applied to each pixel so that the pixel is turned on and off in accordance with a data signal written in the memory of each pixel after the lapse of Electro-optical device. 6. The voltage control circuit applies a voltage to each pixel such that the pixel is turned on or off during a data transfer period in each subfield regardless of a data signal written in a memory of the pixel. The electro-optical device according to claim 5, wherein the applied voltage is controlled. 7. An electro-optical device having a plurality of pixels arranged corresponding to respective intersections of a plurality of scanning lines and a plurality of data lines, wherein each of a plurality of sub-fields obtained by dividing one field is provided. A scanning line driving circuit that sequentially supplies a scanning signal that enables voltage application from a data line to a pixel to each of the scanning lines; and a voltage that turns on a pixel or an off voltage in each of the plurality of subfields. A data line driving circuit for sequentially generating a data signal instructing application of a voltage to be applied in accordance with the grayscale data, and supplying the data signal to each data line while the scanning signal is supplied, Each pixel is provided with a pixel electrode, a counter electrode facing the pixel electrode, an electro-optical material sandwiched between the pixel electrode and the counter electrode, and a scan signal given through the scan line. A memory for storing a data signal supplied through the data line, and a data transfer period in which, in each of the plurality of subfields, at least a period in which the data signal is written to the memories of all the pixels. And a selection circuit for selecting one of two types of voltages according to the data signal written in the memory after the elapse of the time and applying the selected voltage to the pixel electrode. 8. The pixel selection circuit selects one of two types of voltages and applies it to the pixel electrode during a data transfer period in each subfield regardless of a data signal written in the memory. The electro-optical device according to claim 7, wherein: 9. An electronic apparatus comprising the electro-optical device according to claim 5 as a display device.