JP2001094357A - Linear high output amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To miniaturize a linear high output amplifier and to drop voltage of the amplifier. SOLUTION: A unit amplifier cell 25 is arranged so that one terminal of a gate 21 may be connected with a common gate terminal 27 and that the other end may face a common drain terminal 29. A unit, variable resistance cell 28 is arranged between the cell 25 and the terminal 29. Then, a unit cell 11 consists of the cell 25 and the cell 28. This cell 11 is arranged and connected in parallel between the terminal 27 and the terminal 29.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a linear high-power amplifying device used in a band of several hundred MHz or more, such as a personal wireless communication, a mobile communication, a satellite communication, etc. The present invention relates to a linear high-power amplifying device suitable for a portable terminal requiring strictly low-voltage operation.

[0002]

2. Description of the Related Art With the spread of mobile communication services represented by mobile phones, there is an increasing demand for further miniaturization and lower power consumption of mobile terminals. For this reason, it is extremely important to reduce the size and efficiency of a power amplifier that consumes a large amount of power and to operate it at a low voltage.

In general, there is a trade-off between high efficiency and linearization of an amplifier. Therefore, if the linearity is impaired due to the improvement in efficiency, inter-modulation distortion causes an increase in adjacent channel leakage power, resulting in deterioration of communication quality. Therefore, it is required to improve efficiency while securing linearity.

In order to solve these problems, a method of controlling the bias of an amplifier in accordance with the amplitude of an input signal and linearizing the same is known. This conventional method controls the output current to decrease when the amplitude of the input signal decreases, thereby reducing power consumption while ensuring linearity or linearizing the input / output amplitude characteristics. It is a technology that can be achieved.

However, in the configuration for controlling the gate bias, control cannot be performed in the vicinity of the saturation region where the dynamic range is reduced and the efficiency is high. In the configuration for controlling the drain bias, the power consumption by the DC-DC converter is large. There is a problem that becomes.

To overcome these problems, a configuration has been devised for controlling the gate bias of a common-gate FET in a cascode-connected FET. 1995 IEEE GaAs
This structure described in ICSymp.Dig., Pp.288-291 is shown in FIG.
It is shown in FIG.

The principle of operation of this conventional amplifying device is that the output power of the cascode FET circuit 51 composed of the common-source FET 51A and the common-gate FET 51B is converted to the common-gate FE.
Based on the fact that control is possible with the gate bias of T51B, it can be said that the configuration combines the advantage of not requiring a DC-DC converter of the gate bias control method with the advantage of being able to control up to the saturation region of the drain bias control method. 12
A and 12B are matching circuits, 52 is a high-frequency grounding capacitor, and 53 is a high-frequency cut choke inductor.

The signal obtained by distributing the input signal by the distributor 1 is input to a cascode FET circuit 51 via a matching circuit 12A, and is also input to an envelope detector 2 where the amplitude is detected and the A / D converter 3 The amplitude characteristic is converted by a ROM 4 as an LUT, and is converted into an analog signal by a D / A converter 5 to be converted into a gate voltage Vc. Here, by setting the data in the ROM 4 so that the input / output characteristics of the amplifier become linear, distortion can be reduced in the vicinity of the saturation region where the efficiency is increased.

[0009]

However, in this conventional example, since two FETs are used, a device size that is almost twice as large as that of an amplifier having one FET is required.
Two FETs 51A and 51B having a common source and a common gate
In this case, it is necessary to supply a bias in series. This is because the voltage (Vdd) applied through the choke inductor 53 is
The voltage is divided by the common source FET 51A and the common gate FET 51B.

For example, in the case of a Li-ion battery which is widely applied to portable terminals at present, power is supplied to about 3 V. However, when a power amplifier operating at 3 V is constituted by the cascode FET circuit 51, the latter stage which contributes to the output Gate ground F
The voltage of ET51B is limited to about 2V or less. For this reason, when trying to obtain the same output as that of a single-stage FET 1-stage amplifier operating at 3 V, it is necessary to increase the gate width by about twice in order to increase the current. However, there is a problem that the cost increases.

On the other hand, as a method for controlling the output of a low-voltage operation FET amplifier, there is a configuration of a variable negative feedback amplifier. However, in order to realize a high-output FET, a series / parallel combination of relatively small unit cells is used to realize a large total gate width F.
Since ET is configured, if variable negative feedback is applied collectively between human outputs with a common feedback circuit, (1)
If the wiring length of the feedback circuit becomes longer in proportion to the FET size, and this cannot be ignored compared to the wavelength, the frequency characteristic occurs in the variable negative feedback signal. (2) In proportion to the arrangement interval between small unit cells Since a phenomenon occurs in which a phase difference occurs in the variable negative feedback signal, there is a problem that band limitation is caused and linearization control becomes difficult. In particular, in the case of using in an ultra-high frequency region above the microwave band, there is a problem that this becomes more remarkable as the frequency becomes higher.

An object of the present invention is to solve the above-mentioned conventional problems and to provide an economical linear high-power amplifier which can be easily applied to a portable terminal, can operate at a low voltage, and is economical.

[0013]

According to a first aspect of the present invention, there is provided a variable negative feedback amplifier for amplifying and outputting an input signal, and a feedback of the variable negative feedback amplifier according to the amplitude of the input signal. A control signal generating means for generating a control signal for controlling the amount of the variable negative feedback amplifier, wherein the variable negative feedback amplifier is connected in parallel between a common input terminal and a common output terminal. Wherein each of the unit cells includes a gate having a first connection point at one end connected to the common input terminal and a second connection point at the other end facing the common output terminal, and a source connected to ground. And an amplifying FET having a drain connected to the common output terminal, a source or a drain connected to the second connection point, the other connected to the common output terminal via a first capacitor, and a gate connected to the common output terminal. Control signal And configured to include a variable resistor for FET connected to a control line connected to the raw device.

In a second aspect based on the first aspect, the variable resistance FET is connected between the second connection point and the common connection point or between the amplification FET and the common connection terminal. It was configured to be arranged in.

In a third aspect based on the first or second aspect, a fixed resistor is connected between the second connection point or the common output terminal and a source or a drain of the variable resistor FET. Configured.

According to a fourth aspect of the present invention, in the first to third aspects, the gate of the variable resistance FET is connected to the source of the amplification FET via a second capacitor.

In a fifth aspect based on the fourth aspect, the second capacitor is arranged between the source of the amplifying FET and the gate of the variable resistor FET in each of the unit cells. It was configured to be.

According to a sixth aspect, in the first to fifth aspects, the amplifying FET is replaced with an amplifying bipolar transistor, and the variable resistor FET is replaced with a variable resistor bipolar transistor.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] FIG. 1 is a diagram showing a circuit configuration of a linear high-power amplifier according to a first embodiment of the present invention. The linear high-power amplifier according to the present embodiment includes a distributor 1 for distributing an input signal, an envelope detector 2 for detecting an amplitude of an envelope of the input signal, and an A / D converter for converting the envelope signal into a digital signal. 3, ROM 4 as LUT, digital signal is converted to analog control voltage Vc
And a variable negative feedback amplifier 7 having a control terminal 6 to which the control voltage Vc is input.

The variable negative feedback amplifier 7 includes a source-grounded amplification FET 8 and a variable resistance FET constituting a feedback circuit.
9, and a circuit comprising a DC cut capacitor 10 similarly constituting a feedback circuit as a unit cell 11 and connecting six parallel circuits to a matching circuit 12A on the input side and a matching circuit 12B on the output side. ing. The control terminal 6, which is the gate bias terminal of the variable resistance FET 9, is grounded at a high frequency via the capacitor 13. This configuration is the same as the conventional example shown in FIG. 14 except that the variable negative feedback amplifier 7 is used as the amplifier.

FIG. 2 shows input / output matching circuits 12A and 12A.
7 shows an example of a pattern layout of the variable negative feedback amplifier 7 excluding B. In this variable negative feedback amplifier 7, two gates 21,
A two-gate finger type unit amplification cell 25 (the amplification FET 8) is formed by the drain 22, the source 23, and the air bridge 24A interconnecting the source 23, and six of them are arranged and connected in parallel.

The gate 21 of the unit amplification cell 25 is connected to a common gate terminal (common input terminal) 27 via a wiring 31 by a first gate connection point 26A, and to a wiring 32 by a second gate connection point 26B. The source is connected to the source of the unit variable resistance cell 28 (the variable resistance FET 9) through the gate. This unit variable resistance cell 28 is also of a two-gate finger type, and each drain is connected to a common drain terminal (common output terminal) 29 via a capacitor 10 having a predetermined capacitance value.
It is connected to the. That is, this unit variable resistance cell 2
8 is arranged between the second gate connection point 26B of the unit amplification cell 25 and the common drain terminal 29. As described above, the variable negative feedback is applied from the drain to the gate of each unit amplification cell 25 by the individual unit variable resistance cell 28 for each unit amplification cell 25.

The drain 22 of the unit amplification cell 25 and the common drain terminal 29 are connected by an air bridge 24B. The gate of the unit variable resistance cell 28 is connected to the control wiring 30 via a third gate connection point 26C, and further connected to the control terminal 6 via the control wiring 30. The control wiring 30 is connected to the source 23 via the capacitor 13 having a predetermined capacitance value and the ground wiring 33, and is grounded at a high frequency in order to reduce the amount of phase change due to the influence of the parasitic capacitance of the unit variable resistance cell 28. ing. Also,
The control wiring 30 is formed by a lower wiring, and the wiring 32 connecting the second gate connection point 26B and the source of the unit variable resistance cell 28 is formed by an upper wiring, whereby a control voltage can be applied.

Since the variable resistance realized by the variable resistance FET 9 is approximately several hundred ohms or more, the gate width of the unit variable resistance cell 29 as the variable resistance FET 9 is limited to the unit amplification as the amplification FET 8. It can be made much smaller than the gate width of the cell 25.

As described above, in the present variable negative feedback amplifier 7,
(1) The whole device can be configured with almost the size of the amplifying FET, which makes it possible to reduce the size and simplification of the device. (2) Since the amplifying device is composed of a single-source FET, low voltage (3) A second gate connection point is provided on the common drain terminal side of the unit amplification cell, and a variable negative feedback circuit composed of a variable resistance FET is arranged between the gate connection point and the common drain terminal. Therefore, regardless of the size of the gate width of the unit amplification cell, the unit variable resistance cell can be connected to the shortest. (4) FET, especially on a semiconductor substrate,
In the case of an MMIC in which a resistor, a capacitor, and the like are integrally formed, the physical lengths of the unit variable resistance cells for variable negative feedback provided for each unit amplification cell are exactly the same, regardless of the number of unit cells. There are features like

For this reason, the present invention can be easily applied to a portable terminal which is required to be reduced in size and economy and to reduce the burden on a battery. Also, due to the effects of the above (3) and (4), even when the gate width of the unit amplification cell 25 is increased or the number of the unit cells 11 is increased in order to increase the output, even up to the ultra-high frequency region. Since the influence of the inductance of the feedback circuit can be greatly reduced and the feedback amplitude / phase can be kept the same between the unit amplification cells 25, it is possible to easily cope with higher output and higher frequency.

FIG. 3 is a diagram showing characteristics obtained by measuring the dependence of the gain on the amount of feedback with respect to the input power of the variable negative feedback amplifier circuit 7 of the present invention actually manufactured using the pattern of FIG. This figure 3
It can be seen that the gain can be controlled by the variable negative feedback effect as shown in FIG. Here, if the feedback amount is controlled in accordance with the input level, as indicated by the mark in the figure, the AM-AM conversion characteristic can be greatly improved as indicated by the arrow, and the linearization of the amplifier can be achieved. Understand.

Therefore, as shown in FIG. 1, the amplitude detected by the envelope detector 2 is converted to the A / D converter 3, R
When converting the data into the control voltage Vc via the OM 4 and the D / A converter 5, the data in the ROM 4
By setting the AM conversion characteristic (input signal level / gain characteristic) to be linear, distortion can be reduced even in the vicinity of the saturation region where the efficiency is high.

FIG. 4 is a diagram showing a pattern layout of a modified example of the variable negative feedback amplifier 7, in which a single-gate finger type unit amplification cell 25 'of a common source FET 8 and a unit variable resistance cell 28' of a variable resistance FET 9 are shown. Are formed to form a unit cell 11, and the unit cells 11 are arranged in six rows. Here, the drain 22 of the unit amplification cell 25 ′ is directly connected to the common drain terminal 29 on the lower surface of the capacitor 10. In the unit variable resistance cell 28 ′, the drain is connected to the gate of the unit amplification cell 25 ′, and the source is connected to the drain of the unit amplification cell 25 ′ via the capacitor 10.
In ET, there is no problem because the same function can be realized even if the source and drain are switched.

[Second Embodiment] FIGS. 5 and 6 are diagrams showing equivalent circuits of a variable negative feedback amplifier 7 according to a second embodiment of the present invention. The feature of this embodiment is that the variable resistor F
A fixed resistor 14 having a predetermined resistance value is arranged and connected in parallel between the source and the drain of the ET 9 to unit cell 11A (FIG. 5).
Or the source of the variable resistance FET 9 and the amplification F
That is, a unit cell 11B (FIG. 6) is arranged and connected to the fixed resistor 15 between the unit cell 11B and the gate of the ET8.

Thus, although the variable gain range is reduced, the amount of phase change due to the influence of the parasitic capacitance of the variable resistor FET 9 can be further reduced, so that the variable negative feedback operation can be stabilized.

FIG. 7 is a diagram showing an example of a pattern layout of the variable negative feedback amplifier 7 of the embodiment corresponding to FIG. 6 to which a fixed resistor 15 connected in series is added. Here, in the pattern layout shown in FIG. 2, the second gate connection point 2
The configuration is such that the fixed resistor 15 is arranged between 6B and the wiring 32 connected to the source of the unit variable resistance cell 28 (9).

By adopting such a pattern layout, the unit variable resistance cell 28 can be formed similarly to the first embodiment.
(9) can be arranged between the drain and the gate of the unit amplification cell 25 at the shortest. Therefore, the physical length of the unit variable resistance cell 28 (9) can be almost ignored, and an ideal variable negative feedback characteristic free from the influence of inductance and phase rotation can be realized in a wide band. Note that the fixed resistor 15 can be connected between the common drain terminal 29 and the drain of the unit variable resistance cell 28 (9).

FIG. 8 shows the configuration of FIG. 7 in which a one-gate finger type unit amplification cell 25 '(8) and a unit variable resistance cell 28' are used.
This is an example of the pattern layout modified in (9), and the same effect as the configuration in FIG. 7 can be realized.

FIG. 9 is a diagram showing a pattern layout when the parallel-connected fixed resistor 14 shown in FIG. 5 is used. The one-gate finger type unit amplification cell 25 '(8),
This is applied to the unit variable resistance cell 28 '(9), and the fixed resistance 14 is arranged and connected between the unit variable resistance cell 28' (9) and the common drain terminal 29. 41,
Reference numeral 42 denotes a wiring for connecting the fixed resistor 14 between the source and the drain of the unit variable resistance cell 28 '(9).

[Third Embodiment] FIGS. 10, 11, and 1
FIG. 2 is a diagram showing an equivalent circuit of the variable negative feedback amplifier 7 according to the third embodiment of the present invention. Here, FIG.
The variable negative feedback amplifier 7 of FIG.
5 shows a form in which the variable negative feedback amplifier 7 shown in FIGS. 5 and 6 is developed.

The feature of this embodiment is that each unit cell 11
The gate of the variable resistance FET 9 of C (same for 11D and 11E) is grounded at a high frequency by a capacitor 13a. Thereby, the unit cells 11C, 11D, 11E
The inductance component caused by the increase in the physical length of the control terminal 6 (the control wiring 30) with the increase in the number of the resistors can be reduced to a negligible level, so that the influence of the parasitic capacitance of the variable resistance FET 9 is further reduced. it can.

FIG. 13 is a diagram showing a pattern layout of the variable negative feedback amplifier 7 corresponding to FIG. Here, in the pattern layout shown in FIG.
The gate of 8 '(9) is connected to the unit amplification cell 25' (8) in the same unit cell 11E at the shortest distance via the capacitor 13a.
Is connected to the source 22 of the first embodiment. By adopting such a pattern layout, it becomes possible to ground the gates of all the unit variable resistance cells 28 '(9) at the same connection distance and at the shortest frequency with high frequency.

Therefore, the variable negative feedback control of each unit cell 11E can be made exactly the same, and the variable resistor FET 9
It is possible to realize an extremely ideal variable negative feedback, in which the influence of the parasitic capacitance is largely removed. Although not shown in the drawing, the present invention can be similarly applied to the two-gate finger configuration shown in FIG.

[Other Embodiments] In the linear high-power amplifier of the embodiment shown in FIG. 1, the amplitude of the envelope of the input signal is detected before the high-power amplifier.
The detection is not limited to the stage preceding the amplifier, and may be detected inside the amplifier or at the output stage. Also, the level of the input signal may be detected as it is without using the envelope detection and used as the control signal.

In all of the above embodiments,
Although an FET is used as the transistor, a similar effect can be expected by using a bipolar transistor. At this time, the gate is a base, the drain is a collector, the source is an emitter, the common gate terminal is a common base terminal, the common drain terminal is a common collector terminal,
Will be replaced respectively.

[0042]

As described above, according to the present invention, (1) the variable negative feedback amplifier can be constituted by the size of the amplifying element substantially, so that the device can be reduced in size and simplified. Low voltage operation is possible because the element is configured in one stage. (3) Since the variable resistance cell is provided between the unit amplification cell and the common output terminal, the size of the unit amplification cell can be reduced. Irrespective of the number of unit cells, the unit variable resistance cell can be connected as short as possible. (4) In the case of an MMIC in which an amplifier, a resistor, a capacitor, etc. are integrally formed on a semiconductor substrate, the unit variable There is a feature that the physical lengths of the resistance cells can be made exactly the same.

Therefore, the power amplifier can be reduced in size and economy,
In addition to achieving low distortion, high efficiency, and reduced burden on the battery, even if the unit cell size is increased or the number of cells is increased to increase the output, the feedback circuit extends to the ultra-high frequency range. Can greatly reduce the effect of inductance, and the feedback amplitude /
Since the phases can be kept the same, it is possible to easily cope with higher output and higher frequency.

From the above, the linear power amplifier of the present invention is
Miniaturization and economy of high-power amplifiers for portable terminals that can contribute to broadband, low distortion, and low cost of high-power amplifiers of approximately several hundred MHz band or more used for personal wireless communication, mobile communication, satellite communication, etc. It greatly contributes to the development.

[Brief description of the drawings]

FIG. 1 is a block diagram of a linear high-power amplifier according to a first embodiment of the present invention.

2 is a pattern layout diagram using a two-gate finger type unit cell in the variable negative feedback amplifier of FIG. 1;

FIG. 3 is a characteristic diagram of gain with respect to an input signal of the variable negative feedback amplifier of FIG. 1;

FIG. 4 is a pattern layout diagram using a one-gate finger type unit cell in the variable negative feedback amplifier of FIG. 1;

FIG. 5 is a circuit diagram of a variable negative feedback amplifier according to a second embodiment.

FIG. 6 is a circuit diagram of a variable negative feedback amplifier according to a modification of the second embodiment.

7 is a pattern layout diagram using a two-gate finger type unit cell in the variable negative feedback amplifier of FIG. 6;

8 is a pattern layout diagram using a one-gate finger type unit cell for the variable negative feedback amplifier of FIG. 6;

9 is a pattern layout diagram using a one-gate finger type unit cell for the variable negative feedback amplifier of FIG. 5;

FIG. 10 is a circuit diagram of a variable negative feedback amplifier according to a third embodiment.

FIG. 11 is a circuit diagram of a variable negative feedback amplifier according to a modification of the third embodiment.

FIG. 12 is a circuit diagram of a variable negative feedback amplifier according to another modification of the third embodiment.

FIG. 13 is a pattern layout diagram using a one-gate finger type unit cell for the variable negative feedback amplifier of FIG. 11;

FIG. 14 is a block diagram of a conventional linear high-power amplifier.

[Explanation of symbols]

1: distributor, 2: envelope detector, 3: A / D converter, 4: ROM, 5: D / A converter, 6: control terminal, 7: variable negative feedback amplifier, 8: amplifying FET, 9: Variable resistance FET, 10: capacitor, 11, 11A-1
1E: unit cell, 12A, 12B: matching circuit, 13: capacitor, 14, 15: fixed resistance, 21: gate, 2
2: drain, 23: source, 24A, 24B: air bridge, 25: unit amplification cell, 26A, 26B, 26
C: gate connection point, 27: common gate terminal (common input terminal), 28: unit variable resistance cell, 29: common drain terminal (common output terminal), 30: control wiring, 31, 32: wiring, 33: ground wiring , 41, 42: wiring.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (reference) // H01L 21/06 21/8232 F term (reference) 5F102 FA07 GA01 GA16 GA17 GB01 GC01 GD01 GS09 GV01 5J090 AA01 AA21 AA41 CA21 CA36 CA62 CA87 CA92 FA10 FA15 FA17 GN06 HA09 HA25 HA27 HA29 HN13 KA29 KA34 KA55 MA13 MA19 QA03 SA14 TA01 TA02 5J092 AA01 AA21 AA41 CA21 CA36 CA62 CA92 FA10 FA15 FA17 GR09 HA09 HA25 HA27 HA19 KA29 KA29 KA29 5J100 JA01 KA05 LA11 QA01 SA01

Claims (6)

[Claims] A variable negative feedback amplifier for amplifying and outputting an input signal; and control signal generating means for generating a control signal for controlling a feedback amount of the variable negative feedback amplifier in accordance with an amplitude of the input signal. Wherein the variable negative feedback amplifier has a plurality of identical unit cells connected in parallel between a common input terminal and a common output terminal, and each of the unit cells has a first terminal at one end. An amplifying FET having a connection point of 1 connected to the common input terminal and a second connection point of the other end facing the common output terminal, a source grounded and a drain connected to the common output terminal; A variable resistor having one of a source and a drain connected to the second connection point, the other connected to the common output terminal via a first capacitor, and a gate connected to a control wiring connected to the control signal generation means; for Linear high-power amplifier apparatus characterized by comprising a ET. 2. The variable resistance FET according to claim 1, wherein
Is disposed between the second connection point and the common connection point or between the amplifying FET and the common connection terminal. 3. The linear circuit according to claim 1, wherein a fixed resistor is connected between the second connection point or the common output terminal and a source or a drain of the variable resistor FET. High power amplifier. 4. A linear high-power amplifier according to claim 1, wherein a gate of said variable resistor FET is connected to a source of said amplifier FET via a second capacitor. 5. The device according to claim 4, wherein the second capacitor is arranged between the source of the amplifying FET and the gate of the variable resistor FET in each of the unit cells. Linear high power amplifier. 6. The linear high-power amplifier according to claim 1, wherein said amplifying FET is replaced with an amplifying bipolar transistor, and said variable-resistance FET is replaced with a variable-resistance bipolar transistor. .