JP2001086504A - Mpeg video decoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease a capacity of a memory used for reconfiguring and displaying a B-Picture in compliance with the MPEG(moving picture experts group) to 16 Mbits or below. SOLUTION: A bit stream once stored in an input bit stream buffer by an input control section is decoded by a VLD(variable length decoder), inversely quantized by an IQ, subjected to inverse discrete cosine transform by an IDCT (inverse discrete cosine transform). The P and B-Pictures in the processed stream are reconfigured by a frame buffer and an MC and the result is displayed via a display macro block buffer. In this case, since the B-Pictures are not buffered by one frame, data deficient in reconfiguring the B-Pictures are obtained from data read from the stream buffer by the input control section and decoded by the VLD at high speed and displayed through the reconfiguration. Part of the frame buffer is used for displaying the P and B-Pictures so as to decrease the capacity of the frame buffer and the display macro block buffer to 16 Mbits or below in the case of the PAL stream.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an MPEG (Moving
The present invention relates to an MPEG video decoding device for decompressing and decoding an image compressed and coded according to the Picture Expert Group (Picture Expert Group) standard, and particularly to a technique for reducing a necessary memory capacity.

[0002]

2. Description of the Related Art Conventionally, since image data obtained by reproducing a DVD or receiving a communication satellite broadcast or the like has been compression-encoded according to the MPEG standard, an apparatus for expanding and decoding the image data is required.

FIG. 12 is a block diagram showing a configuration example of a conventional MPEG video decoding device. MPEG-encoded image data is temporarily stored in an input bit stream buffer 1 and then stored in a VLD (Valuable Length Decoder).
2 (demodulation decoding) to decompress the MPEG-encoded image data, decompress the decompressed image data by pulling a quantization table by an IQ (Inverse Quantizer) 3, and further decompress it. IDCT (Inverse Di
An I-Picture is obtained by performing an inverse discrete cosine transform using a discrete cosine transform (screte 4).

[0004] After that, using the MC (Motion Compensation) 5 and the I and P-Pictures held in the two frame buffers 6, the MPEG B-Picture is forward-predicted and backward-predicted to be reconstructed. , B-Picture via the display frame buffer 7 to a CRT or the like (not shown). Note that the system controller 8 controls the above operation entirely and individually, and decodes the MPEG-encoded image data into the original displayable image data.

[0005]

As described above, the conventional M
In the PEG video decoding apparatus, in order to perform forward prediction and backward prediction to reconstruct an MPEG B-Picture, two frame buffers 6 for reference images and one frame buffer for buffering images are displayed. The image memory of the display frame buffer 7 was required.

However, when the capacity of one image is the PAL system, the required memory capacity slightly exceeds 16 Mbit because the horizontal capacity is 720 × vertical 576 × (luminance 8 bits + color difference 4 bits), which is 5 Mbit. In order to use one memory as a memory, a 64 Mbit memory must be used, which is extremely uneconomical.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems.
The memory capacity required for reconstructing the picture is reduced, and even in the case of the PAL method,
An object of the present invention is to provide an MPEG video decoding device that can use a 16 Mbit memory.

[0008]

In order to achieve the above object, a feature of the first aspect of the present invention is that an MPEG-encoded bit stream is once input to a bit stream buffer, and then the input bit stream is read. Decoding, inverse quantization, inverse discrete cosine transform, and I-Pict
ure, B-Picture, and P-Picture are decoded and played back.
B-Picture and P-Picture are reconstructed using a frame buffer, and a part of data necessary for displaying a B-Picture in an MPEG video decoding device that outputs a display image via a display buffer. Is stored in the display buffer, necessary data among the data not stored is read out from the bit stream buffer, decoded at high speed, and then inversely quantized and subjected to inverse discrete cosine transform.

A feature of the present invention resides in that a display macro block buffer memory for storing 9 macro blocks × 1 line is used as the display buffer.

A feature of the invention according to claim 3 is that, when reconstructing a B-Picture from the bit stream buffer, necessary data among the unretained data is embedded in the bit stream. A control unit for reading out from the bit stream buffer using a read pointer is provided.

According to a fourth aspect of the present invention, there is provided a pre-decoding means for pre-decoding the bit stream connected to at least one of means for reading the bit stream from the bit stream buffer and means for decoding the read bit stream. Detecting means for detecting an error during decoding by pre-decoding the bit stream by means of the pre-decoding means; and detecting the error-free image when the error is detected by the detecting means. And display means for displaying the information as.

A feature of the invention of claim 5 is that a predetermined offset time is added to the decoding start timing of the bit stream read from the bit stream buffer.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the MPEG video decoding apparatus of the present invention. An MPEG video decoding device includes an input bit stream buffer 11 for temporarily storing an MPEG encoded bit stream, and a VLD (Valuable Length Decoder) 1 for decoding an MPEG encoded bit stream.
2. I for dequantizing image data obtained by decoding
Q (Inverse Quantizer) 13, IDCT (Inverse Discrete) for performing inverse discrete cosine transform of inversely quantized image data
te Cosine Transform) 14, MPEG B-Picture and P
-MC (Motion Compensation) 1 for reconstructing Picture
5. Frame buffer 16 for holding I and P-Picture
a, 16b, a display macroblock buffer 17 for holding display image data in macroblock units, a system controller 18 for controlling the operation of decoding the MPEG encoded bit stream as a whole and individually, and an input bitstream buffer 11. An input control unit 19 that controls writing and reading of the MPEG-encoded bit stream is provided. Display macro block buffer 17
Has a capacity of, for example, 9 macroblocks × 1 line.

Next, the operation of this embodiment will be described. The MPEG-encoded bit stream obtained from reproduction from DVD or the like or broadcast reception is written to the input bit stream buffer 11 by the input control unit 19, temporarily stored, and then read out by the input control unit 19. The reason why the MPEG-encoded bit stream is temporarily stored in the input bit stream buffer 11 is to absorb the difference between the bit stream usage speed and the bit stream input speed due to the decoding process of the VLD 12.

As shown in FIG. 2, the input control unit 19 indicates a buffer write position by a write pointer 191 and a buffer read position by a read pointer 192.
The bit stream is not overwritten by control so that the write pointer 191 does not overtake the read pointer. When the input bit stream buffer 11 becomes empty, the input controller 19
Issues a buffer empty flag. When the input bit stream buffer 11 becomes full, a buffer full flag is issued to the bit stream write destination.

The VLD 12 decodes the input bit stream in accordance with the MPEG grammar (variable length decoding).
I do. The IQ 13 inversely quantizes the signal decoded by the VLD 12 using a quantization table according to the MPEG grammar. IDCT14 converts the output signal of IQ13 to MPE
Inverse discrete cosine transform is performed according to the grammar of G, and I-Pict
get ure.

Here, when decoding and reproducing the I-Picture, the I-Picture is used for the B-Picture and the P-Picture.
Are stored in the frame buffers 16a and 16b. P-Pi
When decoding and reproducing the cture, the frame buffer 16a,
A reproduced image is composed of the reference image and the motion compensation vector stored in 16b, and stored in the frame buffers 16a and 16b.

When decoding and reproducing a B-Picture, forward and backward references are performed using two images stored in the frame buffers 16a and 16b to reconstruct an output image. In the case of an I-Picture or a P-Picture, the order of decoding and display is different, so they are reordered and displayed via the display macroblock buffer 17.

In this embodiment, the display macro block buffer 1
7 has only a part of the memory capacity of one frame (the sum of the solid line and the broken line in FIG. 3). However, B-Pict
When reconstructing ure, image data for two fields may be used. Nevertheless, since the display macro block buffer 17 cannot hold image data for two fields, in that case, necessary data is read again from the input bit stream buffer 11 using the read pointer 192, and a series of processing is performed. Use something.

For this reason, the processing speed of the VLD 12 is more than twice that of the conventional processing, and necessary data is decoded in time and sent to the IQ 13.

Accordingly, even when the B-Picture must be held for display, as in the case of the BB repeat shown in FIG. 4, one field of the B-Picture is stored in the input bit stream buffer 11. , Decoding, and decoding, the display can be performed even if the memory capacity of the display macro block buffer 17 is not one frame.

5 to 10 show a display macro block buffer 17 having a minimum unit capacity required for display by storing image data in a display macro block buffer 17 and frame buffers 16a and 16b in an appropriate order. FIG. 5 is an explanatory diagram showing a method of displaying. However, in the figure,
A thick arrow indicates a Picture being decoded, and a thin arrow indicates a Picture being displayed.

In FIGS. 5 and 6, B-Pict is decoded while decoding.
ure is displayed.

In the grammar of the MPEG, since the vertical motion search range is a maximum of 8 macroblocks, a total of 9 macroblocks × 1 line of 1 macroblock × 1 line for macroblock raster conversion and the 8 macroblocks × 1 line is used. If so, the P-Picture after holding 8 macroblocks × 1 line may be overwritten.

In FIG. 5, B-Picture is decoded and displayed using the display macroblock buffer 17 of the frame buffer 16a. In FIG. 6, the frame buffer 16
A is decoded and displayed by overwriting B-Picture on a.

FIG. 7 shows that the reference P-Picture is overwritten. In order to display the first B-Picture, it is necessary to decode I and P 2-Pictures for forward and backward reference. During that time (between FIG. 7 and FIG. 9), the last B-
You need to keep the Picture displayed.

FIG. 7 shows the last B-Picture while decoding the I-Picture by overwriting the frame buffer 16a. FIG. 8 shows the B-Picture again while decoding by overwriting the P-Picture on the frame buffer 16a. FIG. 9-
FIG. 10 shows the last B-Picture while decoding the P-Picture by overwriting the unnecessary B-Picture in the frame buffer 16a.

In the above-described encoding operation of the MPEG encoded bit stream, an STC (System Time Clock) in the system controller 18 is used as a reference.
Various operations are performed. The DTS (Decode Time Stamp), which is the timing at which the VLD 12 starts decoding,
The STC is determined based on the STC, and when the DTS is exceeded, decoding of the VLD 12 is started.

However, as described above, since the memory capacity of the display macro block buffer 17 is reduced, the time for buffering data is short in the above embodiment, and the decoded image is immediately displayed. The image decoding process is faster than the system decoding process.

Therefore, the decoding start control circuit 181 of the system controller 18 puts a predetermined offset on the DTS so as to delay the image output timing so as to synchronize with the audio output timing.

According to the present embodiment, when reconstructing a B-Picture, image data for two fields may be used. At this time, necessary data is read out and the input bit stream buffer is read out using the pointer 192. 11, the read data is decoded at a high speed of twice or more the conventional speed, subjected to a series of processes, and used, and
By temporarily storing display image data using a part of the frame buffers 16a and 16b as a display buffer, the memory capacity of the display macroblock buffer 17 can be reduced to a minimum of 9 macroblocks × 1 line.

Thus, the two frame buffers 16
a, 16b and the display macro block buffer 17 together have a memory capacity of 16 Mbit or less, and
A 6Mbit general-purpose memory can be used, and the memory can be used very economically.

In the above embodiment, the system controller 18 determines whether the bit stream is a B-Picture by interpreting the bit stream according to the grammar of the MPEG. As a result, in the case of B-Picture, the image read pointer 192 embedded in the bit stream is sent to the input control unit 19 to perform control not to overwrite for future re-reading, Is stored in the pointer. If the image is not B-Picture, there is no need to rewind the image read pointer.

However, it is determined whether or not the image is B-Picture.
Since the bit stream has already been interpreted by the VLD 12 according to the MPEG grammar,
The information determined by the LD 12 as B-Picture is input to the input control unit 1.
9, and may be controlled so as not to be overwritten for rereading in the future, and may be stored in a pointer for reading. With this configuration, the circuit for determining the type of Picture described above is omitted from the system controller 18, and the circuit scale of the system controller 18 can be reduced.

In cases other than B-Picture, there is no need to uselessly hold the bit stream in the input bit stream buffer 11, so that the capacity of the input bit stream buffer 11 can be held small.

Further, if the bit stream interpretation unit is an MPEG
Interpret the bit stream according to the grammar, and it is B-Pi
Unlike the configuration that holds the image read pointer 192 at the time of cture, the bit stream interpretation unit can be shared with the time of decoding, so that the circuit scale can be reduced.

The DT is controlled by the decode start control circuit 181.
Since a predetermined offset is put on S, decoding of the video,
The display time can be delayed, and when the synchronization target is slow (for example, the audio decoding / reproduction time is PTS
(If later than the Presentation Time Stamp). Furthermore, if the video synchronization and display time are delayed when the partner to be synchronized is late, the compressed data will be retained, so the memory capacity for retaining the decoded and decompressed data will be smaller than buffering the decompressed data. it can.

FIG. 11 is a block diagram showing a second embodiment of the MPEG video decoding apparatus according to the present invention. The configuration of this example is almost the same as that of the first embodiment shown in FIG. 1, but differs in that a predecoder circuit 20 for predecoding a bit stream is provided.

In this example, as in the first embodiment shown in FIG. 1, since the memory capacity of the display macro block buffer 17 is small, it is not possible to perform buffering in B-Picture units, and It will be displayed while decoding the data. Therefore, if there is an error during decoding, the error is found at the end of the decoding operation.
The error cannot be concealed and the broken picture is displayed as it is.

However, in this example, if there is an error during decoding by pre-decoding at the stage of decoding the VLD 12 or at the stage of reading the bit stream from the input bit stream buffer 11 by the input control unit 19, Since an error can be detected in advance and an image having no error before that can be displayed for error concealment, it is possible to prevent a broken picture from being displayed.

According to the present embodiment, since an error during decoding can be detected in advance by the predecoder circuit 20, an image having no error before that can be displayed for error concealment, thereby improving the apparent image quality. be able to.

[0042]

As described above in detail, according to the first or second aspect of the present invention, the B-Picture of MPEG is displayed by decoding and displaying without decoding the B-Picture in units of Picture. By reducing the memory capacity required for reconfiguration, even in the case of the PAL system, 16
With Mbit or less, a 16-Mbit memory of one chip can be used, and the memory can be used very economically.

According to the invention of claim 3, Pictur of VLD
e By using the type determination function, a circuit for determining the type of Picture from the system controller can be omitted, and the circuit scale of the system controller 18 can be reduced.

According to the fourth aspect of the invention, by providing a predecoder in the input control unit or the VLD, an error during decoding can be detected in advance, so that an image without an error before that can be used for error concealment. It can be displayed and apparent image quality can be improved.

According to the fifth aspect of the present invention, an image can be displayed in synchronization with an audio output whose decoding operation is slow by adding an offset to the decoding start timing of the bit stream.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of an MPEG video decoding device according to the present invention.

FIG. 2 is a diagram illustrating an operation of writing and reading a bit stream to and from an input bit stream buffer shown in FIG.

FIG. 3 is a diagram illustrating a configuration of one frame image data.

FIG. 4 is a diagram showing a BB repeat.

FIG. 5 is a diagram illustrating how to use a buffer when decoding and displaying a B-Picture using the frame buffer and the macroblock buffer illustrated in FIG. 1;

FIG. 6 is a diagram illustrating how to use a buffer when decoding and displaying a B-Picture using the frame buffer and the macro block buffer shown in FIG. 1;

FIG. 7 is a diagram for explaining how to use a buffer when decoding and displaying a B-Picture using the frame buffer and the macro block buffer shown in FIG. 1;

FIG. 8 is a view for explaining how to use a buffer when decoding and displaying a B-Picture using the frame buffer and the macro block buffer shown in FIG. 1;

FIG. 9 is a diagram for explaining how to use a buffer when decoding and displaying a B-Picture using the frame buffer and the macro block buffer shown in FIG. 1;

FIG. 10 is a diagram illustrating how to use a buffer when decoding and displaying a B-Picture using the frame buffer and the macroblock buffer illustrated in FIG. 1;

FIG. 11 is a block diagram showing a second embodiment of the MPEG video decoding device of the present invention.

FIG. 12 is a block diagram illustrating a configuration example of a conventional MPEG video decoding device.

[Explanation of symbols]

 Reference Signs List 11 input bit stream buffer 12 VLD 13 IQ 14 IDCT 15 MC 16a, 16b frame buffer 17 display macro block buffer 18 system controller 19 input control unit 20 predecoder circuit 181 decoding start control circuit 191 write pointer 192 read pointer

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Goichi Otomo 1 Tokoba Toshiba-cho, Komukai-ku, Kawasaki-shi, Kanagawa Prefecture (72) Inventor Koichi Kurihara 3-chome, Shimbashi, Minato-ku, Tokyo No. 3-9 Toshiba D-Buoy Co., Ltd. F-term (reference) 5C059 KK08 MA00 MA23 MC11 ME01 PP05 PP06 PP07 RB13 RC24 RF01 SS06 SS13 UA05 UA06 UA38 5J064 AA03 AA04 CA01 CB12 CB13 CC08

Claims (5)

[Claims] 1. An MPEG-encoded bit stream is once input to a bit stream buffer, and then the input bit stream is read out, decoded, inverse-quantized, and inverse discrete cosine-transformed to obtain I-Picture and B-Pictu.
When decoding and reproducing re, P-Picture, B-Picture, P-Picture
In an MPEG video decoding apparatus for reconstructing a Picture using a frame buffer and outputting a display image via a display buffer, a part of data necessary for displaying a B-Picture is stored in the display buffer. MPEG video decoding characterized in that necessary data among the data not retained is read out from the bit stream buffer, decoded at high speed, inversely quantized, and inverse discrete cosine transformed. apparatus. 2. The MP according to claim 1, wherein a display macro block buffer memory for storing 9 macro blocks × 1 line is used as the display buffer.
EG video decoding device. 3. The bit stream buffer,
When reconstructing a picture, a control unit that reads out necessary data from the non-retained data from the bit stream buffer using a read pointer embedded in the bit stream is provided. 3. The MPEG video decoding apparatus according to claim 1, wherein: 4. A pre-decoding means for pre-decoding the bit stream connected to at least one of a means for reading a bit stream from the bit stream buffer and a means for decoding the read bit stream; Detecting means for detecting an error during decoding by pre-decoding the bit stream, and when the error is detected by the detecting means, display means for displaying a previous error-free image for error concealment, The MPEG video decoding apparatus according to any one of claims 1 to 3, further comprising: 5. A decoding start timing of a bit stream read from the bit stream buffer,
5. The MPEG video decoding apparatus according to claim 1, wherein a predetermined offset time is added.