JP2001084158A - Microprocessor and emulation system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the developing efficiency of a user system. SOLUTION: This microprocessor is provided with a control means 216D which asserts a fault signal for realizing the transition of a central processing unit (213) to an instruction waiting state after unstuck, and releases the instruction waiting state of the central processing unit when a request signal for the release of the instruction waiting state is asserted in the instruction waiting state of the central processing unit. The fault signal is asserted by the control means, and when the request signal for the release of the instruction waiting state is asserted in the instruction waiting state of the central processing unit, the instruction waiting state of the central processing unit is released. Thus, it is possible to improve the developing efficiency of the user system by synchronizing different microprocessors, and parallelizing emulation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer and an emulation system for system debugging in the microcomputer.

[0002]

2. Description of the Related Art In the development of microprocessor (microcomputer) application equipment, an in-circuit emulator is used to debug an application system and to evaluate the system in detail. The in-circuit emulator consists of a parent computer for software development,
It is connected to the target system under development and acts as a debugger while taking over the functions of the microprocessor (target processor) included in the target system, and supports detailed system debugging. In such an emulator, the end of a cable extended from the main body can be coupled to a target system via a plug such as a socket for a target processor,
In addition, various debugging functions such as a real-time tracing function that samples various data and status signals in real time during emulation execution and stores them in a trace memory unit, etc., and a break function that substantially stops emulation operation are provided. .

In addition, an on-chip function for tracing the execution state of software in real time, and for reading / writing data from / in a built-in RAM (random access memory) for debugging, while being a real chip. A microcomputer having a debugging function is provided. Here, the real chip refers to a CPU actually mounted on the user system, and is distinguished from an emulation chip configured to output necessary information in emulation to the outside.

As an example of a document describing the operation of the emulator, there is "All about microcomputer development (pages 78 to 95)" issued by Denpa Shimbun on June 20, 1989.

[0005]

In some user systems, a plurality of CPUs (central processing units) may be mounted in order to improve the processing capability. In the conventional emulation, basically, one emulator is required for each CPU.
In a user system in which U is mounted, basically two emulators are required.

However, even if two emulators are connected to a user system equipped with two CPUs, the two CPUs are not synchronized with each other.
Emulation cannot be performed at the same time. In other words, even if two emulators are connected to the user system, the execution of the target program is stopped in the other emulator during one emulation, or the other C emulator is stopped during the one emulation.
An actual chip was mounted on the PU socket.

In the emulation of a user system equipped with two CPUs as described above, even if two emulators are connected, the emulation must be performed separately, thereby improving the development efficiency of the user system. Was hindered.

An object of the present invention is to provide a technique for improving the development efficiency of a user system.

Another object of the present invention is to provide a technique for enabling simultaneous execution of target programs in emulation of a user system having a plurality of CPUs.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, when a break condition is satisfied during execution of a user program, stack processing for transitioning to the break mode is performed, and a return instruction for returning from the break mode is executed in the break mode, thereby returning to the user mode. A central processing unit for performing an unstack process for transition, and asserting a fault signal for causing the central processing unit to transition to an instruction waiting state after the unstacking, and in the instruction waiting state of the central processing unit, The microprocessor includes a control unit for releasing the instruction waiting state of the central processing unit when the waiting state release request signal is asserted.

According to the above means, the control means asserts the fault signal, and in the instruction waiting state of the central processing unit, the release request signal of the instruction waiting state is asserted, whereby the central processing unit is controlled. Release the instruction waiting state. This synchronizes different microprocessors and achieves an improvement in user system development efficiency by emulation parallelization.

Further, when a break condition is satisfied during execution of the user program, a stack process for transitioning to the break mode is performed, and a return instruction for returning from the break mode is executed in the break mode, thereby returning to the user mode. A central processing unit that performs an unstacking process for transition, a discrimination flag storage unit that stores a discrimination flag of a vertical relation, and a case where the state of the discrimination flag stored in the discrimination flag storage unit indicates a higher order
When the state of the first control means for asserting the instruction-waiting state release request signal output to the outside of the microprocessor after the unstack processing and the state of the discrimination flag stored in the discrimination flag storage means indicate lower, After unstacking, a fault signal for causing the central processing unit to transition to the instruction waiting state is asserted, and in the instruction waiting state of the central processing unit, the release request signal is asserted, whereby the instruction of the central processing unit is asserted. And a second control unit for canceling the waiting state.

According to the above-mentioned means, the second control means asserts a fault signal, and in the instruction waiting state of the central processing unit, asserts a signal for requesting release of the instruction waiting state. Cancel the instruction wait state. This synchronizes different microprocessors and achieves an improvement in user system development efficiency by emulation parallelization.

At this time, a bus controller for asserting a fault signal for causing the central processing unit to transition to an instruction execution waiting state in response to a bus request or a bus release request from the outside, and a fault signal from the bus controller. A gate circuit which obtains a logical sum of the fault signal from the fault control circuit and supplies the logical sum to the central processing unit can be provided.

And such a microprocessor,
An emulation system is configured including the emulator body.

[0018]

FIG. 5 shows an example of the overall configuration of an emulation system according to the present invention.

As shown in FIG. 5, this emulation system is not particularly limited, but the user system 5
1st emulation processor 511 mounted on 1
And the second emulation processor 512, the emulator main body 52, and the control computer 53.

The user system 51 has two CPU sockets, each of which is equipped with a CPU. The first emulation processor 511 and the second emulation processor 512 have basically the same functions as the real chip originally mounted on the user system 51, and are configured to enable external output of internal bus information. Chip.

Both the first emulation processor 511 and the second emulation processor 512 have an on-chip debugging function that enables debugging while the chip is mounted on a system board. In particular, the first
The emulation processor 511 includes a connector 513 provided in the vicinity thereof and a cable 5 coupled thereto.
By being connected to the emulator main body 52 through the emulator 24, debugging by the above-mentioned on-chip debugging function is performed. The external terminal of the second emulation processor 512 is connected to the C of the user system 51.
It is coupled to the user system via the PU socket and to the emulator main body 52 via the cable 525. Thus, the emulation information of the second emulation processor 512 can be collected in the emulator main body 52. Although not particularly limited, the control computer 53 is a personal computer, and is connected to the emulator main body 52 via a cable 516.
, Exchange of various control information and collected data relating to emulation with the emulator main body 52 is enabled.

FIG. 1 shows an example of the configuration of the emulator main body 52.

As shown in FIG. 1, the emulator main body 52 has, although not particularly limited, emulation functions different from each other, such as an in-circuit emulation (ICE) function and an on-chip debugging function. The ICE function is realized by the ICE function block. This ICE function block includes a control CPU 1
1, break circuit 12, trace circuit 13, monitor circuit 14, firmware RAM (random access memory)
15 and a performance circuit 16. The on-chip debugging function is realized by the control CPU 11 and the on-chip controller 17.

The control CPU 11 controls the break circuit 12 and the trace circuit 1 via a control bus 23.
3. It is coupled to the monitor circuit 14, the firmware RAM 15, the performance circuit 16, and the on-chip controller 17 so that various kinds of information can be exchanged therewith. Also, the second emulation processor 512
Is connected to the break circuit 1 via the emulation bus 24.
2, trace circuit 13, monitor circuit 14, firmware RA
M15, and the second
It is possible to collect various information in the emulation operation of the emulation processor 512. The on-chip controller 17 is connected to the first emulation processor 511 via a signal line 25, and can exchange various information according to a predetermined communication protocol described later.

The break circuit 12 monitors the state of the emulation bus 24, and breaks the emulation operation when the state reaches a preset state. The trace circuit 13 includes an emulation bus 24
Are sequentially traced and stored. The monitor circuit 14 is provided to enable the control computer 53 to monitor the emulation bus 24 via the interface 21. The firmware RAM 15 is provided to store a program executed by the second emulation processor 512. The performance circuit 16 performs the second emulation processor 512 based on the trace information.
It is provided to measure performance of, for example, measurement of execution time.

The on-chip controller 17 is a block that enables on-chip debugging of the first emulation processor 511 under the control of the control CPU 11, and is configured as follows.

FIG. 2 shows the on-chip controller 17.
Is shown.

As shown in FIG. 2, the on-chip controller 17 has a JTAG controller 170 for outputting various signals in JTAG, a bus controller 176, and a clock generation circuit 177. The JTAG controller 170 has buffers 171 to 174 and a register 175 for outputting various signals in JTAG. Clock generation circuit 177 includes an oscillator for generating a clock signal of a fundamental frequency, and a frequency dividing circuit for generating a clock signal of a frequency different from the original frequency by appropriately dividing the generated clock. . The clock signal output from the clock generation circuit 177 is transmitted to the TC
It is transmitted to the first emulation processor 511 as K. The output data TDo is transmitted to the bus controller 176 via the buffer 171, and a signal TD for serially inputting an instruction or data to the test logic is output.
i, a signal TMS for controlling the test operation, a clock signal TCK supplied to the test logic, and a reset signal TRST for initializing the controller are output via buffers 172 and 173 and a register 175, respectively.
The bus controller 176 includes the buffers 171 and 17
2, 173, and the register 175, and signals can be exchanged between the control bus 23.

Although not particularly limited, the first emulation processor 511 and the second emulation processor 512 have the same configuration.

FIG. 3 shows a configuration example of the first emulation processor 511 (512).

As shown in FIG. 3, the first emulation processor 511 (512)
3, RAM 212, serial debug interface 2
11, a peripheral module 215, and an emulation bus controller 216.

When a predetermined program is executed by the CPU 213, the RAM 212 functions as a work area for the arithmetic processing. The serial debug interface 211 is connected to the on-chip controller 17 in the emulator main body 52 to enable the exchange of serial data.

A bus controller 214 is provided.
Weight control between the U 213 and the peripheral module 215 and weight control between the CPU 213 and the external module are performed. Although not particularly limited, the peripheral module 215 enables a serial communication interface that enables serial communication with an external device, a timer for measuring time, and enables data transfer between devices without the intervention of the CPU 213. It includes a direct memory access controller and the like.

The serial debug interface 21
1D is a communication module 211A, a firmware RAM 2
11B, a break circuit 211C, and a trace buffer 211D. The communication module 211A performs communication for on-chip debugging with an external device. Various programs executed by the CPU 213 are stored in the firmware RAM 211B. The break circuit 211C is
It is determined whether a preset break condition has been satisfied. The trace buffer 211D traces a program execution state of the CPU 213.

The emulation controller 21
6 is connected to the internal bus 218 and the emulation bus 24, and performs various controls related to emulation.
Although not particularly limited, the emulation controller 2
16 includes an upper / lower register 216A, a break stack register 216B, a break control circuit 216C, and a fault control circuit 216D. The upper / lower register 216A holds flag information for determining whether the emulation processor containing it is higher or lower in relation to other emulation processors. Although not particularly limited, in FIG. 1, the emulation processor 511 coupled to the emulation bus 24 is ranked higher and the emulation processor 512 coupled to the on-chip controller 17.
Is the lower order. The difference between the upper order and the lower order is largely different in the state after the completion of the unstacking by executing the return instruction from the break mode to the user mode. This will be described later in detail.

When the break condition is satisfied and the state of the CPU 213 shifts from the user mode to the break mode, the break stack register 216B stores the register (EXR, CCR) and program counter (PC) at that time.
And so on.

The break control circuit 216C controls input / output of a break control signal. The break control signal includes a break interrupt request signal, a break acknowledge signal, and the like. The break interrupt is set to low active,
When it is activated, the break control circuit 216
C causes a break interrupt to the CPU 213. A break process is performed by this break interrupt, and the values of the registers (EXR, CCR) and the program counter (PC) at that time are held in the break stack register 216B. CPU by break interrupt
When 213 shifts to the break mode, the break control circuit 216C sets the break acknowledge signal to low level, indicating that the break mode has been set. The break acknowledge signal is at a low level during the break mode, and is set to a high level after the end of the stack of the return from break (RTB) instruction. That is, the break mode is released by executing a dedicated return (RTB) instruction, and the mode is changed from the break mode to the user mode.

A first fault signal FLT1 is output from the bus controller 214, and a second fault signal FLT2 is output from the emulation controller 216. The OR logic of the first fault signal FLT1 and the second fault signal FLT2 is obtained by the OR gate 217, and the OR logic is transmitted to the CPU 213.

The first fault signal FLT1 has a bus request from the outside of the microprocessor or a bus release request from another bus master to the bus controller 214. As a result of bus arbitration, the bus right should be released. In this case, it is asserted high by the bus controller 214. When the first fault signal FLT1 is asserted to a high level, the CPU 213
When the first fault FLT1 is asserted to the high level, the execution of the instruction is stopped while maintaining the internal state (the value of the program counter or the like) (fault state). This releases the bus from the CPU 213.

The second fault signal FLT2 is
It is controlled by the fault control circuit 216D according to the flag state of the upper / lower register 216. That is, when the flag state of the upper / lower register 216 is set to the low level and the emulation processor is set to the lower level, the CPU 213 issues a return instruction from the break mode.
After that, the second fault signal FLT2 is asserted to a high level by the fault control circuit 216D. As a result, in the CPU 213, as in the case where the first fault FLT1 is asserted to the high level, the execution of the instruction is stopped while maintaining the internal state (the value of the program counter or the like) (fault state). This fault condition indicates that the emulation controller 216
Is asserted to a low level, the second fault signal FL
It is maintained until T2 is negated to a low level. That is, when the fault release request signal given from outside the emulation controller 216 is asserted to a low level, the fault control circuit 216D negates the second fault signal FLT2 to a low level. Thereby, the fault state of the CPU 213 is released. Such a control function in the fault control circuit 216D corresponds to the second control means in the present invention.

On the other hand, the upper / lower register 216
When the flag state of A is set to the high level and the emulation processor is set to the higher level, the fault control circuit 216D externally releases the fault to another CPU without asserting the second fault signal FLT2. Assert the request signal. Fault control circuit 2
This control function in 16D corresponds to the first control means in the present invention.

FIG. 4 shows a configuration example of the communication module 211A.

As shown in FIG. 4, the communication module 211A is a JTAG-compatible TAP controller 211.
A-1, an input register 211A-2, and an output register 211A-3. TAP controller 211
A-1 receives a clock signal TCK supplied to the test logic, a reset signal TRST for initializing the controller, and a signal TMS for controlling a test operation. The TAP controller 211-A1 analyzes input commands and performs input / output control based on the analysis. Input register 211A-2 and output register 211A-3
Although not particularly limited, is a shift register having a 32-bit configuration, and shifts the signals TDi and TDo fetched in serial form, respectively.

Next, the return from the break mode to the user mode will be described in detail.

FIG. 6 shows a first emulation processor 511 and a second emulation processor 512
5 shows a procedure from the break mode to the return to the user mode. FIG. 7 shows the operation timing of the main part in that case.

The first emulation processor 511 is a lower-level processor, and the second emulation processor 512 is an upper-level processor.

In the first emulation processor 511, while the program stored in the firmware RAM 211B is being executed, the return (RTB) instruction from the break mode is executed, so that the program counter (PC) and the like are unloaded. Stacking is performed (S711, S721). In this unstack, the flag state of the upper / lower register 216 is checked. Since the first emulation processor 511 is a lower-level processor, the upper / lower register 21
The flag state of No. 6 is at a low level. As a result, the second fault signal FLT2 is asserted to a high level, and the CPU 213 in the first emulation processor 511 is placed in a fault (waiting for the next instruction) state.
That is, despite the unstacking of the program counter (PC) and the like in step S712,
The execution state of the first instruction in the user mode is awaited. This state continues until a fault release request is made from the second emulation processor 512, which is a higher-level processor.

On the other hand, the second emulation processor 5
At 12, during the period when the program stored in the firmware RAM 15 (see FIG. 1) is being executed,
By executing the return from break mode (RTB) instruction, unstacking of the program counter (PC) and the like is performed (S721, S722). In this unstack, the flag state of the upper / lower register 216 is checked. Second emulation processor 5
Since 12 is an upper level processor, the flag state of the upper / lower register 216 is at a high level. Thereby, the emulation controller 216
When the fault release request signal is asserted to a low level, the first emulation processor 511
Is issued (S723). After this release request, the second emulation processor 512
Transitions to the execution of the user program.

Here, when the low-level fault release request signal is transmitted to the first emulation processor 511, the first emulation processor 511 sets the second fault signal FLT2 low by the fault control circuit 216D in the emulation controller 216. Negated to level. As a result, the fault state is released, and the CPU 213 starts executing the user program.

According to the above example, the following functions and effects can be obtained.

(1) When the first emulation processor 511 at the lower level returns from the break mode (R
TB) After executing the instruction, a fault state occurs, and a fault release request (S723) is issued from the second emulation processor 512, which is an upper level, so that the fault state of the first emulation processor 511 is released. The first emulation processor 511 and the second emulation processor 512 are synchronized with each other. That is, even if asynchronous processing is performed in the break mode, the first emulation processor 511 and the second emulation processor 512 perform synchronous processing at the time of starting execution of the user program after returning from the break mode. For this reason, since the first emulation processor 511 and the second emulation processor 512 can be simultaneously executed and emulated, the development efficiency of the user program can be improved.

(2) The emulator main body 52 may be one, and there is no need to separately prepare an emulator for ICE and an emulator for on-chip debugging.

Another configuration example will be described.

As shown in FIG. 8, the on-chip debug emulator main body 85 and the emulator main body 86 may be configured separately. The on-chip debug emulator main body 85 basically includes the on-chip controller 17, the control CPU 11, the interface 21 and the like in FIG.
Trace circuit 13, monitor circuit 14, firmware RAM1
5 and the ICE function realization block such as the performance circuit 16 are not included. The emulator main body 86 includes a break circuit 12, a trace circuit 13, a monitor circuit 14, a firmware RAM 15, a performance circuit 16, a control CPU 11, and an interface 2 in FIG.
1, but the on-chip controller 17 is not included. The control computer 81 is connected to the lower microprocessor side emulator 85, and the upper microprocessor side emulator 86.
Is connected to a control computer 82.

As shown in FIG. 9, the two microprocessors 511 and 512 may perform emulation via an emulation bus.
In this case, the emulator bodies 85 and 86 correspond to the break circuit 12, the trace circuit 13, the monitor circuit 14, the firmware RAM 15, the performance circuit 16, the control CPU 11, and the interface 2 in FIG.
1 and the like.

As shown in FIG. 10, there are cases where two microprocessors shown in FIG. 3 are provided in one microprocessor package. In such a case, the present invention can be applied. In this case, the emulator main body 52 is provided with ICE function realization blocks corresponding to the two microprocessors.

Further, as shown in FIG. 11, when two microprocessors are provided in one microprocessor package, signals are exchanged with the emulator main body by a serial debug interface. be able to. In this case, in the emulator main body 52, two systems of the on-chip controller 17 and the like are provided.

As shown in FIG. 12, the connection relationship between the first emulation processor 511, the second emulation processor 512, and the emulator main body 512 may be made switchable. That is, the control circuit 18 is provided, and to which of the first emulation processor 511 and the second emulation processor 512 the emulation bus 24 is connected is controlled by the control circuit 18. A selector (SEL) 19 is provided, and the on-chip controller 17 selectively
It is connected to the emulation processor 511 and the first emulation processor 512. The above selector 19
Is controlled by the control circuit 18. When data can be exchanged between the first emulation processor 511 and the emulation bus 24 under the control of the control circuit 18, the second emulation processor 512 is disconnected from the emulation bus 24. At this time, the second emulation processor 512 is coupled to the on-chip controller 17 via the selector 19 under the control of the control circuit 18 so that the second emulation processor 51
2 enables on-chip debugging. Similarly, when data can be exchanged between the second emulation processor 512 and the emulation bus 24 under the control of the control circuit 18, the first emulation processor 511 is disconnected from the emulation bus 24. At this time, the control circuit 1
By coupling the first emulation processor 511 to the on-chip controller 17 via the selector 19 under the control of 8, the on-chip debugging in the first emulation processor 511 is enabled.

The present invention can be applied to a case having three or more microprocessors. That is, by setting one of the three or more microprocessors to the higher order and setting all the other microprocessors to the lower order, the same operation and effect as in the above-described example can be obtained.

The release request signal for the fault state may be generated from the control CPU 11.
FIG. 13 shows a configuration example in that case. in this case,
After all of the three microprocessors 511, 512, and 513 are faulted, a fault release request signal supplied from the control CPU 11 to the three microprocessors 511, 512, and 513 can be configured to be asserted. . As a result, the three microprocessors 511, 512, and 513 are simultaneously released from the fault state, and the synchronous execution of the user program is enabled. FIG. 14 shows a specific configuration in this case. An on-chip controller 141 for enabling on-chip debugging of the third emulation processor 513 is provided. The fault release request signal is sent to each emulation processor 51
Control CPU 11 instead of 1, 512, 513
Formed by

Although the invention made by the present inventor has been specifically described above, the present invention is not limited to this, and it goes without saying that various modifications can be made without departing from the gist of the invention.

In the above description, mainly the case where the invention made by the present inventor is applied to a microprocessor, which is the field of application as the background, can be widely applied to various data processing devices.

The present invention can be applied on condition that at least a CPU is included.

[0064]

That is, a fault signal for causing the central processing unit to transition to the instruction waiting state after unstacking is asserted, and in the instruction waiting state of the central processing unit, the instruction waiting state release request signal is asserted. Accordingly, the microprocessor is configured to include the control means for canceling the instruction waiting state of the central processing unit, so that the instruction waiting state cancel request signal is asserted in the instruction waiting state of the central processing unit. The instruction waiting state of the central processing unit is released. Thereby, different microprocessors can be synchronized, and the parallelization of emulation can improve the development efficiency of the user system.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of an emulator main body in an emulation system according to the present invention.

FIG. 2 is a block diagram illustrating a configuration example of an on-chip controller 17 included in the emulator body.

FIG. 3 is a block diagram illustrating a configuration example of an emulation processor used in the emulation system.

FIG. 4 is a block diagram illustrating a configuration example of a communication module included in the emulation processor.

FIG. 5 is an explanatory diagram of an overall configuration example of the emulation system.

FIG. 6 is a flowchart showing a process from the break mode to the return to the user mode in the emulation processor.

FIG. 7 is a timing chart from the break mode to the return to the user mode in the emulation processor.

FIG. 8 is an explanatory diagram of another configuration example of the emulation system.

FIG. 9 is an explanatory diagram of another configuration example of the emulation system.

FIG. 10 is an explanatory diagram of another configuration example of the emulation system.

FIG. 11 is an explanatory diagram of another configuration example of the emulation system.

FIG. 12 is a block diagram illustrating a configuration example of an emulator main body in another configuration example of the emulation system.

FIG. 13 is an explanatory diagram of another configuration example of the emulation system.

FIG. 14 is a block diagram showing a configuration example of an emulator main body in another configuration example of the emulation system.

[Explanation of symbols]

 Reference Signs List 11 control CPU 12 break circuit 13 trace circuit 14 monitor circuit 15 firmware RAM 16 performance circuit 17 on-chip controller 18 control circuit 19 selector 21 interface 23 control bus 24 emulation bus 211 serial debug interface 211A communication module 211B firmware RAM 211C break circuit 211D Trace buffer 212 RAM 213 CPU 214 Bus controller 215 Peripheral module 216 Emulation controller 216A Upper / lower register 216B Break stack register 216C Break control circuit 216D Fault control circuit 217 OR gate 511 First emulation processor 512 Second emulation Activation processor

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Hideya Fujita, Inventor 5--20-1, Kamimizuhoncho, Kodaira-shi, Tokyo Within the Semiconductor Group, Hitachi, Ltd. 20-1 chome, Hitachi, Ltd., Semiconductor Group (72) Inventor Shigesumi Matsui 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Co., Ltd. Within the Hitachi, Ltd. Semiconductor Group (72) Inventor Tadashi Hashimoto Tokyo Hitachi, Ltd. Semiconductor Group Co., Ltd. (72) Inventor Hiroshi Kaneko 5-2-1, Josuihoncho, Kodaira-shi, Tokyo F-term within Hitachi Semiconductor Group, 5-2-1, Josuihoncho, Kodaira-shi, Tokyo (Reference) 5B042 HH03 HH25 HH30 LA07 MC03 MC08 5B048 AA11 BB02

Claims (5)

[Claims] When a break condition is satisfied during execution of a user program, a stack process for transitioning to the break mode is performed, and a return instruction for returning from the break mode is executed in the break mode to enter the user mode. A central processing unit for performing an unstack process for making a transition; asserting a fault signal for causing the central processing unit to transition to an instruction waiting state after the unstacking; Control means for releasing the instruction waiting state of the central processing unit by asserting the waiting state release request signal. 2. When a break condition is satisfied during execution of a user program, a stack process for transitioning to the break mode is performed, and a return instruction for returning from the break mode is executed in the break mode to enter the user mode. A central processing unit for performing an unstack process for making a transition, comprising: a determination flag storage unit configured to store a determination flag of a vertical relationship; and a determination flag stored in the determination flag storage unit. If the state of the instruction indicates a higher order, first control means for asserting, after the unstack processing, an instruction waiting state release request signal output to the outside of the microprocessor, and a discrimination flag stored in the discrimination flag storage means If the status indicates lower, after the above unstacking, the central processing unit is ordered. A second control unit for asserting a fault signal for causing a transition to a wait state, and releasing the instruction wait state of the central processing unit by asserting a release request signal in the instruction wait state of the central processing unit; And a microprocessor. 3. A bus controller for asserting a fault signal for causing the central processing unit to transition to an instruction execution wait state in response to a bus request or a bus release request from outside, a fault signal from the bus controller, 3. The microprocessor according to claim 2, further comprising: a gate circuit that obtains a logical sum of a fault signal from the fault control circuit and supplies the logical sum to the central processing unit. 4. An emulation system comprising: a plurality of processors; and an emulator main body that enables a target program to be debugged by executing the target program on the processor, wherein the micro processor according to claim 2 or 3 is used as the processor. An emulation system characterized by applying a processor. 5. The emulation system according to claim 1, wherein the emulator main body includes a plurality of emulation function realization blocks having different schemes, and a selection unit for selectively assigning the plurality of emulation functions to the microprocessor. .