JP2001084156A - Semiconductor testing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To batch set the same data to a large number of tester pins by a single data transfer by providing pin blocks for selecting a signal and outputting the signal as a write enable(WE) signal. SOLUTION: Each of pin blocks 1 to n has a pin assign block 2 for storing a pin assign number characteristic to a tester pin, a pin define block 6 for storing a pin No. being the same pin in a plurality of DUT(device under test), and a pin group block 11 for storing that a function is the same. For example, a multiplexer(MUX) 10 selects and outputs the block 2 by the output signal of an AND gate 9. An MUX 16 selects a terminal A by the output signal of an AND gate 17. When a setting object pin number is inputted from a line 23, coincidence is obtained by an XNOA 15 and a WE signal at a pin assign number is outputted from the MUX 16.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DUT (Dev
The present invention relates to data transfer means for simultaneously measuring a plurality of devices under test (ice under test). The present invention can also be applied to semiconductor test equipment for logic and the like.

[0002]

2. Description of the Related Art First, an outline of a conventional semiconductor test apparatus will be described. Although the configuration differs slightly depending on the model, FIG. 8 shows a basic schematic diagram of a semiconductor test apparatus called a so-called perpin tester as an example. There is one or more blocks, commonly called CHD (Child) 44, surrounded by long and short dotted lines, and the number varies depending on the number of simultaneous measurements of the DUT.

A test processor 40 controls the entire apparatus. Then, the data of the test program input from the input unit 49 is transferred to a necessary register group via the tester bus 51 and an interface (I / F) 42 as necessary. The logic pattern generation unit 41 generates a logic application pattern to be applied to the DUT 60 based on the data transmitted to the register group, transmits the generated logic application pattern to the plurality of pulse pattern generation units 45, and generates an expected value pattern corresponding to the logic application pattern. Is generated and given to the plurality of logical comparison units 48.

The pulse pattern generator 45 mainly comprises a timing generator and a waveform shaper. The pulse pattern generator 45 receives the applied pattern from the logic pattern generator 41, shapes the test pattern into a test signal waveform, and supplies the test signal waveform to the driver 46. Pulse pattern generator 45
Are prepared for the number of pins of the driver 46. Driver 4
6 is a test signal waveform having a predetermined applied voltage waveform as D
It is given to the input pin of UT60. That is, the plurality of pulse pattern generators 45 and the driver 46 form a pair,
A test signal is applied to the input pin of T60.

[0005] The response signal from the output pin of the DUT 60 is applied to a comparator 47 and converted into a logical pattern. This logic pattern is provided to the logic comparison unit 48.
The logical comparator 48 logically compares the logical pattern of the test result from the comparator 47 with the expected value pattern from the logical pattern generator 41 to detect a match / mismatch.
The quality of the UT 60 is determined. In general, the DUT 60 is tested by the operation of the semiconductor test apparatus as described above.

Incidentally, a semiconductor test apparatus for measuring a memory IC is generally required to measure a large number of DUTs 60 at the same time. This is to reduce test costs. Although the number of simultaneous measurement DUTs may be as large as 64 or more, this specification mainly describes the case of simultaneous measurement of four DUTs. In order to perform simultaneous measurement, data such as waveform mode, voltage level, and timing must be set to tester pins corresponding to each DUT pin of the register group such as the pulse pattern generation unit 45 and the logic comparison unit 48 in FIG. Must.

This will be described with reference to FIG. For example, FIG.
Attention is paid to DUTa of (A). The pins A0 to A7 of DUTa are address pins. The address pin A0 of this DUTa
Normally, the same data such as the waveform mode, the voltage level, and the timing are set to the tester pins corresponding to .about.A7. Looking at other DUTs, the same data is set to the tester pins corresponding to the address pins A0 to A7 of DUTb to DUTd. That is, the address pins A0 to A7 of the DUTa, the DUT
b address pins A0-A7, DUTc address pins A0-
The same data is set to the tester pins corresponding to the address pins A0 to A7 of A7 and DUTd.
FIG. 9B shows an example of the correspondence between the DUT pins and the tester pins. Even for the same DUT pin, the tester pin is given a different series of unique numbers.

When data containing a test program is transmitted to these tester pin register groups, the data shown in FIG.
Are transferred from the input unit 49, for example, a magnetic disk to the register group of each unit via the test processor 40, the tester bus 51, and the interface 42. At this time, in the conventional semiconductor test apparatus, the same data is repeatedly transmitted for each tester pin, that is, for each register of the tester pin to which a unique number (No .; number) is assigned.

FIG. 10 shows a conventional transfer diagram. Input unit 49
From the test processor 40 and the tester bus 5
1 and the I / F 42 are transferred to the register groups of the logical pattern generator 41, the pulse pattern generator 45, and the logical comparator 48. As described above, the same data such as the waveform mode, timing, and input / output level is repeatedly transmitted and set for each register of the tester pin to which the unique number is assigned.

[0010] That is, in FIG.
Select the register to save the setting of (1), send data (Deta), and write it to the register of pin 1. Next, similarly, the pin 2 is selected, the same data as the previous time is sent, and the data is written into the register of the pin 2. Thereafter, the same data is sent many times by selecting the register up to pin n in the same manner. FIG. 10B shows a flowchart in this case.

[0011]

The conventional data transfer means can transfer data correctly. However, sequentially transferring the same data to each of a large number of tester pin registers is too time-consuming and wasteful.

According to the present invention, when the same data is set for a large number of tester pins as in the case of simultaneous measurement of a large number of pieces, the same concept is used in the DUT direction in FIG. Pin groups and pin groups (PinGr.) For the same function pins such as control pins such as address pins, data pins, and write enable
oup), a data transfer means for collectively transferring data to a tester pin register for storing the same data is provided.

Here, the concepts of pin define and pin group will be described. FIG. 2 is an explanatory diagram of the concept of pin definition and pin group. As shown in FIG. 2, a plurality of DUTs, DUTa, DUTb, DUTc, DUT
The same pin of UTd, for example, all A0 pins of DUT
Define as the same pin in define. Similarly, the A1 pin of all DUTs and the A7 pin of all DUTs are defined by pin definition. On the other hand, address pins A0 to A7, data pins, and various control pins are grouped in a pin group.

Although the concept of pin definition has been conventionally known as a theoretical concept in a memory tester, it has not been possible to know which pin block the tester pin itself belongs to in a hardware configuration. As described above, the same data setting is transferred many times for each pin. The concept of pin groups existed in logic testers but not in hardware in memory testers.

The present invention uses the concept of a new pin define and pin group so that the tester pin channel itself can know which pin block it is on in hardware. That is, in the concept of pin definition, each tester pin stores and recognizes that each is the same pin of a plurality of DUTs, and in the concept of pin group, stores and recognizes that the pins are the same function pin. Hardware that can process the two concepts in combination is provided so that the same data can be set to a large number of tester pins by a single data transfer.

[0016]

To achieve the above object, the present invention provides a new pin block for each tester pin. The pin lock may be provided in each of the pin modules, or may be provided collectively in the I / F. The main configuration of this pin block is a pin assignment block that stores a pin assignment number that is a series of numbers (No .; number) unique to the tester pin, and a pin No that is the same pin in a plurality of DUTs. .
And a pin group (Pi Define) block that stores the same function.
n Group) block, and a plurality of input gates and a plurality of output gates.

It is assumed that the definition of the pin definition and the grouping of the pin groups as shown in FIG. 2 have been performed in advance, and the test program has been generated. In a pin block having the number of tester pins, pin assignment is first set. This stores the serial number as a unique number in each pin assignment block. For example, the tester pin No. in FIG. With this setting, each pin block knows its own pin No. Therefore,
After that, when common data is transmitted to the tester bus, the setting is performed by determining whether each pin block itself is targeted.

Next, pin definition is set. A plurality of numbers defined by pin-definition and the refined data are transmitted via the tester bus. Each pin block stores the refined data in the pin define block when the transmitted pin define No. matches its own unique No. The defined data stores a predetermined number of a group of numbers defined by pin define.

Next, a pin group is set. There are two ways to perform pin grouping. In other words, do you use your own unique pin assignment No. or pin definition N?
o. DU if done with Pin Assign No.
Grouping is performed for each T. When the grouping is performed with the pin definition No., the grouping is performed including all the DUTs. The selection is made by selecting the output signal of the pin assign block and the output signal of the pin define block by a gate circuit and applying the selected signal to the pin group block.
Then, the No. is added to the grouping data from the tester bus.
, The data is latched and stored as a 1-bit pin grouping signal. By the means described above, the pin assignment No., the pin definition No., and the pin grouping signal unique to the self are stored.

Then, WE (Write) is stored in the register for storing various setting data such as the waveform mode from the pin block.
Enable) signal output. When outputting, one of the above three data or signals stored in the pin block is selected by a gate circuit. In the case of data, the signal is converted into one signal by a coincidence circuit, and the WE signal is given to the register of the corresponding tester pin as a WE signal. The register of the corresponding tester pin is assigned to the register of each tester pin in the case of pin assignment No., and to the register of the tester pin corresponding to the same pin of all DUTs in the case of pin definition No. In this case, the WE signal is supplied to the register of the tester pin corresponding to each DUT group or all DUT groups, and the same data from the tester bus is stored simultaneously and collectively. Therefore, it is possible to simultaneously set the pin definition and the pin group in combination.

The operation of the simultaneous setting means combining the pin define and the pin group will be described with reference to FIG.
The case of FIG. 2 will be described. 1. A tester pin No. corresponding to the same pin in the DUT direction is defined as pin define. 2. Tester pins No. corresponding to the same function pins are grouped as a pin group. 3. Set waveform mode, voltage level, timing, etc. to pin 1. 9, 17, 25 pin-defined pins
Expanded to pins. 5. 2, 3, grouped in the same group as pin 1.
Expanded to 4, 5, 6, 7, and 8 pins. 6. Pin-defined pins 10, 18, 2
Expanded to 6 pins. 7.3 Pins 11, 19, 2 pin defined
Expanded to 7 pins. 12, 20, 2 pin-defined as 8.4 pins
Expanded to 8 pins. 13, 21, 2 pin-defined as 9.5 pins
Expanded to 9 pins. 14, 22, pin-defined as 10.6 pins
Expanded to 30 pins. 15, 23, pin-defined as 11.7 pins
Expanded to 31 pins. 16, 24 pin-defined as 12.8 pins
Expanded to 32 pins. Here, for the sake of explanation, it is shown that the pins are developed step by step, but in actuality, only one setting to one pin is performed as shown in FIG.
And the same data is set for all tester pins.

The configuration of the invention will be described. The first invention is a basic invention. That is, the test program data input from the input unit is transferred to a plurality of tester pin registers via a test processor and a tester bus, and a plurality of test pattern signals and expected value pattern signals are generated based on the transferred data. In a semiconductor test apparatus for simultaneously measuring a DUT, a pin for storing a pin assignment number unique to a tester pin from a tester bus by a control signal.
An assign block, and a pin define block that stores a pin define number from the tester bus by a control signal when the pin number to be measured in the data transferred from the tester bus is the pin assign number.
A pin group block for latching a grouping signal by a control signal when the grouping data transferred from the tester bus matches the pin assign number or the pin define number; The number of pin blocks for selecting the number or the pin definition number or the grouping signal and outputting the write enable signal to a register for storing various setting data of the tester pin as the number of tester pins is provided. A semiconductor test apparatus characterized in that:

The second invention clarifies the pin define block. In other words, the pin define block inputs the pin assignment number and the pin number to be set from the tester bus to the exclusive OR circuit and inputs a write enable signal when they match, and inputs the write command signal to the gate terminal. 2. The semiconductor test apparatus according to claim 1, wherein the refined data from the tester bus input into the register is stored in a register.

The third invention clarifies a pin / group block. In other words, the pin group block selects the numerical value of the pin assign number or the pin define number and the 1-bit signal of the numerical data weighted for each order of the pin grouping data from the tester bus by the selection circuit. 2. The semiconductor test apparatus according to claim 1, wherein the data is stored in a register.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described based on embodiments with reference to the drawings. FIG. 1 is a configuration diagram of one embodiment of the present invention, FIG. 2 is a diagram illustrating the concept of the present invention, FIG. 3 is an explanatory diagram of pin number setting of a pin define block,
FIG. 4 is an explanatory diagram of the setting to the pin group block, and FIG. 5 is a diagram showing the WE (write / write) when the pin assignment is selected.
FIG. 6 shows a path diagram for outputting a WE signal when pin definition is selected, and FIG. 7 shows a path diagram for outputting a WE signal when a pin group is selected. Is shown.

First, FIG. 1 will be described. The pin block 1 is connected to the tester bus 51 or the interface (I /
F) 42 and a bus 54. In this specification, the tester bus 51 will be described. The number of the pin blocks 1 is equal to the number of the tester pins, and a WE (write enable) signal is output to the register of the corresponding tester pin.

The pin assignment block 2 includes a plurality of registers 3 and a NAND circuit 4. NAND circuit 4
Inputs a channel assign machine word (ChassnMW) and a control signal of a write command (hereinafter referred to as “WCMD”). When both are positive, the register 3 opens a gate,
The pin assignment number from the assigned data line 20 at that time is latched in the register 3. This pin assignment number is the tester pin No. in FIG. 9B. The register 3 provides the latched pin number unique to the tester pin to the A terminal of the multiplexer (hereinafter referred to as “MUX”) 10 and the exclusive OR circuit (hereinafter referred to as “XOR”) 5.

The pin define block 6 has a / WE
It comprises a plurality of registers 7 with (write enable) and a NAND circuit 8. When the register 7 matches one of the group of numbers defined by the pin definition from the line 22 which is the input signal of the XOR 5 with the pin assignment number, the register 7 is write-enabled, and the pin definition table of the control signal is set. Machine word (PinDef.TB M
W) and WCMD are received by the NAND circuit 8, and the refined data at that time is latched. As the defined data, predetermined numbers of a group of numbers defined by pin definition shown in FIG. 3A are stored, for example, as shown in FIG. 3B. That is, pin 1, pin 9, pin 17, and pin 25 of the pin assignment numbers are set as one pin. Similarly, pins 2, 10, 18, and 26 are set as two pins. The same applies hereinafter. The latched defined data is referred to as a pin define number.
The pin define number is output to the B terminal of the MUX 10.

MUX 10 is a data selector, which controls the control signals PinDefineMW and PinDe
By the output signal by the logical product of f.Sel. and WriteMode,
One of the number data input to the two input terminals A and B is given to the selection circuit 14 and the XNOR 15 of the pin / group block 11. Here, “B” is selected when the output signal of the AND gate 9 is active.

The pin group block 11 includes the DUT 6
Pin numbers are grouped in order to set the same setting to the same function pin of 0. Therefore, the selection circuits 14 and 1
And a bit register 12. A pin assign number or a pin define number is applied to the S terminal of the selection circuit 14. The grouping data transmitted from the line 24 applied to the other input terminal is composed of, for example, 32 bits, and each bit is weighted numerically in the order of the bit from the head. For example, the first bit is a numerical value 1, the second bit is a numerical value 2, and so on. Therefore, the grouped data contains “1” in the weighted order bit of the numerical value of the pin assign number or pin define number to be grouped.
And “0” is described in bits in the order not to be grouped.

The selecting circuit 14 selects the weighted bits of the grouped data based on the numerical value input to the S terminal and transmits the selected bits to the register 12. The 1-bit register 12 stores a signal from the selection circuit 14 at the time of a control signal from the NAND gate 13. Nandgate 1
3, a control signal of PinGroupTBMW and a control signal of WCMD are given. When both are positive, a control signal is given to the register 12, and the gate is opened to store a signal of grouping data. “1”
When the signal is latched, the register 12 becomes active,
The pins become grouped.

FIG. 4A shows a case of grouping by pin assignment number. They are grouped for each DUT.
FIG. 4B shows a case in which the data is grouped by pin-definition numbers. All DUTs are grouped together. In the above description, the storage means of the pin assign number, the pin define number and the pin group signal is understood.

Next, a path for generating a WE (write enable) signal in a register for storing various setting data of the corresponding tester pin by the pin block 1 will be described. Here, the S input is active for both MUX10 and MUX16.
In this case, the "B" input terminal is selected, and when NotActive, the "A" input terminal is selected.

First, a case where a WE signal is output with a pin assign number will be described. In this case, PinDefineMW and P
inDef.Sel becomes a negative signal, and the output signal of the AND gate 9 becomes NotActive. Therefore, as shown by the thick line in FIG. 5, the MUX 10 selects and outputs the A terminal, that is, the pin assignment block 2. PinGroupMW is also negative. The output signal of the AND gate 17 is also NotActive.
Therefore, the MUX 16 also selects the A terminal. At this time, when the setting target pin number is input from the line 23, X
A match is obtained in NOA15, a WE signal is generated, and the MU signal is output.
The WE signal is output from X16.

Next, a case where a WE signal is output with a pin-definition number will be described. In this case, PinDefineMW
And PinDef.Sel become positive signals, and the output signal of the AND gate 9 becomes Active. Therefore, as shown by the thick line in FIG.
The MUX 10 selects and outputs the B terminal, that is, the pin define block 6. Since PinGroupMW is negative, the output signal of AND gate 17 is NotActive. Therefore,
The MUX 16 selects the A terminal. At this time, line 23
When the setting target pin number is input from the
A match is obtained at 5, and a WE signal is generated, and the MUX 16 outputs the WE signal.

Finally, W from the pin / group block
The case where the E signal is output will be described. In this case, WriteM
When the PinGroupMW signal is input at the time of ode, the output signal of the AND gate 17 becomes Active, and as shown in FIG.
The UX 16 selects the B terminal, that is, selects the pin group block 11 and outputs a WE signal. When the register 12 of the pin group block 11 stores the “1” signal by the pin assignment number, each DUT 60
If the “1” signal is stored in the register of all the same function pins with the pin-defined block number, all D
Data is written to the registers of all the same function pins of the UT 60 by one setting. Here, when a WE signal of a constant width (constant time) is required, an output signal of the MUX 16 is input to one input terminal using a two-terminal AND gate and is not shown, although not shown. It is preferable to output a timing signal having a width.

[0037]

As described above in detail, in the conventional semiconductor test apparatus, the same data is sequentially transmitted to many tester pin registers for each register. Therefore, it took too much time and wasted much.

According to the present invention, when the same concept is transmitted to the tester pin register by simultaneously realizing the two concepts of the pin definition and the pin group on the hardware for the first time, the same function pins of the DUT are also provided. ,
Further, the same data can be simultaneously transferred to the same pin and the same function pin of many DUTs at the same time at the same time.

According to the calculation, the calculation data is omitted,
In the case of simultaneous measurement of 8 DUTs and 1CHD measurement of a 9-bit 16 MW memory LSI with 96 drivers of 96 drivers and 36 drivers, the number of data transfer times is about 1K from the conventional 1.3M to 14K. / 90 times. If this is the case of 64 simultaneous measurements, the time is further reduced. The technical effects of the present invention are significant.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a diagram illustrating the concept of the present invention.

FIG. 3 is an explanatory diagram of a pin number setting of a pin define block according to the present invention.

FIG. 4 is an explanatory diagram of setting to a pin / group block according to the present invention.

FIG. 5 shows W when the pin assignment of the present invention is selected.
FIG. 7 is a path diagram for outputting an E (write enable) signal.

FIG. 6 is a path diagram for outputting a WE signal when a pin define of the present invention is selected.

FIG. 7 shows W when the pin group of the present invention is selected.
FIG. 5 is a path diagram for outputting an E signal.

FIG. 8 is a basic schematic diagram of a semiconductor test apparatus.

FIG. 9 shows a DU at the time of simultaneous measurement of a plurality of DUTs according to the conventional method.
It is explanatory drawing which shows the relationship between pin No. of T and tester pin specific NO.

FIG. 10 is a data transfer diagram of a conventional method.

[Explanation of symbols]

1 pin block 2 pin assign block (Pin Assign block) 3 pin assign register 4, 8, NAND gate 5 Exclusive OR circuit (XOR) 6 pin define block (Pin Define block) 7 pin Define register 9, 13, 17 AND gate 10, 16 multiplexer (MUX) 11 pin group block (Pin Group block) 12 pin group register 14 selection circuit 15 exclusive OR circuit (XNOR) 20 Assigned data line 21 Defined data line 22, 23 line 24 Grouped data line 28, 29 Select signal 30 Write enable to register group (Write En)
able) signal 40 test processor 41 logic pattern generation unit 42 interface (I / F) 43 register group 45 pulse pattern generation unit 46 driver (DR) 47 comparator (CP) 48 logic comparison unit 49 input unit 50 output unit 51 tester bus 52 application Logical pattern 53 Expected value pattern

Claims (3)

[Claims] 1. A semiconductor test apparatus for transferring data of a test program inputted from an input unit to a plurality of tester pin registers via a test processor and a tester bus, and simultaneously measuring a plurality of DUTs based on the transferred data. , Control signal from tester bus to tester pin specific pin
A pin assign block that stores an assign number, and a pin define that stores a pin define number from the tester bus by a control signal when the pin number to be set in the data transferred from the tester bus is the relevant pin assign number. A block and a pin group block for latching a grouping signal by a control signal when the grouping data transferred from the tester bus matches the pin assign number or the pin define number. Select the pin assignment number or the pin definition number or the grouping signal and select the pin block that outputs as a write enable signal to the register that saves various tester pin setting data. To have a minute Characteristic semiconductor test equipment. 2. The pin define block inputs a write enable signal when the pin assign number and the number defined by the pin define from the tester bus are input to the exclusive-OR circuit and coincide with each other, and 2. The semiconductor test apparatus according to claim 1, wherein a write command signal is input to a gate terminal, and the refined data from the tester bus is stored in a register. 3. A pin group block selects a 1-bit signal of data in which a numerical value of a pin assign number or a pin define number matches a numerical value weighted for each order of pin grouping data from a tester bus. 2. The semiconductor test apparatus according to claim 1, wherein said semiconductor test apparatus is selected by a circuit and stored in a register.