JP2001053246A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a silicide film in a plug, to reduce the resistance of the plug and also to prevent the silicide layer in the plug from being connected with the capacitor lower electrode of a capacitor. SOLUTION: This manufacturing method of a semiconductor device is performed by a method, wherein a polysilicon film 13 is formed in a contact hole 12 formed in a first interlayer insulating film 11 on a silicon substrate 10, in such a way that the upper part of the film 13 is left in the hole 12. Thereafter a heat treatment is performed on a cobalt film deposited on the film 3 to form a cobalt silicide layer 15 on the surface part of the film 13, a barrier layer 17 is formed on the layer 15 to form a plug 18 consisting of the film 13 and the layers 15 and 17. Then a recessed part 20 is formed in a second interlayer insulating film 19 deposited on the film 11, in such a way that the upper surface of the plug 18 is exposed, a conductive film 21, which is formed as a capacitor lower electrode, is deposited on the wall surface and bottom of the recessed part 20.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having a capacitor embedded in an insulating film on a semiconductor substrate and a method of manufacturing the same.

[0002]

2. Description of the Related Art With the miniaturization of semiconductor devices such as DRAMs (Dynamic Random Access Memories), a stack type or a trench type is used instead of a planar type as a memory cell structure. They have been arranged in a dimensional manner to increase the accumulated charge per unit area, that is, the capacitance.

Hereinafter, a conventional semiconductor device will be described with reference to FIG.

As shown in FIG. 12, a first insulating film 51 is formed on a semiconductor substrate 50 on which a transistor (not shown) forming a memory cell is formed. Is formed with a plug 52 connected to the semiconductor substrate 50 (a diffusion layer of the transistor).
The plug 52 includes a polysilicon film 52a and a barrier layer 52b sequentially embedded in the first insulating film 51.

A second insulating film 53 is formed on the first insulating film 51, and the second insulating film 53
A capacitor 54 connected to the plug 52 is formed. The capacitor 54 includes a lower electrode 54a, a capacitor insulating film 54b, and an upper electrode 54c which are sequentially embedded in the second insulating film 53.

According to the conventional semiconductor device, since the barrier layer 52b is formed on the polysilicon film 52a in the plug 52, the polysilicon film 52a of the plug 52 is formed.
And the lower electrode 54a of the capacitor 54 can be prevented from contacting. Therefore, it is possible to prevent a situation in which the polysilicon film 52a of the plug 52 is oxidized when the capacitor 54 is formed and the electrical characteristics of the plug 52 are deteriorated.

[0007]

However, in the conventional semiconductor device, the first problem is that the electrical resistance of the plug 52 mainly composed of the polysilicon film 52a increases as the plug diameter decreases with miniaturization. There is.

In the conventional semiconductor device, the lower electrode 54a is contaminated when the capacitor 54 is formed, or the first insulating film 51 or the second insulating film 53 is excessively etched, and There is a second problem that reliability is no longer guaranteed.

In order to reduce the resistance of the plug connected to the capacitor, the present inventors have studied to silicide the polysilicon film forming the plug with respect to the first problem described above. Specifically, the polysilicon film forming the plug was silicided using titanium.

A method for silicidizing a polysilicon film forming a plug using titanium will be described below with reference to FIG.
This will be described with reference to (a) to (d) and FIGS. 14 (a) to (d).

First, as shown in FIG. 13A, a polysilicon film 63 is buried in a contact hole 62 formed in a first interlayer insulating film 61 on a silicon substrate 60. Then, as shown in FIG. As shown, contact holes 62
Removing the upper part of the polysilicon film 63 embedded in the
A recess 62a is formed on the polysilicon film 63 in the contact hole 62.

Next, as shown in FIG. 13C, after a titanium film 64 is deposited on the silicon substrate 60 so as to cover the upper surface of the polysilicon film 63, as shown in FIG. Then, a heat treatment for a silicidation reaction is performed on the titanium film 64 to form a titanium silicide layer 65.

When a barrier layer 67 (see FIG. 14C) is formed on the titanium silicide layer 65 in a later step, a recess is formed so as not to form a void inside the barrier layer 67. The aspect ratio of the portion 62a was set to about 0.5 to 1.0 (about 50 to 100 nm in depth and about 100 to 200 nm in diameter). At this time, FIG.
As shown in FIG. 3C, the titanium film 64 is formed in the recess 62a.
Was formed continuously from the inside to the outside. Further, as shown in FIG. 13D, the titanium silicide layer 65 is
Not only the surface of the polysilicon film 63 but also the recess 6
It was also formed on the wall surface of 2a and outside the recessed portion 62a.
That is, the titanium silicide layer 65 is formed in the recess 62a.
, Ie, near the opening of the contact hole 62.

Next, after the unreacted titanium film 64 is selectively removed by wet etching as shown in FIG. 14A, the titanium film 64 is formed on the titanium silicide layer 65 as shown in FIG. For example, a TiN film 66 is deposited such that the recess 62a is completely filled.

Next, as shown in FIG. 14C, the TiN film 66 and the titanium silicide layer 65 outside the recess 62a are removed by a CMP (chemical mechanical polishing) method to remove the titanium silicide layer in the recess 62a. T inside 65
A barrier layer 67 made of the iN film 66 is formed. As a result, the plug 68 composed of the polysilicon film 63, the titanium silicide layer 65, and the barrier layer 67 is
2 is formed.

Next, as shown in FIG. 14D, after depositing a second interlayer insulating film 69 on the first interlayer insulating film 61, a concave portion 70 is plugged in the second interlayer insulating film 69. Then, a conductive film 71 serving as a capacitor lower electrode of a capacitor is deposited on the second interlayer insulating film 69 so as to cover the wall surface and the bottom of the concave portion 70. .

Subsequently, although not shown, the recess 70
After removing the conductive film 71 on the outside of the substrate and forming a capacitor lower electrode made of the conductive film 71 on the wall surface and the bottom of the concave portion 70, a capacitor insulating film and a capacitor upper electrode are sequentially formed on the capacitor lower electrode. I do.

However, when the above-described method is used, when the heat treatment is performed after the deposition of the conductive film 71 to improve the electrical characteristics of the conductive film 71, the titanium silicide layer 65 and the conductive film Since the titanium silicide layer 71 and the conductive film 71 react with each other due to direct contact with the conductive film 71 (see FIG. 14D), the conductive film 71, that is, the capacitor lower electrode of the capacitor is silicide. It has been turned into. Further, when a capacitance insulating film containing oxygen is formed on the capacitance lower electrode, the titanium silicide layer 6
5 was oxidized and the resistance of the plug 68 was increased, so that the plug 68 could not be used.

In view of the foregoing, it is a first object of the present invention to form a silicide layer on a plug to reduce the resistance of the plug and to prevent contact between the silicide layer of the plug and a lower electrode of a capacitor of a capacitor. A second object is to improve the reliability of the capacitor.

[0020]

Means for Solving the Problems The inventors of the present invention have proposed a method shown in FIG.
14 (a) to 14 (d) and FIGS. 14 (a) to 14 (d), the cause of the direct contact between the titanium silicide layer 65 and the conductive film 71, that is, the titanium silicide layer 65 The cause of formation not only in the surface of the film 63 but also in the vicinity of the opening of the recess 62a was examined. As a result, when a silicidation reaction occurs between the titanium film 64 and the polysilicon film 63, titanium atoms constituting the titanium film 64 continuously formed from the inside to the outside of the recess portion 62a include: Since silicon atoms constituting the polysilicon film 63 are diffused,
It has been found that the titanium silicide layer 65 is also formed near the opening of the recess 62a.

When the present inventors tried to silicide the polysilicon film constituting the plug with tungsten, the silicon atoms constituting the polysilicon film were also included in the tungsten atoms constituting the tungsten film. It has been found that similar problems occur due to the diffusion of atoms.

Therefore, the present inventors disclose that when the silicidation reaction occurs between the metal film and the polysilicon film, the silicon atoms forming the polysilicon film diffuse into the metal atoms forming the metal film. A method for forming a silicide layer while suppressing this was studied. As a result, when the polysilicon film was silicided using cobalt, that is, when a cobalt silicide layer was formed, it was found that cobalt atoms constituting the cobalt film diffused into silicon atoms constituting the polysilicon film. .

The present invention has been made based on the above-mentioned knowledge. Specifically, in order to achieve the first object, a semiconductor device according to the present invention is formed on a semiconductor substrate. And a lower electrode, a capacitor insulating film, and an upper electrode sequentially embedded in the second insulating film deposited on the first insulating film and connected to the plug. A plug having a cobalt silicide layer and a barrier layer formed on the cobalt silicide layer.

According to the semiconductor device of the present invention, since the plug has the cobalt silicide layer, the resistance of the plug can be reduced. Further, since the plug has the barrier layer formed on the cobalt silicide layer, contact between the cobalt silicide layer and the lower electrode of the capacitor can be prevented. Therefore, the lower electrode can be prevented from being silicided when the lower electrode is formed, and the cobalt silicide layer, that is, the plug can be prevented from being oxidized when the capacitive insulating film is formed on the lower electrode.

In the semiconductor device of the present invention, it is preferable that a protective insulating film made of a SiN film or a SiAlN film is formed on the first insulating film.

With this configuration, when forming the concave portion for embedding the capacitor in the second insulating film, the protective insulating film can be used as an etching stopper, so that the first insulating film is not damaged. Can be prevented.

In the semiconductor device of the present invention, it is preferable that a protective insulating film made of a SiN film or a SiAlN film is formed on the second insulating film.

Thus, after the conductive film for the lower electrode is deposited on the second insulating film in which the concave portion for embedding the capacitor is formed, the conductive film for the lower electrode outside the concave portion is removed. When the lower electrode is formed in the concave portion, the protective insulating film can be used as an etching stopper, so that the second insulating film can be prevented from being damaged.

In order to achieve the first object, a first method for manufacturing a semiconductor device according to the present invention comprises the steps of: depositing a first insulating film on a semiconductor substrate; A second step of forming a contact hole in the insulating film, a third step of forming a silicon film such that an upper portion thereof remains in the contact hole, and a heat treatment after depositing a cobalt film on the silicon film. Forming a cobalt silicide layer on the surface of the silicon film by reacting the silicon film with the cobalt film, and forming a barrier layer on the cobalt silicide layer so that the contact hole is completely buried. A fifth step of forming a plug composed of a silicon film, a cobalt silicide layer, and a barrier layer in the hole; a sixth step of depositing a second insulating film on the first insulating film; Recess and a seventh step of forming so that the upper surface of the plug is exposed, capacitor lower electrode in the recess, the
An eighth step of sequentially forming a capacitor insulating film and a capacitor upper electrode.

According to the first method of manufacturing a semiconductor device, since the cobalt silicide layer is formed on the plug, the resistance of the plug can be reduced. Also, after depositing a cobalt film on the silicon film formed so that the upper portion remains in the contact hole, when forming a cobalt silicide layer on the surface portion of the silicon film by heat treatment, silicon atoms constituting the silicon film are formed. Since the cobalt atoms constituting the cobalt film diffuse into the silicon film, a cobalt silicide layer is formed only on the surface of the silicon film. In other words, no cobalt silicide layer is formed near the opening of the contact hole. Therefore, when a barrier layer is formed on the cobalt silicide layer and a plug including the silicon film, the cobalt silicide layer, and the barrier layer is formed, the barrier layer can be formed over the entire surface of the cobalt silicide layer. In addition, contact between the cobalt silicide layer of the plug and the capacitor lower electrode of the capacitor formed on the plug can be prevented. Therefore, it is possible to prevent the capacitance lower electrode from being silicided when forming the capacitance lower electrode, and to prevent the cobalt silicide layer, that is, the plug, from being oxidized when forming the capacitance insulating film on the capacitance lower electrode. it can.

In the first method for fabricating a semiconductor device, S is formed on the upper side of the first insulating film between the first step and the second step.
It is preferable that the method further includes a step of forming a protective insulating film made of an iN film or a SiAlN film.

With this configuration, when forming the concave portion in the second insulating film, the protective insulating film can be used as an etching stopper, so that the first insulating film can be prevented from being damaged.

In order to achieve the second object, a second method of manufacturing a semiconductor device according to the present invention comprises a first step of depositing an insulating film on a semiconductor substrate, and a step of depositing the first film on the insulating film. A second step of forming a concave portion, and forming a conductive film on the insulating film in which the first concave portion is formed, and forming a second concave portion inside the conductive film in the first concave portion. A third step of depositing, a fourth step of embedding a protective film in the second recess,
A fifth step of removing the conductive film outside the first recess to form a capacitor lower electrode made of a conductive film on the wall and bottom of the first recess; and removing the protective film to remove the capacitor lower electrode. A sixth step of sequentially forming a capacitor insulating film and a capacitor upper electrode on the capacitor lower electrode after exposing the electrode.

According to the second method for manufacturing a semiconductor device, the conductive film is formed on the insulating film having the first concave portion, and the second concave portion is formed inside the conductive film in the first concave portion. After that, the protective film is buried in the second concave portion, and then the conductive film outside the first concave portion is removed.
A capacitance lower electrode made of a conductive film is formed on the wall and bottom of the first recess. For this reason, the conductive film inside the first concave portion, that is, the portion of the conductive film serving as the capacitor lower electrode is covered with the protective film, and the conductive film outside the first concave portion, that is, the capacitor lower electrode in the conductive film. The portion that does not become an electrode can be removed. Therefore, it is possible to prevent the capacitance lower electrode from being contaminated by the etching residue or the CMP slurry, and to improve the reliability of the capacitor. When a conductive film that oxidizes when exposed to oxygen plasma, for example, a ruthenium film or the like is used as the capacitor lower electrode,
It is possible to prevent the capacitance lower electrode from being oxidized and deteriorated.

In the second method for fabricating a semiconductor device, a step of forming a protective insulating film made of a SiN film or a SiAlN film on the insulating film is provided between the first step and the second step. Is preferred.

With this configuration, when removing the conductive film outside the first concave portion, the protective insulating film can be used as an etching stopper, so that the insulating film can be prevented from being damaged. Further, when the protective film is removed, the protective insulating film can be used as a mask, so that the insulating film can be prevented from being damaged.

In the second method for fabricating a semiconductor device, the conductive film is made of a platinum film, and the third step is to heat-treat the conductive film at about 400 to 750 ° C. after depositing the conductive film. Is preferably included.

In this case, the step coverage is improved by the grain growth of the conductive film, so that the conductive film, that is, the bent portion of the capacitor lower electrode can be prevented from being thinned. For this reason, it is possible to prevent the bent portion of the capacitor insulating film deposited on the capacitor lower electrode from being thinned due to the step coverage of the capacitor insulating film, so that the gap between the capacitor lower electrode and the capacitor upper electrode can be prevented. Can be suppressed from increasing the leak current.

In the second method for manufacturing a semiconductor device, the fifth step is a step of etching the conductive film using the protective film as a mask to remove the conductive film outside the first recess. It is preferred to include.

In this manner, a higher etching selectivity with respect to the conductive film can be obtained as compared with the conventional method of performing etch back using a resist, so that the conductive film outside the first concave portion can be formed. It can be removed accurately and easily.

In the second method for manufacturing a semiconductor device, the protective film has an insulating property, and in the sixth step, the protective film is removed so that the protective film remains at the bent portion of the lower electrode of the capacitor. Preferably, a step is included.

With this configuration, when the bent portion of the capacitor lower electrode is thinned, the thinned portion can be covered with the remaining protective film. It is possible to prevent the bent portion of the capacitor insulating film deposited on the lower electrode from becoming thin.
For this reason, it is possible to suppress an increase in leakage current generated between the lower capacitor electrode and the upper capacitor electrode. Further, when the bent portion of the capacitor insulating film is thinned, a short circuit between the capacitor lower electrode and the capacitor upper electrode can be prevented since the protective film remains under the thinned portion.

[0043]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing a specific embodiment, the first object, that is, forming a silicide layer on a plug to lower the resistance of the plug,
The principle for achieving the object of preventing the contact between the silicide layer of the plug and the capacitor lower electrode of the capacitor will be described with reference to the drawings.

FIGS. 1A to 1 D and FIGS.
(D) is sectional drawing which shows each process of the method of silicidizing the polysilicon film which comprises a plug using cobalt.

First, as shown in FIG. 1A, after a polysilicon film 13 is buried in a contact hole 12 formed in a first interlayer insulating film 11 on a silicon substrate 10,
As shown in FIG. 1B, an upper portion of the polysilicon film 13 buried in the contact hole 12 is removed, and a recess 12a is formed on the polysilicon film 13 in the contact hole 12.

Next, as shown in FIG. 1C, after a cobalt film 14 is deposited on the silicon substrate 10 so as to cover the upper surface of the polysilicon film 13, as shown in FIG. Then, a heat treatment for a silicidation reaction is performed on the cobalt film 14 to form a cobalt silicide layer 15.

At this time, since the cobalt atoms constituting the cobalt film 14 diffuse into the silicon atoms constituting the polysilicon film 13, the cobalt silicide layer 15 is formed only on the surface of the polysilicon film 13. In other words, the cobalt silicide layer 15 is not formed outside the recess 12a, that is, outside the contact hole 12, or formed near the opening of the contact hole 12.

Next, as shown in FIG. 2A, the unreacted cobalt film 14 is selectively removed by, for example, wet etching, and then, as shown in FIG. For example, a TiN film 16 is
2a is deposited so as to be completely buried.

Next, as shown in FIG. 2C, the TiN film 16 outside the recess 12a is removed by, for example, a CMP method to form a TiN film 16 on the cobalt silicide layer 15 in the recess 12a. The barrier layer 17 is formed. As a result, a plug 18 including the polysilicon film 13, the cobalt silicide layer 15, and the barrier layer 17 is formed in the contact hole 12.

At this time, since the cobalt silicide layer 15 is formed only on the surface of the polysilicon film 13 in the step shown in FIG. 1D, the barrier layer 17 of the plug 18 is entirely over the cobalt silicide layer 15. Is formed over.

Next, as shown in FIG. 2D, after a second interlayer insulating film 19 is deposited on the first interlayer insulating film 11, a recess 20 is plugged in the second interlayer insulating film 19. Then, a conductive film 21 serving as a capacitor lower electrode of a capacitor is deposited on the second interlayer insulating film 19 so as to cover the wall surface and the bottom of the concave portion 20. .

At this time, since the barrier layer 17 is formed over the entire surface of the cobalt silicide layer 15 in the step shown in FIG.
And the conductive film 21, that is, the lower electrode of the capacitor, can be prevented from contacting.

Subsequently, although not shown, the recess 20
After removing the conductive film 21 on the outside of the substrate and forming a capacitor lower electrode made of the conductive film 21 on the wall surface and the bottom of the concave portion 20, a capacitor insulating film and a capacitor upper electrode are sequentially formed on the capacitor lower electrode. I do.

(First Embodiment) A semiconductor device according to a first embodiment of the present invention, specifically, FIGS. 1 (a) to 1 (d)
A semiconductor device manufactured using the method shown in FIGS. 2A to 2D will be described with reference to the drawings. still,
The semiconductor device according to the first embodiment has one transistor
The present invention is directed to a DRAM in which one-capacitor type memory cells are arranged in a matrix. However, the present invention is not limited to this, and may be applied to other semiconductor memory devices or semiconductor devices in which memory and logic are mixed. it can.

FIG. 3 is a plan view of the semiconductor device according to the first embodiment, FIG. 4 is a sectional view taken along the line II in FIG. 3, and FIG. 5 is a sectional view taken along the line II-II in FIG. It is.

As shown in FIGS. 3 to 5, the silicon substrate 1
An active region 102 surrounded by an STI (element isolation insulating film) 101 is formed at
A word line 103 serving as a gate electrode is formed on the second channel region. In addition, the silicon substrate 100
A first interlayer insulating film 10 made of, for example, an SiO ₂ film
4, and a first protective insulating film 10 made of, for example, a SiN film
5 are sequentially deposited and the first interlayer insulating film 10
A plug (storage node contact) 106 electrically connected to the source region of the active region 102 is formed in the fourth and first protective insulating films 105. Plug 106
Are the first interlayer insulating film 104 and the first protective insulating film 10
5 comprises a polysilicon film 106a, a cobalt silicide layer 106b, and a barrier layer 106c which are sequentially buried. As the barrier layer 106c, for example, a TiN film or Ti
An AlN film or the like is used.

The semiconductor device according to the first embodiment is
Since it is manufactured using the method shown in FIGS. 1A to 1D and FIGS. 2A to 2D, the plug 106
The barrier layer 106c is formed over the entire surface of the cobalt silicide layer 106b.

Further, below the first interlayer insulating film 104,
A bit line contact 107 electrically connected to the drain region of the active region 102 is formed, and a bit line contact 1 is formed above the bit line contact 107 in the first interlayer insulating film 104.
The bit line 108 electrically connected to the bit line 07 is formed.

Further, a second interlayer insulating film 109 made of, for example, a SiO ₂ film and a second protective insulating film 110 made of, for example, a SiN film are sequentially deposited on the first protective insulating film 105. The second interlayer insulating film 109 and the second
A capacitor 111 electrically connected to the plug 106 is formed on the protective insulating film 110. Capacitor 11
1 denotes a second interlayer insulating film 109 and a second protective insulating film 1
10 comprises a lower electrode 111a, a capacitor insulating film 111b, and an upper electrode 111c which are sequentially embedded. Lower electrode 11
For example, a platinum film is used as 1a or the upper electrode 111c. For example, a BST (barium strontium titanium oxide) film is used as the capacitor insulating film 111b.

According to the first embodiment, since the plug 106 has the cobalt silicide layer 106b, the resistance of the plug 106 can be reduced. In addition, plug 1
06 has a barrier layer 106c formed over the entire surface of the cobalt silicide layer 106b, so that contact between the cobalt silicide layer 106b and the lower electrode 111a of the capacitor 111 can be prevented. Therefore, the lower electrode 1
When the lower electrode 111a is formed, the lower electrode 111a can be prevented from being silicided, and when the capacitive insulating film 111b is formed on the lower electrode 111a, the cobalt silicide layer 106b, that is, the plug 106 can be prevented from being oxidized. .

According to the first embodiment, since the first protective insulating film 105 made of a SiN film is formed above the first interlayer insulating film 104, a recess for embedding the capacitor 111 is formed. When the second interlayer insulating film 109 is formed, the first protective insulating film 105 can be used as an etching stopper, so that the first interlayer insulating film 104 can be prevented from being damaged.

Further, according to the first embodiment, since the second protective insulating film 110 made of a SiN film is formed above the second interlayer insulating film 109, when forming the lower electrode 111a, Specifically, after a conductive film for a lower electrode is deposited on the second interlayer insulating film 109 in which a recess for embedding the capacitor 111 is formed, the conductive film for the lower electrode outside the recess is removed. When the lower electrode 111a is formed in the concave portion, the second protective insulating film 110 can be used as an etching stopper. Therefore, it is possible to prevent the second interlayer insulating film 109 from being damaged.

In the first embodiment, the plug 10
Although the polysilicon film 106a is used as the constituent material of No. 6, an amorphous silicon film or the like may be used instead.

In the first embodiment, as the first protective insulating film 105 or the second protective insulating film 110, S
Although the iN film is used, a SiAlN film may be used instead.

In the first embodiment, a platinum film is used as the lower electrode 111a or the upper electrode 111c. Instead, a ruthenium (Ru) film, an iridium (Ir) film, a palladium (Pd) film, or the like is used. May be used, or an alloy film or the like made of at least two kinds of metals among platinum, ruthenium, iridium and palladium may be used.

In the first embodiment, a BST film is used as the capacitance insulating film 111b.
A tantalum pentoxide (Ta ₂ O ₅ ) film or the like may be used.

In the first embodiment, the bit line 108 is arranged below the capacitor 111, but the bit line 108 may be arranged above the capacitor 111 instead.

(Second Embodiment) A method for manufacturing a semiconductor device according to a second embodiment of the present invention will be described with reference to the drawings.

The method of manufacturing a semiconductor device according to the second embodiment is directed to a method of manufacturing a DRAM in which memory cells of one transistor and one capacitor are arranged in a matrix. The present invention is not limited thereto, and can be used for a method of manufacturing another semiconductor memory device or a method of manufacturing a semiconductor device in which a memory and a logic are mixed.

FIGS. 6A to 6D and FIGS.
(D), FIGS. 8 (a) to (c), FIGS. 9 (a) to (c), and FIGS. 10 (a) to (c) show the steps of the method for manufacturing a semiconductor device according to the second embodiment. FIG.

First, as shown in FIG. 6A, for example, a CVD (chemical) is formed on a silicon substrate 200 on which a transistor (not shown) constituting a memory cell is formed.
After depositing a first interlayer insulating film 201 made of a SiO ₂ film by a vapor deposition method, the first interlayer insulating film 201 is flattened by, for example, a CMP method, and then the flattened first interlayer insulating film 201 is formed. A first protective insulating film 202 made of, for example, a SiN film is deposited thereon.

Next, dry etching is sequentially performed on the first protective insulating film 202 and the first interlayer insulating film 201 using a resist pattern (not shown) formed on the first protective insulating film 202 as a mask. Then, as shown in FIG. 6B, a contact hole 203 is formed in the first interlayer insulating film 201 and the first protective insulating film 202.

Next, as shown in FIG. 6C, a polysilicon film 204 is embedded in the contact hole 203. Specifically, after a polysilicon film 204 is deposited over the entire surface of the silicon substrate 200 by, for example, a CVD method so that the contact hole 203 is completely filled, the polysilicon film 204 outside the contact hole 203 is formed by, for example, It is removed by a CMP method or dry etching.

Next, as shown in FIG. 6D, the upper portion of the polysilicon film 204 embedded in the contact hole 203 is removed by, for example, dry etching, and a recess is formed on the polysilicon film 204 in the contact hole 203. The part 203a is formed.

Next, as shown in FIG. 7A, a cobalt film 205 is
After being deposited so as to cover the top surface of the cobalt silicide layer 20, the cobalt film 205 is subjected to a heat treatment for a silicidation reaction, as shown in FIG.
6 is formed.

At this time, since the cobalt atoms constituting the cobalt film 205 diffuse into the silicon atoms constituting the polysilicon film 204, the cobalt silicide layer 206
Is formed only on the surface of the polysilicon film 204. In other words, the cobalt silicide layer 206 is
It is not formed outside of the contact hole 203a, that is, outside of the contact hole 203, or near the opening of the contact hole 203.

Next, as shown in FIG. 7C, after the unreacted cobalt film 205 is selectively removed by wet etching, the unreacted cobalt film 205 is formed on the cobalt silicide layer 206 as shown in FIG. For example, the TiN film 207 is
03a is completely deposited.

Next, as shown in FIG. 8A, the TiN film 207 outside the contact hole 203 is removed by, for example, CMP.
Then, a barrier layer 208 made of a TiN film 207 is formed on the cobalt silicide layer 206 in the contact hole 203 by a method or dry etching. As a result, the polysilicon substrate 204, the cobalt silicide layer 206, and the barrier layer 208
A plug 209 electrically connected to the contact hole 203 is formed in the contact hole 203.

At this time, since the cobalt silicide layer 206 is formed only on the surface of the polysilicon film 204 in the step shown in FIG. 7B, the barrier layer 208 of the plug 209 is entirely over the cobalt silicide layer 206. Is formed over.

Next, as shown in FIG. 8B, a second interlayer insulating film 210 made of, for example, an SiO ₂ film and a second protection made of, for example, a SiN film are formed on the entire surface of the silicon substrate 200. An insulating film 211 is sequentially deposited.

Next, dry etching is sequentially performed on the second protective insulating film 211 and the second interlayer insulating film 210 using a resist pattern (not shown) formed on the second protective insulating film 211 as a mask. 8C, a first concave portion 212 is formed in the second interlayer insulating film 210 and the second protective insulating film 211, and an upper surface of the plug 209 and an upper surface of the first protective insulating film 202 are formed. Plug 209 in
Is formed to expose the vicinity of the.

At this time, the first protective insulating film 202 (Si
N film) has an etching selectivity with respect to the second interlayer insulating film 210 (SiO ₂ film). Therefore, when forming the first concave portion 212 in the second interlayer insulating film 210, the first Since the protective insulating film 202 functions as an etching stopper, the first interlayer insulating film 201 can be prevented from being removed.

Next, as shown in FIG. 9A, a first conductive film 213 made of, for example, a platinum film is formed on the entire surface of the silicon substrate 200 by forming a wall surface and a bottom portion of the first concave portion 212. , In other words, the first recess 21
The second concave portion 2 is provided inside the first conductive film 213 in FIG.
14 are deposited.

In the case where a platinum film is used as the first conductive film 213, a heat treatment at about 400 to 750 ° C. is performed on the first conductive film 213 after the deposition of the first conductive film 213. Since the step coverage is improved by the grain growth of the first conductive film 213, it is possible to prevent the bent portion (R _{0 in} FIG. 9A) of the first conductive film 213 from becoming thin.

Next, as shown in FIG. 9B, a protective film 215 made of, for example, an SiO ₂ film is embedded in the second concave portion 214. Specifically, over the entire surface of the silicon substrate 200, for example, after a SiO ₂ film second recess 214 is deposited to completely fill the CVD method, the SiO ₂
The film is etched back using, for example, a CMP method or dry etching to remove the SiO ₂ film outside the second concave portion 214. Thereby, the first concave portion 21
The first conductive film 213 outside the second conductive film 213 is exposed.

Next, the first conductive film 213 is subjected to, for example, dry etching using the protective film 215 as a mask, and as shown in FIG. The conductive film 213 is removed, and the first concave portion 21 is removed.
A lower electrode 216 made of the first conductive film 213 is formed on the wall surface and the bottom of the second electrode 216.

At this time, the second protective insulating film 211 (Si
N film) has an etching selectivity with respect to the first conductive film 213 (platinum film), so that when the first conductive film 213 outside the first concave portion 212 is removed, Since the second protective insulating film 211 functions as an etching stopper, the second interlayer insulating film 210 can be prevented from being removed.

Next, the protective film 215 is removed by, for example, wet etching or dry etching, and FIG.
As shown in (a), the lower electrode 216 is exposed.

At this time, the second protective insulating film 211 (Si
N film) has an etching selectivity with respect to the protective film 215 (SiO ₂ film), so that when removing the protective film 215, the second protective insulating film 211 acts as a mask. Can be prevented from being removed.

Next, as shown in FIG. 10B, a capacitor insulating film 217 made of, for example, a BST (barium strontium titanium oxide) film is formed on the lower electrode 216.
Is deposited such that the upper portion of the second concave portion 214 remains.

Next, as shown in FIG. 10C, after depositing a second conductive film made of, for example, a platinum film on the capacitance insulating film 217, the second conductive film is patterned. To form an upper electrode 218. Thereby, the lower electrode 21
6, a capacitor 219 which is composed of a capacitive insulating film 217 and an upper electrode 218 and is electrically connected to the plug 209.
Is formed in the concave portion 212.

Subsequently, although not shown, after an interlayer insulating film is deposited on the capacitor 219, the upper electrode 21 is formed.
8, that is, a wiring or a plug connected to the plate electrode of the DRAM is formed.

As described above, according to the second embodiment, since the cobalt silicide layer 206 is formed on the plug 209, the resistance of the plug 209 can be reduced. Further, after depositing a cobalt film 205 on the polysilicon film 204 formed so that the upper portion thereof remains in the contact hole 203, the polysilicon film 20 is formed by heat treatment.
When the cobalt silicide layer 206 is formed on the surface of the polysilicon film 204, the cobalt atoms constituting the cobalt film 205 diffuse into the silicon atoms constituting the polysilicon film 204. A silicide layer 206 is formed. In other words, the cobalt silicide layer 206 is not formed near the opening of the contact hole 203. Therefore, when the barrier layer 208 is formed on the cobalt silicide layer 206 and the plug 209 including the polysilicon film 204, the cobalt silicide layer 206, and the barrier layer 208 is formed, the entire surface is formed on the cobalt silicide layer 206. Since the barrier layer 208 can be formed over the entire surface, the cobalt silicide layer 206 can be formed.
Then, contact with the lower electrode 216 of the capacitor 219 formed on the plug 209 can be prevented. Therefore, the lower electrode 216 can be prevented from being silicided when the lower electrode 216 is formed, and the cobalt silicide layer 206, that is, the plug 209 is oxidized when the capacitance insulating film 217 is formed on the lower electrode 216. Can be prevented.

Further, according to the second embodiment, the first conductive film 213 is formed on the second interlayer insulating film 210 in which the first concave portion 212 is formed, and the first conductive film 213 is formed on the first concave portion 212. Is deposited so as to form the second recess 214 inside the conductive film 213 of FIG.
15, the first conductive film 213 outside the first concave portion 212 is removed, and the lower electrode 2 made of the first conductive film 213 is formed on the wall and bottom of the first concave portion 212.
16 are formed. For this reason, the first conductive film 213 inside the first concave portion 212, that is, the portion that becomes the lower electrode 216 in the first conductive film 213 is covered with the protective film 215, and the first conductive film 213 is formed outside the first concave portion 212. The first conductive film 213, that is, a portion of the first conductive film 213 which does not become the lower electrode 216 can be removed. Therefore, it is possible to prevent the lower electrode 216 from being contaminated by an etching residue or the like, and to improve the reliability of the capacitor 219. The lower electrode 216, that is, the first conductive film 21
When a material that oxidizes when exposed to oxygen plasma, for example, ruthenium (Ru) or the like,
6 can be prevented from being oxidized and deteriorated.

According to the second embodiment, since the first protective insulating film 202 made of a SiN film is formed on the first interlayer insulating film 201, it is deposited on the first interlayer insulating film 201. The first concave portion 21 is formed in the second interlayer insulating film 210 thus formed.
Since the first protective insulating film 202 can be used as an etching stopper when forming the second insulating film 2, the first interlayer insulating film 201 can be prevented from being damaged.

According to the second embodiment, since the second protective insulating film 211 made of a SiN film is formed above the second interlayer insulating film 210, the first protective insulating film 211 outside the first concave portion 212 is formed. When the conductive film 213 is removed, the second protective insulating film 211 can be used as an etching stopper, so that the second interlayer insulating film 210 can be prevented from being damaged. Further, when the protective film 215 is removed, the second protective insulating film 211 can be used as a mask, so that the second interlayer insulating film 210 can be prevented from being damaged.

Also, according to the second embodiment, the first conductive film 213 is made of a platinum film, and after the first conductive film 213 is deposited, the first conductive film 213
Since the heat treatment at about 00 to 750 ° C. is performed, the step coverage is improved by the grain growth of the first conductive film 213, so that the first conductive film 213, that is, the bent portion of the lower electrode 216 becomes thinner. Can be prevented. For this reason,
Due to the step coverage of the capacitance insulating film 217, the lower electrode 2
Since it is possible to prevent the bent portion of the capacitance insulating film 217 deposited on the thin film 16 from becoming thinner, it is possible to suppress an increase in leak current generated between the lower electrode 216 and the upper electrode 218.

According to the second embodiment, the protective film 2
Etching back using a conventional resist in order to remove the first conductive film 213 outside the first concave portion 212 by etching the first conductive film 213 using the mask 15 as a mask. Compared to the first conductive film 2
13, a higher etching selectivity can be obtained, so that the first conductive film 213 outside the first concave portion 212 can be accurately and easily removed.

In the second embodiment, the plug 20
Although a polysilicon film was used as the constituent material of No. 9, an amorphous silicon film or the like may be used instead.

In the second embodiment, the SiN film is used as the first protective insulating film 202. However, the present invention is not limited to this. Another insulating film having an etching selectivity with respect to the second interlayer insulating film 210 is used. A membrane can be used. Specifically, when a SiO ₂ film is used as the second interlayer insulating film 210, a SiAlN film may be used as the first protective insulating film 202. In this way, by controlling the ratio of mixing AlN which is a harder material with a higher density than SiN (when the ratio is x, the film becomes a Si _1-x Al _x N film), the second interlayer insulating film is formed. The etching selectivity with respect to the film 210 can be controlled.

In the second embodiment, the SiN film is used as the second protective insulating film 211. However, the present invention is not limited to this, and the etching selectivity with respect to the first conductive film 213 or the protective film 215 is not limited to this. Other insulating films can be used. Specifically, the first conductive film 213 and the protective film 2
In the case where a platinum film and a SiO ₂ film are used as 15 respectively, a SiAlN film may be used as the second protective insulating film 211. By doing so, the etching selectivity with respect to the first conductive film 213 or the etching selectivity with respect to the protective film 215 can be controlled by the mixing ratio of AlN which is a harder material than the SiN.

In the second embodiment, dry etching is used to remove the first conductive film 213 outside the first concave portion 212. Instead, CMP is used.
Method may be used. By doing so, the first recess 21
Since the first conductive film 213 outside the first concave portion 212 can be removed while covering the first conductive film 213 inside 2 with the protective film 215, the lower electrode 216 is contaminated by CMP slurry or the like. To prevent the capacitor 2
19 can be improved. In this case, it is preferable to use an insulating film whose polishing rate by CMP is lower than that of the first conductive film 213 as the second protective insulating film 211. Specifically, when a platinum film is used as the first conductive film 213, a SiN film or a SiAlN film can be used as the second protective insulating film 211.

In the second embodiment, a TiN film is used as the barrier layer 208.
An AlN film or the like may be used.

In the second embodiment, a platinum film is used as the lower electrode 216 or the upper electrode 218. Instead, a ruthenium (Ru) film, an iridium (I
An r) film or a palladium (Pd) film, or an alloy film made of at least two metals of platinum, ruthenium, iridium, and palladium may be used.

In the second embodiment, the BST film is used as the capacitance insulating film 217.
An a ₂ O ₅ film or the like may be used.

(Third Embodiment) A method of manufacturing a semiconductor device according to a third embodiment of the present invention will be described with reference to the drawings.

In the third embodiment, the semiconductor device manufacturing method according to the second embodiment is shown in FIGS.
(D), the same processes as those shown in FIGS. 7 (a) to (d), FIGS. 8 (a) to (c) and FIGS. 9 (a) to (c) are performed. Steps subsequent to the illustrated steps will be described with reference to FIGS.

First, the protective film 215 (see FIG. 9C) is removed by, for example, wet etching or dry etching, and as shown in FIG.
To expose. At this time, a part of the protective film 215 is left as a partial protective film 215a in the bent portion of the lower electrode 216.

Next, as shown in FIG. 11B, B, for example, is formed on the lower electrode 216 and the partial protection film 215a.
The capacitor insulating film 217 made of the ST film is formed in the second concave portion 214.
Is deposited so that the upper part of remains.

Next, as shown in FIG. 11C, after depositing a second conductive film made of, for example, a platinum film on the capacitance insulating film 217, the second conductive film is patterned. To form an upper electrode 218. Thereby, the lower electrode 21
6, a capacitor 219 which is composed of a capacitive insulating film 217 and an upper electrode 218 and is electrically connected to the plug 209.
Is formed in the concave portion 212.

According to the third embodiment, the following effects can be obtained in addition to the effects obtained in the second embodiment.

That is, the protective film 21 made of a SiO ₂ film
5 is removed, a part of the protective film 215 is left as a partial protective film 215a at the bent portion of the lower electrode 216. Therefore, when the bent portion of the lower electrode 216 is thinned, the thinned portion is partially protected. It can be covered by the film 215a. For this reason, it is possible to prevent the bent portion of the capacitor insulating film 217 deposited on the lower electrode 216 from being thinned due to the step coverage of the capacitor insulating film 217, so that the lower electrode 216 and the upper electrode 218 can be connected to each other. Can be prevented from increasing in the leakage current generated during the operation. In addition, when the bent portion of the capacitor insulating film 217 is thinned, the partial protection film 215a remains under the thinned portion, so that a short circuit between the lower electrode 216 and the upper electrode 218 can be prevented.

[0113]

According to the present invention, the resistance of the plug can be reduced by forming a cobalt silicide layer on the plug. Further, since the barrier layer can be formed over the entire surface of the cobalt silicide layer, contact between the cobalt silicide layer of the plug and the lower electrode of the capacitor formed on the plug can be prevented. Therefore, it is possible to prevent the capacitance lower electrode from being silicided when forming the capacitance lower electrode, and to prevent the cobalt silicide layer, that is, the plug, from being oxidized when forming the capacitance insulating film on the capacitance lower electrode. it can.

Further, according to the present invention, it is possible to prevent the capacitance lower electrode from being contaminated by the etching residue or the CMP slurry, so that the reliability of the capacitor can be improved.

[Brief description of the drawings]

FIGS. 1A to 1D are cross-sectional views showing respective steps of a method of silicidizing a polysilicon film forming a plug using cobalt.

FIGS. 2A to 2D are cross-sectional views showing steps of a method of silicidizing a polysilicon film forming a plug using cobalt.

FIG. 3 is a plan view of the semiconductor device according to the first embodiment.

FIG. 4 is a sectional view taken along line II in FIG. 1;

FIG. 5 is a sectional view taken along line II-II in FIG.

FIGS. 6A to 6D are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a second embodiment.

FIGS. 7A to 7D are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a second embodiment.

FIGS. 8A to 8C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to a second embodiment.

FIGS. 9A to 9C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a second embodiment.

FIGS. 10A to 10C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a second embodiment.

FIGS. 11A to 11C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a third embodiment.

FIG. 12 is a sectional view of a conventional semiconductor device.

FIGS. 13A to 13D are cross-sectional views showing steps of a method of silicidizing a polysilicon film forming a plug using titanium.

FIGS. 14A to 14D are cross-sectional views showing steps of a method of silicidizing a polysilicon film forming a plug using titanium.

[Explanation of symbols]

 Reference Signs List 10 silicon substrate 11 first interlayer insulating film 12 contact hole 12a recess 13 polysilicon film 14 cobalt film 15 cobalt silicide layer 16 TiN film 17 barrier layer 18 plug 19 second interlayer insulating film 20 recess 21 conductive film 100 silicon Substrate 101 STI 102 Active region 103 Word line 104 First interlayer insulating film 105 First protective insulating film 106 Plug 106a Polysilicon film 106b Cobalt silicide layer 106c Barrier layer 107 Bit line contact 108 Bit line 109 Second interlayer insulating film 110 Second protective insulating film 111 Capacitor 111a Lower electrode 111b Capacitive insulating film 111c Upper electrode 200 Silicon substrate 201 First interlayer insulating film 202 First protective insulating film 203 Contact L 203a Recessed part 204 Polysilicon film 205 Cobalt film 206 Cobalt silicide layer 207 TiN film 208 Barrier layer 209 Plug 210 Second interlayer insulating film 211 Second protective insulating film 212 First concave portion 213 First conductive film 214 Second concave portion 215 Protective film 215a Partial protective film 216 Lower electrode 217 Capacitive insulating film 218 Upper electrode 219 Capacitor R0 Bent portion

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Yoshihiro Mori 1006 Kazuma Kadoma, Osaka Pref. Matsushita Electric Industrial Co., Ltd. F-term (reference) PR21 PR33 PR39 PR40

Claims (10)

[Claims] A plug embedded in a first insulating film deposited on a semiconductor substrate; a lower electrode sequentially embedded in a second insulating film deposited on the first insulating film; A semiconductor device comprising a film and an upper electrode, the capacitor being connected to the plug, the plug having a cobalt silicide layer and a barrier layer formed on the cobalt silicide layer . 2. The semiconductor device according to claim 1, wherein a protective insulating film made of a SiN film or a SiAlN film is formed above the first insulating film. 3. The semiconductor device according to claim 1, wherein a protective insulating film made of a SiN film or a SiAlN film is formed above the second insulating film. 4. A first step of depositing a first insulating film on a semiconductor substrate, a second step of forming a contact hole in the first insulating film, and an upper portion remaining in the contact hole. Forming a silicon film on the silicon film; and depositing a cobalt film on the silicon film, and then reacting the silicon film and the cobalt film by heat treatment to form a cobalt silicide layer on the surface of the silicon film. Forming a barrier layer on the cobalt silicide layer so as to completely fill the contact hole, and forming a plug comprising the silicon film, the cobalt silicide layer, and the barrier layer in the contact hole. A sixth step of depositing a second insulating film on the first insulating film; and forming a recess in the second insulating film, A method of manufacturing a semiconductor device, comprising: a seventh step of forming an upper surface to be exposed; and an eighth step of sequentially forming a capacitor lower electrode, a capacitor insulating film, and a capacitor upper electrode in the recess. Method. 5. An SiN film or a SiAlN film on the upper side of the first insulating film between the first step and the second step.
5. The method according to claim 4, further comprising the step of forming a protective insulating film made of a film. 6. A first step of depositing an insulating film on a semiconductor substrate; a second step of forming a first concave portion in the insulating film; and the insulating film in which the first concave portion is formed. A third step of depositing a conductive film on the first concave portion so that a second concave portion is formed inside the conductive film in the first concave portion; and embedding a protective film in the second concave portion. A fifth step of removing the conductive film outside the first concave portion and forming a capacitive lower electrode made of the conductive film on a wall surface and a bottom portion of the first concave portion; Removing the protective film and exposing the capacitor lower electrode, and subsequently forming a capacitor insulating film and a capacitor upper electrode on the capacitor lower electrode in a sixth step. A method for manufacturing a semiconductor device. 7. The method according to claim 1, further comprising a step of forming a protective insulating film made of a SiN film or a SiAlN film on the insulating film, between the first step and the second step. The method for manufacturing a semiconductor device according to claim 6. 8. The conductive film is made of a platinum film, and the third step includes a step of performing a heat treatment at about 400 to 750 ° C. on the conductive film after depositing the conductive film. 7. The method for manufacturing a semiconductor device according to claim 6, wherein: 9. The method according to claim 9, wherein the fifth step includes a step of etching the conductive film using the protective film as a mask to remove the conductive film outside the first recess. The method of manufacturing a semiconductor device according to claim 6, wherein: 10. The protection film has an insulating property, and the sixth step includes a step of removing the protection film so that the protection film remains at a bent portion of the lower capacitor electrode. 7. The method for manufacturing a semiconductor device according to claim 6, wherein: